Wafer-level bidirectional TVS packaging structure based on thin film technology

Abstract

The invention relates to the technical field of semiconductor device packaging, in particular to a wafer-level bidirectional TVS (Transient Voltage Suppressor) packaging structure based on a thin film process, which comprises a wafer substrate, and a bidirectional TVS chip unit array, a thin film interconnection structure, a passivation layer and an extraction electrode layer are arranged on the wafer substrate; the bidirectional TVS chip unit array comprises a plurality of TVS chip units arranged on the surface of the wafer substrate in an array, and the thin film interconnection structure is electrically connected with the extraction electrode layer; the wafer substrate, the thin film interconnection structure and the passivation layer are cut corresponding to two groups of adjacent TVS chip units to form a plurality of packaging units; the packaging unit is sleeved with a shell, two pins are fixedly installed on the shell corresponding to the extraction electrode layer, and the pins are electrically connected with the extraction electrode layer. Through structural innovation and process optimization, a miniaturized, high-integration, low-parasitism, high-reliability and wide-adaptation bidirectional TVS protection function is realized, strict requirements of current electronic equipment on a protection device are effectively met, and the bidirectional TVS protection circuit has remarkable technical value and market prospect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device packaging technology, and more specifically to a wafer-level bidirectional TVS packaging structure based on thin-film technology. Background Technology

[0002] With the rapid development of electronic technology, electronic devices are constantly moving towards miniaturization, high integration, and high reliability, which places more stringent requirements on the protection devices within them. As a highly efficient transient voltage protection device, TVS can clamp excessively high transient voltages within a safe range in a very short time, thereby protecting subsequent circuits from damage. In existing technologies, traditional TVS packaging mostly adopts discrete device packaging. However, discrete TVS devices are relatively large in size, making it difficult to meet the current electronic device requirements for miniaturization and high integration. Especially in wafer-level integrated systems, discrete devices occupy too much circuit board space, which restricts the improvement of overall system performance. Therefore, wafer-level packaging technology has gradually attracted attention. Wafer-level packaging can significantly reduce package size and improve integration. However, most existing wafer-level TVS packaging structures are unidirectional protection structures. In applications requiring bidirectional voltage protection, two unidirectional TVS devices are often connected in reverse series to achieve bidirectional protection. This not only increases the number of devices and manufacturing costs but also further increases the package size. In addition, the connection between the two devices introduces additional parasitic parameters, reducing protection performance. Therefore, developing a wafer-level bidirectional TVS packaging structure based on thin-film technology to achieve miniaturization, high integration, low parasitic parameters, and high reliability of bidirectional transient voltage protection has become an urgent technical problem to be solved in the current semiconductor device packaging field. Summary of the Invention

[0003] To overcome the shortcomings of existing technologies, such as large size, low integration, high cost and large parasitic parameters due to the need for multiple devices to be connected in series for bidirectional protection, and poor performance of metal interconnect layers in wafer-level packaging processes, this application provides a wafer-level bidirectional TVS packaging structure based on thin-film technology.

[0004] The wafer-level bidirectional TVS packaging structure based on thin-film technology provided in this application adopts the following technical solution: A wafer-level bidirectional TVS packaging structure based on thin-film technology includes a wafer substrate, on which a bidirectional TVS chip cell array is disposed, and a thin-film interconnect structure is electrically connected to the bidirectional TVS chip cell array. The thin-film interconnect structure has a passivation layer and a lead-out electrode layer. The bidirectional TVS chip cell array includes multiple TVS chip cells arrayed on the surface of the wafer substrate, and a first insulating heat dissipation layer is disposed on the outer side of each TVS chip cell. The thin-film interconnect structure is electrically connected to the lead-out electrode layer. The wafer substrate, together with the thin-film interconnect structure and the passivation layer, is cut into multiple packaging units corresponding to two adjacent groups of TVS chip cells. Each packaging unit is encased in a housing, on which two pins are fixedly mounted corresponding to the lead-out electrode layer, and the pins are electrically connected to the lead-out electrode layer.

[0005] Furthermore, the TVS chip unit includes an N-type semiconductor layer and a P-type semiconductor layer, with a PN junction disposed between the N-type semiconductor layer and the P-type semiconductor layer. The N-type semiconductor layer and the P-type semiconductor layer in two adjacent TVS chip units are alternately arranged to form a bidirectional conductive structure.

[0006] Furthermore, the thin-film interconnect structure includes a first metal interconnect layer and a second metal interconnect layer, with a second insulating and heat-dissipating layer disposed on the outer side of the first metal interconnect layer and the second metal interconnect layer; the first metal interconnect layer covers the alternately arranged N-type semiconductor layers and P-type semiconductor layers located on one side of the PN junction, and electrically connects all the N-type semiconductor layers and P-type semiconductor layers together; the second metal interconnect layer covers the alternately arranged N-type semiconductor layers and P-type semiconductor layers located on the other side of the PN junction, and electrically connects all the N-type semiconductor layers and P-type semiconductor layers together.

[0007] Furthermore, the passivation layer covers the thin-film interconnect structure, and two windows are opened on the passivation layer corresponding to each of the packaging units; the lead electrode layer includes a first electrode and a second electrode, the first electrode and the second electrode pass through the windows respectively, and the first electrode and the second electrode are electrically connected to the first metal interconnect layer and the second metal interconnect layer respectively.

[0008] Furthermore, the N-type semiconductor layer is made of N-type doped silicon material; the P-type semiconductor layer is made of P-type doped silicon material. Furthermore, a back heat dissipation layer is provided on the side of the wafer substrate away from the bidirectional TVS chip unit array. The back heat dissipation layer is prepared by physical vapor deposition and is a titanium-copper-nickel-gold composite metal layer.

[0009] Furthermore, the thin-film interconnect structure is fabricated using a thin-film process, which includes one or more combinations of physical vapor deposition, chemical vapor deposition, or atomic layer deposition; the materials of the first metal interconnect layer and the second metal interconnect layer are one or more alloys of copper, aluminum, gold, or silver.

[0010] Furthermore, an ohmic contact layer is provided in the contact area between the first metal interconnect layer and the second metal interconnect layer and the TVS chip unit, and the ohmic contact layer is a nickel-silicon alloy layer.

[0011] Furthermore, the passivation layer is prepared using polyimide; the lead-out electrode layer is prepared using an electroplating process, and the material is a copper-nickel alloy. Furthermore, the sidewall of the window is tapered, and the angle between the sidewall of the window and the upper surface of the passivation layer is 30° to 60°.

[0012] Beneficial effects achieved: This application achieves bidirectional TVS protection with "miniaturization, high integration, low parasitics, high reliability, and wide adaptability" through structural innovation and process optimization. It effectively meets the stringent requirements of current electronic devices for protection devices and can be widely used in consumer electronics, automotive electronics, industrial control, communication equipment and other fields. It has significant technical value and market prospects. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the overall structure of one embodiment of this application.

[0014] Figure 2 This is an exploded view of the structure of one embodiment of this application.

[0015] Figure 3 This is an exploded view of the structure of the TVS chip unit, thin film interconnect structure, passivation layer and lead-out electrode layer in one embodiment of this application.

[0016] Figure 4 This is a schematic diagram of the overall structure of the packaging unit in one embodiment of this application.

[0017] Figure 5 This is an exploded view of the packaging unit in one embodiment of this application.

[0018] Figure 6 This is a schematic diagram of the pin mounting structure in one embodiment of this application.

[0019] Figure 7 This is a schematic diagram of the installation structure of the dustproof plate in one embodiment of this application.

[0020] Explanation of reference numerals in the attached figures: 100, wafer substrate; 200, bidirectional TVS chip cell array; 201, TVS chip cell; 2011, N-type semiconductor layer; 2012, P-type semiconductor layer; 2013, PN junction; 202, first insulating heat dissipation layer; 300, thin film interconnect structure; 301, first metal interconnect layer; 302, second metal interconnect layer; 303, second insulating heat dissipation layer; 400, passivation layer; 401, window; 500, lead electrode layer; 501, first electrode; 502, second electrode; 600, packaging unit; 601, housing; 602, pin; 603, heat dissipation cavity; 604, heat dissipation hole; 605, dustproof plate; 606, thermally conductive block; 607, piston chamber; 608, piston body; 609, piston rod; 610, connecting rod; 700, back heat dissipation layer. Detailed Implementation

[0021] The following is in conjunction with the appendix Figures 1-7 This application will be described in further detail.

[0022] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] This application discloses a wafer-level bidirectional TVS packaging structure based on thin-film technology.

[0025] Please refer to the above as well. Figures 1 to 7In one embodiment of this application, a wafer-level bidirectional TVS packaging structure based on thin-film technology includes a wafer substrate 100, on which a bidirectional TVS chip cell array 200 is disposed, and a thin-film interconnect structure 300 is electrically connected to the bidirectional TVS chip cell array 200. A passivation layer 400 and a lead-out electrode layer 500 are disposed on the thin-film interconnect structure 300. The bidirectional TVS chip cell array 200 includes a plurality of TVS chip cells 201 arrayed on the surface of the wafer substrate 100, and a first insulating heat dissipation layer 202 is disposed on the outer side of each TVS chip cell 201. The thin-film interconnect structure 300 is electrically connected to the lead-out electrode layer 500. The wafer substrate 100, together with the thin-film interconnect structure 300 and the passivation layer 400, corresponds to two adjacent groups of TVS chip cells 201 along... Figure 1 The dashed lines shown form multiple packaging units 600. Each packaging unit 600 is fitted with a housing 601. Two pins 602 are fixedly mounted on the housing 601 corresponding to the lead-out electrode layer 500. The pins 602 are electrically connected to the lead-out electrode layer 500.

[0026] During operation, it is connected to an external circuit via pin 602. When an instantaneous overvoltage occurs in the external circuit, the bidirectional TVS chip unit 201 in the package unit 600 will respond quickly. Its core semiconductor structure will switch from a high-resistance state to a low-resistance state, guiding the large current generated by the overvoltage to itself, thus preventing the overvoltage signal from damaging the sensitive downstream circuit. Since the TVS chip unit 201 is bidirectional, it can achieve the same level of protection regardless of the polarity of the overvoltage signal.

[0027] The thin-film interconnect structure 300 serves as the core for signal and current transmission. On the one hand, it realizes the electrical connection between multiple TVS chip units 201 through thin-film technology. On the other hand, it leads the electrode signals of the TVS chip units 201 to the lead-out electrode layer 500. The lead-out electrode layer 500 then connects to the external circuit through the pins 602 on the housing 601, forming a complete electrical signal path from the external circuit, pins, lead-out electrode layer, thin-film interconnect to the TVS chip unit 201 in sequence, ensuring stable signal transmission during normal operation and efficient triggering of protection functions during overvoltage.

[0028] In addition, the first insulating heat dissipation layer 202 wraps around the outside of the TVS chip unit 201, which not only avoids the risk of leakage between chip units, but also quickly conducts the heat generated when the TVS is turned on; the passivation layer 400 protects the thin film interconnect structure 300, preventing the external environment from causing corrosion or short circuits to the interconnect lines, and ensuring the long-term reliability of the structure.

[0029] Please refer to the above as well. Figures 1 to 7 In one specific embodiment of this application, the wafer substrate 100 is one of a silicon substrate, a sapphire substrate, or a silicon carbide substrate, with a thickness of 100-500 μm.

[0030] During operation, the wafer substrate 100 serves as the basic carrier of the entire packaging structure, and the selection of its material and thickness directly serves the three core requirements of structural support, thermal management, and electrical insulation.

[0031] Silicon substrates, sapphire substrates, and silicon carbide substrates all possess excellent mechanical strength, which can stably support the multi-layer structure such as the bidirectional TVS chip cell array 200 and thin film interconnect structure 300 on top, ensuring that the wafer level is not easily deformed or damaged during batch processing such as thin film deposition, photolithography, and dicing. At the same time, all three types of substrates are electrically insulating materials, which can prevent the substrate itself from becoming a conductive path and prevent leakage interference between TVS chip cells 201 or between the chip and external circuits.

[0032] A thickness range of 100-500μm represents a balance between support and functionality. If the thickness is too thin (<100μm), the substrate lacks sufficient mechanical strength and is prone to breakage during cutting, packaging, and other processes. If the thickness is too thick (>500μm), it increases the length of the heat conduction path, reduces heat dissipation efficiency, and increases the overall volume of the packaged unit. This thickness range ensures that the substrate provides stable support without hindering the transfer of heat from the TVS chip unit 201 to the outside through the substrate.

[0033] Please refer to the above as well. Figures 1 to 7 In one specific embodiment of this application, the TVS chip unit 201 includes an N-type semiconductor layer 2011 and a P-type semiconductor layer 2012. A PN junction 2013 is provided between the N-type semiconductor layer 2011 and the P-type semiconductor layer 2012. The N-type semiconductor layer 2011 and the P-type semiconductor layer 2012 in two adjacent TVS chip units 201 are alternately arranged to form a bidirectional conductive structure.

[0034] During operation, the core function of the TVS chip unit 201 is to achieve overvoltage protection based on the reverse breakdown characteristics of the PN junction 2013, while the alternating arrangement of adjacent units gives the whole unit bidirectional conductivity.

[0035] In a single TVS chip unit 201, the PN junction 2013 formed by the N-type semiconductor layer 2011 and the P-type semiconductor layer 2012 is in a reverse cutoff state under normal operating voltage, allowing only a weak leakage current to pass through, which does not affect the normal signal transmission of the circuit; when an external positive overvoltage occurs, the PN junction is reverse broken down and instantly turns into a low-resistance state, discharging the large current generated by the overvoltage and achieving protection.

[0036] The N-type and P-type semiconductor layers of two adjacent TVS chip units 201 are arranged alternately to form complementary conductive paths: when a forward overvoltage is applied externally, the PN junction of the preceding unit breaks down and conducts in the reverse direction; when a reverse overvoltage is applied, the PN junction of the following unit breaks down and conducts in the reverse direction. This structure eliminates the need for additional integrated reverse diodes and achieves equal response to positive and negative overvoltages through the synergistic effect of the array units, thus forming a complete bidirectional protection mechanism.

[0037] Please refer to the above as well. Figures 1 to 7 In one specific embodiment of this application, the thin-film interconnect structure 300 includes a first metal interconnect layer 301 and a second metal interconnect layer 302. A second insulating heat dissipation layer 303 is disposed on the outer side of the first metal interconnect layer 301 and the second metal interconnect layer 302. The first metal interconnect layer 301 covers the alternately arranged N-type semiconductor layers 2011 and P-type semiconductor layers 2012 located on one side of the PN junction 2013 and electrically connects all the N-type semiconductor layers 2011 and P-type semiconductor layers 2012 together. The second metal interconnect layer 302 covers the alternately arranged N-type semiconductor layers 2011 and P-type semiconductor layers 2012 located on the other side of the PN junction 2013 and electrically connects all the N-type semiconductor layers 2011 and P-type semiconductor layers 2012 together.

[0038] During operation, the thin-film interconnect structure 300 achieves electrical connection and signal output of the TVS chip unit 201 array through the symmetrical design of the double-layer metal interconnect layer, while relying on the insulating heat dissipation layer to ensure stability.

[0039] The first metal interconnect layer 301 and the second metal interconnect layer 302 respectively cover the semiconductor layers on both sides of the PN junction 2013: For the N-type and P-type semiconductor layers that are alternately arranged on one side of the PN junction, the first metal interconnect layer 301 electrically connects them all to form a common electrode; similarly, the alternately arranged semiconductor layers on the other side of the PN junction are connected to form another common electrode through the second metal interconnect layer 302.

[0040] This connection method allows all TVS chip units 201 to be integrated in reverse parallel. When a forward overvoltage is applied between the two common electrodes, the PN junction on one side breaks down and conducts in reverse. When a reverse overvoltage is applied, the PN junction on the other side breaks down and conducts in reverse, thus forming a complete bidirectional protection path through the lead-out of the double interconnect layer.

[0041] The second insulating heat dissipation layer 303 wraps around the outside of the first metal interconnect layer 301 and the second metal interconnect layer 302. On the one hand, it isolates the electrical interference between the first metal interconnect layer 301 and the second metal interconnect layer 302 to prevent short circuits; on the other hand, it conducts the heat generated by the TVS chip unit 201 during operation to the outside to prevent the interconnect layer from failing due to high temperature.

[0042] Please refer to the above as well. Figures 1 to 7 In one specific embodiment of this application, both the first insulating heat dissipation layer 202 and the second insulating heat dissipation layer 303 are prepared using aluminum nitride (AlN) or beryllium oxide (BeO) ceramic matrix composite materials, with a thickness of 2-5 μm. They are uniformly covered on the target area using plasma-enhanced chemical vapor deposition (PECVD). Both aluminum nitride and beryllium oxide are high thermal conductivity insulating materials, with aluminum nitride having a thermal conductivity of 180-200 W / (m·K) and beryllium oxide having a thermal conductivity of 250-300 W / (m·K), far exceeding that of traditional organic insulating materials, such as epoxy resin, which has a thermal conductivity of only 0.2-0.5 W / (m·K). Simultaneously, both have a volume resistivity > 10⁻⁶. 14 With an insulation strength of Ω·cm, it exhibits excellent insulation properties and can effectively isolate the risk of leakage between adjacent TVS chip units or metal interconnect layers.

[0043] It should be noted that beryllium oxide insulating heat dissipation layers are only suitable for high-temperature industrial applications and must be deposited in an inert gas environment to avoid dust leakage; aluminum nitride materials are preferred for consumer electronics applications.

[0044] Please refer to the above as well. Figures 1 to 7 In one specific embodiment of this application, a passivation layer 400 covers the thin-film interconnect structure 300, and two windows 401 are opened on the passivation layer 400 corresponding to each packaging unit 600; the lead electrode layer 500 includes a first electrode 501 and a second electrode 502, the first electrode 501 and the second electrode 502 pass through the windows 401 respectively, and the first electrode 501 and the second electrode 502 are electrically connected to the first metal interconnect layer 301 and the second metal interconnect layer 302 respectively.

[0045] During operation, the passivation layer 400 and the lead electrode layer 500 work together to achieve protection of the thin film interconnect structure and efficient connection with external circuits.

[0046] The passivation layer 400 completely covers the thin-film interconnect structure 300, utilizing its insulating properties to isolate moisture, impurities, and mechanical damage from the external environment. This prevents corrosion, short circuits, or open circuits between the first metal interconnect layer 301 and the second metal interconnect layer 302, ensuring the long-term stability of the interconnect circuitry. Simultaneously, the two windows 401 on the passivation layer 400 for each packaging unit 600 provide precise electrical connection points for the lead-out electrode layer 500.

[0047] The first electrode 501 in the lead-out electrode layer 500 contacts the first metal interconnect layer 301 through window 401, and the second electrode 502 contacts the second metal interconnect layer 302 through another window 401, forming a conductive path between the metal interconnect layer and the lead-out electrode. When the TVS chip unit 201 is working, the electrical signal converges through the first metal interconnect layer 301 and the second metal interconnect layer 302, and is then transmitted to the external pin 602 via the lead-out electrode layer 500, ultimately forming a closed loop with the external circuit to ensure the continuity of signal transmission and the effectiveness of the protection function.

[0048] Please refer to the above as well. Figures 1 to 7 In one specific embodiment of this application, the N-type semiconductor layer 2011 is made of N-type doped silicon material with a doping concentration of 1×10⁻⁶. 15 ~1×10 19 cm -3 The thickness is 1–5 μm; the P-type semiconductor layer 2012 uses P-type doped silicon material with a doping concentration of 1 × 10⁻⁶. 15 ~1×10 19 cm -3 The thickness is 1–5 μm.

[0049] During operation, the material selection, doping concentration, and thickness parameters of the N-type and P-type semiconductor layers directly determine the electrical characteristics of the PN junction and the protection performance of the TVS chip unit 201.

[0050] N-type and P-type doped silicon differ in carrier concentration due to doping: the N-type layer has free electrons as the majority carriers, while the P-type layer has holes as the majority carriers, forming a PN junction barrier at the interface. (Doping concentration 1×10⁻⁶) 15 ~1×10 19 cm -3 The concentration determines the barrier height and the width of the depletion region. The higher the concentration, the narrower the barrier region and the lower the reverse breakdown voltage. For example, high concentration doping can achieve low-voltage breakdown and is suitable for low-voltage circuit protection. The lower the concentration, the wider the barrier region and the higher the breakdown voltage.

[0051] The 1–5 μm thickness design ensures that the depletion region is completely contained within the semiconductor layer, avoiding interference from the substrate or other layers on the PN junction characteristics, while ensuring sufficient carrier channels to support large current discharge under overvoltage.

[0052] When an external voltage is applied to a PN junction, the doping concentration and thickness together determine the threshold and speed of reverse breakdown: within a set range, the carrier concentration is moderate, which avoids response delay due to too low concentration and prevents breakdown voltage stability from decreasing due to too high concentration, ensuring that the TVS is accurately triggered for protection within nanoseconds.

[0053] Please refer to the above as well. Figures 1 to 7In one specific embodiment of this application, a back heat dissipation layer 700 is provided on the side of the wafer substrate 100 away from the bidirectional TVS chip unit array 200. The back heat dissipation layer 700 is prepared by physical vapor deposition and is a titanium-copper-nickel-gold composite metal layer with a total thickness of 0.5 to 2 μm. Among them, the titanium layer has a thickness of 30 to 80 nm, the copper layer has a thickness of 0.3 to 1.8 μm, the nickel layer has a thickness of 0.3 to 0.8 μm, and the gold layer has a thickness of 50 to 200 nm.

[0054] During operation, the back heat dissipation layer 700, through the synergistic effect of the composite metal layer, constructs an efficient heat dissipation path and ensures structural stability.

[0055] During overvoltage protection, the PN junction of the TVS chip unit 201 breaks down, instantly generating a large amount of heat. This heat is conducted through the wafer substrate 100 to the side furthest from the chip array. The back heat dissipation layer 700 adopts a titanium-copper-nickel-gold composite structure. The titanium layer is in direct contact with the wafer substrate, and the high adhesion between titanium and the substrate material ensures that the entire composite layer is not easily detached. The middle copper layer serves as the core heat dissipation layer, and the excellent thermal conductivity of copper quickly diffuses the heat conducted by the substrate to the entire heat dissipation layer. The nickel layer covers the copper layer to prevent the copper from being oxidized or corroded, while also enhancing the bonding force with the outer gold layer. The gold layer, as the outermost layer, utilizes the chemical stability and high conductivity of gold to prevent the nickel layer from oxidizing and can also interface with the external heat dissipation structure in subsequent packaging, forming a complete heat dissipation link of chip-substrate-composite heat dissipation layer-external heat sink.

[0056] Physical vapor deposition (PVD) technology ensures that each metal layer is uniform and dense, with precise and controllable thickness, which maximizes heat dissipation efficiency without increasing the overall thickness of the package.

[0057] Please refer to the above as well. Figures 1 to 7 In one specific embodiment of this application, a heat dissipation cavity 603 is provided at the bottom of the outer shell 601, and a heat dissipation hole 604 communicating with the heat dissipation cavity 603 is provided on the side wall of the outer shell 601. A dustproof plate 605 is slidably connected to the inner wall surface of the heat dissipation cavity 603. A heat-conducting block 606 is fixedly installed inside the heat-conducting block 606. A piston cavity 607 is provided inside the heat-conducting block 606. A piston body 608 is slidably connected to the piston cavity 607. One end of the piston body 608 facing the inside of the piston cavity 607 is filled with a thermal expansion medium inside the piston cavity 607. A piston rod 609 is fixedly installed at the end of the piston body 608 away from the inside of the piston cavity 607. A connecting rod 610 is fixedly connected to the end of the piston rod 609 away from the piston body 608. The connecting rod 610 is drivenly connected to the dustproof plate 605. The dustproof plate 605 covers the heat dissipation hole 604 at room temperature.

[0058] During operation, especially during overvoltage protection, the heat generated by the TVS package unit 600 is transferred to the piston chamber 607 via the heat-conducting block 606. The thermal expansion medium inside the piston chamber 607 expands due to the increased temperature, pushing the piston body 608 to slide within the piston chamber 607. This, in turn, drives the connecting rod 610 via the piston rod 609. The connecting rod 610 drives the dustproof plate 605 to slide against the inner wall of the heat dissipation cavity 603, removing the dustproof plate 605 from its position blocking the heat dissipation hole 604, exposing the heat dissipation hole 604. At this time, the heat dissipation cavity 603 is connected to the external environment through the heat dissipation hole 604. The heat inside the package unit is conducted to the heat dissipation cavity via the heat-conducting block 606 and then dissipated to the outside through the heat dissipation hole, achieving efficient heat dissipation.

[0059] When the equipment is in a low temperature or low load state, that is, when the heat is reduced, the fluid in the piston chamber shrinks in volume due to the decrease in temperature. The piston body 608 resets under the action of negative pressure, and drives the dustproof plate 605 to block the heat dissipation hole 604 again through the connecting rod 610, so as to prevent external dust and moisture from entering the encapsulation unit through the heat dissipation hole and avoid contamination or corrosion of the internal structure.

[0060] In one specific embodiment of this application, the thermal expansion medium is silicone oil, such as methyl silicone oil or phenyl silicone oil. Silicone oil, as a fluid that expands and contracts with temperature changes, exhibits significant and linear thermal expansion and contraction characteristics in the temperature range of -50°C to 200°C, and its coefficient of thermal expansion is approximately 1.0 × 10⁻⁶. -3 ~1.5×10 -3 ℃ -1 The volume changes uniformly with temperature, and can accurately respond to temperature fluctuations when the TVS chip unit 201 is working, that is, from room temperature to instantaneous high temperature during overpressure protection, ensuring that the sliding stroke of the piston body 608 has a stable correspondence with temperature changes, and avoiding abnormal opening and closing of the dustproof plate 605 due to unstable fluid characteristics.

[0061] Meanwhile, silicone oil has excellent oxidation and aging resistance, and does not chemically react with the metal inner wall of piston cavity 607. Long-term use will not cause corrosion, deterioration or sudden change in viscosity, which can ensure the reliability of piston body 608 sealing and sliding, and avoid fluid leakage from affecting the driving effect.

[0062] Furthermore, silicone oil typically has a boiling point >200℃ and a freezing point <-50℃. Within the temperature range of -55℃ to 150℃ of the TVS packaging unit, it will not experience a sudden decrease in volume due to high-temperature volatilization, nor will it lose its fluidity due to low-temperature solidification, ensuring that the dustproof plate 605 can still be driven to complete the opening and closing action even under extreme working conditions.

[0063] Please refer to the above as well. Figures 1 to 7In one specific embodiment of this application, the thin film interconnect structure 300 is prepared using a thin film process, which includes one or more combinations of physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The first metal interconnect layer 301 and the second metal interconnect layer 302 are made of one or more alloys of copper, aluminum, gold, or silver, and have a thickness of 0.5 to 2 μm.

[0064] During the process, thin film deposition techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) are employed to achieve high-precision fabrication of metal layers at the wafer level. PVD is suitable for depositing highly conductive metals, using high-energy particles to bombard a target to deposit metal atoms onto the substrate surface, forming a uniform and dense thin film. CVD generates metal layers through chemical reactions of gaseous precursors, making it suitable for covering complex morphologies. ALD achieves precise control of nanometer-scale thickness through atomic-level layer-by-layer deposition. These processes together ensure that the first metal interconnect layer 301 and the second metal interconnect layer 302 can tightly cover the semiconductor layer surface, with controllable linewidth and thickness, meeting the high-density interconnection requirements of chip cell arrays.

[0065] Furthermore, copper, aluminum, gold, silver, and their alloys are all highly conductive materials that can effectively reduce the resistance loss of the interconnect layer and ensure the efficient transmission of large currents during overvoltage protection. The thickness design of 0.5 to 2 μm achieves a balance between conductivity and process feasibility. A thickness > 0.5 μm can avoid excessive resistance caused by skin effect or defects, while a thickness < 2 μm can avoid cracking or peeling caused by thin film stress.

[0066] Please refer to the above as well. Figures 1 to 7 In one specific embodiment of this application, the wiring width of the first metal interconnect layer 301 and the second metal interconnect layer 302 is 5-15 μm, the wiring spacing is 8-20 μm, and an ohmic contact layer is provided in the contact area between the first metal interconnect layer 301 and the second metal interconnect layer 302 and the TVS chip unit 201. The ohmic contact layer is a nickel-silicon alloy layer with a thickness of 10-30 nm, formed by high-temperature annealing at a temperature of 800-950°C for 10-30 seconds.

[0067] During operation, the first metal interconnect layer 301 and the second metal interconnect layer 302 adopt a wiring width of 5-15μm and a wiring spacing of 8-20μm, which is a balanced choice that takes into account both current carrying capacity and high-density integration: the wiring width determines the cross-sectional area of ​​the interconnect layer. A width of more than 5μm can ensure that no melting occurs when a large current passes through during overvoltage protection; a spacing of more than 8μm can avoid short circuits caused by photolithography precision errors or metal migration between adjacent wirings, and adapt to the compactness requirements of wafer-level array layout.

[0068] When an ohmic contact layer formed by high-temperature annealing of a nickel-silicon alloy layer comes into direct contact with a semiconductor layer, a Schottky barrier can form due to the difference in work function between the materials, resulting in excessively high contact resistance, potentially reaching 10 ohms. -3 Ω·cm 2 The above factors hinder current transmission; however, the reaction between nickel and silicon at high temperatures forms a low-resistance nickel-silicon alloy, such as NiSi2, which can eliminate the Schottky barrier and form an ohmic contact, meaning the contact resistance drops to 10 ohms. -6 Ω·cm 2 The following ensures unimpeded current conduction between the metal and semiconductor layers. A thickness design of 10–30 nm ensures that the alloy layer completely covers the contact area while avoiding damage to the semiconductor layer surface due to excessive thickness.

[0069] Please refer to the above as well. Figures 1 to 7 In one specific embodiment of this application, the passivation layer 400 is made of polyimide and has a thickness of 1 to 3 μm; the lead electrode layer 500 is made by electroplating and is made of copper-nickel alloy with a thickness of 2 to 5 μm.

[0070] During operation, the selection of materials, processes, and thickness design of the passivation layer 400 and the lead electrode layer 500 revolve around "insulation protection - high-efficiency lead-out - structural compatibility". Through the matching of material properties and processes, the stability of the thin film interconnect structure and the reliable connection of external circuits are ensured.

[0071] Passivation layer 400 is prepared using polyimide. As an organic polymer material, polyimide has a volume resistivity > 10. 14 With a thickness of Ω·cm, polyimide exhibits excellent insulation and mechanical flexibility. A thickness of 1–3 μm can completely cover the thin-film interconnect structure 300, isolating external moisture and impurities from contact with the metal interconnect layer and preventing short circuits or corrosion. At the same time, polyimide is heat-resistant, with a long-term operating temperature of over 200°C, and can withstand the temperature shock of subsequent packaging processes, such as welding and cutting. Furthermore, polyimide has good compatibility with wafer-level thin-film processes and can be mass-produced through coating, curing, and other steps, making it suitable for large-area uniform coverage requirements.

[0072] The electrode layer 500 is prepared using a copper-nickel alloy through an electroplating process. Utilizing the high deposition rate and patterning capability of electroplating, the window 401 of the passivation layer can be precisely filled, forming an electrical connection with the first metal interconnect layer 301 and the second metal interconnect layer 302. The copper-nickel alloy has a conductivity of approximately 1.0 × 10⁻⁶. 7 ~5.0×10 7 S / m, with high conductivity and nickel's oxidation resistance, and a thickness of 2-5μm, ensures the structural strength of the electrode, preventing breakage during subsequent pin soldering, while also reducing contact resistance, ensuring that current is efficiently transferred from the metal interconnect layer through the lead electrode layer to the external pin 602.

[0073] Please refer to the above as well. Figures 1 to 7 In one specific embodiment of this application, the sidewall of window 401 is formed into a cone shape by controlling the gradient power of dry etching, and the angle between the sidewall surface of window 401 and the upper surface of passivation layer 400 is 30° to 60°.

[0074] During operation, the tapered sidewall of window 401 forms a sloping structure at the edge of window 401, which optimizes the deposition morphology of the lead-out electrode layer 500 and solves the common problem of poor step coverage in thin film processing.

[0075] The window 401 on the passivation layer 400 is used to lead out the electrical connection between the electrode layer 500 and the metal interconnect layer. If the edge of the window is a right angle, the electrode material is prone to uneven thickness or even breakage at the right angle corner when electroplating or depositing metal. Due to the uneven electric field distribution at the right angle, the metal ions are deposited faster on the outside of the corner and slower on the inside, forming a step that is thick at the tip and thin on the inside. In severe cases, the inside will have gaps due to insufficient deposition, resulting in poor contact between the electrode and the interconnect layer.

[0076] The 30°–60° slope structure achieved through gradual power control in dry etching involves progressively reducing the etching power to allow the edge etching rate to transition from fast to slow, transforming right-angled edges into gentle slopes. When electrode material is deposited on the slope surface, ions can spread continuously along the slope, avoiding uneven deposition caused by electric field concentration. This ensures that the electrode layer forms a continuous and uniform coverage from the passivation layer surface to the interconnect layer surface at the window edge, eliminating the risk of breakage or voids at the step.

[0077] The implementation principle of the wafer-level bidirectional TVS packaging structure based on thin-film technology in this application embodiment is as follows: taking wafer-level integration combined with thin-film technology as the core framework, and through the collaborative design of multi-layer structures, a full-function closed loop of bidirectional overvoltage protection, efficient signal interconnection, stable environmental protection, and dynamic heat dissipation control is achieved.

[0078] First, using a wafer substrate 100 as the base carrier, an array of multiple TVS chip units 201 is constructed on its surface. Each unit is formed by alternating N-type and P-type semiconductor layers, creating a PN junction structure with complementary polarities between adjacent units. The semiconductor layers on both sides of the PN junction are shorted into two common electrodes by the first metal interconnect layer 301 and the second metal interconnect layer 302, effectively achieving reverse parallel connection of all PN junctions. During forward overvoltage, one side of the PN junction breaks down and discharges current in reverse, while during reverse overvoltage, the other side of the PN junction breaks down, achieving bidirectional protection without the need for an additional diode.

[0079] Secondly, relying on thin film processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), a dense metal interconnect layer is prepared to ensure low-resistance connection between the metal interconnect layer and the semiconductor layer through a nickel-silicon alloy ohmic contact layer, eliminating the bottleneck in current transmission. Simultaneously, a polyimide passivation layer 400 covers the interconnect layer to isolate moisture and impurities. Windows 401 with a 30°–60° slope are only opened at the corresponding packaging unit to avoid poor step coverage in the electroplated copper-nickel alloy lead electrode layer 500. This ultimately forms a complete path from TVS chip unit → metal interconnect layer → lead electrode layer → pin, ensuring low-loss transmission of normal signals and efficient discharge of overvoltage current.

[0080] Furthermore, the first insulating heat dissipation layer 202 on the outside of the TVS chip unit 201 not only prevents leakage between units but also assists in heat conduction. The second insulating heat dissipation layer 303 on the outside of the thin-film interconnect layer can prevent interlayer short circuits; the polyimide passivation layer 400 resists external corrosion. The outer shell 601 of the packaging unit provides mechanical protection. At the same time, the material selection takes into account the requirements of the application scenario. The wafer substrate can be silicon, sapphire, or silicon carbide. Silicon has the advantage of low cost, sapphire has the advantage of high temperature resistance, while silicon carbide has the advantage of high thermal conductivity. The back heat dissipation layer 700 adopts a titanium-copper-nickel-gold composite structure. The titanium layer ensures adhesion, the copper layer conducts heat efficiently, and the nickel-gold layer prevents oxidation, forming a heat conduction link from chip to substrate to back heat dissipation layer, solving the problem of instantaneous heat generation under overvoltage.

[0081] Furthermore, the heat-conducting block 606 in the heat dissipation cavity at the bottom of the outer casing 601 transfers the chip's heat to the piston cavity 607. The silicone oil in the cavity expands due to heat, pushing the piston body 608. This, in turn, drives the dustproof plate 605 to slide via the piston rod 609 and connecting rod 610, opening the heat dissipation hole 604 to achieve active heat dissipation. At low temperatures or low loads, the silicone oil contracts, and the dustproof plate resets, blocking the heat dissipation hole to prevent dust and moisture from entering. The entire process requires no additional power consumption and achieves adaptive matching between temperature and heat dissipation efficiency through fluid physics properties, balancing heat dissipation requirements with structural cleanliness.

[0082] In summary, this packaging structure simplifies the process through wafer-level integration, improves precision through thin-film technology, ensures performance through material adaptation, and optimizes reliability through dynamic control. Ultimately, it achieves miniaturization, high integration, long lifespan, and bidirectional TVS protection across a wide range of applications, making it widely applicable in consumer electronics, automotive electronics, industrial control, and other fields.

[0083] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A wafer-level bidirectional TVS packaging structure based on thin-film technology, characterized in that: The device includes a wafer substrate (100), on which a bidirectional TVS chip cell array (200) is disposed. A thin-film interconnect structure (300) is electrically connected to the bidirectional TVS chip cell array (200). A passivation layer (400) and a lead-out electrode layer (500) are disposed on the thin-film interconnect structure (300). The bidirectional TVS chip cell array (200) includes a plurality of TVS chip cells (201) arrayed on the surface of the wafer substrate (100). A first insulating heat dissipation layer is disposed on the outer side of each TVS chip cell (201). (202); The thin film interconnect structure (300) is electrically connected to the lead electrode layer (500); The wafer substrate (100), together with the thin film interconnect structure (300) and the passivation layer (400), is cut into multiple packaging units (600) corresponding to two adjacent TVS chip units (201); The packaging unit (600) is fitted with a shell (601), and two pins (602) are fixedly installed on the shell (601) corresponding to the lead electrode layer (500), and the pins (602) are electrically connected to the lead electrode layer (500).

2. The wafer-level bidirectional TVS packaging structure based on thin-film technology according to claim 1, characterized in that: The TVS chip unit (201) includes an N-type semiconductor layer (2011) and a P-type semiconductor layer (2012). A PN junction (2013) is provided between the N-type semiconductor layer (2011) and the P-type semiconductor layer (2012). The N-type semiconductor layer (2011) and the P-type semiconductor layer (2012) in two adjacent TVS chip units (201) are arranged alternately to form a bidirectional conductive structure.

3. The wafer-level bidirectional TVS packaging structure based on thin-film technology according to claim 2, characterized in that: The thin-film interconnect structure (300) includes a first metal interconnect layer (301) and a second metal interconnect layer (302). A second insulating heat dissipation layer (303) is disposed on the outer side of the first metal interconnect layer (301) and the second metal interconnect layer (302). The first metal interconnect layer (301) covers the alternating N-type semiconductor layer (2011) and the P-type semiconductor layer (2012) located on one side of the PN junction (2013) and electrically connects all the N-type semiconductor layer (2011) and the P-type semiconductor layer (2012) together. The second metal interconnect layer (302) covers the alternating N-type semiconductor layer (2011) and the P-type semiconductor layer (2012) located on the other side of the PN junction (2013) and electrically connects all the N-type semiconductor layer (2011) and the P-type semiconductor layer (2012) together.

4. The wafer-level bidirectional TVS packaging structure based on thin-film technology according to claim 3, characterized in that: The passivation layer (400) covers the thin film interconnect structure (300), and two windows (401) are opened on the passivation layer (400) corresponding to each of the packaging units (600); the lead electrode layer (500) includes a first electrode (501) and a second electrode (502), the first electrode (501) and the second electrode (502) pass through the window (401) respectively, and the first electrode (501) and the second electrode (502) are electrically connected to the first metal interconnect layer (301) and the second metal interconnect layer (302) respectively.

5. The wafer-level bidirectional TVS packaging structure based on thin-film technology according to claim 2, characterized in that: The N-type semiconductor layer (2011) is made of N-type doped silicon material; the P-type semiconductor layer (2012) is made of P-type doped silicon material.

6. The wafer-level bidirectional TVS packaging structure based on thin-film technology according to claim 1, characterized in that: A back heat dissipation layer (700) is provided on the side of the wafer substrate (100) away from the bidirectional TVS chip unit array (200). The back heat dissipation layer (700) is prepared by physical vapor deposition and is a titanium-copper-nickel-gold composite metal layer.

7. The wafer-level bidirectional TVS packaging structure based on thin-film technology according to claim 3, characterized in that: The thin-film interconnect structure (300) is prepared using a thin-film process, which includes one or more combinations of physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The materials of the first metal interconnect layer (301) and the second metal interconnect layer (302) are one or more alloys of copper, aluminum, gold, or silver.

8. The wafer-level bidirectional TVS packaging structure based on thin-film technology according to claim 3, characterized in that: An ohmic contact layer is provided in the contact area between the first metal interconnect layer (301) and the second metal interconnect layer (302) and the TVS chip unit (201), and the ohmic contact layer is a nickel-silicon alloy layer.

9. The wafer-level bidirectional TVS packaging structure based on thin-film technology according to claim 1, characterized in that: The passivation layer (400) is made of polyimide; the lead-out electrode layer (500) is made by electroplating and the material is a copper-nickel alloy.

10. The wafer-level bidirectional TVS packaging structure based on thin-film technology according to claim 4, characterized in that: The sidewall of the window (401) is conical, and the angle between the sidewall of the window (401) and the upper surface of the passivation layer (400) is 30° to 60°.

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