Wafer offset detection method and system, electronic equipment and storage medium

Abstract

The invention provides a wafer offset detection method and system, electronic equipment and a storage medium, and the method comprises the steps: testing each chip on a target wafer through testing equipment, and obtaining a wafer graph of the target wafer; the edge yield of each preset edge in the wafer graph is calculated, the distance between the center of the wafer graph and the center of the target wafer is calculated, and whether the target wafer deviates or not is determined by combining the edge yield of each preset edge in the wafer graph and the distance between the center of the wafer graph and the center of the target wafer. According to the invention, the wafer offset can be accurately detected, and mistaken placement and abnormal material mixing of the picked chips are avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a wafer offset detection method and system, an electronic device, and a storage medium. BACKGROUND

[0002] In the process of semiconductor manufacturing, testing, grinding, cutting, etc., wafer alignment is an important link. Usually, the edge and the positioning groove and the characteristic pattern of the wafer are used to guide the equipment to accurately position and align, and a corresponding reference coordinate system is established, and the chips are identified by X, Y coordinates. Accurate positioning and establishment of the reference coordinate system can express the specific position of each chip on the wafer in coordinates in each semiconductor process chain. In the process of testing and packaging and picking chips, if there is an alignment offset (X or Y coordinate offset), the wafer map as a whole will be misaligned, resulting in misplacement and abnormal mixing of the final picked chips. SUMMARY

[0003] Therefore, the present application aims to provide a wafer offset detection method and system, an electronic device, and a storage medium to solve the above technical problems.

[0004] To achieve the above purpose, the first aspect of the present application provides a wafer offset detection method, which comprises: testing each chip on a target wafer by using a test device to obtain a wafer map of the target wafer; calculating the edge yield of each preset edge in the wafer map; calculating the distance between the center of the wafer map and the center of the target wafer; determining whether the target wafer has an offset in combination with the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer.

[0005] In one embodiment, determining whether the target wafer has an offset in combination with the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer comprises: when there is at least one preset edge in the wafer map whose edge yield is less than the corresponding yield threshold, and the distance between the center of the wafer map and the center of the target wafer is less than or equal to one fourth of the size of the chip, it is determined that the target wafer does not have an offset; when the edge yield of each preset edge in the wafer map is greater than or equal to the corresponding yield threshold, and the distance between the center of the wafer map and the center of the target wafer is less than one half of the size of the chip, it is determined that the target wafer does not have an offset; determining that the target wafer has a misalignment when the distance between the center of the wafer map and the center of the target wafer is greater than or equal to one half of the size of the chip. determining that the target wafer has a misalignment when the distance between the center of the wafer map and the center of the target wafer is greater than or equal to one half of the size of the chip.

[0006] In one embodiment, the determination of whether the target wafer has a misalignment is based on the edge yield of each of the preset edges in the wafer map and the distance between the center of the wafer map and the center of the target wafer, and further comprises: alerting a staff member to perform an abnormality handling when it is determined that the target wafer has a misalignment.

[0007] In one embodiment, the preset edges include an upper edge, a lower edge, a left edge, a right edge, a top-left edge, a top-right edge, a bottom-left edge, and a bottom-right edge, and the yield threshold corresponding to different preset edges can be different.

[0008] In one embodiment, the testing of each chip on the target wafer by the testing device to obtain the wafer map of the target wafer further comprises: fixing the target wafer on a vacuum chuck of a probe station, identifying a notch or a flat feature of the target wafer by an auto-alignment system, positioning and calibrating the center of the target wafer, and establishing a rectangular coordinate system with the center of the target wafer as the origin; The calculation of the distance between the center of the wafer map and the center of the target wafer comprises: calculating the average of the coordinates of all chips in the wafer map as the center coordinate of the wafer map; calculating the distance between the center coordinate of the wafer map and the origin as the distance between the center of the wafer map and the center of the target wafer.

[0009] Based on the same inventive concept, a second aspect of the present application provides a wafer misalignment detection system, which comprises: a testing module for testing each chip on a target wafer by a testing device to obtain a wafer map of the target wafer; a first calculation module for calculating the edge yield of each of the preset edges in the wafer map; a second calculation module for calculating the distance between the center of the wafer map and the center of the target wafer; The offset determination module is configured to determine whether the target wafer has an offset based on edge yields of each preset edge in the wafer map and a distance between the center of the wafer map and the center of the target wafer.

[0010] In one embodiment, the offset determination module is configured to determine that the target wafer has no offset when the edge yield of at least one preset edge in the wafer map is less than a corresponding yield threshold and the distance between the center of the wafer map and the center of the target wafer is less than or equal to one fourth of the size of the chip. The offset determination module is configured to determine that the target wafer has no offset when the edge yield of each preset edge in the wafer map is greater than or equal to a corresponding yield threshold and the distance between the center of the wafer map and the center of the target wafer is less than one half of the size of the chip. The offset determination module is configured to determine that the target wafer has an offset when the edge yield of at least one preset edge in the wafer map is less than a corresponding yield threshold and the distance between the center of the wafer map and the center of the target wafer is greater than one fourth of the size of the chip and less than one half of the size of the chip. The offset determination module is configured to determine that the target wafer has an offset when the distance between the center of the wafer map and the center of the target wafer is greater than or equal to one half of the size of the chip. In one embodiment, the wafer offset detection device further comprises: The alarm module is configured to alarm and notify a staff to perform an abnormality treatment when it is determined that the target wafer has an offset.

[0011] Based on the same inventive concept, a third aspect of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the wafer offset detection method of the first aspect.

[0012] Based on the same inventive concept, a fourth aspect of the present application provides a non-transitory computer readable storage medium, which stores computer instructions for causing a computer to execute the wafer offset detection method of the first aspect.

[0013] As can be seen from the above, the wafer offset detection method provided in this application calculates the edge yield of each preset edge in the wafer diagram, calculates the distance between the center of the wafer diagram and the center of the target wafer, and combines the edge yield of each preset edge in the wafer diagram with the distance between the center of the wafer diagram and the center of the target wafer to determine whether the target wafer is offset. This method can accurately detect wafer offset and avoid misplacement and mixing of chips during chip picking. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A flowchart of a wafer offset detection method provided in an embodiment of this application; Figure 2 A schematic diagram showing a wafer offset to the right, provided for another embodiment of this application; Figure 3 A wafer pattern provided for another embodiment of this application; Figure 4 This is a schematic diagram of the center of the target wafer and the center of the wafer pattern provided in another embodiment of this application; Figure 5 This is a schematic diagram of a wafer offset detection system provided in another embodiment of this application; Figure 6 A schematic diagram of an electronic device provided in another embodiment of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0017] It should be noted that the technical terms or scientific terms used in the embodiments of the present application should be understood as the general meaning understood by those skilled in the art to which the embodiments of the present application belong, unless otherwise defined. The terms "first", "second" and the like used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. The terms "include" or "contain" and the like mean that the elements or objects before the terms cover the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may also change accordingly.

[0018] Referring to Figure 1 An embodiment of the present application provides a wafer offset detection method, which comprises the following steps: Step S10, testing each chip on the target wafer by using a test device to obtain a wafer map of the target wafer; Step S20, calculating the edge yield of each preset edge in the wafer map; wherein the edge yield of each preset edge is the ratio of the number of defective chips of the preset edge to the total number of chips of the preset edge.

[0019] Step S30, calculating the distance between the center of the wafer map and the center of the target wafer; Step S40, determining whether the target wafer has an offset in combination with the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer.

[0020] The wafer offset detection method provided by the embodiment can accurately detect wafer offset, avoid misplacement of picked chips and abnormal mixing of materials, by calculating the edge yield of each preset edge in the wafer map, calculating the distance between the center of the wafer map and the center of the target wafer, and determining whether the target wafer has an offset in combination with the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer.

[0021] Further, before step S10, the following steps are further included: Step S01, fixing the target wafer on a vacuum chuck of a probe station, identifying the notch or flat edge feature of the target wafer by an automatic alignment system, positioning and calibrating the center of the target wafer, and establishing a rectangular coordinate system with the center of the target wafer as the origin. At the same time, the signal calibration of the probe card needle tip and the automatic test equipment is completed.

[0022] Specifically, the step S10 comprises: the probe station generates the coordinates of each chip according to the wafer chip array parameters, drives the X / Y axis unit to move the probe card, so that the probe accurately contacts the chip test pads; then the automatic test equipment applies test signals to the chip according to the preset program, collects and analyzes the chip response data, judges whether the chip is a good product, a defective product or a marked invalid chip to be skipped, and synchronously records the coordinates of each valid chip in the rectangular coordinate system and the test results. After the whole wafer test is completed, the valid data is screened and verified, the chips are mapped according to the coordinates and are given different colors (such as green for good products and red for defective products) according to the test results, and finally a visual wafer map containing the wafer number, test time, chip distribution and state is generated.

[0023] In one embodiment, the step S40 of determining whether the target wafer exists offset by combining the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer comprises the following steps: The step S41 of determining that the target wafer does not exist offset when the edge yield of at least one preset edge in the wafer map is less than the corresponding yield threshold and the distance between the center of the wafer map and the center of the target wafer is less than or equal to one fourth of the size of the chip; The step S42 of determining that the target wafer does not exist offset when the edge yield of each preset edge in the wafer map is greater than or equal to the corresponding yield threshold and the distance between the center of the wafer map and the center of the target wafer is less than one half of the size of the chip; The step S43 of determining that the target wafer exists offset when the edge yield of at least one preset edge in the wafer map is less than the corresponding yield threshold and the distance between the center of the wafer map and the center of the target wafer is greater than one fourth of the size of the chip and less than one half of the size of the chip; The step S44 of determining that the target wafer exists offset when the distance between the center of the wafer map and the center of the target wafer is greater than or equal to one half of the size of the chip.

[0024] By combining the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer, whether the target wafer exists offset can be accurately detected, and the risk of misjudgment is reduced. The size of the chip is the length between the opposite corners of the chip.

[0025] In one embodiment, the step S40 of determining whether the target wafer exists offset by combining the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer further comprises the following steps: The step S50 of alarming to inform the staff to handle the abnormality when it is determined that the target wafer exists offset, so as to intervene artificially in time.

[0026] In one embodiment, the preset edges include: an upper edge, a lower edge, a left edge, a right edge, a left upper edge, a right upper edge, a left lower edge, and a right lower edge; wherein the yield threshold values corresponding to different preset edges can be different.

[0027] In this embodiment, the preset edges are divided into an upper edge, a lower edge, a left edge, a right edge, a left upper edge, a right upper edge, a left lower edge, and a right lower edge, so as to realize the calculation of the edge yield in 8 directions, and the yield threshold values corresponding to different preset edges can be different, thereby more accurately detecting whether the target wafer exists offset and reducing the risk of misjudgment.

[0028] Specifically, the yield threshold values corresponding to different preset edges can be determined according to historical data in the database, such as 80%, 85%, 90%, and the like. For example, the yield threshold value of the upper edge is 85%, and the yield threshold value of the left upper edge is 80%. In other embodiments, in order to facilitate calculation, the yield threshold values corresponding to different preset edges can be the same.

[0029] Referring to Figure 2 , a schematic diagram of the wafer offset to the right is shown. In this case, the wafer map obtained by testing is shown in Figure 3 . In which, the chips are endowed with different colors according to the test results, and the gray represents the good products, and the black represents the defective products. As can be seen from the figure, there are more defective products on the right edge.

[0030] In one embodiment, step S30 of calculating the distance between the center of the wafer map and the center of the target wafer includes the following steps: Step S31, calculating the average value of the coordinates of all chips in the wafer map as the center coordinates of the wafer map; Step S32, calculating the distance between the center coordinates of the wafer map and the origin as the distance between the center of the wafer map and the center of the target wafer.

[0031] Specifically, as can be known from the above description, when the wafer map is obtained in step S10, the coordinates of each chip in the rectangular coordinate system established with the center of the target wafer as the origin have been recorded. Therefore, here, the average value of the coordinates of all chips in the wafer map can be calculated as the center coordinates of the wafer map. Referring to Figure 4 , point A is the center of the target wafer, and point B is the center of the wafer map. The coordinates of point A are (0, 0), and the coordinates of point B are (x, y). Then the distance between the center of the wafer map and the center of the target wafer is .

[0032] It should be noted that the method of the embodiments of the present application can be executed by a single device, for example, a computer or a server, etc. The method of the embodiments can also be applied to a distributed scenario, and be completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only execute one or more steps in the method of the embodiments of the present application, and the multiple devices can interact with each other to complete the method.

[0033] It should be noted that some embodiments of the present application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0034] Based on the same inventive concept, the present application also provides a wafer offset detection system corresponding to the method of any of the above embodiments, which, as shown in Figure 5 The system comprises the following modules: A test module is configured to test each chip on the target wafer by using a test device to obtain a wafer map of the target wafer. Specifically, the target wafer is fixed on a vacuum chuck of a probe station, a notch or flat edge feature of the target wafer is identified by an auto-alignment system, the center of the target wafer is positioned and calibrated, and a rectangular coordinate system is established with the center of the target wafer as the origin.

[0035] A first calculation module is configured to calculate an edge yield of each preset edge in the wafer map, wherein the edge yield of each preset edge is a ratio of the number of defective chips of the preset edge to the total number of chips of the preset edge. Optionally, the preset edges include an upper edge, a lower edge, a left edge, a right edge, a top-left edge, a top-right edge, a bottom-left edge, and a bottom-right edge, wherein the yield threshold values corresponding to different preset edges can be different.

[0036] A second calculation module is configured to calculate a distance between the center of the wafer map and the center of the target wafer.

[0037] An offset determination module is configured to determine whether the target wafer has an offset in combination with the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer.

[0038] The wafer offset detection system provided in the embodiment can accurately detect wafer offset, and avoid misplacement and abnormal mixing of selected chips by calculating the edge yield of each preset edge in the wafer map, calculating the distance between the center of the wafer map and the center of the target wafer, and determining whether the target wafer is offset by combining the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer.

[0039] In one of the embodiments, the offset determination module is configured to determine that the target wafer is not offset when the edge yield of at least one preset edge in the wafer map is less than the corresponding yield threshold, and the distance between the center of the wafer map and the center of the target wafer is less than or equal to one fourth of the size of the chip. The offset determination module is configured to determine that the target wafer is not offset when the edge yield of each preset edge in the wafer map is greater than or equal to the corresponding yield threshold, and the distance between the center of the wafer map and the center of the target wafer is less than one half of the size of the chip. The offset determination module is configured to determine that the target wafer is offset when the edge yield of at least one preset edge in the wafer map is less than the corresponding yield threshold, and the distance between the center of the wafer map and the center of the target wafer is greater than one fourth of the size of the chip and less than one half of the size of the chip. The offset determination module is configured to determine that the target wafer is offset when the distance between the center of the wafer map and the center of the target wafer is greater than or equal to one half of the size of the chip. In one of the embodiments, the wafer offset detection system further comprises an alarm module configured to alarm and notify a worker to perform abnormal processing when it is determined that the target wafer is offset.

[0040] In one of the embodiments, the second calculation module comprises: A first calculation submodule configured to calculate the average value of the coordinates of all chips in the wafer map as the center coordinate of the wafer map. A second calculation submodule configured to calculate the distance between the center coordinate of the wafer map and the origin as the distance between the center of the wafer map and the center of the target wafer.

[0041] The wafer offset detection system in the embodiment has the beneficial effects of the method embodiments, which will not be described herein.

[0042] Based on the same inventive concept, the present application also provides an electronic device corresponding to any of the above-mentioned method embodiments, which comprises a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the processor implements the wafer offset detection method of any of the embodiments when executing the program.

[0043] Figure 6A more specific electronic device hardware structure schematic diagram provided by the embodiment is shown. The device can include a processor 1101, a memory 1102, an input / output interface 1103, a communication interface 1104, and a bus 1105. The processor 1101, the memory 1102, the input / output interface 1103, and the communication interface 1104 are connected to each other through the bus 1105 for internal communication.

[0044] The processor 1101 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits, etc., for executing related programs to implement the technical solutions provided by the embodiments of the present specification.

[0045] The memory 1102 can be implemented by a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, etc. The memory 1102 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present specification are implemented by software or firmware, the related program codes are stored in the memory 1102 and are called and executed by the processor 1101.

[0046] The input / output interface 1103 is used to connect input / output modules to realize information input and output. The input / output modules can be configured as components in the device (not shown in the figure) or can be externally connected to the device to provide corresponding functions. The input device can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device can include a display, a speaker, a vibrator, an indicator light, etc.

[0047] The communication interface 1104 is used to connect a communication module (not shown in the figure) to realize the communication interaction between the device and other devices. The communication module can realize communication through a wired manner (such as USB, network cable, etc.) or through a wireless manner (such as mobile network, WIFI, Bluetooth, etc.).

[0048] The bus 1105 includes a channel for transmitting information between various components (such as the processor 1101, the memory 1102, the input / output interface 1103, and the communication interface 1104) of the device.

[0049] It should be noted that although the above device only shows the processor 1101, the memory 1102, the input / output interface 1103, the communication interface 1104 and the bus 1105, but in the specific implementation process, the device can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above device can also only contain the components necessary to implement the scheme of the embodiments of the present application, and does not have to contain all the components shown in the figure.

[0050] The electronic device of the above embodiment is used to implement the wafer offset detection method corresponding to any of the preceding embodiments, and has the beneficial effects of the corresponding method embodiments, which are not described here.

[0051] Based on the same inventive concept, corresponding to any of the above method embodiments, the present application also provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to execute the wafer offset detection method of any of the above embodiments.

[0052] The computer readable medium of the present embodiment includes permanent and non-permanent, removable and non-removable media, which can be implemented by any method or technology to store information. The information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0053] The computer instructions stored in the storage medium of the above embodiment are used to cause the computer to execute the wafer offset detection method of any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which are not described here.

[0054] Those skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope (including claims) of the present application is limited to these examples; under the idea of the present application, the above embodiments or technical features in different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the embodiments of the present application as described above. In order to be brief, they are not provided in detail.

[0055] Additionally, to simplify the description and discussion, and so as not to obscure the embodiments of the application being presented, the well-known functions or constructions of integrated circuit (IC) chips and other components can or can not be shown in the figures and will be omitted as not to unnecessarily obscure the embodiments of the application being presented. Moreover, the apparatus can be shown in block diagram form in order to avoid obscuring the embodiments of the application, and this also acknowledges the fact that the details in regards to the implementation of such block diagram apparatus are highly dependent on the platform within which the application is to be implemented (i.e., such details should be well within the purview of one of ordinary skill in the art to consider given the specific application). Where specific details are set forth in order to describe an illustrative embodiment of the application, it will be apparent to one of ordinary skill in the art that the application can be practiced without, or with variations of, these specific details. Thus, the description is to be considered as illustrative and not restrictive, and the scope of the application should be determined not with reference to the above description, but should be given to the appended claims.

[0056] While the application has been described in connection with specific embodiments thereof, many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) can use the embodiments discussed.

[0057] Embodiments of the application are intended to cover all such alternatives, modifications and variations as falling within the scope of the appended claims. Accordingly, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principle of the embodiments of the application should be included in the scope of protection of the application.

Claims

1. A wafer offset detection method, characterized in that, include: Each chip on the target wafer is tested using testing equipment to obtain a wafer map of the target wafer; Calculate the edge yield of each preset edge in the wafer diagram; Calculate the distance between the center of the wafer pattern and the center of the target wafer; The edge yield of each preset edge in the wafer diagram and the distance between the center of the wafer diagram and the center of the target wafer are used to determine whether the target wafer has an offset.

2. The wafer offset detection method according to claim 1, characterized in that, Determining whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer image and the distance between the center of the wafer image and the center of the target wafer includes: When the edge yield of at least one preset edge in the wafer pattern is less than the corresponding yield threshold, and the distance between the center of the wafer pattern and the center of the target wafer is less than or equal to one-quarter of the chip size, it is determined that the target wafer has no offset. When the edge yield of each preset edge in the wafer diagram is greater than or equal to the corresponding yield threshold, and the distance between the center of the wafer diagram and the center of the target wafer is less than half the size of the chip, it is determined that the target wafer has no offset. When the edge yield of at least one preset edge in the wafer pattern is less than the corresponding yield threshold, and the distance between the center of the wafer pattern and the center of the target wafer is greater than one-quarter of the chip size and less than one-half of the chip size, it is determined that the target wafer has an offset. When the distance between the center of the wafer pattern and the center of the target wafer is greater than or equal to half the size of the chip, it is determined that the target wafer has an offset.

3. The wafer offset detection method according to claim 2, characterized in that, The method of determining whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer image and the distance between the center of the wafer image and the center of the target wafer, further includes: When it is determined that the target wafer is offset, an alarm is triggered to notify the staff to handle the anomaly.

4. The wafer offset detection method according to claim 2, characterized in that, The preset edges include: top edge, bottom edge, left edge, right edge, top left edge, top right edge, bottom left edge, and bottom right edge; wherein, the yield thresholds corresponding to different preset edges may be different.

5. The wafer offset detection method according to claim 1, characterized in that, The step of testing each chip on the target wafer using testing equipment to obtain a wafer map of the target wafer also includes: The target wafer is fixed on the vacuum chuck of the probe station. The notch or flat edge features of the target wafer are identified by the automatic alignment system. The center of the target wafer is located and calibrated. A rectangular coordinate system is established with the center of the target wafer as the origin. The calculation of the distance between the center of the wafer pattern and the center of the target wafer includes: Calculate the average of the coordinates of all chips in the wafer diagram, and use it as the center coordinate of the wafer diagram; Calculate the distance between the center coordinates of the wafer image and the origin, and use this distance as the distance between the center of the wafer image and the center of the target wafer.

6. A wafer offset detection system, characterized in that, include: The testing module is used to test each chip on the target wafer using testing equipment to obtain a wafer map of the target wafer; The first calculation module is used to calculate the edge yield of each preset edge in the wafer diagram; The second calculation module is used to calculate the distance between the center of the wafer pattern and the center of the target wafer; The offset determination module is used to determine whether the target wafer has an offset by combining the edge yield of each preset edge in the wafer map and the distance between the center of the wafer map and the center of the target wafer.

7. The wafer offset detection system according to claim 6, characterized in that, The offset determination module is used to determine that the target wafer has no offset when the edge yield of at least one preset edge in the wafer image is less than the corresponding yield threshold, and the distance between the center of the wafer image and the center of the target wafer is less than or equal to one-quarter of the size of the chip. The offset determination module is used to determine that the target wafer has no offset when the edge yield of each preset edge in the wafer diagram is greater than or equal to the corresponding yield threshold, and the distance between the center of the wafer diagram and the center of the target wafer is less than half the size of the chip. The offset determination module is used to determine that the target wafer has an offset when the edge yield of at least one preset edge in the wafer image is less than the corresponding yield threshold, and the distance between the center of the wafer image and the center of the target wafer is greater than one-quarter of the chip size and less than one-half of the chip size. The offset determination module is used to determine that the target wafer has an offset when the distance between the center of the wafer pattern and the center of the target wafer is greater than or equal to half the size of the chip.

8. The wafer offset detection system according to claim 6, characterized in that, Also includes: The alarm module is used to notify staff to handle the abnormality when it is determined that the target wafer is offset.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the wafer offset detection method as described in any one of claims 1 to 5.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the wafer offset detection method according to any one of claims 1 to 5.

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