Three-dimensional chip stacking power supply system and method based on power supply wafer

Abstract

The invention relates to the technical field of semiconductor packaging and chip power supply, in particular to a three-dimensional chip stacking power supply system and method based on a power wafer, and the system comprises an integrated power wafer, a calculation chip and a power peripheral device. A high-density capacitor array is integrated in the integrated power supply wafer, a rewiring layer is formed on the surface of the integrated power supply wafer, and a distributed voltage regulation module is configured; the computing chip is a known qualified chip and is inversely mounted on the rewiring layer through a micro bump / copper column, and a power supply bonding pad is directly connected with a power supply node; the power supply peripheral device is attached to the free area of the integrated power supply wafer or the same packaging substrate. The method comprises the steps of prefabrication of an integrated power supply wafer, flip mounting of a computing chip, bottom filling and integration with a packaging substrate. Through chip-wafer integration, the power supply path is shortened, resistance and noise are reduced, precision pipe and heterogeneous integration is achieved, the yield is increased, cost is reduced, bidirectional heat dissipation is achieved, and the power supply method is suitable for high-performance chip power supply.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging and chip power supply technology, and in particular to a three-dimensional chip stacking power supply system and method based on power wafers. Background Technology

[0002] As semiconductor processes advance to the nanoscale, the power density and transient current requirements of chips increase dramatically, posing a severe "power wall" challenge to traditional edge-powered packaging. In traditional packaging structures, power is introduced from solder balls at the package edge, transmitted through substrate wiring to power pads on the chip surface. This long power supply path leads to significant IR voltage drop (resistance voltage drop) and Ldi / dt noise (current variation noise caused by inductance). IR voltage drop causes the actual supply voltage in the chip's core area to be lower than the design value, affecting the chip's operating frequency; Ldi / dt noise interferes with signal transmission, leading to chip instability. Both factors together limit further improvements in chip performance.

[0003] To improve power supply performance, existing technologies attempt to integrate power supply networks on the front or back of the chip, such as fabricating metal wiring layers and capacitor structures on the back of the chip using wafer-level packaging processes. However, such solutions are still limited by the area of ​​the silicon wafer itself and process compatibility: on the one hand, chip area is prioritized for computing units, leaving limited space for the layout of the power supply network, making it impossible to integrate large-capacity capacitors and multiple voltage regulation modules; on the other hand, there is still a gap between the physical distance between the power supply network on the front / back of the chip and the computing units, making it difficult to provide independent and optimal power management for each computing unit (such as each CPU core), especially unsuitable for integration scenarios of heterogeneous chips such as CPU, GPU, and high-bandwidth memory (HBM).

[0004] Therefore, there is an urgent need for a new power supply architecture that can fundamentally shorten the power supply path, achieve refined power management, and at the same time take into account the flexibility, yield and cost of system integration, so as to meet the high-performance power supply requirements of nanoscale chips. Summary of the Invention

[0005] The purpose of this invention is to overcome the problems of the prior art and provide a three-dimensional chip stacking power supply system and method based on a power wafer. By flip-chip mounting the computing chip on a multi-functional integrated power wafer, an optimized balance between power supply performance and integration cost is achieved, solving the problems of long power supply paths, coarse power management, and low integration yield of traditional power supply methods.

[0006] The above objectives are achieved through the following technical solutions: A three-dimensional chip stacked power supply system and method based on a power wafer includes: An integrated power supply wafer, wherein a high-density capacitor array is integrated within the integrated power supply wafer, a high-density redistribution layer is formed on the surface of the integrated power supply wafer, and a distributed voltage regulation module is also configured on the integrated power supply wafer; At least one computing chip, which is a known qualified chip that has been tested, is mounted on the redistribution layer of the integrated power wafer via a flip-chip interconnect structure, and the power pads of the computing chip are directly connected to the power supply nodes on the integrated power wafer via the flip-chip interconnect structure. Power peripheral devices are mounted on an unoccupied area of ​​the integrated power wafer that is not occupied by the computing chip, or are integrated on the same package substrate as the integrated power wafer; wherein the integrated power wafer supplies power to the computing chip through its internal power supply network, the power supply network including the high-density capacitor array, the distributed voltage regulation module and the redistribution layer.

[0007] As a further optimization of this system, the flip-chip interconnect structure is a microbump, copper pillar, or a thermo-press bonding structure using a non-conductive thin film.

[0008] As a further optimization of this system, the distributed voltage regulation module is mounted on the integrated power wafer in the form of a chip, or is directly integrated into the integrated power wafer during the manufacturing process of the integrated power wafer. The output terminal of the distributed voltage regulation module is connected to the power pad of the computing chip through the metal wiring of the redistribution layer.

[0009] As a further optimization of this system, the location of the distributed voltage regulation module on the integrated power wafer corresponds one-to-one with the high-power functional areas (including but not limited to the core area) on the computing chip in the vertical direction.

[0010] As a further optimization of this system, the high-density capacitor array is a deep trench capacitor array or a metal-insulator-metal (MIM) capacitor array. The high-density capacitor array serves as a decoupling unit and energy storage unit for the power supply network, and is used to reduce power supply noise.

[0011] A method for manufacturing the above-mentioned three-dimensional chip stacked power supply system based on a power wafer includes the following steps: S1: Provide an integrated power supply wafer, wherein the integrated power supply wafer has pre-fabricated a high-density capacitor array, a distributed voltage regulation module and a high-density redistribution layer, and the redistribution layer has formed interconnect nodes for connecting computing chips. S2: Test and screen the computing chip to obtain known qualified chips, and mount the known qualified chips onto the redistribution layer of the integrated power wafer through flip chip process, so that the power pads of the computing chip are connected to the power supply nodes of the redistribution layer. S3: Perform a bottom filling process at the gap between the computing chip and the integrated power wafer to fill with insulating material to enhance the mechanical reliability of the interconnect structure; S4: Integrate the integrated power wafer with the completed computing chip mounting to the packaging substrate, and achieve electrical connection between the integrated power wafer and the packaging substrate through solder balls or metal pillars to complete the system packaging.

[0012] As a further optimization of this method, the fabrication of the integrated power wafer in step S1 also includes forming through-silicon vias (TSVs) inside it, which are used for the downward conduction of heat from the subsequent computing chip.

[0013] As a further optimization of this method, the flip chip process in step S2 is a microbump bonding process, a copper pillar bonding process, or a non-conductive thin film thermo-press bonding process, in order to shorten the power supply path.

[0014] As a further optimization of this method, the insulating material used for bottom filling in step S3 is epoxy resin-based bottom filler, which is cured by a thermosetting process after filling.

[0015] As a further optimization of this method, the integration of the integrated power wafer and the packaging substrate in step S4 also includes setting a heat dissipation cover on the back of the packaging substrate. The heat dissipation cover is attached to the packaging substrate by thermal grease to form a heat dissipation path with the back of the computing chip facing upward, which together with the heat dissipation path with the through silicon via facing downward constitutes a bidirectional heat dissipation structure.

[0016] This invention provides a three-dimensional chip stacking power supply system and method based on a power wafer. By flip-chip mounting computing chips onto an integrated power wafer, the power supply path is shortened, reducing power supply impedance and noise, and ensuring a clean and stable power supply. Integration with "known qualified chips" avoids the risk of wafer scrap, improving yield and reducing costs. The power wafer supports heterogeneous chip integration, enabling flexible system integration. A bidirectional heat dissipation path improves chip thermal stability, adapting to high-performance computing requirements. Compared with existing technologies, the specific beneficial effects are as follows: 1. High-performance power supply: The power supply path is shortened from the long distance of traditional edge power supply to a short distance, and the power supply impedance (including resistance and inductance) is significantly reduced, effectively reducing IR voltage drop and Ldi / dt noise, providing a cleaner and more stable power supply for computing chips, enabling the chips to operate stably at higher frequencies.

[0017] 2. High integration and flexibility: Supports heterogeneous integration of chips with different process nodes and functions (CPU, GPU, HBM, dedicated ASIC) to achieve chip-level system integration; no need to redesign the overall chip, just select different chips according to the requirements and mount them on the integrated power wafer, shortening the product development cycle and reducing R&D costs.

[0018] 3. Improved yield and cost-effectiveness: Using known qualified chips for integration avoids the risk of scrapping the entire wafer due to the failure of a single chip in traditional wafer-to-wafer bonding; at the same time, integrated power wafers can be prefabricated in batches, and calculated chips can be mounted on demand, reducing the fixed cost of a single production run and making it suitable for large-scale mass production.

[0019] 4. Efficient Heat Dissipation Path: The heat generated by the computing chip can be dissipated through two paths: one is a downward path, conducted through the TSV within the integrated power wafer to the packaging substrate, and then transferred through the substrate to the heat sink; the other is an upward path, directly transferred through the back of the computing chip to the top heat sink. This bidirectional heat dissipation lowers the chip's junction temperature, preventing performance throttling and shortened lifespan due to high temperatures, and improving the long-term reliability of the system. Attached Figure Description

[0020] Figure 1 This is a schematic cross-sectional view of the structure of a three-dimensional chip stacking power supply system based on a power wafer, as described in this invention. Figure 2 This is a top view of the layout of the top redistribution layer and distributed power supply nodes of the integrated power wafer in a three-dimensional chip stacked power supply system based on a power wafer, as described in this invention. Figure 3 This is a partially enlarged view of the interconnection between the computing chip and the power wafer via microbumps in a three-dimensional chip stacking power supply system based on a power wafer, as described in this invention. Figure 4 This is a schematic diagram of an embodiment of a three-dimensional chip stacking power supply system based on a power wafer, according to the present invention, in which multiple computing chips and high-bandwidth memory chips are mounted together on the same power wafer. Detailed Implementation

[0021] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The described embodiments are merely some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This solution provides a three-dimensional chip stacked power supply system based on a power wafer. This system uses an integrated power wafer as the core power supply carrier, and, in conjunction with computing chips, peripheral power devices, and interconnect structures, forms a complete three-dimensional stacked power supply architecture. The detailed structure and connection relationships of each component are as follows: like Figure 1 and Figure 2 As shown, the integrated power supply wafer serves as the core carrier and power supply platform of the system, and its functional and structural design is as follows: Core components of the power supply network: The integrated power supply wafer has a high-density capacitor array integrated inside or on its surface. The capacitor array is a deep trench capacitor or a metal-insulator-metal (MIM) capacitor array, which is used as a decoupling unit (to suppress power supply noise) and an energy storage unit (to meet transient current requirements) of the power supply network. Distributed Voltage Regulator (VRM): The VRM has two integration methods: one is to mount it on the surface of the integrated power wafer as an independent chip, and the other is to integrate it directly into the wafer during the manufacturing process of the integrated power wafer; the number of the distributed voltage regulator modules matches the number of high-power areas of the computing chip, and the position of the distributed voltage regulator modules on the integrated power wafer corresponds one-to-one with the high-power areas (such as the core area) of the computing chip above (i.e., spatial alignment) in the vertical direction, ensuring that the voltage regulation signal can be transmitted to the high-power area through the shortest path; High-density redistribution layer: Located on top of the integrated power wafer, it is fabricated using wafer-level redistribution technology and contains fine metal wiring. The functions of this redistribution layer include: distributing the VRM output voltage to various interconnect nodes, connecting the capacitor array inside the integrated power wafer to the power pads of the computing chip, and providing electrical connection interfaces for peripheral power devices, such as… Figure 2 As shown, the metal wiring of the redistribution layer is distributed in a grid pattern, and each power supply node corresponds to a power pad of the computing chip.

[0023] In this embodiment, the number of computing chips is one or more, all of which are known and qualified chips that have undergone electrical testing, to avoid the entire system being scrapped due to chip failure. The computing chips are mounted on the redistribution layer of the integrated power wafer via a flip-chip interconnect structure, such as... Figure 3 As shown in the figure, microbumps are visible on the bottom of the computing chip. The bottom of the microbumps is in direct contact with the metal contacts of the redistribution layer on the integrated power wafer. A non-conductive thin film fills the space between the microbumps and the redistribution layer. The gap between the computing chip and the integrated power wafer will be filled with underfill adhesive later. Specific interconnection methods include: Interconnection structure types: microbumps, copper pillars, or thermo-pressed bonding structures using non-conductive thin films; Electrical connection path: The power pads of the computing chip are directly connected to the power supply nodes of the integrated power wafer redistribution layer through the above interconnection structure, which greatly shortens the power supply path, much shorter than the traditional edge power supply path; in addition, the signal pads of the computing chip can also achieve signal interaction with the packaging substrate or other chips (such as HBM chips) through the redistribution layer.

[0024] The power supply peripheral devices described in this embodiment include power inductors (for energy conversion in the VRM), large-capacity capacitors (for supplementary energy storage), and power management chips (PMICs), etc., and their integration methods are divided into two types: Direct mounting: Components such as power inductors and large-capacity capacitors are directly mounted on the top of the integrated power supply wafer in unused areas not occupied by computing chips. Figure 1 As shown in the figure, peripheral devices are mounted on both sides of the integrated power supply wafer, which do not interfere with the computing chip in the middle. Substrate integration: such as small power management chips, which are integrated on the same packaging substrate as the integrated power wafer, and are connected to the redistribution layer of the integrated power wafer through the wiring of the packaging substrate.

[0025] This system supports heterogeneous integration of chips with different functions and process nodes. For example, CPU chips, GPU chips, and high-bandwidth memory chips can be simultaneously mounted on the same integrated power wafer. Figure 4 As shown in the figure, two computing chips (such as CPU chips) and one HBM chip are mounted on the integrated power wafer. The HBM chip is located between the two computing chips. All three are connected to the redistribution layer through microbumps. The metal wiring of the redistribution layer enables signal interaction and unified power supply between the computing chips and the HBM chip.

[0026] This solution also provides a method for manufacturing the aforementioned three-dimensional chip stacked power supply system based on a power wafer. This method is based on existing semiconductor manufacturing processes and specifically includes the following steps: Step S1: Pre-fabrication of integrated power supply wafers Wafer substrate selection: Standard-sized silicon wafers are used as the substrate; Capacitor array manufacturing: Deep trenches are formed inside a silicon wafer by deep trench etching, and then filled with dielectric and electrode materials to form a deep trench capacitor array; or a metal-insulator-metal structure is deposited on the wafer surface by sputtering to form a MIM capacitor array. Distributed VRM integration: If a surface mount method is used, the VRM chip is mounted to a preset position (corresponding to the high-power area of ​​the subsequent computing chip) on the wafer surface using solder paste printing; if a direct integration method is used, the power transistors, control circuits and other components of the VRM are fabricated inside the wafer using CMOS technology. Redistribution layer fabrication: A high-density redistribution layer is formed on the top of the wafer using photolithography, sputtering, and electroplating processes. After the redistribution is completed, a passivation layer is fabricated, and contact windows for interconnection are opened on the passivation layer. Through-Silicon Via (TSV) fabrication (optional): Through-silicon vias are formed inside the wafer through deep hole drilling and electroplating processes for subsequent heat dissipation and electrical connection. The inner wall of the TSV is covered with an insulating layer and a barrier layer, and the interior is filled with conductive material.

[0027] Step S2: Flip-chip mounting of the computing chip Computing chip screening: Electrical tests (including functional tests, performance tests, and reliability tests) are performed on the computing chips after wafer dicing to screen out known qualified chips (KGD). Flip-chip process implementation: Apply flux or mount a non-conductive film at the redistribution layer contact window of the integrated power wafer, and then align the microbumps / copper pillars of the computing chip with the contacts of the redistribution layer using flip-chip bonding equipment, and apply pressure and temperature to bond them. Interconnect quality inspection: The void ratio of the interconnect structure is detected by X-ray inspection and ultrasonic scanning to ensure interconnect quality.

[0028] Step S3: Bottom Filling Process Filler material selection: Epoxy resin-based bottom filler is used, whose coefficient of thermal expansion matches that of the chip and wafer; Filling and curing: The bottom filler adhesive is injected into the gap between the computing chip and the integrated power wafer using a dispensing device, ensuring that the adhesive is completely filled without air bubbles; then the entire structure is placed in an oven for heat curing, which forms mechanical support after curing, improving the impact resistance and thermal cycling resistance of the interconnect structure.

[0029] Step S4: Integration with the packaging substrate Pre-treatment of packaging substrate: Select organic substrate or ceramic substrate, and fabricate wiring layers and pads on the substrate surface; Integrated power supply wafer mounting: Solder paste is printed on the pads of the packaging substrate. The integrated power supply wafer with the computing chip mounted is placed on the packaging substrate by a pick-and-place machine, so that the bottom solder balls (or copper pillars) of the integrated power supply wafer are aligned with the pads of the packaging substrate. Reflow soldering: The entire structure is placed in a reflow oven and soldered according to a preset temperature profile to achieve electrical connection between the integrated power supply wafer and the packaging substrate. Heat dissipation structure assembly (optional): Apply thermal grease to the back of the packaging substrate, attach and fix the metal heat sink to form a heat dissipation path with the back of the chip facing upward; at the same time, the TSV inside the integrated power wafer can conduct the heat generated by the computing chip to the packaging substrate, forming bidirectional heat dissipation.

[0030] The above description is merely illustrative of the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A three-dimensional chip stacking power supply system based on a power wafer, characterized in that, include: An integrated power supply wafer, wherein a high-density capacitor array is integrated within the integrated power supply wafer, a high-density redistribution layer is formed on the surface of the integrated power supply wafer, and a distributed voltage regulation module is also configured on the integrated power supply wafer; At least one computing chip, which is a known qualified chip that has been tested, is mounted on the redistribution layer of the integrated power wafer via a flip-chip interconnect structure, and the power pads of the computing chip are directly connected to the power supply nodes on the integrated power wafer via the flip-chip interconnect structure. Power peripheral devices are mounted on an unoccupied area of ​​the integrated power wafer that is not occupied by the computing chip, or are integrated on the same package substrate as the integrated power wafer; wherein the integrated power wafer supplies power to the computing chip through its internal power supply network, the power supply network including the high-density capacitor array, the distributed voltage regulation module and the redistribution layer.

2. The three-dimensional chip stacking power supply system based on a power wafer according to claim 1, characterized in that, The flip-chip interconnect structure is a microbump, copper pillar, or a thermo-pressed bonding structure using a non-conductive thin film.

3. The three-dimensional chip stacking power supply system based on a power wafer according to claim 1, characterized in that, The distributed voltage regulation module is mounted on the integrated power wafer in the form of a chip, or is directly integrated into the integrated power wafer during the manufacturing process of the integrated power wafer. The output terminal of the distributed voltage regulation module is connected to the power pad of the computing chip through the metal wiring of the redistribution layer.

4. The three-dimensional chip stacking power supply system based on a power wafer according to claim 3, characterized in that, The location of the distributed voltage regulation module on the integrated power wafer corresponds one-to-one with the high-power functional area on the computing chip in the vertical direction.

5. A three-dimensional chip stacking power supply system based on a power wafer according to claim 1, characterized in that, The high-density capacitor array is a deep trench capacitor array or a metal-insulator-metal capacitor array. The high-density capacitor array serves as a decoupling unit and energy storage unit for the power supply network, and is used to reduce power supply noise.

6. A method for manufacturing a three-dimensional chip stacked power supply system based on a power wafer as described in any one of claims 1-5, characterized in that, Includes the following steps: S1: Provide an integrated power supply wafer, wherein the integrated power supply wafer has pre-fabricated a high-density capacitor array, a distributed voltage regulation module and a high-density redistribution layer, and the redistribution layer has formed interconnect nodes for connecting computing chips. S2: Test and screen the computing chip to obtain known qualified chips, and mount the known qualified chips onto the redistribution layer of the integrated power wafer through flip chip process, so that the power pads of the computing chip are connected to the power supply nodes of the redistribution layer. S3: Perform a bottom filling process at the gap between the computing chip and the integrated power wafer to fill with insulating material to enhance the mechanical reliability of the interconnect structure; S4: Integrate the integrated power wafer with the completed computing chip mounting to the packaging substrate, and achieve electrical connection between the integrated power wafer and the packaging substrate through solder balls or metal pillars to complete the system packaging.

7. A three-dimensional chip stacking power supply system based on a power wafer according to claim 6, characterized in that, The manufacturing of the integrated power wafer in step S1 also includes forming through-silicon vias (TSVs) inside it, which are used for the downward conduction of heat from the subsequent computing chip.

8. A three-dimensional chip stacking power supply system based on a power wafer according to claim 6, characterized in that, The flip-chip process in step S2 is a microbump bonding process, a copper pillar bonding process, or a non-conductive thin film thermo-press bonding process, in order to shorten the power supply path.

9. A three-dimensional chip stacking power supply system and method based on a power wafer according to claim 6, characterized in that, In step S3, the insulating material used for bottom filling is epoxy resin-based bottom filler, which is cured by a thermosetting process after filling.

10. A three-dimensional chip stacking power supply system and method based on a power wafer according to claim 6, characterized in that, The integration of the integrated power supply wafer and the packaging substrate in step S4 also includes setting a heat dissipation cover on the back of the packaging substrate. The heat dissipation cover is attached to the packaging substrate by thermal grease to form a heat dissipation path with the back of the computing chip facing upward, which together with the heat dissipation path with the through silicon via downward constitutes a bidirectional heat dissipation structure.

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