Manufacturing method of 3D packaging structure of optical engine module and CPO module

Abstract

The invention provides a manufacturing method of a 3D packaging structure of an optical engine module and a CPO module, and relates to the technical field of semiconductor packaging. Firstly, an optical chip wafer is provided, then an electric chip and an optical port protection piece are mounted on the basis of the surface of the optical chip wafer, plastic packaging is carried out on the basis of the upper portion of the optical chip wafer, the electric chip and the optical port protection piece are wrapped by plastic packaging materials, and then the plastic packaging materials are thinned until the optical chip and the optical port protection piece are exposed; the method comprises the following steps: manufacturing a TSV through hole on the basis of an optical chip wafer, thinning the bottom surface of the optical chip wafer until the TSV through hole is exposed, manufacturing an RDL layer and a solder ball on the basis of the bottom surface of the optical chip wafer, connecting the RDL layer with the TSV through hole, removing an optical port protection piece, and finally cutting the optical chip wafer to form a single optical engine module. According to the scheme provided by the invention, the optical chip is prevented from being damaged in the packaging process, and the design flexibility of the optical port is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and more specifically, to a method for fabricating a 3D packaging structure for a light engine module and a CPO module. Background Technology

[0002] For server applications, to reduce high-speed electrical signal attenuation and transmission latency, it is desirable to place the high-speed electrical signals of the optical transceiver module as close as possible to the ASIC, GPU, or switch chip. One way to achieve this is to develop and implement co-package optics (CPO) systems by mounting transceiver optics components next to these chips. CPO technology effectively reduces signal attenuation and latency by packaging optical and electrical chips together.

[0003] There are various stacking methods when optical and electrical chips are packaged together, and companies in the industry often choose the appropriate stacking method based on their own process platforms and product performance requirements. Due to the complexity of optical chip functions and internal structures, and the fact that they often employ mature, high-linewidth semiconductor processes, optical chips are generally larger than electrical chips. When the two chips are stacked together, a structure with the optical chip at the bottom and the electrical chip on top is more stable and easier to implement. A relevant packaging structure is shown in the comparative document CN202511465947.4.

[0004] In this type of structure, the optical chip needs to use a TSV (Through Silicon Via) via structure to achieve signal uplink and downlink transmission. The TSV via structure requires a reduction in the thickness of the optical chip (typically around 100µm), which results in a larger length and width but a thinner thickness, making the chip prone to cracking during packaging and subsequent operation. Additionally, optical port contamination is likely to occur during packaging. Summary of the Invention

[0005] The purpose of this application is to provide a 3D packaging structure fabrication method and CPO module for an optical engine module, so as to solve the problems of avoiding chip cracking and optical port contamination during the packaging process.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a method for fabricating a 3D packaging structure for a light engine module, the method comprising: An optical chip wafer is provided, wherein an optical port is provided on the surface of the optical chip wafer, and a TSV via is provided inside the optical chip wafer; The optical chip wafer is based on an electrical chip and an optical port protection component mounted on it; wherein the electrical chip is located in the non-overlapping area of ​​the optical port, and the optical port protection component is located in the overlapping area of ​​the optical port and blocks the optical port; The optical chip wafer is encapsulated in plastic, and the plastic encapsulation material encapsulates the electrical chip and the optical port protection component. The molding compound is thinned until the optical chip and the optical port protection component are exposed. The bottom surface of the optical chip wafer is thinned until the TSV via is exposed; An RDL layer and solder balls are fabricated on the bottom surface of the optical chip wafer, wherein the RDL layer is connected to the TSV via. Remove the optical port protection component; The optical chip wafer is diced to form a single optical engine module.

[0007] Optionally, the step of mounting an electrical chip and an optical port protection component on the surface of the optical chip wafer includes: Electrical chips are mounted on the surface of the optical chip wafer by soldering or hybrid bonding.

[0008] Optionally, the step of mounting an electrical chip and an optical port protection component on the surface of the optical chip wafer includes: Adhesive is applied to the location of the optical port; wherein, the adhesive can be removed by heating, ultraviolet light irradiation, or laser irradiation; The optical port protective component is mounted on the surface of the adhesive.

[0009] Optionally, the light port protection element is a light-transmitting protection element.

[0010] Optionally, prior to the molding and encapsulation step on top of the optical chip wafer, the method further includes: When the optical chip is mounted using a solder joint mounting method, underfilling is performed based on the underside of the electrical chip.

[0011] Optionally, the step of thinning the bottom surface of the optical chip wafer until the TSV via is exposed includes: The bottom surface of the optical chip wafer is initially ground until it is close to the lower end of the TSV via. The substrate is etched on the bottom surface of the optical chip wafer, and a passivation layer is deposited. The bottom surface of the optical chip wafer is CMP polished to expose the TSV vias.

[0012] Optionally, the step of fabricating an RDL layer and solder balls based on the bottom surface of the optical chip wafer includes: An RDL layer and solder balls are fabricated on the bottom surface of the optical chip wafer, away from the orthogonal projection area of ​​the optical port.

[0013] Optionally, the optical port protection component is attached to the surface of the optical chip wafer using adhesive, and the step of removing the optical port protection component includes: The adhesiveness is removed by heating, ultraviolet light irradiation, or laser irradiation; Remove the optical port protective component; Clean the optical port area with detergent and deionized water; After drying and heating the optical port area, the optical port area is then subjected to deionized air blowing and plasma cleaning.

[0014] Optionally, after the step of dicing the optical chip wafer to form a single optical engine module, the method further includes: The individual optical engine modules are mounted onto the target carrier board; Optical coupling is performed based on the position of the optical port.

[0015] On the other hand, this application embodiment also provides a CPO module, the CPO module including a target substrate and a light engine module manufactured as described above, the light engine module being mounted on the target substrate.

[0016] Compared with the prior art, this application has the following advantages: This application provides a 3D packaging structure fabrication method and CPO module for an optical engine module. First, an optical chip wafer is provided, wherein an optical port is provided on the surface of the optical chip wafer, and a TSV via is provided inside the optical chip wafer. Next, an electrical chip and an optical port protection component are mounted on the surface of the optical chip wafer; wherein the electrical chip is located in the non-overlapping area of ​​the optical port, and the optical port protection component is located in the overlapping area of ​​the optical port and blocks the optical port. Then, a molding compound is applied to the top of the optical chip wafer, encapsulating the electrical chip and the optical port protection component. The molding compound is then thinned until the optical chip and the optical port protection component are exposed. Next, the bottom surface of the optical chip wafer is thinned until the TSV via is exposed. Then, an RDL layer and solder balls are fabricated on the bottom surface of the optical chip wafer, wherein the RDL layer is connected to the TSV via. Next, the optical port protection component is removed. Finally, the optical chip wafer is diced to form a single optical engine module.

[0017] On the one hand, by encapsulating the optical and electrical chips together with molding compound, a robust and integrated module is formed. When mounting the module onto the target substrate, the object of the operation is the entire module, not the fragile thin optical chip, effectively preventing chip breakage and improving the product's mechanical reliability over long-term use. On the other hand, the use of a protective element for the optical port ensures that the molding compound only covers the outer edge of the protective element and cannot access the port itself. Furthermore, the protective element can be directly removed later without exposing the port through cutting, allowing for greater flexibility in optical port design.

[0018] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 An exemplary flowchart illustrating the method for fabricating a 3D packaging structure of a light engine module provided in this application embodiment.

[0021] Figure 2 This is a cross-sectional schematic diagram of the optical chip wafer provided in an embodiment of this application.

[0022] Figure 3 This is a cross-sectional schematic diagram corresponding to S104 provided in the embodiments of this application.

[0023] Figure 4 This is a cross-sectional schematic diagram corresponding to S106 provided in the embodiments of this application.

[0024] Figure 5 This is a cross-sectional schematic diagram corresponding to S108 provided in the embodiments of this application.

[0025] Figure 6 This is a cross-sectional schematic diagram corresponding to S110 provided in the embodiments of this application.

[0026] Figure 7 This is a cross-sectional schematic diagram corresponding to S112 provided in the embodiments of this application.

[0027] Figure 8 This is another cross-sectional schematic diagram corresponding to S112 provided in the embodiment of this application.

[0028] Figure 9This is a cross-sectional schematic diagram of one of the CPO modules provided in the embodiments of this application.

[0029] Figure 10 This is another cross-sectional schematic diagram of the CPO module provided in the embodiments of this application.

[0030] In the picture: 110 - Optical chip wafer; 120 - Optical port; 130 - TSV via; 140 - Electrical chip; 150 - Optical port protection component; 160 - Molding compound; 170 - Underfill layer; 180 - Target carrier. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0033] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0034] It should be noted that in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0035] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0036] As described in the background section, currently, during CPO module packaging, the optical chip is prone to cracking.

[0037] In view of this, in order to solve the above problems, this application provides a method for fabricating a 3D packaging structure of an optical engine module. This method involves mounting an electrical chip 140 onto the surface of an optical chip, with the upper surface of the optical chip covered by a molding compound 160, and providing an optical port protection component 150 in the optical port 120 area. This achieves mechanical reinforcement of the optical chip and electrical chip 140 while cleverly reserving a clean channel for the optical port 120 using the removable optical port protection component 150. This solves the technical problems of the fragility of ultra-thin, large-size optical chips in packaging and application, and the susceptibility of the optical port 120 to contamination.

[0038] The following is an exemplary description of the 3D encapsulation structure fabrication method for the light engine module provided in this application. For one implementation method, please refer to [link / reference needed]. Figure 1 The method includes: S102 provides an optical chip wafer, wherein the surface of the optical chip wafer is provided with an optical port, and the interior of the optical chip wafer is provided with a TSV via.

[0039] S104 is based on mounting an electrical chip and an optical port protection component on the surface of an optical chip wafer; wherein the electrical chip is located in the non-overlapping area of ​​the optical port, and the optical port protection component is located in the overlapping area of ​​the optical port and blocks the optical port.

[0040] S106 is based on the top of the optical chip wafer being molded, and the molding compound encapsulates the electrical chip and the optical port protection component.

[0041] S108, thins the molding compound until the optical chip and optical port protection components are exposed.

[0042] S. Thin the bottom surface of the optical chip wafer until the TSV via is exposed.

[0043] S112, an RDL layer and solder balls are fabricated on the bottom surface of the optical chip wafer, wherein the RDL layer is connected to the TSV via.

[0044] S114, Remove the optical port protection component.

[0045] S116 cuts the optical chip wafer to form a single optical engine module.

[0046] like Figure 2 As shown, a PIC wafer 110 is first provided. Multiple optical chip units are fabricated on this wafer, arranged in an array (only one optical chip unit is shown in the figure). For each optical chip unit, a specific area on its top surface is provided with an optical port 120 for optical signal coupling. Simultaneously, through-silicon vias (TSVs) have been fabricated inside the optical chip to transmit electrical signals from the top surface to the bottom surface. Naturally, a wiring layer is provided on the top surface of the optical chip, which will not be elaborated here.

[0047] For example, the wafer can be a silicon-based optoelectronic chip or an optoelectronic chip wafer 110 made of other compound semiconductor materials (such as InP, GaAs). The optical port 120 region is a specific area on the top surface of the wafer (i.e., the same side as the subsequent mounting of the electrical chip 140), where an optical port 120 for optical signal input / output is predefined and fabricated. This optical port 120 can be a grating coupler or an end-face coupler structure. For example, in this embodiment, the optical port 120 is designed as a grating coupler, located in a non-edge region of the chip, providing greater flexibility for subsequent optical path design. Through-Silicon Vias (TSVs) structures are fabricated inside the optoelectronic chip wafer 110 for vertical electrical interconnection. These TSVs are located on a silicon substrate, vertically leading the electrical signal connection points (e.g., pads for connecting the electrical chip 140) from the top surface of the optoelectronic chip to the bottom surface of the chip.

[0048] It should be noted that the thickness of the optical chip wafer 110 at this time is usually a standard thickness (e.g., 750 micrometers) to facilitate front-end process operations. Furthermore, the depth of the TSV via 130 is less than the thickness of the wafer; for example, the depth of the TSV via 130 is 50-100 micrometers, corresponding to the final thinned chip thickness. Copper is used as the conductive material inside the TSV via 130.

[0049] Subsequently, an electrical chip 140 and an optical port protection component 150 are mounted on the surface of the optical chip wafer 110. In this process, the mounting of active devices (electrical chip 140) and passive protection structures (protection components) are processed in parallel.

[0050] refer to Figure 3 When mounting the electrical chip 140 on the optical chip wafer 110, firstly, the electrical chip 140 is mounted to the predetermined position on each unit of the optical chip wafer 110 using a high-precision flip-chip bonding device. Before mounting, the corresponding pads on the optical chip wafer 110 and the bumps on the electrical chip 140 need to be aligned. Current mounting methods can include ball bonding and a hybrid die-to-wafer bonding method. When using solder ball soldering, microbumps, such as copper pillars, solder caps, or solder balls, are pre-fabricated on the pads of the electrical chip 140. During mounting, with the aid of flux, the electrical chip 140 is aligned and placed on the optical chip wafer 110, followed by reflow soldering. The reflow soldering temperature depends on the solder composition and will not be elaborated here. It should be noted that when using solder ball soldering, a raised connection is actually formed between the electrical chip 140 and the optical chip.

[0051] When using hybrid bonding, both the optical chip and the electrical chip 140 require highly flat chemical mechanical polishing to form embedded metal pads. During mounting, precise alignment and pre-bonding are performed at room temperature, followed by a high-temperature annealing process to allow thermal diffusion at the interface, achieving metal bonding while the dielectric layer also undergoes fusion bonding. This approach eliminates the need for solder and underfill, resulting in an extremely thin interconnect layer and improved thermal conductivity. It should be noted that when using hybrid bonding, a direct, bump-free connection is actually formed between the electrical chip 140 and the optical chip.

[0052] Furthermore, since the optical port 120 area of ​​the optical chip needs to be reserved for subsequent optical signals to pass through, it cannot be blocked by the electrical chip 140. Therefore, when mounting the electrical chip 140, it must be ensured that the coverage area of ​​the electrical chip 140 does not overlap with the optical port 120 area.

[0053] Next, a special adhesive is applied to the area of ​​the optical port 120, and then the optical port protective component 150 is attached to the adhesive to completely cover the optical port 120. In this embodiment, the optical port protective component 150 is a light-transmitting protective component, and the material used to manufacture the optical port protective component 150 includes silicon dioxide, silicon, or silicon nitride, etc., and is not limited thereto. Furthermore, this application does not limit the shape of the optical port protective component 150; it can be a cube, a semi-cone, or other shapes. The adhesive is a material whose stickiness can be removed by heating, ultraviolet light irradiation, or laser irradiation.

[0054] Furthermore, during the application of the adhesive, a layer of adhesive with controllable thickness is applied to the optical port 120 area of ​​the optical chip wafer 110 using a precision dispensing or spraying process. The adhesive used in this embodiment is a special photosensitive or heat-sensitive adhesive that can undergo a chemical change under specific conditions (such as ultraviolet light irradiation, heating, or laser irradiation of a specific wavelength), thereby losing its adhesiveness. The dispensing thickness needs to be precisely controlled; too thin a layer may result in inadequate coverage of the protective component, while too thick a layer may overflow the optical port 120 area or affect subsequent molding.

[0055] When mounting the optical port protector 150, the pre-prepared optical port protector 150 is picked up and placed directly above the optical port 120 coated with adhesive. The size of the protector should be slightly larger than the area of ​​the optical port 120 to ensure complete coverage. During mounting, a certain pressure and temperature (e.g., 50℃-80℃) are applied to allow the adhesive to flow and fill the tiny gaps between the protector and the chip surface, ensuring a tight fit between the protector and the chip surface and preventing subsequent molding compound 160 from seeping in.

[0056] It should be noted that the material of the optical port protective component 150 is preferably the same as the wavelength used for subsequent optical coupling, such as fused silica (silicon dioxide), silicon, silicon nitride, or glass. The advantage of using a transparent material is that even if there are minor residues on the protective component before removal, or if alignment in subsequent processes requires observation through it, it will not cause serious problems. At the same time, the transparent optical port protective component 150 facilitates photo-based adhesive removal during the subsequent removal process.

[0057] When the optical chip is mounted by soldering, since the optical chip and the electrical chip 140 are directly connected by bumps, there is a gap between them. In order to achieve a strong connection between them, it is also necessary to form an underfill layer 170 under the electrical chip 140.

[0058] For example, please refer to Figure 4 Using a capillary underfill process, liquid underfill adhesive is dotted along the edge of the electrical chip 140. Utilizing capillary action, the adhesive automatically flows into the gap between the electrical chip 140 and the optical chip, completely encapsulating the solder balls. It is then baked to cure the adhesive. Understandably, this underfill process serves two purposes: firstly, it enhances mechanical strength by absorbing thermal stress caused by mismatched coefficients of thermal expansion, preventing solder joint fatigue fracture; secondly, it protects the solder joints from environmental factors such as moisture and ion contamination.

[0059] Of course, if a hybrid bonding process is used to mount the electrical chip 140, the gap between the electrical chip 140 and the optical chip is extremely small and there are no solder balls, so there is no need for underfill.

[0060] Next, wafer-level molding is performed to encapsulate the electrical chip 140 and the protective component. It should be noted that common molding processes include compression molding, thin-film assisted molding, and spraying or spin coating. Compression molding involves placing liquid or granular molding compound 160 between a mold and the wafer, then heating and pressurizing it after mold closing to melt and flow the molding compound 160, filling all the gaps between the chips and covering the top of the chips and the protective component. High-temperature curing then hardens the molding compound 160. Thin-film assisted molding is suitable for scenarios requiring protection of specific areas. Spraying or spin coating is used for scenarios requiring extremely thin molding layers, applying liquid photosensitive or thermosetting resins.

[0061] After molding, the electrical chip 140 and the protective component are completely encapsulated in a rigid molding compound 160. This molding compound 160 provides mechanical support for subsequent processes and temporarily connects the previously independent chips into a single unit, facilitating subsequent wafer-level processing. It should be noted that because the optical chip wafer 110 is relatively thick when mounting the electrical chip 140 and the optical port protective component 150, chip cracking of the optical chip wafer 110 is less likely during mounting. After molding, because the molding compound 160 encapsulates the electrical chip 140 and the optical chip into a single unit, chip cracking of the optical chip wafer 110 is also less likely. Therefore, throughout the entire packaging process, chip cracking of the optical chip wafer 110 is not a significant concern.

[0062] Since the molding compound encapsulates both the entire electrical chip 140 and the optical port protection component 150, the molding compound needs to be ground and thinned in order to remove the optical port protection component 150 in subsequent processes.

[0063] Specifically, a wafer back-grinding machine is used to mechanically grind and thin the upper surface of the cured molding compound 160. The grinding process typically consists of two steps: coarse grinding and fine grinding. Coarse grinding uses a large-particle grinding wheel to quickly remove most of the molding compound 160; fine grinding uses a fine-particle grinding wheel to precisely control the grinding thickness until the back surface of the electronic chip 140 and the top surface of the optical port protection component 150 are completely exposed. Figure 5 As shown.

[0064] During the grinding process, precise control of the grinding stop point is crucial. When mounting the electrical chip 140 and the optical port protection component 150, their surfaces are typically set flush. However, due to slight differences in the thickness of the electrical chip 140, it is essential to ensure that the back side of all electrical chips 140 are ground, without over-grinding and damaging the active areas of the electrical chip 140. This is usually achieved through a high-precision online thickness measurement system on the equipment, ensuring precise control of the grinding stop point.

[0065] Furthermore, the surface exposed after grinding should have good flatness and low roughness, laying the foundation for subsequent possible processes (such as rewiring) or final appearance requirements. A polishing or chemical mechanical polishing step is usually performed after grinding to remove the grinding damage layer and microcracks, resulting in a smooth surface. After grinding and thinning the molding compound 160, a flat and robust composite wafer structure can be formed, consisting of the molding compound 160, the electrical chip 140, and the optical port protection component 150.

[0066] Please refer to the following: Figure 6The bottom surface of the optical chip wafer 110 is thinned to expose the lower end of the TSV via 130. In practical applications, the wafer is flipped over to process the back side of the optical chip wafer 110. The purpose of this step is to thin the optical chip to the target thickness and precisely expose the TSV structure for subsequent electrical connections.

[0067] In this application, when thinning the wafer, the bottom surface of the optical chip wafer 110 is first pre-ground until it is ground to near the lower end of the TSV via 130. Then, substrate etching is performed on the bottom surface of the optical chip wafer 110, and passivation layer deposition is performed. Finally, CMP grinding is performed on the bottom surface of the optical chip wafer 110 to expose the TSV via 130.

[0068] Specifically, a mechanical polishing process is first used to quickly remove most of the silicon material on the back of the optical chip. Polishing stops when the chip is close to the lower end of the TSV via 130. Here, "close to the lower end of the TSV via 130" means stopping when the distance from the bottom of the TSV is less than a threshold, for example, stopping when there are still about 10-20 micrometers left to go to avoid mechanical stress damaging the TSV structure or causing the chip to crack.

[0069] Since mechanical polishing leaves a damaged layer and stress on the silicon surface, this application also employs wet etching or dry etching (such as plasma etching) to remove this damaged layer and continue thinning until the TSV is exposed. Dry etching has better anisotropy and selectivity, allowing for more precise control and avoiding over-etching of the TSV copper pillars.

[0070] Furthermore, an insulating passivation layer, such as silicon oxide or silicon nitride, is deposited on the etched back side. This passivation layer covers the entire back side, including the silicon substrate and the sides of the TSV copper pillars, serving as insulation and protection. However, this passivation layer needs to be removed from the end faces of the TSV copper pillars because subsequent circuits need to be led out. Therefore, a short CMP process is used to planarize the back side and remove the passivation layer covering the end faces of the TSV copper pillars, exposing a clean, flat copper surface, providing a good contact interface for subsequent redistribution layers.

[0071] Please refer to the following: Figure 7The process involves fabricating a redistribution layer and solder balls on the bottom surface of the wafer. An RDL layer is fabricated on the back side of the wafer, redistributing the electrode terminals from the TSV leads and fabricating solder balls for connecting external circuitry. The fabrication of the redistribution layer includes seed layer deposition, such as depositing a titanium / copper or titanium-tungsten / copper layer on the back side as a seed layer for electroplating via physical vapor deposition. Photolithography is then performed, involving the application of photoresist to define the pattern of the RDL circuitry. Thick copper is then electroplated in the exposed seed layer area in an electroplating bath to form the actual wiring layer. The photoresist is then removed, and unwanted seed layers are rapidly etched away. A dielectric layer is then fabricated on top of the RDL circuitry for insulating protection, and openings for connecting solder balls are photolithographically formed.

[0072] When fabricating solder balls, they are created at the openings of the RDL pads by either ball placement or electroplating. Ball placement involves placing the solder balls on flux and then reflowing them. Electroplating involves electroplating solder onto a pattern defined by photolithography.

[0073] It should be noted that when designing the RDL layout, the projection area directly below the optical port 120 can be intentionally avoided. This means that no metal traces or solder balls should be placed directly below the optical port 120. The advantage of doing so is that if alignment or inspection from the bottom of the chip is required during future optical coupling, the obstruction and interference from the bottom metal structure can be reduced.

[0074] It should also be noted that the embodiments of this application do not limit the structure of the optical port protection component 150 or the form of the optical port 120. For example, please refer to... Figure 8 The optical port protector 150 can also be configured with a large upper surface area and a small lower surface area, with the area gradually decreasing from top to bottom. For example, the optical port protector 150 can be configured as an inverted trapezoidal structure. This configuration allows for a smaller bonding area at the bottom and a larger area at the top when the optical port protector 150 is bonded, making it easier to pick up and remove the optical port protector 150 during subsequent removal.

[0075] Furthermore, the optical port 120 can also be configured to emit light from the top, rather than the side. When the optical port 120 with top light emission is combined with the inverted trapezoidal structure of the optical port protection component 150, the bottom area of ​​the optical port protection component 150 has a small adhesive area, making it easier to remove and less likely to damage the optical port.

[0076] After all hard structures (RDL, solder balls) are fabricated, the optical port protection component 150 that previously protected the optical port 120 is removed, thereby exposing the optical port 120. Since this step is performed after processes such as molding and polishing, it effectively avoids the problem of contamination of the optical port 120.

[0077] When removing the optical port protective component 150, the adhesive can be removed first by heating, ultraviolet light irradiation, or laser irradiation. Then, the optical port protective component 150 can be removed. After that, the optical port 120 area is cleaned with detergent and deionized water. Finally, the optical port 120 area is dried and heated, and then deionized air blowing and plasma cleaning are performed on the optical port 120 area.

[0078] In removing adhesiveness, appropriate external stimuli can be applied based on the properties of the adhesive. For example, if the adhesive is UV-dissolving, ultraviolet light is used to irradiate the aperture 120 area from the top of the wafer through a protective cover or from the side. The UV light triggers a reaction in the photosensitizer in the adhesive, causing the polymer chains to break or depolymerize, thus losing its adhesiveness. If the adhesive is thermally dissolving, the wafer is placed on a heating plate and heated to a specific temperature (e.g., 150℃-200℃) to cause the adhesive to foam or soften and lose its adhesiveness. Alternatively, a laser can be used to scan the aperture 120 area, instantly heating and decomposing the adhesive.

[0079] After the adhesive loses its stickiness, a pick-and-place machine or automated equipment with a special nozzle can be used to pick up and remove the protective components one by one or the entire sheet. Since the adhesive is no longer sticky, the removal process will not cause physical damage to the optical port 120.

[0080] After the protective component is removed, trace amounts of adhesive may still remain on the surface of the optical port 120. Thorough cleaning is required. First, use an organic solvent compatible with the adhesive (such as acetone or isopropanol) for spraying or immersion cleaning to dissolve most of the residue. Next, perform plasma cleaning, such as using oxygen plasma (O2 plasma) or hydrogen plasma (H2 plasma). Through the physical bombardment and chemical reaction of high-energy plasma, nanoscale organic residues in the optical port 120 area are thoroughly removed, restoring the cleanliness of the optical port 120. Finally, rinse with plenty of deionized water and dry with high-speed spin drying or nitrogen blowing.

[0081] Next, the entire wafer, after all processes have been completed, is diced and separated into multiple independent optical engine modules. For example, before dicing, a dicing film can be attached to the front side of the wafer to fix the chip and protect the front optical port 120 and the surface.

[0082] During cutting, blade cutting or laser cutting can be used. Laser cutting has the advantages of narrow kerf and minimal chipping, making it particularly suitable for structures sensitive to mechanical stress. The cutting path needs to be precisely planned within the area between the chips to avoid damaging the chip body.

[0083] After cutting, the dust generated during cutting is washed away with deionized water. Then, the cut film is irradiated under ultraviolet light to reduce its adhesiveness, followed by film expansion. This increases the spacing between the individual modules after cutting, facilitating subsequent pick-up and mounting. After cutting, it can be separated into multiple independent light engine modules.

[0084] Based on this, please refer to Figure 9 or Figure 10 A single optical engine module can be mounted onto the target carrier board 180; and optical coupling can be performed based on the position of the optical port 120 to complete the encapsulation of the CPO module.

[0085] Specifically, the individual optical engine modules, after being cut and separated, are picked up and flip-chip mounted onto the target substrate 180 (such as a PCB, glass substrate, or silicon substrate) using solder balls at the bottom. The mounting process also requires steps such as mounting, reflow soldering, and flux cleaning. Because the optical engine module is now completely encapsulated by the rigid molding compound 160, its overall warpage is much lower than that of a simple thin optical chip. Therefore, the module maintains a good shape during pick-up, alignment, placement, and reflow soldering, and is less prone to warping, deformation, or cracking. This greatly improves the mounting yield and the long-term reliability of the product. Compared with existing technologies, the overall module one-time mounting method of this application has significant advantages, avoiding the yield loss caused by the fragility of the thin optical chip during the first mounting.

[0086] Next, based on the design of the optical engine module (i.e., the orientation of optical port 120), a suitable coupling scheme is selected. If optical port 120 is facing upwards (i.e., pointing away from the carrier board), a fiber array unit (FAU) with a suitable structure and size can be selected. Active or passive alignment is then performed directly above optical port 120, and it is then fixed with UV adhesive. Because optical port 120 is perfectly protected during the wafer fabrication stage, it is clean and uncontaminated, ensuring the highest coupling efficiency.

[0087] When the optical port 120 faces to the side, if it is designed on the side of the chip for system heat dissipation or space layout considerations, a miniature prism or 45° reflector can be precisely mounted above or to the side of the optical port 120. Light emitted from (or entering) the optical port 120 is reflected by the prism, changes direction, and couples with the horizontally oriented FAU. This solution provides system architects with great flexibility, allowing them to freely plan the optical path according to chassis airflow, connector placement, and other requirements.

[0088] Understandably, when the optical engine in this application is mounted onto the substrate or PCB, it operates as an integrated module consisting of the electrical chip 140 and the optical chip. Due to the encapsulation of the molding compound 160, the overall mechanical support performance of the module is better, and it is less prone to damage during operation; in subsequent work, its mechanical reliability is also better.

[0089] If there is no 160mm molding compound for encapsulation, the optical chip needs to be mounted from bottom to top when mounting it onto the substrate or PCB. Due to the small thickness and large length and width of the optical chip, it is easy to break during mounting and is prone to poor soldering due to warping. In subsequent work, overall warping can also easily cause the optical chip to break, resulting in poor mechanical reliability.

[0090] For a package structure where the molding compound 160 covers the optical chip, the protection and exposure of the optical port 120 are common issues. The optical chip can only be covered by the molding compound 160 when the optical port 120 is on the side; then, the optical port 120 on the side of the chip is exposed using a wafer dicing process, but deviations in the dicing position can easily lead to damage to the optical port 120 or failure to fully expose it.

[0091] This application uses a protective component to shield the area of ​​the optical port 120, preventing the molding compound 160 from contaminating the optical port 120 and creating conditions for subsequent optical coupling; in addition, since the position of the optical port 120 can be designed at a non-edge position of the chip, the positional deviation of the wafer dicing process will not affect the optical port 120.

[0092] Based on the above implementation, this application also provides a CPO module, which includes a target carrier board 180 and a light engine module manufactured by the above method, wherein the light engine module is mounted on the target carrier board 180. Currently, the carrier board can be a substrate or a PCB board, and is not limited thereto.

[0093] Understandably, when this application employs an electrical chip 140 on top and an optical chip below, and uses molding compound 160 for overall encapsulation, the optical chip's optical port 120 has an opening in the molding compound 160. Due to the encapsulation of the molding compound 160, the overall mechanical support performance of the module is better, making it less prone to damage during operation; in subsequent work, mechanical reliability is also better. Furthermore, the optical port 120 area is protected using a light-transmitting protective component and an adhesive that can be removed under specific conditions; this prevents the molding compound 160 from contaminating the optical port 120, creating conditions for subsequent optical coupling; in addition, since the position of the optical port 120 can be designed at a non-edge position of the chip, the positional deviation of the wafer dicing process will not affect the optical port 120.

[0094] In summary, this application provides a 3D packaging structure fabrication method and CPO module for an optical engine module. First, an optical chip wafer is provided, wherein an optical port is provided on the surface of the optical chip wafer, and a TSV via is provided inside the optical chip wafer. Next, an electrical chip and an optical port protection component are mounted on the surface of the optical chip wafer; wherein the electrical chip is located in the non-overlapping area of ​​the optical port, and the optical port protection component is located in the overlapping area of ​​the optical port and blocks the optical port. Then, a molding compound is applied to the top of the optical chip wafer, encapsulating the electrical chip and the optical port protection component. The molding compound is then thinned until the optical chip and the optical port protection component are exposed. Next, the bottom surface of the optical chip wafer is thinned until the TSV via is exposed. Then, an RDL layer and solder balls are fabricated on the bottom surface of the optical chip wafer, wherein the RDL layer is connected to the TSV via. Next, the optical port protection component is removed. Finally, the optical chip wafer is diced to form a single optical engine module.

[0095] On the one hand, by encapsulating the optical and electrical chips together with molding compound, a robust and integrated module is formed. When mounting the module onto the target substrate, the object of the operation is the entire module, not the fragile thin optical chip, effectively preventing chip breakage and improving the product's mechanical reliability over long-term use. On the other hand, the use of a protective element for the optical port ensures that the molding compound only covers the outer edge of the protective element and cannot access the port itself. Furthermore, the protective element can be directly removed later without exposing the port through cutting, allowing for greater flexibility in optical port design.

[0096] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0097] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for fabricating a 3D packaging structure for a light engine module, characterized in that, The method includes: An optical chip wafer is provided, wherein an optical port is provided on the surface of the optical chip wafer, and a TSV via is provided inside the optical chip wafer; The optical chip wafer is based on an electrical chip and an optical port protection component mounted on it; wherein the electrical chip is located in the non-overlapping area of ​​the optical port, and the optical port protection component is located in the overlapping area of ​​the optical port and blocks the optical port; The optical chip wafer is encapsulated in plastic, and the plastic encapsulation material encapsulates the electrical chip and the optical port protection component. The molding compound is thinned until the optical chip and the optical port protection component are exposed. The bottom surface of the optical chip wafer is thinned until the TSV via is exposed; An RDL layer and solder balls are fabricated on the bottom surface of the optical chip wafer, wherein the RDL layer is connected to the TSV via. Remove the optical port protection component; The optical chip wafer is diced to form a single optical engine module.

2. The method for fabricating the 3D packaging structure of the light engine module according to claim 1, characterized in that, The steps for mounting an electrical chip and an optical port protection component on the surface of the optical chip wafer include: Electrical chips are mounted on the surface of the optical chip wafer by soldering or hybrid bonding.

3. The method for fabricating the 3D packaging structure of the light engine module according to claim 1, characterized in that, The steps for mounting an electrical chip and an optical port protection component on the surface of the optical chip wafer include: Adhesive is applied to the location of the optical port; wherein, the adhesive can be removed by heating, ultraviolet light irradiation, or laser irradiation; The optical port protective component is mounted on the surface of the adhesive.

4. The method for fabricating the 3D packaging structure of the light engine module according to claim 1, characterized in that, The light port protection component is a light-transmitting protection component.

5. The method for fabricating the 3D packaging structure of the light engine module according to claim 1, characterized in that, Prior to the molding and encapsulation step on top of the optical chip wafer, the method further includes: When the optical chip is mounted using a solder joint mounting method, underfilling is performed based on the underside of the electrical chip.

6. The method for fabricating the 3D packaging structure of the light engine module according to claim 1, characterized in that, The step of thinning the bottom surface of the optical chip wafer until the TSV via is exposed includes: The bottom surface of the optical chip wafer is initially ground until it is close to the lower end of the TSV via. The substrate is etched on the bottom surface of the optical chip wafer, and a passivation layer is deposited. The bottom surface of the optical chip wafer is CMP polished to expose the TSV vias.

7. The method for fabricating the 3D packaging structure of the light engine module according to claim 1, characterized in that, The steps for fabricating the RDL layer and solder balls on the bottom surface of the optical chip wafer include: An RDL layer and solder balls are fabricated on the bottom surface of the optical chip wafer, away from the orthogonal projection area of ​​the optical port.

8. The method for fabricating the 3D packaging structure of the light engine module according to claim 1, characterized in that, The optical port protective component is attached to the surface of the optical chip wafer using adhesive. The step of removing the optical port protective component includes: The adhesiveness is removed by heating, ultraviolet light irradiation, or laser irradiation; Remove the optical port protective component; Clean the optical port area with detergent and deionized water; After drying and heating the optical port area, the optical port area is then subjected to deionized air blowing and plasma cleaning.

9. The method for fabricating the 3D packaging structure of the light engine module according to claim 1, characterized in that, After the step of dicing the optical chip wafer to form a single optical engine module, the method further includes: The individual optical engine modules are mounted onto the target carrier board; Optical coupling is performed based on the position of the optical port.

10. A CPO module, characterized in that, The CPO module includes a target substrate and a light engine module manufactured by the method described in any one of claims 1 to 9, the light engine module being mounted on the target substrate.

Images