A reliability testing method and system for silicon carbide MOSFETs

Abstract

This invention discloses a reliability testing method and system for silicon carbide MOSFETs. The reliability testing method for silicon carbide MOSFETs includes the following steps: preparation, connecting the device under test (DUT) to the system; initial measurement, measuring initial electrical parameters; cyclic testing, sequentially performing a heating step, a testing step, and a cooling step; the heating step involves raising the junction temperature of the DUT to a target junction temperature and maintaining it stable under the combined effects of ambient temperature and the self-heating of the DUT; the testing step involves real-time monitoring of high-temperature electrical parameters; the cooling step involves measuring intermediate electrical parameters; and the calculation involves calculating the estimated lifetime of the DUT at the actual junction temperature. The reliability testing method for silicon carbide MOSFETs of this invention can detect the reliability of the high-temperature conduction state of silicon carbide MOSFETs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing, and in particular to a reliability testing method and system for silicon carbide MOSFETs. Background Technology

[0002] Silicon carbide (SiC) MOSFETs are metal-oxide-semiconductor field-effect transistors based on silicon carbide materials. Due to their advantages such as high frequency, high voltage withstand capability, and high thermal conductivity, they have been widely used in new energy vehicles, rail transportation, industrial power conversion, and smart grids. Compared to traditional silicon-based power devices, SiC MOSFETs offer higher operating efficiency and power density.

[0003] Existing reliability testing methods for silicon carbide MOSFETs have significant shortcomings:

[0004] Large differences in operating junction temperature: The operating junction temperature of silicon carbide MOSFETs typically reaches 150-200℃, which is higher than that of traditional silicon devices (≈150℃ and below). However, existing reliability testing standards (such as JEDEC standards) are mainly developed based on traditional silicon-based devices and are insufficient to accurately reflect the reliability characteristics of SiC devices at extreme high temperatures.

[0005] The testing methods are one-sided: existing testing methods mainly focus on the thermal cycling of devices or short-term electrical stress (ESD, overload, etc.), but there is insufficient research on the degradation mechanism under long-term steady-state conduction conditions. In practical applications, many industrial applications (such as industrial power supplies and main drives for new energy vehicles) require devices to conduct stably for a long time at high temperatures.

[0006] Insufficient time span: Traditional accelerated aging test cycles are short (hundreds of hours), making it difficult to stimulate chronic degradation mechanisms (such as threshold voltage drift, increased on-resistance, and gate oxide degradation).

[0007] Lack of a systematic testing framework: Currently, the industry lacks standardized testing methods and judgment criteria for the long-term steady-state conduction reliability of silicon carbide MOSFETs, making it difficult to compare test results from different research institutions. Summary of the Invention

[0008] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a reliability testing method for silicon carbide MOSFETs, capable of detecting the reliability of the high-temperature conduction state of silicon carbide MOSFETs.

[0009] The present invention also proposes a test system for the reliability testing method of the above-mentioned silicon carbide MOSFET.

[0010] A reliability testing method for a silicon carbide MOSFET according to a first aspect of the present invention includes the following steps: preparation, taking multiple silicon carbide MOSFETs to be tested as devices under test, placing the devices under test in a high-temperature environment chamber, and connecting the devices under test to a drive circuit, a current source, a temperature sensor, and an electrical parameter acquisition system; initial test, measuring and recording the initial electrical parameters of the devices under test at room temperature, wherein the room temperature is 20-30℃; cyclic test, setting a maximum number of cycles N, with the initial number of cycles being zero, sequentially performing a heating step, a testing step, and a cooling step, incrementing the number of cycles by one, ending the cyclic test step when the number of cycles reaches the maximum number of cycles N or when all devices under test fail, otherwise continuing the cyclic test step; the heating step involves setting the high-temperature environment chamber to a specified temperature, applying a driving voltage to the gate of the device under test through the drive circuit to turn on the device under test, and then... A current source applies a DC current to the device under test (DUT), causing the DUT to self-heat. Under the combined effect of ambient temperature and the self-heating of the DUT, the junction temperature of the DUT rises to a target junction temperature and remains stable, wherein the target junction temperature is not less than 150°C. The test steps are as follows: stabilizing the junction temperature of the DUT to the target junction temperature, keeping the DUT conductive, and continuously monitoring the high-temperature electrical parameters of the DUT in real time through the electrical parameter acquisition system for a specified test time. The cooling step involves lowering the junction temperature of the DUT to room temperature, measuring and recording the intermediate electrical parameters of the DUT, comparing the intermediate electrical parameters with the initial electrical parameters according to a predetermined failure criterion to determine whether the DUT has failed, and removing the failed DUT from the high-temperature environmental chamber. After the cyclic test steps are completed, the estimated lifetime of the DUT at the actual junction temperature is calculated based on the high-temperature electrical parameters, the intermediate electrical parameters, and the initial electrical parameters.

[0011] According to a first aspect of the present invention, a reliability testing method for a silicon carbide MOSFET has at least the following technical effects: during the test, the junction temperature of the device under test is stabilized at the target junction temperature, which is not less than 150°C, and the device under test remains in the conducting state during the test. Finally, based on the parameters recorded during the test, the estimated lifetime of the device under test at the actual junction temperature can be calculated, thereby enabling the evaluation of the reliability of the silicon carbide MOSFET in the high-temperature conducting state.

[0012] According to some embodiments of the present invention, the initial electrical parameters, the high-temperature electrical parameters, and the intermediate electrical parameters all include the on-resistance of the device under test.

[0013] According to some embodiments of the present invention, the conduction resistance in the initial electrical parameters is the initial conduction resistance, the conduction resistance in the intermediate electrical parameters is the intermediate conduction resistance, the intermediate conduction resistance minus the initial conduction resistance is obtained as the intermediate conduction resistance difference, the intermediate conduction resistance difference divided by the initial conduction resistance is obtained as the percentage value of the intermediate conduction resistance difference, and the failure criterion is: the percentage value of the intermediate conduction resistance difference is greater than a preset failure percentage value.

[0014] According to some embodiments of the present invention, in the test step: at the beginning of the test step, the on-resistance in the high-temperature electrical parameters is recorded as the initial high-temperature on-resistance; from the beginning to the end of the test step, the on-resistance in the high-temperature electrical parameters is recorded in real time as the real-time high-temperature on-resistance; the real-time high-temperature on-resistance difference is obtained by subtracting the initial high-temperature on-resistance from the real-time high-temperature on-resistance difference, and the percentage value of the real-time high-temperature on-resistance difference is obtained by dividing the real-time high-temperature on-resistance difference by the initial high-temperature on-resistance difference; when the percentage value of the real-time high-temperature on-resistance difference of a device under test is greater than a preset abnormal percentage value, the time is recorded, and the device under test is marked as an abnormal individual; after the cooling step, it is recorded whether the abnormal individual has failed.

[0015] According to some embodiments of the present invention, the device under test is further connected to a feedback controller and an active cooling system. The specified temperature is greater than the target junction temperature. During the heating and testing steps, the feedback controller adjusts the magnitude of the DC current applied to the device under test by the current source, and the feedback controller adjusts the cooling power of the active cooling system, thereby stabilizing the junction temperature of the device under test to the target junction temperature.

[0016] According to some embodiments of the present invention, the device under test is further connected to a feedback controller. The specified temperature is lower than the target junction temperature. During the heating and testing steps, the feedback controller adjusts the magnitude of the DC current applied to the device under test by the current source, thereby stabilizing the junction temperature of the device under test to the target junction temperature.

[0017] According to some embodiments of the present invention, in the cooling step, the heating power of the high-temperature environment chamber and the magnitude of the DC current applied to the device under test by the current source are gradually reduced. When the high-temperature environment chamber reduces the ambient temperature by a specified amount, the heating power of the high-temperature environment chamber and the magnitude of the DC current applied to the device under test by the current source are kept unchanged for a specified time. Then, the heating power of the high-temperature environment chamber and the magnitude of the DC current applied to the device under test by the current source are gradually reduced until the junction temperature of the device under test reaches room temperature.

[0018] According to some embodiments of the present invention, in the test step or the cooling step, the failure time of each device under test is recorded; in the calculation step, the average failure time t1 of all failed devices under test is calculated; the total time t2 of the test step is recorded; and the acceleration factor AF is calculated, wherein the formula for calculating the acceleration factor AF is:

[0019] ;

[0020] in:

[0021] E a This refers to the activation energy of a silicon carbide MOSFET.

[0022] k B The Boltzmann constant is 8.617 × 10⁻⁶. -5 eV / K;

[0023] T test The target junction temperature;

[0024] T use This refers to the actual junction temperature;

[0025] The estimated lifetime MTTF was calculated using the failure rate conversion formula. use :

[0026] ;

[0027] ;

[0028] ;

[0029] in:

[0030] N f This represents the number of failed devices under test.

[0031] N t This represents the total number of devices under test.

[0032] If all devices under test fail during the cyclic test steps, then t = t1; otherwise, t = t2.

[0033] λ stress To test the failure rate;

[0034] λ use To estimate the actual failure rate.

[0035] According to some embodiments of the present invention, an analysis step is also included, in which physical failure analysis is performed on the failed device under test after the cooling step.

[0036] A reliability testing system for a silicon carbide MOSFET according to a second aspect of the present invention is used to test the device under test in the above-described reliability testing method, comprising: a high-temperature environmental chamber for placing the device under test; a driving circuit for connecting to the device under test to apply a driving voltage to the gate of the device under test; a current source for connecting to the device under test to apply a direct current to the device under test; a temperature sensor for connecting to the device under test to measure the temperature of the device under test; and an electrical parameter acquisition system for connecting to the device under test to acquire the electrical parameters of the device under test.

[0037] According to a second aspect of the present invention, a reliability testing system for a silicon carbide MOSFET has at least the following technical advantages: a high-temperature environment chamber can heat up and maintain the temperature of the environment where the device under test is located; a drive circuit is connected to the device under test to keep the device under test conducting; a current source is connected to the device under test to make the device under test self-heat; a temperature sensor monitors the junction temperature of the device under test in real time for convenient and timely adjustment; and an electrical parameter acquisition system collects and records the electrical parameters of the device under test in real time for convenient subsequent statistical calculations.

[0038] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0039] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0040] Figure 1 This is a schematic flowchart of a reliability testing method for a silicon carbide MOSFET according to an embodiment of the present invention;

[0041] Figure 2 This is a connection diagram of the reliability testing system for a silicon carbide MOSFET according to the first embodiment of the present invention;

[0042] Figure 3 This is a connection diagram of the reliability testing system for a silicon carbide MOSFET according to the second embodiment of the present invention. Detailed Implementation

[0043] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0044] In the description of this invention, it should be understood that the directional descriptions, such as "up," "down," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "point," "inner," "outer," "axial," "radial," "circumferential," and "around," are based on the directional or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, sidewalls refer to the left side wall and / or the right side wall.

[0045] In the description of this invention, "a plurality of" means two or more; "greater than," "less than," "exceeding," etc., are understood to exclude the number itself; and "above," "below," "within," etc., are understood to include the number itself. Where "second" is used, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0046] In the description of this invention, it should be understood that "A is set on B" or "A is set on B" describes the connection or positional relationship between A and B, and does not mean that A is necessarily above B.

[0047] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, movable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. "Bolt connection" and "screw connection" can be used interchangeably. Those skilled in the art can understand the specific meaning of the above terms in this invention in light of the specific circumstances. It should be understood that multiple similar features in this invention are distinguished only by different prefixes. Therefore, in this invention, the feature name without distinguishing prefixes (or the feature name with partial prefixes) is used to represent the synthesis of this type of similar features.

[0048] Reference Figure 1 , Figure 2 and Figure 3 The reliability testing method for silicon carbide MOSFETs according to embodiments of the present invention (hereinafter referred to as the testing method) includes the following steps:

[0049] Preparation: Multiple silicon carbide MOSFETs to be tested are used as devices under test. The devices under test are placed in a high-temperature environment chamber, and the devices under test are connected to a drive circuit, a current source, a temperature sensor, and an electrical parameter acquisition system.

[0050] Initially, the initial electrical parameters of the device under test were measured and recorded at room temperature (25±5℃).

[0051] The cyclic test is set to a maximum number of cycles N, with the initial number of cycles being zero. The heating step, the testing step, and the cooling step are performed sequentially, and the number of cycles is incremented by one. The cyclic test ends when the number of cycles reaches the maximum number of cycles N or when all devices under test fail; otherwise, the cyclic test continues.

[0052] The heating process involves setting the high-temperature environment chamber to a specified temperature, applying a driving voltage to the gate of the device under test (DUT) through a driving circuit to turn on the DUT, and applying a DC current to the DUT through a current source to cause the DUT to self-heat. Under the combined effect of the ambient temperature and the self-heating of the DUT, the junction temperature of the DUT rises to the target junction temperature and remains stable. The target junction temperature is not less than 150°C.

[0053] The test procedure is as follows: stabilize the junction temperature of the device under test (DUT) to the target junction temperature, keep the DUT conducting, monitor the high-temperature electrical parameters of the DUT in real time through the electrical parameter acquisition system, and continue the test for the specified time.

[0054] The cooling process involves lowering the junction temperature of the device under test (DUT) to room temperature, measuring and recording the intermediate electrical parameters of the DUT, comparing the intermediate electrical parameters with the initial electrical parameters based on predetermined failure criteria, determining whether the DUT has failed, and removing the failed DUT from the high-temperature environment chamber.

[0055] After the cyclic testing steps are completed, the estimated lifetime of the device under test at the actual junction temperature is calculated based on the high-temperature electrical parameters, intermediate electrical parameters, and initial electrical parameters.

[0056] In the preparation steps, to ensure the reliability of the test results, the number of devices under test (DUTs) is relatively large, generally more than 16, and they usually come from the same batch to ensure process consistency. High-temperature environmental chambers (hereinafter referred to as chambers or environmental chambers) are commonly used equipment in existing testing systems. Their specific structure, principle, and working process will not be elaborated here. The same applies to drive circuits, current sources, temperature sensors, electrical parameter acquisition systems, feedback controllers, and active cooling systems. High-temperature environmental chambers can raise the temperature inside the chamber, thereby providing a high-temperature environment for the DUTs inside, simulating the harsh high-temperature operating scenarios of silicon carbide MOSFETs in actual use. It is important to understand that high-temperature environmental chambers generally come with their own temperature sensors and control systems, allowing for the setting of a predetermined temperature. The temperature sensor can monitor the ambient temperature inside the chamber in real time, and the control system can regulate and maintain the ambient temperature at approximately the predetermined temperature. In some embodiments, the chamber has built-in or additional test fixtures to fix the DUTs in place. The temperature of the device under test (DUT) may differ from the ambient temperature inside the high-temperature chamber (due to self-heating, active cooling systems, etc.), so an additional temperature sensor is required to monitor the DUT's temperature in real time. The temperature sensor is generally in direct contact with the DUT, resulting in more accurate and faster detection results.

[0057] In the initial testing steps, the ambient temperature inside the chamber is maintained at 20-30℃, which can be considered as being in a room temperature environment. Initial electrical parameters may include: on-resistance Rds(on), measured under specified gate voltage and drain-source current; threshold voltage Vth, the boundary between device conduction and cutoff; gate leakage current Igss, the leakage current under specified gate-source voltage; reverse transfer capacitance Crss, etc. One or more of these electrical parameters can be measured, or more parameters can be selected for measurement. Similarly, in subsequent testing and cooling steps, the high-temperature and intermediate electrical parameters that need to be measured can refer to these parameters. It is particularly important to understand that the specific data types of the initial, high-temperature, and intermediate electrical parameters must at least include one data type of the same type (e.g., all including on-resistance). This facilitates subsequent calculation steps in estimating the lifetime and determining the reliability of the silicon carbide MOSFET based on this data. It should be understood that in this invention, A±B (unit of measurement) and AB (unit of measurement) have the same unit of measurement for A and B and include the number itself; specifically, for example, 25±5℃ and 20-30℃ represent 25℃±5℃ and 20℃-30℃, respectively, and include 20℃ and 30℃. Other similar descriptions in this invention are similar.

[0058] In the cyclic testing, the maximum number of cycles N is a positive integer. 'Initial cycle count of zero' and 'cycle count incremented by one' mean that the cycle count is set to zero during the initial cyclic testing step. After the initial cyclic testing step (sequentially performing the heating step, testing step, and cooling step), the cycle count is incremented by one, becoming one; after the second cyclic testing step, the cycle count is incremented by one, becoming two; and so on. The determination of device-under-test failure is generally based on the failure criteria unique to this invention.

[0059] In the heating step, the high-temperature environment chamber is set to a specified temperature (or a predetermined temperature), which is generally a built-in function of the high-temperature environment chamber. After setting the high-temperature environment chamber to the specified temperature, it can raise the ambient temperature inside the chamber to that specified temperature and maintain it, thus ensuring that the ambient temperature around the device under test (DUT) is that specified temperature. In this embodiment, the specified temperature is generally not less than 100°C. The driving circuit is electrically connected to the gate and source of the DUT, and applies a driving voltage to the gate of the DUT to form a driving voltage, thereby enabling the DUT to conduct. The current source applies a DC current to the DUT. Initially, it is generally 70%-90% of the rated current Irated of the DUT (for example, if Irated = 100A, then Ids = 70-90A), causing the DUT to self-heat (I... 2 R (loss) more closely resembles real-world operating conditions; adjustments can then be made based on actual circumstances. Junction temperature refers to the actual operating temperature of the semiconductor chip (the silicon carbide MOSFET and the device under test in this invention) in the electronic device. Ambient temperature refers to the temperature of the environment surrounding the device under test, which is typically the specified temperature of the high-temperature environment chamber since the device under test is located in a high-temperature chamber. Using both ambient temperature and self-heating to raise the temperature and maintain a stable junction temperature not only better reflects real-world operating conditions and realistically simulates high-temperature conduction conditions in actual applications, but also allows for real-time control of the DC current applied to the device under test, thereby controlling the degree of self-heating and accurately controlling and stabilizing the junction temperature at the target value. The target junction temperature is not less than 150°C, placing the device under test at a high temperature, making the test results more consistent with the high-temperature operating conditions of silicon carbide MOSFETs; more specifically, to accelerate aging tests, the target junction temperature can be set to 180±2°C, a typical high operating temperature, close to the actual application of SiC devices.

[0060] In the testing procedure, the junction temperature of the device under test (DUT) is stabilized to the target junction temperature by real-time control of the DC current applied to the DUT or by other operations (such as controlling the operating power of the active cooling system). Keeping the DUT continuously on for a specified test time facilitates testing the reliability of silicon carbide MOSFETs under prolonged high-temperature conduction. The specified test time is generally long, such as around 168 hours (7 days), to ensure more accurate test results. This is long enough to induce aging while remaining within the experimentally feasible timeframe. Furthermore, a large maximum cycle number N is set, for example, N=16. Overall, the test cycle (i.e., the total test time = 168 * 7 = 2688 hours) is relatively long, resulting in more accurate, reliable, and trustworthy reliability test results for silicon carbide MOSFETs under prolonged high-temperature conduction. The high-temperature electrical parameters measured in the test procedure can specifically include instantaneous drain-source current Ids, drain-source voltage Vds, ambient temperature, cooling power, and current value. Based on these, the current on-resistance Rds(on) = Vds / Ids is calculated and recorded.

[0061] During the cooling process, the junction temperature of the device under test (DUT) is reduced. This can be achieved through one or more methods, such as lowering the temperature of the high-temperature ambient chamber (or reducing the heating power of the high-temperature ambient chamber), reducing the DC current applied to the DUT by the current source (reducing self-heating), enabling natural cooling of the high-temperature ambient chamber, or increasing the operating power of the active cooling system. Failure criteria are generally based on the difference in abnormal data after comparing data of the same type. For example, both the initial test and cooling steps measure the difference in the on-resistance of the DUT. If the on-resistance measured in the cooling step differs significantly from that measured in the initial test, failure can be determined. Other examples include threshold voltage drift exceeding the set threshold (0.5V), parameters measured at any point during the test exceeding the specification range, or other application-related reliability criteria. To promptly analyze the cause of DUT failure and prevent subsequent high-temperature interference, DUTs deemed to have failed are removed immediately after cooling to room temperature. The intermediate electrical parameters measured during the cooling process can specifically include key parameters such as intermediate on-resistance, threshold voltage, and gate leakage current. The percentage drift of these parameters relative to their initial electrical parameter values ​​can also be calculated.

[0062] In the calculation process, the actual junction temperature refers to the operating temperature of the silicon carbide MOSFET to be tested in actual operation (such as when it is used as a chip in a new energy vehicle under high summer temperatures), especially the operating temperature under some extreme high-temperature conditions. Based on the measured data, the lifetime of the device under test (DUT) at the target junction temperature can be actually obtained or calculated. Specifically, when the target junction temperature is very close to the actual junction temperature, the estimated lifetime of the DUT at the actual junction temperature can be directly obtained or calculated. When the target junction temperature is higher than the actual junction temperature, accelerated aging and accelerated lifetime testing can be performed. By applying the Arrhenius accelerated aging model, failure rate conversion formula, etc., the estimated lifetime of the DUT at the actual junction temperature can be calculated, ultimately completing the lifetime test in the reliability test.

[0063] It is important to understand that, unless otherwise specified, the term 'time' in this invention refers to cumulative time. Specifically, 'test time' refers to the cumulative test time, the time recorded for abnormal individuals, and also the cumulative testing duration of that individual. 'Failure time' refers to the duration of testing (i.e., the cumulative test time) that the failed device had undergone before failure. It is also important to understand that the prefixes 'initial,' 'high temperature,' and 'intermediate' in 'initial electrical parameters,' 'high temperature electrical parameters,' and 'intermediate electrical parameters' in the description of this invention are merely for the convenience of distinguishing between different groups of data, and do not indicate that these electrical parameters have special properties; the same applies to other similar descriptions.

[0064] Reference Figure 1 , Figure 2 and Figure 3 In some embodiments of the present invention, the initial electrical parameters, high-temperature electrical parameters, and intermediate electrical parameters all include the on-resistance of the device under test.

[0065] On-resistance reflects the overall performance of a silicon carbide MOSFET. Therefore, using on-resistance as a parameter to calculate the lifetime of the device under test is more accurate and stable, and it can reflect various failure modes of silicon carbide MOSFETs. It helps prevent situations where a particular failure mode has a very small and singular impact, making it easy to miss. For example, if a failure mode only affects the threshold voltage and not the drain-source voltage, then detecting only the drain-source voltage will not detect this failure mode.

[0066] Reference Figure 1 , Figure 2 and Figure 3In some embodiments of the present invention, the on-resistance in the initial electrical parameters is the initial on-resistance, the on-resistance in the intermediate electrical parameters is the intermediate on-resistance, the difference between the intermediate and intermediate on-resistance is obtained by subtracting the initial on-resistance from the intermediate on-resistance, and the percentage value of the difference between the intermediate and intermediate on-resistance is obtained by dividing the difference between the intermediate and intermediate on-resistance by the initial on-resistance. The failure criterion is that the percentage value of the difference between the intermediate and intermediate on-resistance is greater than a preset failure percentage value.

[0067] As the testing time increases, under the long-term high-temperature conduction test environment, the abnormality of the on-resistance and other data of the device under test (the difference from the initial value) will also increase slowly with aging. Therefore, there are two types of failure criteria. One is to judge that the device under test whose data exceeds the failure criterion is severely aged. Although it can still work with difficulty, it will seriously slow down the working efficiency (similar to a mobile phone that is very slow but still usable). Therefore, the device under test is judged to be failed. The other is that the device under test has completely failed and can no longer work normally (similar to a mobile phone that cannot be charged and is completely unusable). At this time, the various data of the device under test will abnormally jump to a range that other devices under test, even if they are aged, cannot enter. Therefore, a failure criterion can be set in turn to distinguish between normal devices (including aged devices) and completely failed devices. For example, suppose the initial on-resistance is measured to be 100mΩ. When the device under test (DUT) is not faulty, its on-resistance will slowly increase as the test progresses. However, when it increases to 110mΩ, the device is found to be severely aged and its operating efficiency is significantly reduced. Therefore, a failure criterion can be set as ΔRds(on) > 10%. As the test continues, the on-resistance of the DUT will still slowly increase, but it will only increase to about 115mΩ at most. After that, as the test continues, the device will completely fail, and the on-resistance will jump to 200mΩ or even 300mΩ in a very short time. Therefore, a failure criterion can also be set as ΔRds(on) > 20% (or 30%, 40%, etc.). In actual testing, a specific failure criterion can be selected based on actual needs. For example, a failure criterion for severely aged devices can be selected to make subsequent lifespan estimates more consistent with actual requirements. Alternatively, a failure criterion for complete failure can be selected to more completely and clearly analyze the chronic degradation mechanism and failure mode of silicon carbide MOSFETs under high-temperature conduction environment. This allows for better analysis of failure mechanism results and the implementation of design or process improvement measures in advance to improve product reliability.

[0068] It is important to understand that since temperature has a certain impact on on-resistance, the intermediate on-resistance measured after the device under test has cooled to room temperature should be compared with the initial on-resistance measured at room temperature during the initial measurement step. This difference accurately reflects the impact of device aging and failure on on-resistance, rather than simply the effect of temperature. It is also important to understand that the specific temperature data settings in this invention, unless otherwise specified, generally have an allowable error range of ±2℃. Similarly, the specific time data settings in this invention, such as specific time intervals ('4 hours', '10 minutes', '5-10 minutes', etc.), relative time ('real-time', 'simultaneous', etc.), or other time data settings, generally have a certain allowable error range, unless otherwise specified. For example, for larger time intervals or relative time data, an allowable error range of ±10 minutes is generally permitted.

[0069] Reference Figure 1 , Figure 2 and Figure 3 In some embodiments of the present invention, during the testing steps: at the beginning of the testing step, the on-resistance in the high-temperature electrical parameters is recorded as the initial high-temperature on-resistance; from the beginning to the end of the testing step, the on-resistance in the high-temperature electrical parameters is recorded in real time as the real-time high-temperature on-resistance; the real-time high-temperature on-resistance difference is obtained by subtracting the initial high-temperature on-resistance from the real-time high-temperature on-resistance difference, and the percentage value of the real-time high-temperature on-resistance difference is obtained by dividing the real-time high-temperature on-resistance difference by the initial high-temperature on-resistance difference (which can be simply referred to as the drift percentage relative to the initial value); when the percentage value of the real-time high-temperature on-resistance difference of a device under test is greater than a preset abnormal percentage value, the time is recorded, and the device under test is marked as an abnormal individual; after the cooling step, it is recorded whether the abnormal individual has failed.

[0070] For devices under test (DUTs) that fail during testing, determining failure solely based on intermediate electrical parameters measured after the DUT has cooled to room temperature has two drawbacks. First, this method is delayed and outdated, failing to accurately determine the specific failure time of the DUT. The failure time can only be recorded as the time when the DUT cooled to room temperature, which is not accurate enough and may affect the lifespan estimation in subsequent calculation steps. Second, it is not conducive to data analysis, resulting in a lack of useful data that can help with the analysis steps. Using the above method, for completely failed devices, the moment of resistance jump can be accurately recorded, thus accurately determining the specific failure time. It also allows for the precise selection of devices that completely fail later in the testing process for analysis, reducing the impact of subsequent high temperatures on failed devices. For aging devices, some potentially failing devices (those whose real-time high-temperature on-resistance difference percentage is greater than a preset abnormal percentage value) can be recorded as abnormal individuals. Subsequent testing (using failure criteria) can then determine whether these abnormal individuals have failed. If failure is determined, on the one hand, the previously recorded time can be used to more accurately pinpoint the actual failure time; on the other hand, by judging multiple abnormal individuals, a more precise preset abnormal percentage value can be gradually established. This allows for further precise prediction of device aging failure based on the preset abnormal percentage value, recording the more accurate actual failure time. Furthermore, changes in other electrical parameters of the device can be checked near this precise failure time for subsequent reference and research.

[0071] It is important to understand that "real-time recording" and "real-time monitoring" in this invention refer to the continuous recording and monitoring of data, or recording and monitoring data at fixed intervals (e.g., 30 minutes, 1 hour, 2 hours, 12 hours, etc.). It is also important to understand that because temperature has a certain impact on on-resistance, it is necessary to compare the initial high-temperature on-resistance measured after the junction temperature of the device under test has stabilized at the target junction temperature with the real-time high-temperature on-resistance recorded from the start to the end of the test (while the device junction temperature remains at the target junction temperature). Only this difference can more accurately reflect the impact of device aging and failure on the on-resistance, rather than the effect of temperature.

[0072] It should be understood that the on-resistance mentioned above can be replaced with other electrical parameters, such as instantaneous drain-source current, drain-source voltage, etc. The setting of failure criteria and the recording of abnormal values ​​are basically the same, and the design principle is the same.

[0073] Reference Figure 1 , Figure 2 and Figure 3In some embodiments of the present invention, the device under test is also connected to a feedback controller and an active cooling system. The specified temperature is higher than the target junction temperature. During the heating and testing steps, the feedback controller adjusts the magnitude of the DC current applied to the device under test by the current source, and the feedback controller adjusts the cooling power of the active cooling system, thereby stabilizing the junction temperature of the device under test to the target junction temperature.

[0074] Throughout the cyclic testing process, the DC current applied to the device under test (DUT) by the current source can be adjusted via the feedback controller to regulate the self-heating of the DUT, thereby stabilizing the junction temperature of the DUT to the target junction temperature. When the specified temperature is higher than the target junction temperature, since the ambient temperature is higher than the DUT's own temperature and the device generates its own heat, an active cooling system is required to help cool the DUT.

[0075] In some embodiments, the heating step specifically involves setting the temperature of the high-temperature ambient chamber to a constant high temperature value (e.g., a specified temperature of 220°C) and stabilizing the ambient temperature; activating the active cooling system; applying a driving voltage to the device gate to fully turn on the device, while simultaneously applying a DC current from a current source, initially set to 70%-90% of the device's rated current Irated (e.g., if Irated = 100A, then Ids = 70-90A), causing the device to generate self-heat; and combining ambient heating (220°C) and self-heating (Irated)... 2 The combined effect of R (residual heat loss) causes the device junction temperature to rise. A feedback control system monitors the junction temperature in real time, simultaneously adjusting the active cooling power and load current to ensure a slow and stable rise to the target value. Once the junction temperature stabilizes at the target value (e.g., target junction temperature = 180℃), testing begins. The active cooling system and heating source operate in parallel, achieving thermal equilibrium: self-heating power + ambient heating power = heat removed by the active cooling system. Precise feedback control (±0.5℃ accuracy) ensures accurate and stable control of the junction temperature.

[0076] Reference Figure 1 , Figure 2 and Figure 3 In some embodiments of the present invention, the device under test is also connected to a feedback controller. The specified temperature is lower than the target junction temperature. During the heating and testing steps, the feedback controller adjusts the magnitude of the DC current applied to the device under test by the current source, thereby stabilizing the junction temperature of the device under test to the target junction temperature.

[0077] When the specified temperature is lower than the target junction temperature, the ambient temperature is lower than the temperature of the device under test, and the device itself generates heat, the device temperature can be higher than the ambient temperature and eventually stabilize at the target junction temperature.

[0078] In some embodiments, the heating step specifically involves setting the temperature of the high-temperature ambient chamber to a relatively high value (e.g., a specified temperature of 140°C) and stabilizing the ambient temperature; eliminating the need to activate the active cooling system (reducing costs and simplifying the system); applying a drive voltage to the device gate to fully turn on the device; simultaneously applying a DC current from a current source, initially set to 70%-90% of the device's rated current Irated, causing the device to generate self-heat; and combining ambient heating (140°C) and self-heating (Irated)... 2 Due to the combined effects of R (residual heat loss), the junction temperature of the device gradually increases. A feedback control system monitors the junction temperature in real time and adjusts the load current to ensure a slow and stable rise to the target temperature. Once the junction temperature stabilizes at the target value (e.g., target junction temperature = 180℃), testing begins. With an ambient temperature of 140℃ lower than the target junction temperature of 180℃, the temperature difference is bridged by adjusting the device's self-heating, creating a temperature gradient. This approach is more suitable for initial feasibility assessments or cost-sensitive applications.

[0079] Through a dual-channel independent control mechanism (using cooling + current in some embodiments, and only current regulation in others), the device junction temperature can be precisely controlled and stabilized at the target junction temperature, realistically simulating high-temperature conduction conditions in actual applications. Using cooling + current is physically sound and allows for more rigorous testing; using only current regulation simplifies the system and makes it more flexible in application.

[0080] Reference Figure 1 , Figure 2 and Figure 3 In some embodiments of the present invention, during the cooling step, the heating power of the high-temperature environment chamber and the magnitude of the DC current applied to the device under test by the current source are gradually reduced. When the high-temperature environment chamber has reduced the ambient temperature by a specified amount, the heating power of the high-temperature environment chamber and the magnitude of the DC current applied to the device under test by the current source are kept unchanged for a specified time. Then, the heating power of the high-temperature environment chamber and the magnitude of the DC current applied to the device under test by the current source are gradually reduced until the junction temperature of the device under test reaches room temperature.

[0081] 'Gradual reduction' means reducing the power at a certain percentage or according to a function curve. Specifically, this typically involves reducing the power at fixed intervals, such as reducing the heating power and DC current by 10% every 10 minutes. Alternatively, it can be reduced according to the function power (current) = ab * t, where a and b are positive numbers and t is time. More specifically, if the ambient temperature is specified as 10℃ and the initial ambient temperature is 220℃, then the cooling process would involve the ambient temperature changing from 220℃ to 210℃ to 200℃, and so on, until stabilizing at each temperature step for 5-10 minutes. Furthermore, during the stabilization phase of the temperature steps (i.e., within a specified time), the electrical parameters of the device under test can be measured to enrich the test data, which is beneficial for subsequent statistical analysis. It's important to understand that if the test involves an active cooling system, the power of the active cooling system must be reduced synchronously and gradually.

[0082] During the cooling process, control parameters are adjusted synchronously to ensure that the junction temperature decreases slowly and steadily with the ambient temperature, avoiding thermal shock. The step-cooling strategy avoids the thermal shock of the device caused by a large instantaneous temperature difference, and prevents the test itself from causing unnecessary mechanical stress and damage to the device, so that the test results can more accurately reflect long-term natural aging.

[0083] Reference Figure 1 , Figure 2 and Figure 3 In some embodiments of the present invention, during the testing or cooling steps, the failure time of each device under test is recorded; during the calculation step, the average failure time t1 of all failed devices under test is calculated; the total time t2 of the testing steps is recorded; and the acceleration factor AF is calculated. The formula for calculating the acceleration factor AF is as follows:

[0084] ;

[0085] in:

[0086] E a This refers to the activation energy of a silicon carbide MOSFET.

[0087] k B The Boltzmann constant is 8.617 × 10⁻⁶. -5 eV / K;

[0088] T test Target junction temperature;

[0089] T use This is the actual junction temperature;

[0090] MTTF (Mean Time To Failure Rate) is calculated using a failure rate conversion formula. use :

[0091] ;

[0092] ;

[0093] ;

[0094] in:

[0095] N f This represents the number of failed devices under test.

[0096] N t This represents the total number of devices under test.

[0097] If all devices under test fail during the cyclic test steps, then t = t1; otherwise, t = t2.

[0098] λ stress To test the failure rate;

[0099] λ use To estimate the actual failure rate.

[0100] E a The activation energy of a silicon carbide MOSFET can be obtained by consulting relevant literature; commonly used is E. a A value of 0.8 is a typical parameter commonly used in wide-bandgap semiconductor devices (such as silicon carbide MOSFETs). The calculation formula for the acceleration factor AF is a typical application of the Arrhenius model. The acceleration factor AF can be used to correct the test failure rate to the estimated actual failure rate. As for the choice of test time t, since the subsequent test time is meaningless when all devices have failed, and it represents the measured lifetime of the silicon carbide MOSFET at the target junction temperature, the measured lifetime can be directly corrected by the acceleration factor AF (multiplied by the acceleration system AF) to obtain the estimated lifetime of the silicon carbide MOSFET at the actual junction temperature. When not all devices have failed, the estimated lifetime can be calculated using the failure rate conversion formula.

[0101] It should be understood that this embodiment is only one possible and temporary calculation method for estimating the lifespan of the device under test at the actual junction temperature. For example, the number of samples that meet the failure criteria out of N test samples can be counted, parameter degradation curves can be plotted, and the degradation curves can be fitted to estimate the lifespan of the device at the actual junction temperature. Because this test method has high reliability and can collect and record electrical parameters during the process, it can be comprehensively statistically analyzed. Therefore, in subsequent developments, the above calculation method and formula may be modified, improved, or even partially or completely abandoned, and a new method may be adopted to calculate the estimated lifespan. This is also because the actual test method steps of this invention have high reliability and complete data collection and recording.

[0102] Reference Figure 1 , Figure 2 and Figure 3 In some embodiments of the present invention, an analysis step is also included, in which physical failure analysis is performed on the failed device under test after the cooling step.

[0103] The calculation step involves analyzing and statistically processing high-temperature electrical parameters, intermediate electrical parameters, and initial electrical parameters to estimate the lifetime of the device under test (DUT) at the actual junction temperature. This primarily involves data processing and analysis. The analysis step allows for physical failure analysis (physical analysis) of failed or near-failure samples. This includes dissection observation, scanning electron microscopy (SEM), and transmission electron microscopy (TEM) analysis to determine the main failure mechanisms. Further research into the chronic degradation mechanisms (such as threshold voltage drift, increased on-resistance, and gate oxide degradation) and failure modes of silicon carbide MOSFETs under high-temperature conduction environments allows for better design or process improvement based on the failure mechanism analysis results, thereby enhancing product reliability. It's important to understand that the analysis step can also include a final comprehensive inspection of each device, going beyond simply measuring common electrical parameters.

[0104] Specifically, let's take a hypothetical example: Visual inspection: No obvious discoloration or cracks on the chip surface, no cracks or metal migration signs on leads and solder joints. Conclusion: This failure mode is mainly caused by internal mechanisms (non-mechanical damage). Scanning electron microscopy (SEM) analysis: Micropores (0.1-1 μm in size) were found at the gate contact area at the interface between the gate oxide layer and the semiconductor, and the oxide layer thickness was uneven, with some areas thickened. It is speculated that the main failure mechanism is the accumulation of traps at the gate oxide layer interface and the formation of micropores, leading to threshold voltage drift and increased on-resistance. Transmission electron microscopy (TEM) analysis: Atomic-scale observation revealed defect clusters in the oxide layer, further confirming that the accumulation of hot carriers and electron traps under high-temperature long-term conduction conditions is the main cause of failure. Final failure analysis conclusion: The failure mode in this test is mainly gate oxide layer degradation, rather than metal layer electromigration or other mechanisms. Recommendations: Improve oxide layer quality control in the process, optimize gate oxide layer thickness and composition, and enhance the device's resistance to aging at high temperatures.

[0105] Reference Figure 1 , Figure 2 and Figure 3 According to an embodiment of the present invention, a reliability testing system for silicon carbide MOSFETs is used to test the device under test in the above-described reliability testing method. The system includes: a high-temperature environmental chamber for placing the device under test; a driving circuit for connecting to the device under test and applying a driving voltage to the gate of the device under test; a current source for connecting to the device under test and applying a direct current to the device under test; a temperature sensor for connecting to the device under test and measuring the temperature of the device under test; and an electrical parameter acquisition system for connecting to the device under test and acquiring the electrical parameters of the device under test.

[0106] A high-temperature environmental chamber raises the temperature inside, providing a high-temperature environment for the device under test (DUT) to simulate the harsh high-temperature operating conditions of silicon carbide MOSFETs in real-world applications. It's important to understand that high-temperature environmental chambers typically include a built-in temperature sensor and control system. The chamber can be pre-set to a predetermined temperature, the temperature sensor monitors the ambient temperature in real time, and the control system maintains the ambient temperature around the predetermined level. In some embodiments, the chamber includes or has additional test fixtures to hold the DUT in place and provide heat dissipation channels, thus offering some cooling functionality. The temperature of the DUT may differ from the ambient temperature inside the high-temperature environmental chamber (due to self-heating, active cooling systems, etc.), therefore, an additional temperature sensor is needed to monitor the DUT's temperature in real time. The temperature sensor typically contacts the DUT directly, resulting in more accurate and faster detection results.

[0107] The drive circuit is connected to the gate and source of the device under test (DUT) and applies a positive voltage (typically +15V to +20V) to the gate to turn the device on. This simulates the switching state during actual operation for subsequent electrical characteristic testing.

[0108] A current source is electrically connected to the drain and source of the device under test (DUT) to provide a constant current or constant voltage output that matches the device's rated current. Specifically, the current source can output a stable DC current or an adjustable pulse current to meet the needs of different test conditions.

[0109] In some embodiments, a temperature sensor specifically involves installing a thermocouple on the surface of the device and / or inside a high-temperature environment chamber (e.g., a high-temperature environment chamber without temperature detection function) to monitor the ambient temperature and the junction temperature of the device in real time.

[0110] An electrical parameter acquisition system can consist of high-precision multimeters or data acquisition cards to record electrical parameters such as drain-source voltage Vds, drain-source current Ids, gate-source voltage Vgs, and junction temperature Tj in real time.

[0111] The feedback controller, specifically, can employ a PID algorithm to automatically adjust the cooling power and load current (the current applied to the device under test by the current source) to ensure accurate and stable junction temperature of the device.

[0112] Active cooling systems can employ semiconductor cooling, liquid cooling, or air cooling. The heat sink in an active cooling system has sufficient contact area with the device under test, and the heat transfer medium is evenly distributed, facilitating heat dissipation.

[0113] It is important to understand that the reliability testing system for silicon carbide MOSFETs (hereinafter referred to as the test system) may also include a feedback controller, which is connected to a current source (and possibly an active cooling system) to control the junction temperature of the device under test; it is also important to understand that the test system may include an active cooling system, which is used to (directly or indirectly) connect to the device under test to cool it down.

[0114] It's important to understand that the test system can also include a control calculator, a high-temperature environmental chamber, drive circuits, current sources, temperature sensors, an electrical parameter acquisition system, an active cooling system, and a feedback controller, all connected to the control calculator to automatically control the test process, data acquisition, and analysis. Specifically, specialized software can be developed to support automated test protocols, data storage, and visualization. Automated test control automatically executes steps such as heating, temperature control, and cooling according to the process, supporting automatic switching between Scheme A (specified temperature greater than the target junction temperature, with an active cooling system) and Scheme B (specified temperature less than the target junction temperature, without an active cooling system), reducing human intervention; real-time data acquisition and monitoring: high-frequency sampling of electrical parameters (≥1kHz), real-time display of temperature and parameter change curves; anomaly alarm: automatic alarm and recording when abnormal parameter deviations are detected; feedback control execution: based on a PID algorithm, real-time adjustment of cooling power and / or load current to maintain junction temperature stability (±0.5℃ accuracy); data storage and analysis: storing all test data in a database, supporting multi-dimensional queries and statistical analysis; report generation: automatically generating test reports, including parameter degradation curves, failure determination results, statistical analysis, etc.

[0115] The testing method of this invention has the following advantages: High realism: Combining environmental heating and self-heating mechanisms, it can accurately simulate the high temperature and high current conduction conditions experienced by silicon carbide MOSFETs in actual applications; Comprehensive evaluation: Through ultra-long-term testing (2688 hours) and multi-stage cycling, it can induce the chronic degradation mechanism of the device within a controllable time, obtaining a complete degradation curve of parameters over time; Minimized damage: The stepped heating and cooling strategy avoids the thermal shock of the device caused by instantaneous large temperature differences, allowing the test results to truly reflect the natural aging process; Efficiency and depth: Within a limited testing time, high-temperature accelerated aging effectively improves testing efficiency, while also estimating the expected lifespan of the device at actual operating temperatures; Standardization and comparability: It provides clear test procedures, parameter settings, test times, and failure criteria, making the test results of different research institutions comparable; Guidance for design improvement: Detailed failure mechanism analysis can guide device manufacturers and system designers to make targeted improvements and improve product reliability; Strong adaptability: It provides two temperature control schemes, Scheme A and Scheme B, to adapt to different application scenarios (high-end high reliability vs. initial evaluation / cost sensitive), etc.

[0116] The reliability testing method for silicon carbide MOSFETs under high temperature and long-term conduction conditions of the present invention has broad application prospects:

[0117] In device manufacturing applications: Quality assurance: This testing method assesses the reliability of newly developed or improved silicon carbide MOSFET designs, guiding process improvements and finished product selection; Reliability certification: Provides reliability data support for products, enhancing market competitiveness; Failure prevention: Based on failure mechanism analysis results, proactive design or process improvement measures are implemented; Cost optimization: Supports Option B for initial evaluation, reducing certification costs. In system application applications: Device selection: In applications such as new energy vehicles and industrial power supplies, devices with higher reliability are selected based on the test results; Design verification: Verifies the suitability of selected devices under extreme operating conditions at the system level; Risk assessment: Predicts potential reliability risks during long-term operation; Lifetime prediction: Accurate lifetime estimation based on the Arrhenius model guides system reliability design; In standardization applications: Standard development: Provides the technical foundation for the development of silicon carbide MOSFET reliability testing standards; International alignment: Promotes international standardization of SiC reliability assessment, fostering standardized industry development; Academic exchange: Provides a reliable testing methodology foundation for the industry; Standardization: Supports flexibility while ensuring comparability of results.

[0118] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method of reliability testing of a silicon carbide MOSFET, characterized by, Includes the following steps: Preparation: Multiple silicon carbide MOSFETs to be tested are used as devices under test. The devices under test are placed in a high-temperature environment chamber, and the devices under test are connected to a drive circuit, a current source, a temperature sensor, and an electrical parameter acquisition system. Initially, the initial electrical parameters of the device under test are measured and recorded at room temperature (20-30°C). The cyclic test is set to a maximum number of cycles N, with the initial number of cycles being zero. The heating step, the testing step, and the cooling step are performed sequentially, and the number of cycles is incremented by one. The cyclic test ends when the number of cycles reaches the maximum number of cycles N or when all devices under test fail; otherwise, the cyclic test continues. The heating step is as follows: the high-temperature environment chamber is set to a specified temperature; a driving voltage is applied to the gate of the device under test through the driving circuit to turn on the device under test; and a DC current is applied to the device under test through the current source to cause the device under test to self-heat. Under the combined effect of the ambient temperature and the self-heating of the device under test, the junction temperature of the device under test rises to the target junction temperature and remains stable. The initial magnitude of the DC current is 70%-90% of the rated current of the device under test, and the target junction temperature is not less than 150°C. The testing steps are as follows: stabilizing the junction temperature of the device under test (DUT) to the target junction temperature, keeping the DUT on, and continuously monitoring the high-temperature electrical parameters of the DUT in real time through the electrical parameter acquisition system for a specified testing time. The cooling step involves lowering the junction temperature of the device under test to room temperature, measuring and recording the intermediate electrical parameters of the device under test, comparing the intermediate electrical parameters with the initial electrical parameters based on a predetermined failure criterion, determining whether the device under test has failed, and removing the failed device under test from the high-temperature environment chamber. After the cyclic test steps are completed, the estimated lifetime of the device under test at the actual junction temperature is calculated based on the high-temperature electrical parameters, the intermediate electrical parameters, and the initial electrical parameters. In the test step or the cooling step, the failure time of each device under test is recorded. In the calculation step, the average failure time t1 of all failed devices under test is calculated. Record the total time t2 spent on each test step; calculate the acceleration factor AF, the formula for which AF is calculated is: ； in: activation energy for silicon carbide MOSFETs; Boltzmann's constant, 8.617 x 10 -5 eV / K; for the target junction temperature; Tj is the actual junction temperature; The estimated life is calculated using a failure rate conversion formula : ； ； ； in: This represents the number of failed devices under test. This represents the total number of devices under test. If all devices under test fail during the cyclic test steps, then t = t1; otherwise, t = t2. To test the failure rate; To estimate the actual failure rate.

2. The reliability testing method for silicon carbide MOSFETs according to claim 1, characterized in that, The initial electrical parameters, the high-temperature electrical parameters, and the intermediate electrical parameters all include the on-resistance of the device under test.

3. The reliability testing method for silicon carbide MOSFETs according to claim 2, characterized in that, The conduction resistance in the initial electrical parameters is the initial conduction resistance, and the conduction resistance in the intermediate electrical parameters is the intermediate conduction resistance. The difference between the intermediate conduction resistance and the initial conduction resistance is obtained by subtracting the initial conduction resistance from the intermediate conduction resistance. The percentage value of the difference between the intermediate conduction resistance and the initial conduction resistance is obtained by dividing the difference between the intermediate conduction resistance and the failure criterion is that the percentage value of the difference between the intermediate conduction resistance and the initial conduction resistance is greater than a preset failure percentage value.

4. The reliability testing method for silicon carbide MOSFETs according to claim 3, characterized in that, In the test steps: at the beginning of the test steps, the on-resistance in the high-temperature electrical parameters is recorded as the initial high-temperature on-resistance; from the beginning to the end of the test steps, the on-resistance in the high-temperature electrical parameters is recorded in real time as the real-time high-temperature on-resistance; the real-time high-temperature on-resistance difference is obtained by subtracting the initial high-temperature on-resistance from the real-time high-temperature on-resistance difference, and the percentage value of the real-time high-temperature on-resistance difference is obtained by dividing the real-time high-temperature on-resistance difference by the initial high-temperature on-resistance difference; when the percentage value of the real-time high-temperature on-resistance difference of a device under test is greater than a preset abnormal percentage value, the time is recorded, and the device under test is marked as an abnormal individual; after the cooling step, it is recorded whether the abnormal individual has failed.

5. The reliability testing method for silicon carbide MOSFETs according to claim 1, characterized in that, The device under test (DUT) is also connected to a feedback controller and an active cooling system. The specified temperature is greater than the target junction temperature. During the heating and testing steps, the feedback controller adjusts the magnitude of the DC current applied to the DUT by the current source and adjusts the cooling power of the active cooling system to stabilize the junction temperature of the DUT at the target junction temperature.

6. The reliability testing method for silicon carbide MOSFETs according to claim 1, characterized in that, The device under test is also connected to a feedback controller. The specified temperature is lower than the target junction temperature. During the heating and testing steps, the feedback controller adjusts the magnitude of the DC current applied to the device under test by the current source, thereby stabilizing the junction temperature of the device under test to the target junction temperature.

7. The reliability testing method for silicon carbide MOSFETs according to claim 1, characterized in that, In the cooling step, the heating power of the high-temperature environment chamber and the magnitude of the DC current applied to the device under test by the current source are gradually reduced. When the high-temperature environment chamber reduces the ambient temperature by a specified amount, the heating power of the high-temperature environment chamber and the magnitude of the DC current applied to the device under test by the current source are kept unchanged for a specified time. Then, the heating power of the high-temperature environment chamber and the magnitude of the DC current applied to the device under test by the current source are gradually reduced until the junction temperature of the device under test reaches room temperature.

8. The reliability testing method for silicon carbide MOSFETs according to claim 1, characterized in that, It also includes an analysis step, after which physical failure analysis is performed on the failed device under test.

9. A reliability testing system for silicon carbide MOSFETs, used to test the device under test in the reliability testing method according to any one of claims 1 to 8, characterized in that, include: A high-temperature environment chamber is used to house the device under test; A driving circuit is used to connect to the device under test (DUT) and thereby apply a driving voltage to the gate of the DUT. A current source is used to connect to the device under test (DUT) so as to apply a direct current to the DUT. A temperature sensor is used to connect to the device under test (DUT) to measure the temperature of the DUT. An electrical parameter acquisition system is used to connect to the device under test (DUT) and acquire its electrical parameters.

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