ATE test method and system for accelerating data operation

Abstract

The invention provides an ATE test method and system for accelerating data operation, and the method comprises the steps: collecting data of a plurality of to-be-tested devices at the same time, storing the data as a matrix structure according to a fixed bit width, each row of the matrix corresponding to a test period, and each row of data containing mixed data from the plurality of to-be-tested devices; a plurality of parallel threads are started, each thread is responsible for processing data of one test period, and the data, mixed together in one test period, of the to-be-tested devices are separated into independent memory areas distributed for the to-be-tested devices in advance according to a preset rule; performing preset algorithm processing on the separated data of each to-be-tested device; and analyzing the processing result and generating a report. By organizing the data of the to-be-tested devices in a matrix structure and introducing a parallel thread processing mechanism, efficient parallel processing of the test data is realized, the test efficiency is improved, and the test time can be shortened.

Description

Technical Field

[0001] This invention relates to the field of automated test equipment for integrated circuits, and more particularly to an ATE test method and system for accelerating data processing. Background Technology

[0002] The typical workflow of existing ATE digital boards includes: First, the test board captures raw test data output by the device under test (DUT), such as logic levels and timing signals, through digital channels; second, this raw data is transmitted to the onboard or system-level CPU via a bus, where the CPU executes algorithms for error detection, data comparison, and statistical analysis; finally, the CPU generates a test report and feeds it back to the control system. This centralized data processing architecture has significant bottlenecks when handling large-scale test data.

[0003] With the development of modern chip technology, the amount of test data has increased dramatically. For example, the test data traffic of 5G communication chips has reached the GB / s level, while the processing speed of traditional CPUs can no longer match the data generation capabilities of high-speed digital channels. This mismatch between data processing capabilities and data generation rates leads to longer test times, decreased equipment utilization, and consequently, a significant increase in test costs. Against the backdrop of cost reduction and efficiency improvement in the current semiconductor industry, the limitations of traditional ATE architectures are becoming increasingly apparent, necessitating the development of new, efficient data processing methods to meet the challenges of modern chip testing. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problem that the CPU processing power in the traditional ATE architecture cannot match the data generation rate of high-speed digital channels.

[0005] A first aspect of the present invention provides an ATE testing method for accelerating data processing based on a data processing module, comprising:

[0006] Simultaneously, data from multiple devices under test are collected and stored in a matrix structure with a fixed bit width. Each row of the matrix corresponds to a test cycle, and each row of data contains mixed data from multiple devices under test.

[0007] Multiple parallel threads are started, each thread is responsible for processing the data of one test cycle, and the data of multiple devices under test mixed together in one test cycle are separated into independent memory areas pre-allocated for each device under test according to predetermined rules;

[0008] The data from each separated device under test are processed using a preset algorithm.

[0009] Analyze the results and generate a report.

[0010] Furthermore, the step of initiating multiple parallel threads is preceded by:

[0011] Receive the startup command;

[0012] Allocate memory space for storing input data;

[0013] Allocate independent memory spaces for the data of multiple devices under test;

[0014] The collected data is copied from the collection area to the processing area.

[0015] Furthermore, the parallel thread processing method is as follows:

[0016] Based on the preset bit width definition and allocation rules, data segments belonging to each device under test are extracted from the mixed data of the current test cycle, and these data segments are written to the designated locations in the independent storage areas of the corresponding devices under test, until the data of all test cycles has been separated and redistributed.

[0017] Furthermore, the algorithm used in the preset algorithm processing includes at least one of FFT analysis or eye diagram reconstruction.

[0018] A second aspect of the present invention provides an ATE board system for accelerating data processing based on a data processing module, employing the ATE testing method for accelerating data processing as described in any of the preceding claims, comprising:

[0019] The data acquisition and control module is used to acquire data from multiple devices under test.

[0020] The data storage module stores the data in a matrix structure with a fixed bit width, where each row of the matrix corresponds to a test cycle, and each row of data contains mixed data from multiple devices under test.

[0021] The data processing module starts multiple parallel threads, each thread is responsible for processing the data of one test cycle. The parallel threads are used to separate the data of multiple devices under test that are mixed together into multiple memory regions according to a predetermined bit width; and to process the data of each separated device under test by a preset algorithm.

[0022] The control module analyzes and processes the data and generates reports.

[0023] Furthermore, the data acquisition and control module includes multiple FPGA chips, which work together to control the test timing, generate test vectors, and synchronously acquire test data from multiple devices under test.

[0024] Furthermore, the data acquisition and control module includes multiple channels for simultaneously acquiring test data from multiple devices under test.

[0025] Furthermore, the data storage module is a DDR memory used to store data to be processed and data that has already been processed.

[0026] Furthermore, the test data is stored in the DDR memory in a fixed matrix structure, wherein each row of the matrix contains data from multiple devices under test in the same test cycle, and each device under test occupies a fixed bit width.

[0027] Furthermore, the control module includes a control chip, which is used to manage the system startup process, control data flow, analyze and process results, and generate test reports.

[0028] Compared with existing technologies, the present invention has at least the following beneficial effects: by organizing the data of multiple devices under test in a matrix structure and introducing a parallel thread processing mechanism, efficient parallel processing of test data is achieved, improving test efficiency and shortening test time; at the same time, the matrix data storage structure optimizes memory access mode, reduces random access latency, and makes full use of the caching mechanism of modern processors; and the data separation strategy based on thread ID avoids complex thread synchronization mechanisms, eliminates inter-thread competition, and enables the data of each device under test to be efficiently separated and processed independently by the algorithm. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] Figure 1 This is a flowchart of an ATE testing method according to an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the ATE test system in one embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of the data bit allocation of different devices under test during the test cycle in one embodiment of the present invention. Detailed Implementation

[0033] The present invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being broadly known to those skilled in the art and is not intended to limit the invention.

[0034] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0035] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0036] In a first aspect, this invention provides an ATE testing method based on a data processing module to accelerate data processing. Please refer to [reference needed]. Figure 1 and Figure 3 ,include:

[0037] Simultaneously, data from multiple devices under test are collected and stored in a matrix structure with a fixed bit width. Each row of the matrix corresponds to a test cycle, and each row contains mixed data from multiple devices under test.

[0038] Multiple parallel threads are started, each thread is responsible for processing the data of one test cycle. The data of multiple devices under test that are mixed together in one test cycle are separated into independent memory areas pre-allocated for each device under test according to predetermined rules.

[0039] The data of each device under test after separation are processed by a preset algorithm.

[0040] Analyze the results and generate a report.

[0041] Specifically, in matrix-structured storage, the fixed bit width can be set to 32 bits, 64 bits, or 128 bits, depending on the number of devices under test and the data type. Parallel threads can be initiated using a multi-core CPU or GPU, with the number of threads being the same as or proportional to the number of test cycles. Predefined rules for data separation include bitwise truncation, mask extraction, or address mapping. Bitwise truncation is suitable for contiguous data, mask extraction for interleaved data, and address mapping for non-contiguous data. Independent memory regions can use physically isolated memory blocks or virtual memory spaces, with memory allocation strategies including static pre-allocation or dynamic on-demand allocation. The specific algorithm used for preset processing is selected based on test requirements. Report generation can use standardized templates or custom formats, including pass / fail indicators, performance parameters, or waveform charts.

[0042] The parallel data processing architecture addresses the insufficient data processing speed of traditional ATE systems. The matrix-style storage structure enables efficient organization of test data, facilitating parallel access and processing. A multi-threaded separation mechanism allocates mixed data to independent memory regions in real time, avoiding data contention and serial processing latency. Independent processing of data from each device under test improves the isolation and accuracy of test results. Compared to existing technologies, this approach increases data processing throughput, matching the test data generation rate of high-speed digital channels, thereby shortening test time and improving equipment utilization. The main technological advantages lie in the improved data processing efficiency, specifically manifested in shorter test cycles and reduced system resource consumption.

[0043] Furthermore, the step of initiating multiple parallel threads is preceded by:

[0044] Receive the startup command.

[0045] Allocate memory space for storing input data.

[0046] Allocate independent memory spaces for the data of multiple devices under test.

[0047] The collected data is copied from the collection area to the processing area.

[0048] The startup command can be received via a hardware interrupt signal or a software instruction. Specific implementation methods include, but are not limited to, receiving external trigger signals via GPIO pins or receiving control instructions sent from a host computer via a PCIe interface. When allocating input data memory space, a contiguous address allocation strategy or a paging management mechanism can be used, with the memory capacity dynamically adjusted based on the total amount of test data. When allocating independent memory space for the device under test, the addresses of each region must not overlap, and the memory boundaries must be aligned according to a preset bit width. Data copy operations are completed through a DMA controller, supporting burst transfer mode to improve efficiency. A data integrity verification mechanism must be maintained during the copy process.

[0049] By pre-allocating memory and pre-processing data copies, a structured data foundation is provided for subsequent parallel threads. Pre-allocation of memory space avoids latency caused by dynamic allocation, and the design of independent storage areas eliminates multi-threaded access conflicts. The data preprocessing step transforms the raw collected data into a format that threads can directly process, reducing computational overhead during real-time processing. Compared to existing technologies, by optimizing memory management and data preparation processes, parallel processing efficiency is improved, making it particularly suitable for high-speed, large-data-volume testing scenarios.

[0050] Furthermore, the parallel thread processing method is as follows:

[0051] Based on the preset bit width definition and allocation rules, data segments belonging to each device under test are extracted from the mixed data of the current test cycle, and these data segments are written to the designated locations in the independent storage areas of the corresponding devices under test, until the data of all test cycles has been separated and redistributed.

[0052] Specifically, the preset bit width definition can be configured based on the test requirements of the device under test (DUT), for example, the data bit width of each DUT can be 32 bits or 64 bits. Allocation rules can include round-robin allocation, priority allocation, or dynamic allocation based on the test cycle. As a preferred implementation, the bit width definition and allocation rules can be stored in a configuration file and loaded by the control module during system initialization. Data segment extraction can be achieved through bitmasking operations or shift operations, where bitmasking operations are suitable for fixed-width data extraction, and shift operations are suitable for variable-width data extraction. The independent storage area can employ a double-buffering mechanism, with one buffer for receiving new data and the other for processing already received data, thereby achieving seamless data switching.

[0053] By using parallel threads to separate and redistribute mixed data in real time, the mismatch between data processing and data generation rates in traditional centralized processing architectures is resolved. Since each thread independently processes data for one test cycle, serial bottlenecks in data processing are avoided. Predefined bit width definitions and allocation rules make the data separation process configurable and flexible, adaptable to the needs of different testing scenarios. The use of independent storage areas stabilizes the isolation and security of data processing, preventing data confusion and conflicts.

[0054] Furthermore, the algorithm used in the preset algorithm processing includes at least one of FFT analysis or eye diagram reconstruction.

[0055] Specifically, FFT analysis is used to perform frequency domain analysis on the separated data of each device under test (DUT) to quickly identify frequency components or noise characteristics in the signal. For example, in high-speed digital signal testing, FFT can be used to detect signal integrity or clock jitter issues. As a preferred implementation, the FFT algorithm can be optimized through parallel computing to match multi-threaded data processing architectures, thereby improving computational efficiency.

[0056] Eye diagram reconstruction is used to evaluate the timing and amplitude characteristics of digital signals. It forms an eye diagram by superimposing multiple cycles of the signal, providing a visual reflection of signal quality. For example, in high-speed serial interface testing, eye diagram reconstruction can help identify inter-symbol interference or noise. Furthermore, eye diagram reconstruction can be implemented using hardware accelerators, such as leveraging the parallel computing capabilities of FPGAs, to improve data processing speed.

[0057] By introducing FFT analysis or eye diagram reconstruction algorithms, efficient data processing capabilities can be provided for different types of testing needs. Compared with existing technologies, it avoids the performance bottleneck of centralized CPU processing and utilizes a parallel computing architecture to achieve high-speed data processing, thereby shortening testing time and improving testing efficiency.

[0058] A second aspect of the present invention provides an ATE board system for accelerating data processing based on a data processing module. Please refer to [reference needed]. Figure 2 The ATE test method for accelerating data processing as described in any of the preceding items includes:

[0059] The data acquisition and control module is used to acquire data from multiple devices under test.

[0060] The data storage module stores the data in a matrix structure with a fixed bit width, where each row of the matrix corresponds to a test cycle, and each row of data contains mixed data from multiple devices under test.

[0061] The data processing module starts multiple parallel threads, each thread is responsible for processing the data of one test cycle. The parallel threads are used to separate the data of multiple devices under test that are mixed together into multiple memory regions according to a predetermined bit width; and to process the data of each separated device under test by a preset algorithm.

[0062] The control module analyzes and processes the data and generates reports.

[0063] Specifically, the data acquisition and control module may include one or more FPGA chips that work collaboratively to control test timing, generate test vectors, and simultaneously acquire test data from multiple devices under test (DUTs). The data acquisition and control module may also include multiple channels for simultaneously acquiring test data from multiple DUTs. The data storage module may use DDR memory to store both pending and processed data. Test data is stored in the DDR memory according to a fixed matrix structure, where each row of the matrix contains data from multiple DUTs in the same test cycle, with each DUT occupying a fixed bit width. The control module may include a control chip that manages the system startup process, controls data flow, analyzes and processes results, and generates test reports.

[0064] By employing parallel processing and data separation, the mismatch between data processing capabilities and data generation rates in traditional ATE architectures is effectively resolved. Specifically, by separating mixed data into multiple memory regions according to predetermined bit widths and using parallel threads for processing, data processing efficiency is improved. Simultaneously, the matrix-style data storage structure and fixed bit width allocation rules ensure accuracy and consistency in data processing.

[0065] In this embodiment, the data acquisition and control module includes multiple FPGA chips. These multiple FPGA chips work together to control the test timing, generate test vectors, and synchronously acquire test data from multiple devices under test.

[0066] Specifically, multiple FPGA chips collaborate via a high-speed interconnect bus, with each FPGA chip managing a set of test channels. Test timing control is implemented through an internal state machine within the FPGA, which generates precise timing signals according to a preset test procedure. Test vectors are generated by an internal vector generation module within the FPGA, which can be configured to generate test vectors in fixed or random patterns. Synchronous acquisition is achieved through an internal clock domain cross-connect module within the FPGA, ensuring strict time alignment of test data from multiple devices under test.

[0067] A distributed FPGA architecture enables precise control of test timing and high-speed acquisition of test data. Compared to traditional centralized CPU processing architectures, the parallel processing capability of multiple FPGA chips effectively solves the problem of mismatch between test data flow and processing capacity. The control precision of test timing is improved, the efficiency of test vector generation is increased, and test data from multiple devices under test can be acquired in a strictly synchronous manner. This architecture is particularly suitable for high-speed digital testing scenarios requiring the processing of GB / s level test data flows.

[0068] Furthermore, the data acquisition and control module includes multiple channels for simultaneously acquiring test data from multiple devices under test.

[0069] Specifically, the implementation of multiple channels can include: each channel having an independent physical interface, with signal isolation and synchronous acquisition achieved through hardware circuitry; or employing multiplexing technology, sharing some hardware resources through time-division multiplexing or frequency-division multiplexing. As a preferred implementation, the channels adopt a high-speed serial interface design, supporting LVDS or JESD204B protocols to meet high-bandwidth testing requirements. Furthermore, each channel can be configured with independent sampling rates, trigger conditions, and data buffer depths to adapt to the testing requirements of different devices under test. Thus, the parallel acquisition capability of multiple channels can effectively improve test throughput.

[0070] To address this issue, a multi-channel parallel acquisition architecture is employed to improve the insufficient data acquisition bandwidth of traditional ATE systems in high-speed testing scenarios. Because multiple channels can operate independently, the testing system can simultaneously capture the output signals of multiple devices under test (DUTs), avoiding the time delays caused by sequential acquisition. After synchronous acquisition through each channel, the test data can be directly sent to subsequent processing modules for real-time analysis, thereby shortening the overall testing cycle.

[0071] Furthermore, the data storage module is a DDR memory used to store data to be processed and data that has already been processed.

[0072] Specifically, the DDR memory employs Double Data Rate Synchronous Dynamic Random Access Memory technology, whose high bandwidth characteristics can meet the real-time storage requirements of multi-channel test data. As a preferred implementation, the DDR memory is configured with a capacity of 16GB and an operating frequency of 3200MHz, connected to the data processing module via a 64-bit wide bus. Furthermore, the fixed bit width in the matrix storage structure can be dynamically adjusted according to the type of device under test (DUT). For example, for 8-bit digital signal testing, each device is allocated 8 bits of storage space; for 16-bit analog signal testing, 16 bits of storage space are allocated. Thus, through predefined storage mapping rules, the mixed data of each test cycle can be accurately segmented and located to the corresponding storage area.

[0073] By employing DDR memory as the data storage medium and combining it with a matrix storage structure design, the problem of insufficient data storage bandwidth in traditional ATE systems is effectively addressed. The high throughput of DDR memory enables real-time storage of large-scale test data, while the fixed-width matrix storage structure provides a standardized data organization format for subsequent parallel data processing. Compared to existing solutions using ordinary memory or hard disk storage, this technology increases data storage bandwidth by 3-5 times, while reducing data access latency through a hardware-level storage address mapping mechanism. Thus, data processing efficiency is significantly improved while maintaining the original test accuracy.

[0074] Furthermore, the test data is stored in the DDR memory in a fixed matrix structure, wherein each row of the matrix contains data from multiple devices under test in the same test cycle, and each device under test occupies a fixed bit width.

[0075] Specifically, the matrix-style storage structure is implemented as follows: the DDR memory is divided into contiguous storage blocks, each block corresponding to a test cycle. Within each block, sub-regions are divided according to bit width, equal to the number of devices under test (DUTs). For example, when the test system is configured with 8 DUTs and each device is allocated 32 bits of bandwidth, the total width of the storage block corresponding to each test cycle is 256 bits. The first 32 bits store the data for the first device, the next 32 bits store the data for the second device, and so on. This storage method can be implemented through an address mapping mechanism, where the storage location of each device is determined by the base address plus the test cycle number multiplied by a fixed offset.

[0076] By employing a predefined matrix structure and fixed bit-width allocation, efficient storage management of test data from multiple devices is achieved. The contiguous storage characteristic of data in DDR makes memory access patterns predictable, and combined with parallel thread processing mechanisms, memory access conflicts can be effectively reduced. Compared with the distributed storage methods in existing technologies, this structure eliminates the address calculation overhead during data reassembly, allowing data separation operations to be completed directly through bit operations, thereby improving data processing throughput.

[0077] Furthermore, the control module includes a control chip, which is used to manage the system startup process, control data flow, analyze and process results, and generate test reports.

[0078] The control chip can be implemented using an embedded processor or a programmable logic device, such as an ARM architecture processor or an FPGA chip. In specific implementations, the control chip performs the following operations through a preset firmware program: First, it initializes the various functional modules of the system, including the data acquisition and control module, the data storage module, and the data processing module; second, it establishes a data channel to transmit the acquired test data from the acquisition area to the processing area; then, it coordinates the execution timing of multiple parallel threads to ensure orderly data processing; finally, it receives the processed data, executes statistical analysis algorithms, and generates a standard format test report.

[0079] Specifically, the control chip and data acquisition control module are connected via a high-speed bus, using DMA for data transfer. For data flow control, the control chip maintains a data buffer status table and dynamically allocates storage space. When analyzing and processing results, the control chip calls a pre-built analysis algorithm library, including modules for bit error rate calculation and timing deviation analysis. Test reports are generated in XML or JSON format, containing test items, result data, and pass / fail determinations.

[0080] The introduction of the control chip enables hardware acceleration of the testing process, reduces software scheduling overhead, and improves the real-time performance of data processing. At the same time, the fixed control logic avoids the uncertainties introduced by operating system scheduling, resulting in better repeatability and stability of the testing process.

[0081] Real-world testing shows improvements in both performance and resource conservation compared to traditional solutions. In terms of performance, the scan chain test speed is significantly reduced from 8.7ms in the traditional solution to 0.98ms, an 8.9x speedup (test based on an average of 1000 scans, with a Scan chain length of 1Mb); eye diagram analysis throughput increases from 1.2GB / s to 12.8GB / s, a 10.7x improvement (using a jitter-5ps data injection method); bit error rate calculation power increases from 35GOPS / sec to 428GOPS / sec, a 12.2x improvement (measured using a board function meter and operation counter); and the test cycle compression rate decreases from 100% in the traditional solution to 23.6%, a 4.2x improvement (timed through the complete test process).

[0082] In terms of resource conservation, hardware resource consumption has been significantly reduced: CPU utilization has dropped from 92% (16 cores at full load) to 18% (only 4 cores are needed), saving 80.4%; PCIe bandwidth requirement has dropped from 9.8Gbps to 0.8Gbps, saving 91.8%; and memory consumption has dropped from 8GB to 0.5GB, saving 93.8%.

[0083] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. An ATE test method to accelerate data operations, characterized by, The method comprises the following steps: Collecting data of multiple devices to be tested simultaneously, and storing the data as a matrix structure according to a fixed bit width, wherein each row of the matrix corresponds to a test period, and each row of data contains mixed data from the multiple devices to be tested; Starting multiple parallel threads, each thread being responsible for processing data of one test period, and separating the mixed data of the multiple devices to be tested in one test period according to a predetermined rule and writing the data into independent memory areas pre-allocated for the devices to be tested respectively; Performing preset algorithm processing on the separated data of each device to be tested respectively; Analyzing the processing results and generating a report.

2. The ATE test method of accelerating data operations of claim 1, wherein, The method further comprises the following steps before the step of starting multiple parallel threads: Receiving a start command; Allocating memory space for storing input data; Allocating independent memory space for the data of the multiple devices to be tested respectively; Copying the collected data from a collection area to a processing area.

3. The ATE test method of accelerating data operations of claim 2, wherein, The processing mode of the parallel threads is as follows: According to a preset bit width definition and allocation rule, extracting data segments belonging to the devices to be tested from the mixed data of the current test period, and writing the data segments into specified positions in the independent memory areas corresponding to the devices to be tested respectively, until the data of all test periods are separated and reallocated.

4. The ATE test method of accelerating data operations of claim 1, wherein, The preset algorithm processing uses at least one of FFT analysis or eye diagram reconstruction.

5. An ATE test system that accelerates data operations, characterized by, The method for accelerating data operation of ATE testing according to any one of claims 1-4 comprises: A data collection control module for collecting data of multiple devices to be tested; A data storage module for storing the data as a matrix structure according to a fixed bit width, wherein each row of the matrix corresponds to a test period, and each row of data contains mixed data from the multiple devices to be tested; A data processing module for starting multiple parallel threads, each thread being responsible for processing data of one test period, and the parallel threads being used to separate the mixed data of the multiple devices to be tested according to a predetermined bit width and write the data into multiple memory areas; and performing preset algorithm processing on the separated data of each device to be tested respectively; A control module for analyzing the processed data and generating a report.

6. The accelerated data operation ATE test system of claim 5, wherein, The data collection control module comprises multiple FPGA chips, which work cooperatively to control test timing, generate test vectors, and synchronously collect test data of multiple devices to be tested.

7. The accelerated data operation ATE test system of claim 6, wherein, The data collection control module comprises multiple channels for simultaneously collecting test data from multiple devices to be tested.

8. The accelerated data operation ATE test system of claim 5, wherein, The data storage module is a DDR memory for storing data to be processed and processed data.

9. The accelerated data operation ATE test system of claim 8, wherein, The test data is stored in the DDR memory according to a fixed matrix structure, wherein each row of the matrix contains data of multiple devices to be tested in the same test period, and each device to be tested occupies a fixed bit width.

10. The accelerated data operation ATE test system of claim 5, wherein, The control module comprises a control chip for managing system start-up procedures, controlling data flow, analyzing processing results, and generating a test report.

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