A method and system for calculating the reduced order of short-circuit fault current at the port of a T-type DC transformer

Abstract

This application provides a method and system for reducing the order of short-circuit fault current at the port of a T-type DC transformer, comprising: constructing an AC / DC equivalent circuit diagram of the T-type DC transformer fault; constructing a time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault based on the AC / DC equivalent circuit diagram of the T-type DC transformer fault; determining the time-domain expression of the fault current under a port short-circuit fault of a bridge arm reuse type high-voltage DC transformer based on the time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault; and determining the port fault current within a preset time after the port short-circuit fault based on the time-domain expression of the fault current. The method proposed in this application, while ensuring calculation accuracy, effectively reduces the complexity of the model and the difficulty of calculation, improves the possibility of effective inverse transformation of the complex frequency domain equation, and realizes rapid analysis of the transient current waveform in the initial stage of the fault, providing timely and reliable theoretical basis for transformer fault analysis, protection design, and safe system operation.

Description

Technical Field

[0001] This application relates to the field of power electronics, and in particular to a method and system for calculating the reduced-order fault current at the port of a T-type DC transformer. Background Technology

[0002] With the development of flexible DC transmission systems, DC transformers have become core equipment for interconnecting DC systems of different voltage levels. As a type of non-isolated DC transformer, the T-type DC transformer has significant advantages in conversion efficiency, cost, and size, and has broad application prospects. However, this topology has many electrical coupling loops between high and low voltage ports, and faults have severe impacts, among which external port bipolar short-circuit faults are particularly hazardous. When a fault occurs, the short-circuit port will generate an impulse current several times the rated value in a very short time, seriously threatening equipment safety and system stability.

[0003] Currently, the analytical methods for short-circuit faults at the ports of T-type DC transformers have significant limitations. Existing research largely relies on complex high-order equivalent circuits or detailed numerical simulations. While these methods can achieve accurate simulations, they involve complex modeling, large computational loads, and time-consuming solutions, limiting the analysis of fault mechanisms and making it difficult to establish fast-acting and reliable fault protection systems. The lack of a simplified analytical method for quickly and accurately estimating the short-circuit current in the early stages of a fault in a T-type DC transformer directly limits its engineering application and restricts the formulation of rapid protection strategies and the accurate setting of protection devices. Summary of the Invention

[0004] This application provides a method and system for calculating the reduced-order fault current at the port of a T-type DC transformer. To solve the above-mentioned technical problems, this application adopts the following technical methods:

[0005] In a first aspect, this application provides a method for calculating the reduced-order fault current at the port of a T-type DC transformer, including:

[0006] Construct the AC / DC equivalent circuit diagram for a fault in a T-type DC transformer;

[0007] Based on the AC / DC equivalent circuit diagram of the T-type DC transformer fault, a time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault is constructed.

[0008] Based on the time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault, the time-domain expression of the fault current under the port short-circuit fault of the bridge arm reuse type high voltage DC transformer is determined.

[0009] Based on the time-domain expression of the fault current, the port fault current within a preset time after the port short-circuit fault is determined.

[0010] Optionally, the process of constructing the AC / DC equivalent circuit diagram for a fault in a T-type DC transformer is as follows:

[0011] Obtain the equivalent circuit diagram of the bridge arm multiplexed high-voltage DC transformer topology;

[0012] Based on the equivalent circuit diagram of the bridge arm reuse type high voltage DC transformer topology, an equivalent model of the bridge arm cascaded sub-modules and a mathematical model of high voltage side short circuit fault are constructed.

[0013] Based on the equivalent model of the bridge arm cascaded submodule and the mathematical model of the high-voltage side short-circuit fault, an AC / DC equivalent circuit diagram of a T-type DC transformer fault is constructed.

[0014] Optionally, the step of constructing a time-domain reduced-order equivalent circuit diagram of a T-type DC transformer fault based on the AC / DC equivalent circuit diagram of the T-type DC transformer fault includes:

[0015] After decoupling the AC / DC equivalent circuit diagram of the T-type DC transformer fault, a time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault is constructed.

[0016] Optionally, after decoupling the AC / DC equivalent circuit diagram of the T-type DC transformer fault, constructing a time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault includes:

[0017] AC / DC decoupling is performed on the AC / DC equivalent circuit diagram of the T-type DC transformer fault, and then KVL equations are written for each independent closed loop after decoupling.

[0018] The KVL equations are simplified to obtain the reduced KVL synthesis equations.

[0019] Based on the KVL synthesis equations, a time-domain reduced-order equivalent circuit diagram for a T-type DC transformer fault is constructed.

[0020] Optionally, determining the time-domain expression of the fault current under a short-circuit fault at the port of the bridge arm reuse type high-voltage DC transformer based on the reduced-order equivalent circuit diagram of the T-type DC transformer fault includes:

[0021] The time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault is transformed to the complex frequency domain by Laplace transform to obtain the time-domain reduced-order complex frequency domain equivalent circuit diagram of the T-type DC transformer fault.

[0022] Based on the time-domain reduced-order complex frequency domain equivalent circuit diagram of the T-type DC transformer fault, the time-domain expression of the fault current under the port short-circuit fault of the bridge arm reuse type high voltage DC transformer is determined.

[0023] Optionally, determining the time-domain expression of the fault current under a short-circuit fault at the port of the bridge arm reuse type high-voltage DC transformer based on the reduced-order complex frequency domain equivalent circuit diagram of the fault time domain of the T-type DC transformer includes:

[0024] Based on the time-domain reduced-order complex frequency domain equivalent circuit diagram of the T-type DC transformer fault, the complex frequency domain expression of the fault current under the port short-circuit fault of the bridge arm reuse type high voltage DC transformer is determined.

[0025] By performing an inverse Laplace transform on the complex frequency domain expression of the fault current, the time domain expression of the fault current under a short-circuit fault at the port of a bridge arm reused high-voltage DC transformer is obtained.

[0026] Optionally, determining the port fault current within a preset time after a port short-circuit fault based on the time-domain expression of the fault current includes:

[0027] Obtain the parameters of a T-type DC transformer;

[0028] Substitute the parameters of the T-type DC transformer into the time-domain expression of the fault current to determine the port fault current within a preset time after the port short-circuit fault.

[0029] Secondly, this application also provides a computer system, comprising:

[0030] Memory is used to store instructions that can be executed by the processor;

[0031] A processor for executing the instructions to implement the method as described in the first aspect.

[0032] Thirdly, this application also provides a computer-readable medium storing computer program code that, when executed by a processor, implements the method described in the first aspect.

[0033] This application has the following beneficial effects:

[0034] The method proposed in this application effectively reduces the complexity and computational difficulty of the model while ensuring computational accuracy, improves the possibility of effective inverse transformation of complex frequency domain equations, and realizes rapid analysis of transient current waveforms in the early stage of a fault, providing timely and reliable theoretical basis for transformer fault analysis, protection design and system safe operation. Attached Figure Description

[0035] Figure 1 A flowchart illustrating a method for calculating the reduced-order fault current at the port of a T-type DC transformer, provided in an embodiment of this application;

[0036] Figure 2 Equivalent circuit diagram of bridge arm multiplexed high voltage DC transformer topology provided in the embodiments of this application;

[0037] Figure 3 The AC / DC equivalent circuit diagram for a T-type DC transformer fault provided in the embodiments of this application;

[0038] Figure 4 The time-domain reduced-order equivalent circuit diagram of a T-type DC transformer fault provided in the embodiments of this application;

[0039] Figure 5 This application provides an embodiment of the equivalent circuit diagram in the time-domain reduced-order complex frequency domain for a T-type DC transformer fault.

[0040] Figure 6 The figure shows the simulation and calculation results of the short-circuit fault at the high-voltage side port of the bridge arm reuse type DC transformer provided in the embodiments of this application. Detailed Implementation

[0041] To facilitate understanding by those skilled in the art, the present application will be further described below in conjunction with embodiments and accompanying drawings. The content mentioned in the embodiments is not intended to limit the present application.

[0042] To solve the above technical problems, such as Figure 1 As shown, this application proposes a method for reducing the order of short-circuit fault current at the port of a T-type DC transformer, including:

[0043] Step S101: Construct the AC / DC equivalent circuit diagram for a fault in a T-type DC transformer;

[0044] First, obtain such Figure 2 The diagram shown is an equivalent circuit diagram of a bridge arm reuse type high voltage DC transformer topology. This topology consists of three identical phase units, and each phase unit consists of three bridge arms, which are represented as high voltage bridge arm (bridge arm H), low voltage bridge arm (bridge arm L) and reuse bridge arm (bridge arm M). This is the low-voltage side port voltage. This is the voltage at the high-voltage side port. Each bridge arm consists of a certain number of submodules and a bridge arm inductor. The submodules can be configured as half-bridge submodules (HBSM) or full-bridge submodules (FBSM) according to the system design.

[0045] The following assumptions were made before establishing the mathematical model:

[0046] 1. The switching status of the submodule remains unchanged for a very short time after a fault.

[0047] 2. The reused bridge arm submodule and the low-voltage bridge arm submodule did not discharge significantly within a very short time after the fault, and can be regarded as constant voltage sources;

[0048] 3. All high-voltage bridge arm submodules are full-bridge submodules, without considering any fault isolation and protection measures, and without considering the role of control strategies;

[0049] 4. After a fault occurs, the three-phase system of the transformer still maintains symmetrical operation;

[0050] 5. Ignore the influence of external transmission line distributed parameters.

[0051] Subsequently, based on the equivalent circuit diagram of the bridge arm cascaded submodule topology of the high-voltage DC transformer, an equivalent model of the bridge arm cascaded submodule and a mathematical model of the high-voltage side short-circuit fault can be constructed. Then, based on the equivalent model of the bridge arm cascaded submodule and the mathematical model of the high-voltage side short-circuit fault, an AC / DC equivalent circuit diagram of the T-type DC transformer fault can be constructed. The specific process is as follows:

[0052] First, based on the equivalent circuit diagram of the bridge arm reuse type HVDC transformer topology, an equivalent model of the cascaded submodules of the bridge arms is constructed. The switching state of each bridge arm submodule of the bridge arm reuse type HVDC transformer changes continuously over time; therefore, the electrical characteristics exhibited by the transformer are nonlinear. However, assuming that the analysis time after a fault occurs is sufficiently short and the change in the switching state of the submodules is not significant, the cascaded submodules can be equivalently represented as a large capacitor. The energy storage condition and voltage withstand capability of this equivalent capacitor are essentially consistent with those of the cascaded submodules. Assume that all submodules within the bridge arm are half-bridge submodules and the total number is... The number of conductions is , This is the capacitance value of the equivalent large capacitor. Given the capacitance value in a single submodule, according to the law of conservation of energy, we can obtain:

[0053] (1)

[0054] After establishing the equivalent model of the cascaded submodules of the bridge arms, a mathematical model for high-voltage side short-circuit faults is constructed. Considering the influence of port impedance and bridge arm impedance, it is assumed that both the port and the bridge arm have impedance. Since the high-voltage port is not directly connected to the multiplexed bridge arm and the low-voltage bridge arm, the propagation time of the bipolar fault effect to these two bridge arms is longer than that to the high-voltage bridge arm. For circuit simplification, it can be assumed that the multiplexed bridge arm and the low-voltage bridge arm are almost unaffected for a very short time after the fault occurs, i.e., the switching state and charging / discharging state of the submodules remain unchanged, and the voltage of the supporting capacitor remains unchanged. In this case, the cascaded submodules of the multiplexed bridge arm and the low-voltage bridge arm can be regarded as constant voltage sources.

[0055] Based on the above assumptions, the equivalent model of the bridge arm cascaded submodules and the mathematical model of the high-voltage side short-circuit fault can be used to construct, as follows: Figure 3 The diagram shows the AC / DC equivalent circuit for a faulty T-type DC transformer. express Phase bridge arm The current it withstands express Phase bridge arm The voltage that the cascaded submodules withstand. This is the short-circuit current at the high-voltage side port. Indicates the bridge arm inductance. This indicates the low-voltage side port voltage. For short-circuit branch resistance, This is the resistance of one bridge arm. The impedance of the bridge arm is... and .

[0056] Step S102: Based on the AC / DC equivalent circuit diagram of the T-type DC transformer fault, construct the time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault;

[0057] After decoupling the AC / DC equivalent circuit diagram of the T-type DC transformer fault, a time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault is constructed. The specific process is as follows:

[0058] The AC / DC equivalent circuit diagram of the T-type DC transformer under fault conditions is decoupled from the DC circuit. Then, the KVL equations are written for each independent closed loop after decoupling, as follows:

[0059] (2)

[0060] In the formula, express Phase bridge arm The current;

[0061] Since the AC system still maintains symmetrical operation when a bipolar short-circuit fault occurs at the high-voltage side port, and the voltage and current borne by each bridge arm and cascaded submodule remain AC symmetrical, the following equation can be obtained by adding the first three and the last three equations of equation (2):

[0062] (3)

[0063] The coefficients in formula (3) are simplified to obtain the reduced KVL synthesis equation as shown below:

[0064] (4)

[0065] in, Indicates bridge arm DC component of current , Indicates bridge arm DC component of voltage in cascaded submodules As can be seen from equation (4), after the three-phase voltage and current are superimposed, the AC components in the voltage and current will cancel each other out, leaving only the DC component. This indicates that the bipolar short-circuit fault at the high-voltage side port only affects the DC component, that is, the fault mainly affects the DC component, while the AC component has a very small effect and can be ignored in theory.

[0066] Theoretically, the number of high-voltage bridge arm submodules that are turned on It depends on the actual voltage of the cascaded submodules of the high-voltage bridge arm. The voltage fluctuates and changes constantly; for ease of calculation, N needs to be kept as constant as possible. From an averaging perspective, since the average AC voltage is 0 over one cycle, the average voltage of the high-voltage bridge arm cascaded submodules should be equal to the DC voltage. If we consider N as the average number of submodules that are turned on within one cycle, then we have:

[0067] (5)

[0068] Combining equations (1), (5), and the capacitor voltage equation, and considering that the three-phase AC quantities cancel each other out after being added together, we can obtain:

[0069] (6)

[0070] The equivalent capacitance of the cascaded submodule can be obtained from equation (6). for:

[0071] (7)

[0072] For the nodes of the AC / DC equivalent circuit diagram of a T-type DC transformer in fault condition, writing the KCL equations, we have:

[0073] (8)

[0074] In the formula, For bridge arm The current.

[0075] Based on the assumption that the voltage changes of the reuse arm and low-voltage arm cascaded submodules are small in the very short time after the fault, the DC component of their voltages will also not change much. Since the DC component of the low-voltage arm cascaded submodule voltage is 0 in steady state, it can be approximated as follows:

[0076] (9)

[0077] By combining equations (1), (7), (8), and (9), we can obtain:

[0078] (10)

[0079] Clearly, without further consideration of other mathematical relationships related to the bridge arm currents, equation (10) cannot be solved. The time-domain expression is given. However, new time-domain mathematical relations have become difficult to establish, suggesting that solving using a single time-domain equation is not feasible. That's unrealistic.

[0080] Therefore, based on the reduced KVL synthesis equation (i.e., equation (4)), a time-domain reduced-order equivalent circuit diagram of a T-type DC transformer fault can be constructed, such as... Figure 4 As shown. Specifically, the construction process of this reduced-order equivalent circuit diagram strictly follows the core constraints of KCL and KVL to ensure that its electrical characteristics are essentially equivalent to the original fault circuit. Compared with the original fault circuit diagram, this application achieves the elimination of redundant circuit parameters and the focus of key electrical quantities through KVL equation reduction. The constructed fault equivalent circuit diagram significantly reduces the topological complexity and mathematical model order of the circuit while maintaining the core fault characteristics.

[0081] Step S103: Based on the fault time-domain reduced-order equivalent circuit diagram of the T-type DC transformer, determine the time-domain expression of the fault current under the short-circuit fault at the port of the bridge arm reuse type high voltage DC transformer;

[0082] The reduction in circuit complexity and model order results in improved fault current. This provides an efficient path for solving the time-domain expression. Specifically, the time-domain equivalent circuit diagram of a T-type DC transformer fault is reduced to the complex frequency domain using a Laplace transform, resulting in the reduced-order complex frequency domain equivalent circuit diagram of the T-type DC transformer fault, as shown below. Figure 5 As shown. Among them, The initial value of the DC component of the voltage of the high-voltage bridge arm cascaded submodule. To reuse the initial value of the DC component of the bridge arm current, This is the initial value of the low-voltage side port current. This is the initial value of the fault current. For the equivalent resistance... and equivalent inductance ,have:

[0083] (11)

[0084] right Figure 5 After writing the KCL and KVL equations, the complex frequency domain expression of the fault current under a short-circuit fault at the port of a bridge arm reused high-voltage DC transformer can be obtained as follows:

[0085] (12)

[0086] According to equation (12). The implicit expression can be represented as:

[0087] (13)

[0088] in, The coefficients of the polynomial in the numerator of the fraction. The coefficients of the polynomial in the denominator of the fraction. It is a complex variable. Therefore, It is a third-order equation, and its time-domain expression can be obtained through the inverse Laplace transform. Since the inverse Laplace transform is a commonly used mathematical transformation method, the specific process of the inverse Laplace transform is omitted here. After the inverse transform, the time-domain expression of the fault current under a short-circuit fault at the port of a bridge-arm multiplexed HVDC transformer can be obtained as follows:

[0089] (14)

[0090] in, For amplitude coefficient, The attenuation coefficient is... Angular frequency, This represents the initial phase. Expanding the above coefficients, we obtain the following expansions for each coefficient:

[0091] (15)

[0092] in, These are all auxiliary coefficients and have no actual physical meaning. For the equation The real root, and Equations The real and imaginary parts of the conjugate complex roots.

[0093] Step S104: Based on the fault current expression, determine the port fault current within a preset time after the port short-circuit fault.

[0094] Obtain the parameters of the T-type DC transformer in equation (15), substitute them into equation (15), and then into equation (14) to calculate the port fault current that accurately describes the port fault within a preset time after a port short-circuit fault occurs. The preset time is 1ms.

[0095] Simulation verification

[0096] To verify the effectiveness of the proposed fault current reduction calculation method, this application uses a Simulink offline simulation model. In the T-type DC transformer simulation model used, the low-voltage side voltage is 100kV and the turns ratio is 3.2. The specific parameters are listed in Table 1.

[0097] Table 1. Main parameters of the simulation model of the bridge arm reuse type high voltage DC transformer

[0098]

[0099] After the simulation model runs normally for 1.5 seconds, a bipolar short-circuit fault is triggered at the high-voltage side port by setting the voltage source at the high-voltage side port to zero. After the fault is triggered, the simulated short-circuit current value within 1 ms after the fault occurs is compared with the calculated value, as shown in the figure. The blue line represents the calculated short-circuit current value, and the red line represents the measured short-circuit current value. Figure 6 As can be seen, Equation (15) can characterize the current waveforms of the high-voltage port, high-voltage bridge arm, low-voltage bridge arm, and multiplexed bridge arm within 1ms after a fault occurs, with the error remaining within 10%. After 1ms, the calculation error will gradually increase because the half-bridge submodule gradually locks out after the fault and the full-bridge submodule provides reverse voltage. Therefore, the method proposed in this application can accurately characterize the fault current change characteristics of the port under a bipolar short-circuit fault on the high-voltage side.

[0100] In summary, the method proposed in this application effectively reduces the complexity and computational difficulty of the model while ensuring computational accuracy, improves the possibility of effective inverse transformation of complex frequency domain equations, and realizes rapid analysis of transient current waveforms in the early stage of a fault, providing timely and reliable theoretical basis for transformer fault analysis, protection design and system safe operation.

[0101] In some embodiments, this application also provides a computer system including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0102] This application also provides a computer-readable storage medium for storing a computer program. This computer-readable storage medium can be applied to a computer device, and the computer program causes the computer device to execute the corresponding processes in the methods described above in the embodiments of this application; for brevity, further details are omitted here.

[0103] The above embodiments are preferred implementations of this application. In addition, this application can be implemented in other ways. Any obvious substitutions without departing from the concept of this technical solution are within the protection scope of this application.

[0104] To facilitate understanding by those skilled in the art of the improvements made by this application compared to the prior art, some of the accompanying drawings and descriptions have been simplified, and for clarity, some other elements have been omitted from this application. Those skilled in the art should realize that these omitted elements may also constitute the content of this application.

Claims

1. A method for calculating the reduced-order fault current at the port of a T-type DC transformer, characterized in that, include: Construct the AC / DC equivalent circuit diagram for a fault in a T-type DC transformer; Based on the AC / DC equivalent circuit diagram of the T-type DC transformer fault, a time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault is constructed. Based on the time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault, the time-domain expression of the fault current under the port short-circuit fault of the bridge arm reuse type high voltage DC transformer is determined. Based on the time-domain expression of the fault current, the port fault current within a preset time after the port short-circuit fault is determined. The step of constructing a time-domain reduced-order equivalent circuit diagram for a T-type DC transformer fault based on the AC / DC equivalent circuit diagram of the T-type DC transformer fault includes: After decoupling the AC / DC equivalent circuit diagram of the T-type DC transformer fault, a time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault is constructed. After decoupling the AC / DC equivalent circuit diagram of the T-type DC transformer fault, the construction of the time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault includes: AC / DC decoupling is performed on the AC / DC equivalent circuit diagram of the T-type DC transformer fault, and then KVL equations are written for each independent closed loop after decoupling. The KVL equations are simplified to obtain the reduced KVL synthesis equations; Based on the KVL synthesis equations, a time-domain reduced-order equivalent circuit diagram of a T-type DC transformer fault is constructed. The determination of the time-domain expression of the fault current under a short-circuit fault at the port of the bridge arm reuse type high-voltage DC transformer based on the reduced-order equivalent circuit diagram of the fault in the T-type DC transformer includes: The time-domain reduced-order equivalent circuit diagram of the T-type DC transformer fault is transformed to the complex frequency domain by Laplace transform to obtain the time-domain reduced-order complex frequency domain equivalent circuit diagram of the T-type DC transformer fault. Based on the time-domain reduced-order complex frequency domain equivalent circuit diagram of the T-type DC transformer fault, the time-domain expression of the fault current under the port short-circuit fault of the bridge arm multiplex type high voltage DC transformer is determined. The reduced KVL synthesis equation is: ； In the formula, Indicates bridge arm The DC component of the current, X=H,M,L , Indicates bridge arm DC component of voltage in cascaded submodules X=H,M,L , This is the short-circuit current at the high-voltage side port. Indicates the bridge arm inductance. This indicates the low-voltage side port voltage. For bridge arm inductance The current, For short-circuit branch resistance, The bridge arm resistance is [value], and the bridge arm impedance is [value]. and .

2. The method according to claim 1, characterized in that, The process of constructing the AC / DC equivalent circuit diagram for the T-type DC transformer fault is as follows: Obtain the equivalent circuit diagram of the bridge arm multiplexed high-voltage DC transformer topology; Based on the equivalent circuit diagram of the bridge arm reuse type high voltage DC transformer topology, an equivalent model of the bridge arm cascaded sub-modules and a mathematical model of high voltage side short circuit fault are constructed. Based on the equivalent model of the bridge arm cascaded submodule and the mathematical model of the high-voltage side short-circuit fault, an AC / DC equivalent circuit diagram of a T-type DC transformer fault is constructed.

3. The method according to claim 1, characterized in that, The determination of the time-domain expression of the fault current under a short-circuit fault at the port of the bridge arm reuse type high-voltage DC transformer, based on the reduced-order complex frequency domain equivalent circuit diagram of the fault time-domain of the T-type DC transformer, includes: Based on the time-domain reduced-order complex frequency domain equivalent circuit diagram of the T-type DC transformer fault, the complex frequency domain expression of the fault current under the port short-circuit fault of the bridge arm reuse type high voltage DC transformer is determined. By performing an inverse Laplace transform on the complex frequency domain expression of the fault current, the time domain expression of the fault current under a short-circuit fault at the port of a bridge arm reused high-voltage DC transformer is obtained.

4. The method according to claim 1, characterized in that, The determination of the port fault current within a preset time after a port short-circuit fault based on the time-domain expression of the fault current includes: Obtain the parameters of a T-type DC transformer; Substitute the parameters of the T-type DC transformer into the time-domain expression of the fault current to determine the port fault current within a preset time after the port short-circuit fault.

5. A computer system, characterized in that, include: Memory is used to store instructions that can be executed by the processor; A processor for executing the instructions to implement the method as described in any one of claims 1 to 4.

6. A computer-readable medium, characterized in that, The system contains computer program code that, when executed by a processor, implements the method as described in any one of claims 1 to 4.

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