Pre-reading processing method and device for 3D NAND flash memory, equipment and medium

Abstract

The invention relates to the technical field of 3D NAND flash memories, and discloses a pre-reading processing method, device and equipment of a 3D NAND flash memory and a medium, and the method comprises the following steps: monitoring vertical stacking structure characteristics of the 3D NAND flash memory in real time, and analyzing a data access mode of the 3D NAND flash memory to obtain structure access data; acquiring a plane number field of a physical address in the access demand, and detecting whether data access is in the same plane according to the plane number field; if the data access is not in the same plane, predicting a cross-layer conflict according to the activation state of the adjacent plane and historical load data to obtain a conflict prediction result; and processing a pre-reading task according to the structure access data and the conflict prediction result. According to the invention, the pre-reading efficiency of the 3D NAND is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of 3D NAND flash memory, and particularly relates to a 3D NAND flash memory pre-reading processing method and device, equipment and medium. BACKGROUND

[0002] With the rapid development of information technology, the demand for data storage is growing rapidly. As an advanced non-volatile storage technology, 3D NAND flash memory significantly improves storage density and reduces the cost per unit capacity by vertically stacking multiple layers of storage cells, and has become the preferred solution for current enterprise-level solid-state drives (SSDs) and high-end consumer storage devices. However, as the number of stacked layers increases, the complexity of its physical structure also poses a serious challenge to data read / write performance. First, due to the vertical stacking of storage cells, data read / write needs to cross multiple layers, the access path is longer, resulting in increased latency. At the same time, as the number of stacked layers increases, the interlayer interference phenomenon intensifies, and interlayer interference becomes an important factor affecting read / write performance. Second, existing pre-reading strategies are mostly optimized based on the structural characteristics of planar NAND, and do not fully utilize the characteristics of the vertical stacking structure of 3D NAND, resulting in low pre-reading efficiency. SUMMARY

[0003] The present application provides a 3D NAND flash memory pre-reading processing method, device, computer equipment and medium to solve the technical problem of low 3D NAND pre-reading efficiency.

[0004] In a first aspect, a 3D NAND flash memory pre-reading processing method is provided, comprising: monitoring and analyzing the vertical stacking structure characteristics of the 3D NAND flash memory in real time, and analyzing the data access mode of the 3D NAND flash memory to obtain structure access data; obtaining the plane number field of the physical address in the access requirement, and detecting whether the data access is within the same plane according to the plane number field; if the data access is not within the same plane, predicting the cross-layer conflict according to the activation state and historical load data of adjacent planes to obtain a conflict prediction result; processing the pre-reading task according to the structure access data and the conflict prediction result.

[0005] In a second aspect, a 3D NAND flash memory pre-reading processing device is provided, comprising: a monitoring and analyzing unit for monitoring and analyzing the vertical stacking structure characteristics of the 3D NAND flash memory in real time, and analyzing the data access mode of the 3D NAND flash memory to obtain structure access data; The acquisition detection unit is configured to acquire a plane number field of a physical address in an access requirement, and detect whether the data access is in the same plane according to the plane number field. The prediction unit is configured to, if the data access is not in the same plane, predict a cross-layer conflict according to an activation state and historical load data of an adjacent plane to obtain a conflict prediction result. The processing unit is configured to process a pre-read task according to the structure access data and the conflict prediction result.

[0006] In a third aspect, a computer device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the 3D NAND flash pre-read processing method when executing the computer program.

[0007] In a fourth aspect, a computer readable storage medium is provided, which stores a computer program, and the computer program implements the steps of the 3D NAND flash pre-read processing method when executed by a processor.

[0008] The 3D NAND flash pre-read processing method, device, computer device, and storage medium can monitor the vertical stack structure characteristics of the 3D NAND flash in real time, analyze the data access mode of the 3D NAND flash to obtain structure access data, acquire a plane number field of a physical address in an access requirement, detect whether the data access is in the same plane according to the plane number field, predict a cross-layer conflict according to an activation state and historical load data of an adjacent plane to obtain a conflict prediction result if the data access is not in the same plane, and process a pre-read task according to the structure access data and the conflict prediction result. The 3D NAND flash pre-read processing method, device, computer device, and storage medium can monitor the vertical stack structure characteristics of the 3D NAND flash in real time, analyze the data access mode of the 3D NAND flash to obtain structure access data, acquire a plane number field of a physical address in an access requirement, detect whether the data access is in the same plane according to the plane number field, predict a cross-layer conflict according to an activation state and historical load data of an adjacent plane to obtain a conflict prediction result if the data access is not in the same plane, and process a pre-read task according to the structure access data and the conflict prediction result. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative labor.

[0010] Figure 1is a flowchart of a 3D NAND flash pre-reading processing method in an embodiment of the present application; Figure 2 is Figure 1 is a flowchart of a specific embodiment of step S110 in the method; Figure 3 is Figure 1 is a flowchart of a specific embodiment of step S130 in the method; Figure 4 is Figure 1 is a flowchart of a specific embodiment of step S140 in the method; Figure 5 is a schematic block diagram of a 3D NAND flash pre-reading processing device in an embodiment of the present application; Figure 6 is a structural schematic diagram of a computer device in an embodiment of the present application; Figure 7 is another structural schematic diagram of a computer device in an embodiment of the present application. DETAILED DESCRIPTION

[0011] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0012] The 3D NAND flash pre-reading processing method provided by the embodiments of the present application can be applied to a client or a server. The client can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices. The server can be implemented by an independent server or a server cluster composed of multiple servers. At present, in the field of 3D NAND flash, the existing 3D NAND pre-reading efficiency is low. In view of the above problem, the present application provides a 3D NAND flash pre-reading processing method. The method can intelligently identify cross-plane access by real-time sensing the vertical stack structure characteristics of 3D NAND and analyzing the data access mode, and can predict cross-layer conflicts according to the activation state and historical load data of adjacent planes in combination with the detection of the plane number of the physical address. The pre-reading task is processed according to the structure access data and the conflict prediction result, thereby effectively reducing the delay caused by interlayer interference and long access path, and effectively improving the pre-reading efficiency of 3D NAND. The present application will be described in detail through specific embodiments.

[0013] Please refer to Figure 1 as shown, Figure 1A flowchart illustrating a pre-read processing method for 3D NAND flash memory provided in an embodiment of the present invention includes the following steps: S110-S140.

[0014] S110. Monitor the vertical stacking structure characteristics of the 3D NAND flash memory in real time and analyze the data access mode of the 3D NAND flash memory to obtain structure access data. Specifically, such as Figure 2 As shown, step S110 includes steps S111-S113: S111, real-time monitoring of the structural characteristic data of each layer of the 3D NAND flash memory, wherein the structural characteristic data includes inter-layer connection status, charge retention characteristics, read / write endurance, and inter-layer performance differences; S112, analysis of the data access sequence of the 3D NAND flash memory to identify hotspot regions and access locality to obtain access pattern analysis results; S113, using the structural characteristic data and the access pattern analysis results as the structural access data. More specifically, to achieve in-depth optimization of the performance of 3D NAND flash memory, real-time monitoring of structural characteristics is first performed. This process continuously collects multiple key physical parameters of each storage layer: including inter-layer connection status to evaluate the conductivity and insulation integrity of the vertical channel, charge retention characteristics to measure the long-term stability of data storage, read / write endurance to monitor the performance degradation of storage cells after multiple programming / erasing cycles, and differences in access latency, power consumption, and anti-interference capabilities among different layers. While monitoring the vertical stacking structure characteristics of 3D NAND flash memory in real time, in-depth analysis of data access patterns is also performed. Specifically, this involves in-depth analysis of data access sequences and, by statistically analyzing the address distribution and timing patterns of I / O requests, accurately identifying high-frequency access hotspots and determining whether the data access patterns exhibit spatial locality (such as sequential access) or temporal locality characteristics. Ultimately, the aforementioned physical structure characteristic data and access pattern analysis results are integrated into unified structure access data, providing comprehensive decision-making basis for subsequent dynamic adjustment of read-ahead strategies, data layout optimization, and reliability management. This enables refined perception and adaptive scheduling of the 3D NAND flash memory's three-dimensional architecture.

[0015] S120. Obtain the plane number field of the physical address in the access request, and detect whether the data access is in the same plane based on the plane number field; Specifically, in the prefetch optimization process of 3D NAND flash memory, obtaining the plane number field of the physical address in the access request and detecting whether the data access is within the same plane based on the plane number field are key steps. First, the plane number field used to identify the specific physical location of the storage cell is extracted from the physical address carried in the initiated access request. Then, the plane number of the current access request is compared with the plane number of the most recent access in real time. If the plane number of the current access request is the same as the plane number of the most recent access, it is determined that this access is a same-plane access, and a continuous prefetch mode for that plane can be triggered. That is, if the data access is within the same plane, continuous prefetching is performed within the same plane. If the plane number of the current access request is different from the plane number of the most recent access, it is determined to be a cross-plane access. At this time, a cross-layer conflict prediction mechanism will be activated to assess the performance interference that may be caused by accessing different planes.

[0016] S130. If the data access is not in the same plane, then the cross-layer conflict is predicted based on the activation status of adjacent planes and historical load data to obtain the conflict prediction result. Specifically, such as Figure 3As shown, step S130 includes steps S131-S133: S131, monitoring the activation state of adjacent planes; S132, analyzing historical load data to obtain historical load analysis results; S133, predicting cross-layer conflicts based on the activation state and the historical load analysis results to obtain the conflict prediction result. It should be noted that in 3D NAND flash memory, cross-layer conflict prediction is a crucial dynamic management step. Its core lies in real-time monitoring of the activation state of adjacent planes and combining it with historical load data for intelligent analysis to predict potential performance bottlenecks. The specific implementation steps are as follows: First, by real-time monitoring of the activation state of adjacent planes, the current working state of each plane is obtained, for example, determining whether a specific plane is currently performing read, program, or erase operations. This monitoring typically relies on the status registers inside the flash memory controller, which can reflect the concurrent access situation between different planes in real time. Second, historical load data is analyzed, including statistical analysis of the access frequency, operation type distribution (such as read / write ratio), and request queue depth trends of each plane over a period of time. By mining this historical data, periodic patterns or sudden high-load patterns can be identified, allowing for prediction of future access behavior and generating historical load analysis results. Finally, in the cross-layer conflict prediction phase, real-time plane activation states are fused with historical load analysis results. For example, if two physically adjacent planes are detected to be activated simultaneously, and historical data analysis indicates that such concurrent access patterns have repeatedly caused significant performance latency (i.e., cross-layer conflict), a high-probability conflict prediction result is generated. This result quantifies the risk level of the conflict and provides a basis for subsequent pre-read scheduling decisions, effectively avoiding throughput degradation and increased access latency.

[0017] S140. Process the pre-read task based on the structure access data and the conflict prediction result.

[0018] Specifically, such as Figure 4As shown, step S140 includes steps S141-S144: S141, calculating the pre-read depth based on the access pattern analysis results and the conflict prediction results; S142, dynamically adjusting the pre-read range based on the structural characteristic data to obtain the target pre-read range; S143, prioritizing the pre-read tasks based on the pre-read depth, the target pre-read range, and the data importance and access frequency in the access requirements to obtain a scheduling queue; S144, processing the pre-read tasks through the scheduling queue. More specifically, step S141 includes: if the conflict prediction result is a low-risk inter-layer conflict and if the access pattern analysis result shows hot data areas and frequent access paths, then dynamically increasing the pre-read depth based on the access frequency; if the conflict prediction result is a high-risk inter-layer conflict, then decreasing the pre-read depth. Step S142 includes: allocating a larger pre-read range to layers with performance better than average based on the inter-layer performance differences in the structural characteristic data; and allocating a smaller pre-read range to layers with performance lower than average to obtain the target pre-read range. It's important to note that in the cross-layer prefetch scheduling process of 3D NAND flash memory, prefetch depth calculation is the primary step, relying on a deep fusion of access pattern analysis results and cross-layer conflict prediction results. Specifically, when the conflict prediction result indicates a low-risk inter-layer conflict, and the access pattern analysis clearly identifies hot data areas and frequently accessed paths, the current access is determined to have high spatial and temporal locality. Therefore, the prefetch depth is dynamically increased based on the real-time access frequency, aiming to improve cache hit rate and reduce subsequent access latency through more aggressive data preloading. Conversely, if the conflict prediction result indicates a high-risk inter-layer conflict, suggesting that simultaneous access to different planes may cause severe inter-layer interference and performance bottlenecks, a conservative strategy is adopted, proactively reducing the prefetch depth to avoid the prefetch operation itself exacerbating resource contention and leading to overall performance degradation. After determining the prefetch depth, the prefetch range adjustment phase begins. This phase heavily relies on accurate perception of the physical characteristics of 3D NAND flash memory. Detailed analysis of the performance differences between layers revealed in the structural characteristic data, such as access latency, power consumption characteristics, and read / write endurance, is conducted. For storage tiers with significantly above-average performance (such as those with lower access latency or higher stability), a larger prefetch range is allocated. This is equivalent to allocating "highway" resources to high-performance tiers to maximize data prefetch throughput. Conversely, for tiers with relatively lower performance or potential reliability challenges, their prefetch range is appropriately reduced to prevent unnecessary latency introduced by large-scale data prefetching on these tiers. Finally, the prioritization process considers multiple factors, including prefetch depth, target prefetch range, and the importance and real-time access frequency of the data in the access requirements. For example, data blocks with high importance, high frequency of access, and large prefetch depth are given higher execution priority.All these decisions ultimately converge to generate an optimized scheduling queue that dynamically guides the execution order of prefetch tasks, ensuring that the storage controller can prioritize the most critical and profitable data prefetch tasks. This effectively balances performance, power consumption, and reliability in a complex three-dimensional stacked architecture, thereby improving overall storage throughput and reducing access latency.

[0019] To facilitate understanding, the implementation process of steps S110-S140 will be explained using the following specific example: First, the vertical stacking structure characteristics of the target 3D NAND flash memory chip were monitored in real time. Monitoring revealed that, due to slight differences in manufacturing processes, the charge retention characteristics and read / write speeds of the top storage layers (e.g., layers 100 and above) were slightly better than those of the bottom storage layers. Simultaneously, data access patterns were analyzed, identifying that the current computing task was sequentially accessing a large log file, forming a clear sequential access flow, and that the file's data blocks physically spanned multiple planes. Structural characteristics (performance differences between layers) and access patterns (sequential access, cross-plane access) were integrated into structural access data.

[0020] When an access request is received, its physical address points to Plane 2. The Plane ID field of this address is parsed and compared with the previous access request (pointing to Plane 1). The comparison reveals that the current request and the previous request are not in the same plane, therefore this is determined to be a cross-plane access. This determination triggers the subsequent conflict prediction mechanism.

[0021] Since the access is cross-plane, cross-layer conflict prediction is initiated. The activation status of adjacent planes (Plane 1 and Plane 3) is monitored in real time, revealing that Plane 3 is performing high-priority programming operations (status: "Busy"). Simultaneously, historical load data analysis shows that when Plane 2 and Plane 3 are accessed simultaneously, due to shared internal resources, it has historically caused multiple instances of access latency spikes exceeding 30%, resulting in conflict events. Based on the current activation status (Plane 3 busy) and historical patterns, the system predicts a high risk of cross-layer conflict for this cross-plane access and generates corresponding conflict prediction results.

[0022] Finally, all information is processed. If signals indicating "sequential access pattern exists and data spans planes" or "high-risk cross-layer conflict" are received, the prefetch strategy is dynamically adjusted in response: First, considering the sequential access, the prefetch depth is appropriately increased to read subsequent data pages in advance to improve the hit rate. Second, to avoid conflicts with the busy Plane 3, data is preferentially read from the relatively idle Plane 2. Simultaneously, based on the structure access data obtained in the first step, subsequent prefetch requests are preferentially scheduled to the higher-performance top storage layer.

[0023] The 3D NAND flash memory pre-read processing method in this invention senses the vertical stacking structure characteristics of 3D NAND in real time and analyzes data access patterns; combined with the detection of the plane number of physical addresses, it can intelligently identify cross-plane access and predict cross-layer conflicts based on the activation status of adjacent planes and historical load data; and process the pre-read task based on the structure access data and conflict prediction results, thereby effectively reducing the latency caused by inter-layer interference and long access paths, thus effectively improving the pre-read efficiency of 3D NAND.

[0024] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0025] The software tools or components not belonging to our company that appear in the embodiments of this application are merely examples and do not represent actual use.

[0026] In one embodiment, a pre-read processing apparatus 200 for 3D NAND flash memory is provided, which corresponds one-to-one with the pre-read processing method for 3D NAND flash memory in the above embodiments. For example... Figure 5 As shown, the 3D NAND flash memory pre-read processing device 200 includes a monitoring and analysis unit 201, an acquisition and detection unit 202, a prediction unit 203, and a processing unit 204. Detailed descriptions of each functional module are as follows: The monitoring and analysis unit 201 is used to monitor the vertical stacking structure characteristics of the 3D NAND flash memory in real time and analyze the data access mode of the 3D NAND flash memory to obtain structure access data. The detection unit 202 is used to obtain the plane number field of the physical address in the access request, and detect whether the data access is in the same plane according to the plane number field; The prediction unit 203 is used to predict cross-layer conflicts and obtain conflict prediction results based on the activation status of adjacent planes and historical load data if the data access is not in the same plane. Processing unit 204 is used to process the pre-read task based on the structure access data and the conflict prediction result.

[0027] In one embodiment, the monitoring and analysis unit 201 is specifically used for: The structural characteristic data of each layer of the 3D NAND flash memory is monitored in real time, including inter-layer connection status, charge retention characteristics, read / write endurance, and inter-layer performance differences. The data access sequences of the 3D NAND flash memory are analyzed to identify hotspot areas and access locality, resulting in access pattern analysis. The structural characteristic data and the access pattern analysis results are used as the structural access data.

[0028] In one embodiment, the prediction unit 203 is specifically used for: Monitor the activation state of adjacent planes; Analyze historical load data to obtain historical load analysis results; The conflict prediction result is obtained by predicting cross-layer conflicts based on the activation state and the historical load analysis results.

[0029] In one embodiment, the processing unit 204 is specifically used for: Calculate the read-ahead depth based on the access pattern analysis results and the conflict prediction results; The target pre-read range is obtained by dynamically adjusting the pre-read range based on the structural characteristic data. Based on the pre-read depth, target pre-read range, and the importance and frequency of data access in the access requirements, the pre-read tasks are prioritized to obtain a scheduling queue; The pre-read task is processed through the scheduling queue.

[0030] In one embodiment, the processing unit 204 is further configured to: If the conflict prediction result is a low-risk inter-layer conflict and if the access pattern analysis result contains hot data areas and frequent access paths, then the pre-read depth is dynamically increased according to the access frequency. If the conflict prediction result is a high-risk inter-layer conflict, then the pre-read depth is reduced.

[0031] In one embodiment, the processing unit 204 is further configured to: Based on the inter-layer performance differences in the structural characteristic data, layers with performance better than the average level are assigned a larger read-ahead range; The target read range is obtained by assigning a smaller read range to layers with below-average performance.

[0032] In one embodiment, the 3D NAND flash memory pre-read processing device 200 further includes: A pre-read unit is used to perform continuous pre-reading within the same plane if the data accesses are within the same plane.

[0033] The 3D NAND flash memory pre-read processing device of this invention senses the vertical stacking structure characteristics of 3D NAND in real time and analyzes the data access pattern; combined with the detection of the plane number of the physical address, it can intelligently identify cross-plane access and predict cross-layer conflicts based on the activation status of adjacent planes and historical load data; and process the pre-read task based on the structure access data and conflict prediction results, thereby effectively reducing the latency caused by inter-layer interference and long access paths, and thus effectively improving the pre-read efficiency of 3D NAND.

[0034] Specific limitations regarding the prefetching processing device for 3D NAND flash memory can be found in the limitations of the prefetching processing method for 3D NAND flash memory described above, and will not be repeated here. Each unit in the aforementioned prefetching processing device for 3D NAND flash memory can be implemented entirely or partially through software, hardware, or a combination thereof. These units can be embedded in hardware or independently of the processor in a computer device, or stored in software in the memory of a computer device, so that the processor can call and execute the operations corresponding to each of the above modules.

[0035] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile and / or volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface is used to communicate with external clients via a network connection. When the computer program is executed by the processor, it implements the functions or steps of a 3D NAND flash memory pre-read processing method on the server side.

[0036] In one embodiment, a computer device is provided, which may be a client, and its internal structure diagram may be as follows: Figure 7 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface is used to communicate with an external server via a network connection. When executed by the processor, the computer program implements client-side functions or steps of a 3D NAND flash memory pre-read processing method.

[0037] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described 3D NAND flash memory pre-read processing method.

[0038] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described 3D NAND flash memory pre-read processing method.

[0039] It should be noted that the functions or steps that can be implemented by the computer-readable storage medium or computer device described above can be referred to the relevant descriptions on the server side and client side in the foregoing method embodiments. To avoid repetition, they will not be described one by one here.

[0040] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0041] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0042] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A pre-read processing method of 3D NAND flash memory, characterized in that, The application relates to a method for processing a read-ahead task of a 3D NAND flash memory, comprising the following steps: Real-time monitoring of a vertical stack structure characteristic of the 3D NAND flash memory, and analysis of a data access mode of the 3D NAND flash memory to obtain structure access data; Obtaining a plane number field of a physical address in an access requirement, and detecting whether data access is in the same plane according to the plane number field; If the data access is not in the same plane, predicting a cross-layer conflict according to an activation state and historical load data of adjacent planes to obtain a conflict prediction result; Processing the read-ahead task according to the structure access data and the conflict prediction result.

2. The method of claim 1, wherein, The step of real-time monitoring of a vertical stack structure characteristic of the 3D NAND flash memory, and analysis of a data access mode of the 3D NAND flash memory to obtain structure access data, comprises the following steps: Real-time monitoring of structure characteristic data of each layer of the 3D NAND flash memory, wherein the structure characteristic data comprises an interlayer connection state, charge retention characteristics, read-write durability and interlayer performance difference; Analysis of a data access sequence of the 3D NAND flash memory to identify a hot spot area and access locality to obtain an access mode analysis result; The structure characteristic data and the access mode analysis result are taken as the structure access data.

3. The method of claim 2, wherein, The step of processing the read-ahead task according to the structure access data and the conflict prediction result, comprises the following steps: Calculating a read-ahead depth according to the access mode analysis result and the conflict prediction result; Dynamically adjusting a read-ahead range according to the structure characteristic data to obtain a target read-ahead range; According to the read-ahead depth, the target read-ahead range and data importance and access frequency in the access requirement, priority sorting is performed on the read-ahead task to obtain a scheduling queue; The read-ahead task is processed through the scheduling queue.

4. The method of claim 3, wherein, The step of calculating a read-ahead depth according to the access mode analysis result and the conflict prediction result, comprises the following steps: If the conflict prediction result is a low-risk interlayer conflict and if there are hot spot data areas and frequent access paths in the access mode analysis result, the read-ahead depth is dynamically increased according to the access frequency; If the conflict prediction result is a high-risk interlayer conflict, the read-ahead depth is reduced.

5. The method of claim 3, wherein, The step of dynamically adjusting a read-ahead range according to the structure characteristic data to obtain a target read-ahead range, comprises the following steps: According to the interlayer performance difference in the structure characteristic data, a layer with performance better than the average level is allocated a larger read-ahead range; A layer with performance lower than the average level is allocated a smaller read-ahead range to obtain the target read-ahead range.

6. The method of claim 1, wherein, The step of predicting a cross-layer conflict according to an activation state and historical load data of adjacent planes to obtain a conflict prediction result, comprises the following steps: Monitoring the activation state of adjacent planes; Analysis of historical load data to obtain a historical load analysis result; Based on the activation state and the historical load analysis result, a cross-layer conflict is predicted to obtain the conflict prediction result.

7. The method according to any one of claims 1 to 6, characterized in that, After the step of detecting whether data access is in the same plane according to the plane number field, the following step is further included: If the data access is in the same plane, continuous read-ahead is performed in the same plane.

8. A pre-read processing apparatus of 3D NAND flash memory, characterized by, The application relates to a method for processing a read-ahead task of a 3D NAND flash memory, comprising the following steps: The monitoring and analyzing unit is configured to monitor a vertical stack structure characteristic of the 3D NAND flash memory in real time and analyze a data access mode of the 3D NAND flash memory to obtain structure access data. The acquisition and detection unit is configured to acquire a plane number field of a physical address in the access requirement and detect whether the data access is in the same plane according to the plane number field. The prediction unit is configured to, if the data access is not in the same plane, predict a cross-layer conflict according to an activation state and historical load data of adjacent planes to obtain a conflict prediction result. The processing unit is configured to process a pre-read task according to the structure access data and the conflict prediction result.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the pre-read processing method of the 3D NAND flash memory according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 9. The computer program is executed by the processor to implement the steps of the pre-read processing method of the 3D NAND flash memory according to any one of claims 1 to 7.

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