Cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and computer system

Abstract

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

Description

TECHNICAL FIELD

[0001] The present application particularly relates to a method for cross-device memory dynamic complementary utilization based on CXL protocol interconnection and a computer system for executing the method. BACKGROUND

[0002] In existing servers and high-performance computing systems, memory is a key data storage and running support resource, and its reliability and availability directly determine the stable operation of the whole system. However, with the continuous shrinking of DRAM process technology, the unit structure tends to be fine, and the probability of physical defects such as bad areas and weak units generated in the manufacturing process increases significantly, resulting in a decrease in product yield. At the same time, in the long-term operation, due to factors such as electrical stress, temperature drift, and aging, memory cells may also have permanent or intermittent errors, causing system abnormalities or even crashes.

[0003] In the prior art, bad areas or errors of DDR memory are mainly handled by ECC (Error Correcting Code) error correction and local shielding mechanism. Specifically, the DDR controller can detect single-bit errors through ECC verification and automatically correct them when reading out. When multiple-bit errors are detected, the system log is reported for maintenance personnel to judge. However, when the same memory cell has multiple errors, ECC can only correct repeatedly and cannot actively isolate the area. To avoid persistent errors, some memory controllers or firmware use row / column remapping or page-level shielding (Page Offlining), that is, mark the error physical row, column, or page as an unusable area, and shield these areas from the address mapping table by the controller or operating system, so that access requests no longer fall into the bad area. This scheme is usually only performed within a single memory module and belongs to single-device internal repair, which cannot reallocate address space across different DDR devices. For defective memory modules detected at the factory, manufacturers generally replace a small number of bad rows or columns within the chip through BIST self-test and fuse repair. When the number of bad blocks exceeds the repair capability, it is directly determined as defective and scrapped or downgraded for use. Although these schemes can alleviate the problem of local defects in a single DDR to some extent, they still have the disadvantages of limited repair range, resource waste, and inability to achieve cross-module complementation.

[0004] Therefore, the prior art still has the following defects in handling DDR memory bad areas: First, the ECC mechanism can only detect and correct random single-bit errors. It lacks the ability to continuously manage repeated errors in the same physical unit and cannot actively mask or migrate failed units. Second, row / column remapping or page-level masking can usually only be completed within a single DDR module, with a limited repair scope, and cannot achieve bad sector remapping across devices or channels.

[0005] Furthermore, these repair solutions often rely on memory controller or BIOS firmware support and lack runtime dynamic management capabilities. Once the accumulated errors exceed the threshold, they can often only be resolved by powering down or replacing the memory.

[0006] Furthermore, for defective DDR modules detected at the factory, the existing fuse repair process can only replace a very small number of bad rows. Once the defect exceeds the limit, the entire memory module will be scrapped, resulting in wasted resources and increased production costs.

[0007] For example, in patent CN119088614A, the memory module is tested using CXL. After initiating read and write operations on the memory module using CXL, the error location is found by comparison. However, the error location cannot be detected in real time. The method is time-consuming and can be treated as a task.

[0008] For example, in patent US20240176697A1, the memory remapping is an operation performed on the spare line within each device, and does not achieve cross-device memory connections.

[0009] Overall, existing technologies lack a mechanism that can combine hardware testing results to achieve dynamic mapping across devices and complementary utilization of defective modules, making it difficult to simultaneously ensure reliability and utilization.

[0010] The above background information is provided only to aid in understanding the inventive concept and technical solution of this invention. It does not necessarily belong to the prior art of this invention. In the absence of clear evidence that the above information was disclosed before the filing date of this invention, the above background information should not be used to evaluate the novelty and inventiveness of this invention. Summary of the Invention

[0011] In view of this, in order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a method for dynamic complementary utilization of cross-device memory based on CXL protocol interconnection.

[0012] To achieve the above objectives, the present invention adopts the following technical solution: A method for dynamic complementary utilization of cross-device memory based on CXL protocol interconnection includes the following steps: The memory's ECC module detects data during transmission; when a data error is detected, the ECC module locates the error, updates the error counter module corresponding to that location, and generates an error report. When the count value of the error count module reaches a set threshold value, the area corresponding to the position is marked as a failed area; Based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, the state of all memories is evaluated, and a target memory is selected according to the evaluation result of the memory state; Based on the error report and the selected target memory, a new logical address is allocated for the failed area; the logical address is transmitted to the target memory through the CXL protocol, and the address mapping table is updated; After the mapping is successful, the system migrates the data of the failed area to the healthy area of the target memory through the CXL protocol.

[0013] According to some preferred embodiments of the present application, the error report includes one or more of the following information: error type, memory location where the error occurs, memory data where the error occurs; and at least includes the memory location where the error occurs, that is, the error position is necessary to establish a connection with the subsequently selected target memory and transfer data.

[0014] According to some preferred embodiments of the present application, the error type includes single-bit error and multi-bit error; when the error type is detected as single-bit error, the ECC module automatically repairs; when the error type is detected as multi-bit error, the count value of the corresponding error count module is increased by 1.

[0015] According to some preferred embodiments of the present application, each memory address is allocated with an error count module for tracking the number of multi-bit errors occurring at the position.

[0016] According to some preferred embodiments of the present application, the detection is: using the ECC algorithm of the ECC module to check the check bit of the data, if the check bit of the data does not match the expected check value, the data is wrong; if a single bit flip occurs, the data error is single-bit error, if multiple bit flips occur, the data error is multi-bit error.

[0017] According to some preferred embodiments of the present application, the positioning is: based on the data detected with errors, the ECC module returns the number of bits with errors according to the position of the bit flip, and reports the data position where the error occurs. In this way, the position where the error occurs can be obtained in real time during data transmission.

[0018] According to some preferred embodiments of the present application, the evaluation of the state of all memories is to score the state of the memory through the following formula, and the memory with the highest score is selected as the target memory: S=w space ×S space +w health ×S health+w latency ×S latency +w load ×S load In the formula, S space is the space dimension score of the memory, S health is the health dimension score of the memory, S latency is the latency dimension score of the memory, S load is the load dimension score of the memory, w space is the weight coefficient corresponding to the space dimension, w health is the weight coefficient corresponding to the health dimension, w latency is the weight coefficient corresponding to the latency dimension, and w load is the weight coefficient corresponding to the load dimension.

[0019] According to some preferred embodiments of the present application, the space dimension score S space is calculated according to the free space ratio of the memory, and the higher the free space ratio, the higher the score. The score can be directly calculated according to the following formula: S space = free ratio.

[0020] According to some preferred embodiments of the present application, the health dimension score S health is converted from the cumulative value of the multi-bit error to a score between 0 and 1, and the fewer the multi-bit error times, the higher the score. The score is calculated according to the following formula: ; In the formula, err is the cumulative value of the multi-bit error of a single memory device, and err max is the maximum number of multi-bit errors set for a single memory device.

[0021] According to some preferred embodiments of the present application, the latency dimension score S latency is obtained by normalizing the average access latency of a fixed number of cycles, and the smaller the latency, the higher the score. The score is calculated according to the following formula: ; In the formula, latency is the average access latency, and latency max is the maximum access delay set.

[0022] According to some preferred embodiments of the present application, the load dimension score S load is calculated according to the port bandwidth utilization or IOPS utilization, and the lower the load, the higher the score. The formula is S load = 1-Iport load; in which Iport load is the port bandwidth utilization or IOPS utilization.

[0023] According to some preferred embodiments of the present application, the weight coefficient w health corresponding to the space dimension space corresponding to the latency dimension latency corresponding to the load dimension load satisfy the formula w space +w health+ w latency +w load =1.

[0024] According to some preferred embodiments of the present application, the weight coefficient w health corresponding to the space dimension space corresponding to the latency dimension latency corresponding to the load dimension load decrease in turn.

[0025] According to some preferred embodiments of the present application, in the process of selecting the target memory, if the memory corresponding to the failure region has the highest score, the memory with the second highest score is selected as the target memory.

[0026] The present application also provides a computer system for executing the method as described above.

[0027] Due to the adoption of the above technical solutions, compared with the prior art, the present application has the advantages that: the method for cross-device memory dynamic complementary utilization based on CXL protocol interconnection in the present application can perform real-time and dynamic tracking by using the existing ECC module for hardware-side error positioning in the process of data transmission, and can select the target memory based on the space dimension, the health dimension, the latency dimension and the load dimension. The normal storage space between different memory devices is used, and the memory capacity mapped with each other is larger. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0029] Figure 1 FIG. 1 is a schematic diagram of the data interaction process of the method for cross-device memory dynamic complementary utilization based on CXL protocol interconnection in the embodiments of the present application; Figure 2 FIG. 2 is a logic flow diagram of the method for cross-device memory dynamic complementary utilization based on CXL protocol interconnection in the embodiments of the present application. DETAILED DESCRIPTION

[0030] In order for those skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should belong to the scope of protection of the present application.

[0031] Traditional memory error detection mainly relies on the ECC (Error Correcting Code) mechanism, which realizes single-bit error correction and multi-bit error detection through additional check bits on the DDR controller side. However, the function of ECC is limited to detecting and repairing minor random errors. When the same physical unit has multiple errors in a short period of time, ECC can repeatedly correct but cannot actively isolate the area, nor can it realize cross-module physical address remapping. Therefore, long-term use will lead to a decrease in system reliability and even trigger serious multi-bit errors. For defective memory modules detected at the time of shipment, the current industry practice is to scrap or downgrade them, such as shielding the entire Bank or channel, but this will cause a waste of a large amount of available areas, making it difficult to achieve efficient use of defective memory. In the prior art, even if some memory controllers support partial row / column remapping mechanisms, they can only be completed within a single memory chip or module, and cannot be used for bad area compensation and complementary mapping between different DDR devices. With the development of Compute Express Link (CXL) interconnection technology, the host processor can access multiple independent memory devices in a consistent manner, realizing unified addressing and dynamic mapping across physical modules, and providing a new hardware foundation for flexible management of memory resources. However, the existing system has not fully utilized the interconnection and programmable mapping capabilities of CXL to implement bad area isolation and cross-device address repair mechanisms, and lacks joint utilization strategies for defective memory at the time of shipment, resulting in a large number of DDR devices with partial healthy storage units that cannot be put into use. Therefore, how to construct a bad area management method that can dynamically detect (find the location of storage space damage in real time while data is being transmitted), count, and remap across devices in a system with ECC detection function, combined with CXL protocol interconnection technology, to realize self-repairing during runtime and complementary use of defective memory at the time of shipment, has become an urgent need to improve memory reliability and manufacturing yield.

[0032] Specifically, as shown in Figure 1 and Figure 2 The method for dynamic complementary use of cross-device memory based on CXL protocol interconnection of the present application includes the following steps: Step one, error detection.

[0033] The ECC module of the memory detects the data in real time during the transmission of the data.

[0034] The specific steps of the detection are as follows: the ECC algorithm of the ECC module is used to check the check bits of the data, if the check bits of the data do not match the expected check value, the data is erroneous; the error type includes single-bit error and multi-bit error; if a single bit flip occurs, the data error is single-bit error, if multiple bit flips occur, the data error is multi-bit error.

[0035] Step two, error positioning.

[0036] When the data error is detected, the ECC module positions the error, updates the error count module corresponding to the position, and generates an error report. Each memory address is allocated with an error count module for tracking the number of occurrences of multi-bit errors at the position.

[0037] The error report includes one or more of the following information: error type, memory position where the error occurs, memory data where the error occurs; and at least includes the memory position where the error occurs, i.e. the error position is necessary to establish a connection with the subsequently selected target memory and transfer data.

[0038] When the error type is detected as single-bit error, the ECC module automatically repairs it; when the error type is detected as multi-bit error, the count value of the corresponding error count module is incremented by 1.

[0039] The specific steps of the positioning are as follows: based on the data where the error is detected, the ECC module returns the number of bits where the error occurs and reports the data position where the error occurs according to the position of the bit flip. In this way, the position where the error occurs can be obtained in real time during the data transmission.

[0040] Step three, mark the invalid region.

[0041] When the count value of the error count module reaches a set threshold, the region corresponding to the position is marked as an invalid region.

[0042] Step four, select the target memory.

[0043] The states of all memories are evaluated based on the spatial dimension, health dimension, latency dimension and load dimension, and the target memory is selected according to the evaluation results of the memory states.

[0044] The weight coefficient w health of the spatial dimension space The weight coefficient w latency of the latency dimension loadThe numerical values of the space dimension, the health dimension, the time delay dimension and the load dimension are sequentially reduced. health The weight coefficient w space corresponding to the health dimension latency The weight coefficient w load corresponding to the time delay dimension space The weight coefficient w health+ corresponding to the load dimension latency The weight coefficient w load =1.

[0045] The state of all memories is evaluated by scoring the state of the memory by the following formula, and the memory with the highest score is selected as the target memory: S=w space ×S space +w health ×S health +w latency ×S latency +w load ×S load In the formula, S space is the space dimension score of the memory, S health is the health dimension score of the memory, S latency is the time delay dimension score of the memory, S load is the load dimension score of the memory, w space is the weight coefficient corresponding to the space dimension, w health is the weight coefficient corresponding to the health dimension, w latency is the weight coefficient corresponding to the time delay dimension, and w load is the weight coefficient corresponding to the load dimension.

[0046] The space dimension score S space is calculated according to the free space ratio of the memory, and the higher the free space ratio, the higher the score. The free space ratio can be directly calculated according to the following formula: S space =free ratio.

[0047] The health dimension score S health is converted from the cumulative value of multi-bit errors to a score between 0 and 1 (the probability of error occurrence for a single memory device), and the fewer the number of errors and the lower the error rate, the higher the score. The health dimension score S ; In the formula, err is the cumulative value of multi-bit errors of a single memory device, and err max is the maximum number of multi-bit errors set for a single memory device.

[0048] The time delay dimension score S latencyTo normalize according to the average access latency of the fixed number of cycles, the smaller the latency, the higher the score, and the calculation is as follows: ; In the formula, latency is the average access latency, latency max is the set maximum access delay, i.e. the idle time ratio, counted according to the same fixed number of cycles.

[0049] Load dimension score S load For calculation according to port bandwidth utilization or IOPS utilization, the lower the load, the higher the score, and the formula is S load =1-Iport load.

[0050] In the formula, Iport load is the port bandwidth utilization or IOPS utilization.

[0051] In the process of selecting the target memory, if the memory corresponding to the failure area has the highest score, the memory with the second highest score (the second highest total score) is selected as the target memory.

[0052] Step five, establish a connection and transmit data.

[0053] Based on the error report and the selected target memory, a new logical address is allocated for the failure area; the logical address is passed to the target memory through the CXL protocol, and the address mapping table is updated; after the mapping is successful, the system migrates the data of the failure area to the healthy area of the target memory through the CXL protocol.

[0054] The application also provides a computer system for executing the above method, specifically, including a host and a plurality of independent memory expansion devices connected with the host through a CXL (Compute Express Link) interconnection bus, and an upper host corresponding to the upper level of the memory expansion device, such as a switch, and the upper host is provided with a CXL management module or a memory management unit (MMU).

[0055] Embodiment: The CXL protocol interconnection cross-device dynamic mapping and defective memory complementary utilization method of the embodiment is mainly applied to a server or a data center system with multiple DDR memory devices. The host (Host) performs consistent communication with a plurality of independent memory expansion devices (CXL Memory Expander) through a CXL (Compute Express Link) interconnection bus. Each CXL memory device internally includes a DDR storage chip and an ECC module.

[0056] Step one, data reading and error detection.

[0057] 1.1, data reading process Memory Access Request: When a host or application initiates a memory read request, it first sends a read instruction to the memory specifying the physical address to be accessed. These read requests go through the memory controller and are passed to the specific memory device (e.g., DDR).

[0058] Data Read from Memory Device: The memory controller loads the data from the specified memory location (e.g., memory page, row, or column) into the cache and transfers it to the CPU or application through the system bus.

[0059] ECC Check Initiation: After the data is read from the memory module, it passes through the ECC module of the memory controller during data transfer. The ECC module performs real-time checks on the read data to detect bit flips or errors. The specific checking process is as follows: 1.2, ECC Check Process Error Detection: The ECC module checks the read data based on the memory's check bits (usually additional bits added to the data, such as the 8-bit ECC of SEC-DED). If the data's check bits do not match the expected check value, the data is erroneous. If a single bit flip occurs, the data error is a single-bit error, and if multiple bit flips occur, the data error is a multi-bit error.

[0060] In this embodiment, an error counter module is assigned to each memory address (Rank, Row, Page) to track the number of multi-bit errors occurring at that memory location.

[0061] Single-bit Error: Through the ECC algorithm, the ECC module can detect and correct single-bit errors (single bit flips) detected by the automatic repair, ensuring data integrity. After repair, the data continues to be transferred to the host or application.

[0062] Multi-bit Error: Whenever the ECC module detects a multi-bit error, it immediately locates the memory location where the error occurred (Step Two below) and updates the error counter module corresponding to that location, increasing the count by one. When the count reaches a set value, the memory controller marks the region as "unrepairable," i.e., a failed region. As mentioned earlier, the error counter module is maintained separately for each memory page or row, so it can accurately track the number of errors and their locations for each memory region.

[0063] Step Two, Error Localization.

[0064] When the ECC module detects an error, it locates the specific location in the physical address through an algorithm and generates a detailed error report.

[0065] The error report includes: error type (single-bit error, multi-bit error), memory location where the error occurs (specific row number, column number, Rank number, etc. address information), memory data where the error occurs. These information provides the specific bad lane location of the error, and can be used for subsequent bad area (failure area) mapping decision.

[0066] The specific steps of the positioning process are as follows: for the data found to have errors, the ECC module returns the specific number of bits of the error according to the specific position of the bit flip, and reports the data area where the error occurs (for example, a certain cell of a certain row and column). In this way, the position where the error occurs can be obtained in real time during data transmission.

[0067] Step three, mark the failure area.

[0068] When the count value of the error counting module reaches a certain threshold, the system will automatically determine that the area is a "stability failure" area, i.e. a failure area. The ECC module will record the address of the failure area and its corresponding error type (such as single-bit or multi-bit error). The system will construct an address mapping table (step five below) between the address information and the subsequently selected target memory, which is used to track the location of each failure area and avoid the address from being used in the future. That is, if a memory area repeatedly experiences multi-bit errors and the error count exceeds the threshold (such as 3 times), the area will be marked as "unavailable" and needs to be mapped to a free area of another healthy memory device through the CXL protocol.

[0069] That is, for multi-bit errors that cannot be repaired, the ECC module will generate a detailed error report and report it to the system error log. After the number of unrepaired multi-bit errors reaches a threshold, the system will pass the error information (including error location, error type, and number of times) to the CXL management module, which will determine whether to start cross-device mapping or memory reallocation mechanism according to the error frequency and threshold.

[0070] The ECC module will periodically report error information to the upper level such as the CXL management module in the switch or the memory management unit (MMU), and record it in the system log. These information will be used for subsequent bad lane repair, resource reallocation, and memory state evaluation. Specifically, all error events, error types, and error counts of the corresponding memory area will be recorded in the system log file. The error log includes the following information: memory area address (Rank, Row, Page) where the error occurs; error occurrence time; error count (number of times); error type (single-bit error, double-bit error). Once the error is located and counted, the system will decide whether to perform data migration, replacement, or start other fault tolerance mechanisms according to the set repair strategy. The system will perform automatic repair or manual intervention according to these log data.

[0071] Step four, select target memory.

[0072] The state of each memory device not only considers the free space, but also evaluates its health condition (such as ECC error rate, delay, etc.). This helps the system to decide whether to continue using a certain device and how to balance resource utilization.

[0073] In this embodiment, the state of all memories is evaluated based on the space dimension, health dimension, latency dimension and load dimension, and the target memory is selected as the mapping target according to the evaluation result of the memory state, which is more reasonable and can more evenly balance resource utilization. Among them, the space dimension represents the usage rate and the remaining free space of the memory device; the health dimension represents the device error rate, etc.; the load dimension represents the workload, etc.; and the latency dimension represents the access latency of the device. These information is collected through the memory management unit and is updated regularly.

[0074] The above four dimensions are quantitatively evaluated by combining normalized scores and weights. Specifically, in this embodiment, the state of all memories is evaluated by scoring the state of the memory through the following formula, and the memory with the highest score is selected as the target memory: S=w space ×S space +w health ×S health +w latency ×S latency +w load ×S load In the formula, S space is the space dimension score of the memory, S health is the health dimension score of the memory, S latency is the latency dimension score of the memory, S load is the load dimension score of the memory, w space is the weight coefficient corresponding to the space dimension, w health is the weight coefficient corresponding to the health dimension, w latency is the weight coefficient corresponding to the latency dimension, and w load is the weight coefficient corresponding to the load dimension.

[0075] Among them, the space dimension score S space is calculated according to the free space ratio of the memory, and the higher the free space ratio, the higher the score. It can be directly calculated according to the following formula: S space =free ratio.

[0076] The health dimension score S health is converted from the cumulative value of multi-bit errors to a score between 0 and 1, and the fewer the number of multi-bit errors and the lower the error rate, the higher the score. It is calculated according to the following formula: ; In the formula, err is the cumulative value of multi-bit errors occurring in a single memory device; errmax is the maximum number of multi-bit errors set for a single memory device.

[0077] Latency Dimension Score latency To normalize the average access latency based on a fixed number of periods, a lower latency results in a higher score. The calculation is performed using the following formula: ; In the formula, latency is the average access latency, and latency max is the set maximum access latency.

[0078] Load dimension score S load The score is calculated based on port bandwidth utilization or IOPS utilization, with lower load resulting in higher scores. The formula is S. load =1-Iport load, where Iport load is the port bandwidth utilization or IOPS utilization.

[0079] The weighting coefficient w corresponding to the health dimension health The weight coefficient w corresponding to the spatial dimension space The weighting coefficient w corresponding to the time delay dimension latency The weight coefficient w corresponding to the load dimension load The values ​​decrease sequentially. The weight coefficient w corresponding to the health dimension... health The weight coefficient w corresponding to the spatial dimension space The weighting coefficient w corresponding to the time delay dimension latency The weight coefficient w corresponding to the load dimension load Satisfying the formula w space +w health+ w latency +w load =1.

[0080] In a typical "reliability-first" configuration, the following weighting coefficients can be used: W health =0.4; Health score has the highest weight, prioritizing devices with the fewest errors and the lowest error rate; w load =0.2; Taking into account both current load and bandwidth margin, avoid allocating newly mapped bad sectors to devices with high current load, thereby reducing performance bottlenecks; w space =0.3; Select devices with a higher proportion of free space to avoid overfilling any particular device; w latency =0.1; Access latency should be taken into account.

[0081] Based on factors such as free space ratio, device health, latency, and current load, idle and healthy memory devices are prioritized as mapping targets to balance resource utilization.

[0082] When selecting target memory for bad sectors or newly added logical regions, priority is given to selecting the devices with the highest overall scores as candidates. During the selection of target memory, if the memory corresponding to the failed region has the highest score, the memory with the second highest score is selected as the target memory to avoid the occurrence of multiple multi-bit errors in that memory, which would lead to frequent data migrations.

[0083] The weighting parameters can be adjusted by operations and maintenance personnel according to the business scenario. For example, in a "performance-first" scenario, the weighting parameter can be increased. latency and w load The value increases w in a "capacity-first" scenario. space The values ​​enable configurable optimization of space, reliability, performance, and load balancing.

[0084] Step 5: Establish a connection and transfer data.

[0085] The system selects the most suitable device based on priority (i.e., the highest score) and allocates a new logical address to the failed region. This logical address is then transmitted to the target memory via the CXL protocol, simultaneously updating the Memory Remapping Table (MRT). The specific steps are as follows: 5.1 Update the mapping table The system writes the selected target memory and its mapped logical address into the mapping table, and updates the physical address of the target memory. The mapping table ensures that each logical address maps to only one valid physical address.

[0086] 5.2 Data Migration and Repair After successful mapping, the system migrates the data from the original failed region to the healthy region of the target memory via the CXL protocol interconnect. During the data migration process, the system performs data verification (such as ECC or CRC check) to ensure the integrity of the migrated data.

[0087] 5.3 Consistency Verification After Mapping After data migration is complete, the system will perform data consistency verification to ensure that the data stored in the target memory is consistent with the source data. If data corruption or transmission errors are detected, the system will re-migrate the data or take other remedial measures.

[0088] 5.4 Update system logs Each mapping process records relevant information in the system log, including: the memory address and type of the error; the target memory and new address to be mapped; the timestamp and status of the mapping operation; and the data verification result.

[0089] When extracting data later, once it is confirmed that the data belongs to this port, the output port extracts the corresponding data from the new location using the remapped new address information and transmits the data to the host or device that needs it (the initiator of the read data command).

[0090] In existing server and high-performance computing systems, memory reliability directly impacts system stability. While more advanced DDR memory features ECC (Electronic Code Correction) to detect and correct single-bit errors, it cannot isolate repeatedly faulty memory cells or perform cross-module repair across different memory devices, leading to persistent error accumulation and resource waste. For defective DDR modules detected at the factory, current technologies typically scrap or mask bad blocks, failing to achieve complementary utilization of degraded memory. With the development of CXL (Continuous Memory Access) interconnect technology, hosts can achieve consistent addressing and dynamic mapping across multiple independent memory devices, enabling cross-device bad sector remapping and resource integration. However, current systems have not yet combined ECC detection with CXL mapping mechanisms to achieve runtime dynamic repair and factory-detected defective sector complementarity. Therefore, it is necessary to propose a cross-device dynamic mapping and degraded memory complementarity method based on CXL interconnect.

[0091] This invention is applicable to memory management in large-scale server systems, data centers, and high-performance computing environments, especially when memory modules have localized faults or defective areas. With the continuous increase in memory capacity and the increasing complexity of manufacturing technologies, memory modules inevitably suffer physical damage or errors during long-term use. Traditional memory management methods often only address the problem by shielding the entire memory module or a specific area, leading to a significant waste of available memory resources. This invention, however, combines CXL protocol interconnect technology and ECC error detection mechanisms to achieve dynamic repair of bad memory sectors and efficient resource utilization, avoiding the limitations of traditional methods. In large-scale distributed computing or cloud computing platforms, this invention can prioritize the migration and repair of bad sectors from idle memory devices based on real-time memory status (such as device idle rate and health), ensuring the continuous and stable operation of the system. Particularly for enterprise applications with high availability requirements (such as financial systems, online trading platforms, and scientific computing clusters), this invention provides an efficient, transparent, and automated memory management solution, ensuring that memory errors are located and repaired quickly and in real time while maximizing the efficiency of memory resource utilization and reducing hardware maintenance costs. Furthermore, this invention is also applicable to memory subsystem expansion and heterogeneous computing environments, enabling complementary use of resources between different memory devices to improve the performance and reliability of the entire computing system.

[0092] Specifically, the main technical means adopted in this invention include the following aspects: 1. Real-time error detection and counting mechanism based on ECC Utilizing the existing ECC detection function of the memory controller, the physical address information of each memory error is recorded, and an error counting module is set up. The system accumulates the number of errors at the same physical location, and when the count value exceeds a preset threshold, the location is determined to be a persistent failure area.

[0093] 2. Cross-device mapping and dynamic redirection based on CXL protocol interconnection Leveraging the programmable addressing and consistent access features of the CXL bus, logical addresses deemed invalid are remapped to another healthy DDR device. The mapping control module updates the memory address mapping table to complete data migration and address switching without affecting system operation, thus achieving bad sector avoidance across devices.

[0094] 3. Online detection and self-healing mechanism during operation During operation, the system continuously monitors ECC error events and dynamically updates the error count and mapping relationship. When a persistent failure unit is detected, a CXL remapping operation is automatically triggered without system shutdown or manual intervention, thereby achieving online repair and self-healing operation.

[0095] 4. Static residual memory complementary mapping during the factory delivery stage During the manufacturing or testing phase, a full address scan is performed on each DDR device to mark defective regions. Through the CXL mapping mechanism, healthy memory areas from different DDR devices are combined into a logically contiguous memory space, allowing multiple modules with localized defects to be used complementaryly, thus improving product yield.

[0096] 5. Unified bad sector management and logging mechanism Establish a unified bad sector management table at the system level to record error addresses, count values, remapping targets, and operation logs, thereby achieving closed-loop control of error detection, decision-making, and repair, and providing data support for subsequent diagnosis and maintenance.

[0097] Correspondingly, the technical solution of the present invention can solve the following technical problems: 1. The problem of being unable to effectively isolate repeatedly faulty memory cells. Traditional ECC mechanisms can only detect and repair random errors, lacking an automated identification and mitigation mechanism for multiple errors at the same physical address. This invention, through ECC error counting and threshold determination, can identify persistently failing units in real time and automatically trigger migration.

[0098] 2. The issue that bad sectors in memory can only be repaired within a single device. Existing row / column remapping or page-level masking mechanisms are limited to within a single DDR module and cannot achieve cross-device repair. This invention utilizes the unified addressing characteristics of the CXL protocol interconnect to dynamically map bad sector data to other healthy DDR devices, achieving bad sector avoidance and data redirection across modules. Furthermore, existing publicly available device repair methods are pre-processing rather than real-time processing. While pre-processing cross-device repair also uses address remapping, it cannot handle device failure updates under normal operating conditions. Existing cross-device repair methods involve first performing a full read / write check, then mapping the data before direct use. Each time a mapping is re-done, all tasks need to be shut down, a read / write check for errors needs to be initiated, and then address mapping needs to be performed again—unlike the solution of this invention.

[0099] 3. Issues that cannot be dynamically repaired during runtime. Existing solutions often rely on firmware or factory settings, failing to respond to errors in real time during system operation. This invention utilizes the CXL control module to monitor ECC errors in real time during runtime and dynamically update the address mapping table, achieving online repair and system self-healing.

[0100] 4. Problem of wasted DDR resources due to defective products shipped from the factory. In existing manufacturing processes, some memory modules are scrapped entirely due to localized defects. This invention enables a cross-module static mapping scheme, using CXL to combine the healthy areas of multiple defective memory modules into a single complete logical memory, thereby improving DDR utilization and yield.

[0101] 5. The problem of lacking a unified bad sector management and mapping mechanism. In traditional technologies, the detection, statistics, and migration processes are independent of each other. This invention establishes a closed-loop management system based on ECC detection, error counting, and CXL mapping control, realizing an automated management process from error detection to address migration.

[0102] In summary, this invention combines ECC error detection with CXL dynamic mapping to achieve fully automated management of the entire process from error detection and failure identification to cross-device dynamic remapping. It can dynamically repair faulty areas during operation and integrate defective modules at the factory stage, which can significantly improve the reliability and utilization of memory resources and solve key problems such as the inability to repair memory errors across devices, the inability to complement defective modules, and the lack of self-healing capabilities during operation.

[0103] The above embodiments prepared by the method of the present invention are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for cross-device memory dynamic complementary utilization based on CXL protocol interconnection, characterized in that, The method comprises the following steps: An ECC module of the memory detects data during data transmission; when detecting a data error, the ECC module locates the error, updates an error count module corresponding to the location, and generates an error report; When a count value of the error count module reaches a set threshold value, a region corresponding to the location is marked as a failed region; Based on a spatial dimension, a health dimension, a latency dimension, and a load dimension, states of all memories are evaluated, and a target memory is selected according to an evaluation result of the memory states; Based on the error report and the selected target memory, a new logical address is allocated for the failed region; the logical address is transmitted to the target memory through a CXL protocol, and an address mapping table is updated; After mapping is successful, the system migrates data of the failed region to a healthy region of the target memory through the CXL protocol.

2. The method of claim 1, wherein, The error report comprises one or more of the following information: an error type, a memory location where the error occurs, and memory data where the error occurs; and at least the memory location where the error occurs.

3. The method of claim 2, wherein, The error type comprises a single-bit error and a multi-bit error; when detecting that the error type is a single-bit error, the ECC module automatically repairs; when detecting that the error type is a multi-bit error, a count value of the corresponding error count module is increased by 1.

4. The method of claim 3, wherein, Each memory address is allocated with an error count module for tracking a number of occurrences of multi-bit errors of the location.

5. The method of claim 1, wherein, The detection is: using an ECC algorithm of the ECC module to check a check bit of data, if the check bit of data does not match an expected check value, the data is erroneous; if a single bit flip occurs, the data error is a single-bit error, if multiple bit flips occur, the data error is a multi-bit error.

6. The method of claim 5, wherein, The locating is: based on the detected erroneous data, the ECC module returns a number of bits where errors occur and reports a data location where errors occur according to a location of the bit flip.

7. The method of claim 1, wherein, The evaluation of the states of all memories is: scoring the states of the memories through the following formula, and selecting a memory with the highest score as the target memory: S = w space x S space + w health x S health + w latency x S latency + w load x S load In the formula, S space is a space dimension score of the memory, S health is a health dimension score of the memory, S latency is a latency dimension score of the memory, S load is a load dimension score of the memory, w space is a weight coefficient corresponding to the space dimension, w health is a weight coefficient corresponding to the health dimension, w latency is a weight coefficient corresponding to the latency dimension, w load is a weight coefficient corresponding to the load dimension.

8. The method of claim 7, wherein, The space dimension score S space For the calculation according to the free space ratio of memory, the higher the free space ratio, the higher the score, calculated as follows: S space = free ratio.

9. The method of claim 7, wherein, the health dimension score S health To convert the cumulative value of the multi-bit error into a score between 0 and 1, the fewer the number of multi-bit errors, the higher the score, and it is calculated according to the following formula: ； In the formula, err is a cumulative value of multi-bit errors of a single memory device; and err max is a maximum number of multi-bit errors of the single memory device.

10. The method of claim 7, wherein, The time delay dimension score S latency The average access time delay according to the fixed cycle quantity is normalized, and the smaller the time delay is, the higher the score is. The following formula is used for calculation: ； In the formula, latency is an average access latency, and latency max is a set maximum access delay.

11. The method of claim 7, wherein, The load dimension score S load For the calculation according to the port bandwidth utilization or IOPS utilization, the lower the load, the higher the score, and the formula is S load =1-Iport load; in the formula, Iport load is the port bandwidth utilization or IOPS utilization.

12. The method of claim 7, wherein, The weight coefficient w corresponding to the health dimension health The weight coefficient w corresponding to the space dimension space The weight coefficient w corresponding to the time delay dimension latency The weight coefficient w corresponding to the load dimension load Satisfy the formula w space +w health+ w latency +w load =1.

13. The method of claim 7, wherein, The weight coefficient w corresponding to the health dimension health The weight coefficient w corresponding to the space dimension space The weight coefficient w corresponding to the time delay dimension latency The weight coefficient w corresponding to the load dimension load The numerical values of the weight coefficients w of the health dimension, the space dimension, the time delay dimension and the load dimension are sequentially decreased.

14. The method of claim 1, wherein, In the process of selecting the target memory, if a memory corresponding to the failed region has the highest score, a memory with the second highest score is selected as the target memory.

15. A computer system, characterized by A device for performing the method of any one of claims 1-14.

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