Bus access permission allocation method and device, equipment, medium and product

Abstract

The invention relates to the technical field of chips, and provides a bus access permission allocation method and device, equipment, a medium and a product, and the method comprises the steps: obtaining all source units which initiate an access request for a target interface; generating a random number, wherein the random number falls within a numerical range determined by the number of the source units; establishing a mapping relationship between the physical identifier of each source unit and the continuous index value in the numerical range; searching the mapping relation according to the random number, selecting the source unit of which the mapping index value is consistent with the random number as a target source unit, and distributing the bus access authority to the target source unit. According to the method, the problem that individual core performance is limited due to a fixed polling sequence is avoided, the damage of a wooden barrel effect to the overall performance of the GPU is eliminated, and the bus bandwidth utilization rate and the cooperative operation efficiency of the multi-core processor under complex working conditions are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to a bus access permission allocation method, device, equipment, medium and product. BACKGROUND

[0002] In the multi-core architecture of a graphics processing unit (GPU), simultaneous read and write of a plurality of cores to a memory unit can easily cause bus conflicts, and an arbitration device such as a crossbar is usually used to select a core unit that can access the bus to allocate access permission.

[0003] At present, a plurality of source units (Src) are usually connected to a bus interface by a crossbar, and resources are allocated in a fixed order in a round-robin arbitration. Although the round-robin arbitration can prevent long-term inability to obtain bus access permission, when multiple cores cooperate to complete a task, if a specific memory access mode occurs, this method can cause uneven bandwidth allocation among the cores. For example, in a 4x4 crossbar simulation, a specific access order can cause the request processing time of an individual Src to be much higher than that of other Srcs, and this performance difference can seriously damage the overall performance of the GPU according to the principle of the weakest link. SUMMARY

[0004] The present application provides a bus access permission allocation method, device, equipment, medium and product to solve the defects in the related art.

[0005] The present application provides a bus access permission allocation method, comprising the following steps: obtaining all source units that initiate access requests for a target interface; generating a random number, the random number falling within a numerical range determined by the number of source units; establishing a mapping relationship between the physical identifiers of the source units and the consecutive index values within the numerical range; According to the random number, the mapping relationship is searched, and the source unit with the same index value as the random number is selected as a target source unit, and the target source unit is allocated bus access permission.

[0006] According to the bus access permission allocation method provided by the present application, each source unit is configured with a request queue, and the request queue includes a first-level register for storing a current access request and a second-level register for storing a subsequent access request; The bus access permission is allocated to the target source unit, comprising: allocating first-level bus access permission to the first-level register of the target source unit, and determining whether to allocate second-level bus access permission to the second-level register of the target source unit.

[0007] According to the bus access permission allocation method provided by the application, the determining whether to allocate the second-level bus access permission to the second-level register of the target source unit comprises: determining a second target interface in an idle state except for the first target interface occupied by the first-level bus access permission; allocating the second-level bus access permission to the second-level register in a case that an access request in the second-level register of the target source unit is directed to the second target interface.

[0008] According to the bus access permission allocation method provided by the application, the allocating the second-level bus access permission to the second-level register comprises: in a case that the access requests in the second-level registers of multiple target source units are all directed to the same second target interface, arbitrating the multiple target source units, selecting one target source unit from the multiple target source units, and allocating the second-level bus access permission to the second-level register of the selected target source unit.

[0009] According to the bus access permission allocation method provided by the application, after the allocating the bus access permission to the target source unit, further comprising: in a case that the target source unit acquires the first-level bus access permission and the second-level bus access permission, writing a new access request into the first-level register and the second-level register of the target source unit in parallel; in a case that the target source unit acquires only the first-level bus access permission, moving the access request in the second-level register into the first-level register, and writing a new access request into the second-level register.

[0010] According to the bus access permission allocation method provided by the application, the generating the random number comprises: generating an original random sequence by using a linear feedback shift register; performing a truncation operation to the original random sequence to a specified bit number or a modulo operation to a specified range to generate the random number.

[0011] The application further provides a bus access permission allocation device comprising the following modules: an obtaining module, configured to obtain all source units initiating access requests for a target interface; a generating module, configured to generate a random number, wherein the random number falls within a value range determined by the number of source units; an establishing module, configured to establish a mapping relationship between the physical identifiers of the source units and the continuous index values in the value range; The distribution module is configured to find the mapping relationship according to the random number, select a source unit with an index value consistent with the random number as a target source unit, and distribute bus access permission to the target source unit.

[0012] The application further provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the bus access permission distribution method according to any one of the above when executing the program.

[0013] The application further provides a non-transitory computer-readable storage medium, which stores a computer program, and the computer program is executable on a processor to implement the bus access permission distribution method according to any one of the above.

[0014] The application further provides a computer program product, which includes a computer program, and the computer program is executable on a processor to implement the bus access permission distribution method according to any one of the above.

[0015] The application provides a bus access permission distribution method, device, equipment, medium and product, which realizes randomization and fairness of arbitration strategy by acquiring current all source unit requests, dynamically generating a random number based on the number of source units, and then using a mapping mechanism of a physical identifier and a continuous index value to randomly distribute bus permission to one of the source units. Since the random number is used to break the fixed priority order in the traditional polling arbitration, the specific interleaved memory access mode in the multi-core cooperative task can be effectively dealt with, the problem of limited performance of individual core caused by the fixed polling order is avoided, the damage of the bucket effect to the overall performance of the GPU is eliminated, and the bus bandwidth utilization and cooperative operation efficiency of the multi-core processor under complex working conditions are improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is one of the flowcharts of the bus access permission distribution method provided by the application.

[0018] Figure 2 is the second flowchart of the bus access permission distribution method provided by the application.

[0019] Figure 3 is a two-stage arbitration flowchart provided by the application.

[0020] Figure 4 is a structural schematic diagram of a bus access right allocation apparatus provided by the present application.

[0021] Figure 5 is a structural schematic diagram of an electronic device provided by the present application.

[0022] Reference signs: 410: an acquisition module; 420: a generation module; 430: an establishment module; 440: an allocation module; 510: a processor; 520: a communication interface; 530: a memory; 540: a communication bus. DETAILED DESCRIPTION

[0023] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below in combination with the drawings in the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0024] In the current GPU architecture, most of them adopt the architecture of multi-core processors. When multiple cores simultaneously access the storage unit for reading and writing, there may be bus conflicts, at which time an arbitrator is needed to arbitrate the multiple cores that are performing storage unit reading and writing, and the winner can get the bus access right. Especially when multiple cores access multiple bus interfaces, multiple arbitrators or cross switches are usually used to select the core unit that can access the bus. For example, in a 4x4 cross switch structure, 4 arbitrators are used to select 4 Srcs, i.e. the above-mentioned core units, each of which can access 4 bus interfaces.

[0025] Under the above architecture, the commonly used arbitrator currently adopts a round-robin arbitration algorithm, i.e. according to a fixed order, it cyclically allocates resource use right to each Src. In most cases, round-robin arbitration can achieve fairness of each source. However, when the GPU multi-core needs to cooperate to complete a task, according to the characteristics of the current GPU software and hardware, there may be a case that the performance of some cores is significantly less than that of other cores, resulting in that the bandwidth cannot be fully utilized.

[0026] Specifically, through simulation, it is found that when multiple cores cooperatively complete a memory read-write task, the access order of each core may appear a specific interleaving pattern. In this pattern, if a 4x4 arbiter is used and a round-robin arbitration algorithm is adopted, when each Src makes 1000 bus requests, the time consumption of a certain Src may be much higher than that of other Srcs. According to the principle of the weakest link, this unfairness caused by the fixed round-robin order will make the speed of a certain core significantly slower than that of other cores, thereby seriously damaging the overall performance of the GPU.

[0027] To this end, the application provides a bus access permission allocation method, which aims to obtain all source units that initiate access requests to a target interface, establish a mapping between physical identifiers and consecutive index values, and select a target source unit from the source units by using a generated random number, so as to break the fixed order limitation of traditional round-robin arbitration, eliminate the performance bottleneck in a specific access mode, and thus improve the fairness and overall operation performance when multiple cores work cooperatively.

[0028] Among them, Figure 1 is one of the flowcharts of the bus access permission allocation method provided by the application, Figure 2 is another flowchart of the bus access permission allocation method provided by the application, as shown in Figure 1 and Figure 2 The method comprises steps 110, 120, 130 and 140.

[0029] Step 110, obtaining all source units that initiate access requests to a target interface.

[0030] Here, the target interface can be understood as an access entrance of a shared resource, which can be a storage unit interface, a cache interface, or other forms of bus slave device interface. The target interface is used to receive read-write instructions from core units and provide a data channel. The source unit can be understood as an active component that initiates bus access, which can be a streaming multiprocessor in a GPU, a CPU core, etc.

[0031] The source unit refers to a source unit that actually sends an access request in the current arbitration period and the request is valid. Among them, the source unit can be determined by detecting the bus request signal level state of each source unit. For example, if the access requests of source unit 0 (Src0) and source unit 2 (Src2) are high level, and the access requests of source unit 1 (Src1) and source unit 3 (Src3) are low level, then the current source units are determined as Src0 and Src2.

[0032] It should be noted that not all cores will initiate access requests in each clock cycle when performing multi-core cooperative processing. Therefore, the acquisition source unit is the basis for subsequent fair and dynamic arbitration, which can filter out idle cores and avoid resource waste.

[0033] Step 120, generating a random number, the random number falls within a value range determined by the number of source units.

[0034] Specifically, the random number is generated to break the order restriction of fixed priority in traditional polling arbitration. The random number can be generated by a pseudo-random number generator (such as a linear feedback shift register) or a true random number generator.

[0035] Considering that the number of source units participating in competition changes dynamically in different clock cycles, if the generation range of the random number is fixed, it may cause the generated random number to point to an idle port that does not initiate a request, resulting in invalid arbitration or clock cycle waste. Therefore, the random number in this embodiment falls within a value range determined by the number of source units. The value range here can be understood as covering the logical sequence interval of all candidates participating in the current competition, which can be a continuous integer interval.

[0036] For example, if there are N source units, considering that computer logic processing usually starts counting from 0 and in order to facilitate subsequent compact index mapping, the value range of the generated random number R is usually set to integers between 0 and N-1.

[0037] As an optional embodiment, assuming that there are 3 source units (such as Src0, Src1 and Src3) simultaneously requesting access to the same target interface, the number of source units is 3, and the above value range is [0, 2], that is, the random number is generated in the three values 0, 1 and 2.

[0038] Step 130, establishing a mapping relationship between the physical identifiers of each source unit and the continuous index values in the value range.

[0039] Specifically, the physical identifier refers to the fixed number or address of the source unit in the hardware circuit. For example, in a 4-port system, the physical identifiers of the 4 source units are usually 0 (00b), 1 (01b), 2 (10b), and 3 (11b), respectively.

[0040] The continuous index value refers to the logical number after re-compact arrangement of discrete source units to adapt to the continuous random number range generated in step 120.

[0041] Since the physical identifiers of the source units can not be continuous, such as only Src0 and Src3 initiate access requests, the physical IDs are 0 and 3, and the middle 1 and 2 are missing, while the generated random number is continuous. If the random number is directly used to match the physical ID, it can cause no match or matching error. Therefore, a compression mapping from the physical identifier to the continuous index value needs to be established.

[0042] For example, when Src0 (physical ID = 0), Src2 (physical ID = 2), and Src3 (physical ID = 3) initiate access requests, the physical identifier "0" of Src0 is mapped to the index value "0", the physical identifier "2" of Src2 is mapped to the index value "1", and the physical identifier "3" of Src3 is mapped to the index value "2". In this way, no matter which source units are in an active state, the logical index value thereof is always continuously increased from 0, which exactly corresponds to the value range of the random number.

[0043] Step 140: According to the mapping relationship, the source unit with the same index value as the random number is selected as the target source unit, and the bus access permission is allocated to the target source unit.

[0044] Specifically, the target source unit refers to the source unit that is determined to obtain the bus use right in the current arbitration period, and is allowed to transmit data or send a command to the target interface. Considering that the random number itself represents the winning position in the effective request queue, rather than the physical port number, in this embodiment, the mapping relationship is found according to the random number, and the source unit with the same index value as the random number is selected as the target source unit.

[0045] As an optional embodiment, the generated random number can be used as a selection signal to index the corresponding physical identifier in the established mapping relationship through a hardware lookup table or a multiplexer logic, so as to determine the target source unit. In this step, the arbitrator uses the random number as the winning index to inversely find the corresponding target source unit through the mapping relationship established in step 130, and sends an access request permission to the target source unit.

[0046] Continuing the above example, if the random number generated in step 120 is "1", according to the mapping relationship in step 130, the index value "1" corresponds to Src2 with the physical identifier "2". Therefore, Src2 is selected as the target source unit, and Src2 obtains the bus access permission this time.

[0047] The embodiment adopts a random arbitration mode, and mainly aims to solve the performance bottleneck problem of the polling arbitration in a specific mode in the related art. In the related art, if multiple source units cooperatively complete a task and the access sequence presents a specific interleaving mode, the waiting time of some source units is significantly increased when the polling arbitration with a fixed sequence is adopted. According to the barrel principle, the overall performance of the GPU depends on the slowest core.

[0048] The embodiment introduces randomness through steps 120 and 140, so that in each arbitration, the probability of each source unit obtaining the bus permission is dynamic and tends to be equal, and is no longer subject to the fixed polling sequence. This means that even if the access request sequence of a specific source unit is specifically interleaved or partially inverted with the access request sequence of other source units, for example, the request target sequence of a source unit is reversed in time compared with other source units, causing its access request to continuously conflict with the fixed priority sequence of the polling arbitration, the random arbitration of the embodiment can also scatter and allocate the bus permission.

[0049] Since the generated random number is uniformly distributed in the value range determined by the number of source units, and each source unit uniquely corresponds to an index value in the value range through a mapping relationship, the probability of each source unit being selected as a target source unit in a single arbitration process is the same, so in the long term, the opportunity of each source unit to obtain the allocated permission is equal, thereby eliminating the case that any source unit is stuck by a specific sequence and the performance is greatly reduced, so that the processing progress of each source unit is kept synchronized, and the bandwidth is maximally utilized.

[0050] The bus access permission allocation method provided by the embodiment generates a random number based on the number of source units by acquiring the current request of all source units, and then uses the mapping mechanism of the physical identifier and the continuous index value to randomly allocate the bus permission to one of the source units, realizing the randomization and fairness of the arbitration strategy. Since the random number breaks the fixed priority sequence in the traditional polling arbitration, the specific interleaving access mode in the multi-core cooperative task can be effectively dealt with, the problem that the performance of an individual core is limited due to the fixed polling sequence is avoided, the damage of the barrel effect to the overall performance of the GPU is eliminated, and the bus bandwidth utilization and cooperative operation efficiency of the multi-core processor under complex working conditions are improved.

[0051] Considering that in the high-speed bus transmission scenario of the GPU, there is a loss of clock cycles between the completion of arbitration logic judgment by the arbiter and the actual start of data transmission on the bus. If only the current request is processed, and the next round of request and arbitration is re-initiated after each data transmission is completed, idle bubbles can be generated on the bus, resulting in that the bandwidth cannot be utilized to the extreme. Especially when a certain source unit is limited in performance due to a specific interleaving mode, if the internal continuous instruction stream of the source unit cannot be responded quickly, the bucket effect will be further aggravated.

[0052] Based on this, in order to further improve the data throughput efficiency of the winning source unit and mask the arbitration delay, each source unit is configured with a request queue, which includes a first-level register for storing a current access request and a second-level register for storing a subsequent access request.

[0053] Here, the request queue can be understood as a cache structure arranged at the output end of the source unit. The first-level register can be understood as a register directly interacting with the input end of the arbiter, which is used to store the access request at the head of the queue which needs to be processed urgently. The second-level register can be understood as a backup register behind the first-level register, which is used to store the next access request following the current access request. For example, when the source unit (Src1) needs to continuously write two pieces of data to the storage unit, the first write request is stored in the first-level register, and the second write request is stored in the second-level register.

[0054] Correspondingly, after the target source unit is determined in step 140, the process of allocating bus access rights to the target source unit in the embodiment includes: allocating first-level bus access rights to the first-level register of the target source unit, and determining whether to allocate second-level bus access rights to the second-level register of the target source unit.

[0055] First, the arbiter allocates first-level bus access rights to the first-level register of the target source unit, which means that the arbiter sends the first grant signal to the source unit, allowing it to send the address and control signal in the first-level register to the bus to start the current read / write operation.

[0056] Then, at the same time or immediately after the allocation of the first-level rights, the arbiter does not immediately disconnect or turn to the next round of indiscriminate random arbitration, but further determines whether to allocate resources in advance, that is, whether to allocate second-level bus access rights to the second-level register of the target source unit.

[0057] As an optional embodiment, the determining process can be based on the status bit of the second-level register. If the second-level register of the target source unit is empty (i.e. invalid), the second-level privilege is not allocated, the arbiter ends the current process after completing the first-level request processing, and prepares to enter the next arbitration cycle. If the second-level register of the target source unit is not empty (i.e. valid), it indicates that the source unit has continuous access requirements. At this time, in order to reduce the overhead of context switching, the arbiter can determine to allocate the second-level bus access privilege to the second-level register.

[0058] For example, in a certain cooperative task, Src1 as the target source unit accumulates a large number of tasks, and its performance becomes a bottleneck. When Src1 is selected as the target source unit in step 140 according to the random arbitration mechanism of the above embodiment, the first-level register of Src1 stores an access request A, and the second-level register stores an access request B. This embodiment first allows the access request A to access the bus. Then, it is detected that there is an access request B in the second-level register, and the target interface of the access request B is the same as or compatible with the access request A. Therefore, the arbiter can directly approve the access request B to use the bus immediately after the end of the access request A, without the need for the access request B to return to the random pool of all source units again to compete for the bus.

[0059] This embodiment realizes the pipeline processing of continuous bus requests by configuring two-level request queues in the source unit and introducing the pre-judgment allocation mechanism for the second-level register when allocating the privilege. Since the target source unit can continuously process two-level requests when it gets the opportunity to access the bus, the frequency of repeated intervention of the arbitration logic is reduced, the bus transmission gap is effectively filled, and the bus bubble problem caused by frequent arbitration switching is avoided.

[0060] Considering that in a multi-core processor using a crossbar architecture, multiple source units can access different target interfaces at the same time to realize parallel transmission. However, when two continuous access requests initiated by a source unit point to different target interfaces, if the target interface occupied by the first access request and the target interface pointed to by the second access request are both in a busy state, or simple sequential processing leads to insufficient parallelism, the bus utilization rate will be reduced. In order to fully tap the parallel processing potential between multi-level requests and improve the throughput performance under the two-level arbitration architecture while ensuring data consistency.

[0061] Based on this, this embodiment further refines the above step of determining whether to allocate the second-level bus access privilege to the second-level register of the target source unit, specifically including: determining a second target interface in an idle state other than the first target interface occupied by the first-level bus access privilege; In the case that the access request in the second level register of the target source unit is directed to the second target interface, the second level bus access right is allocated to the second level register.

[0062] In particular, the first target interface refers to the bus interface that is being accessed or will be accessed by the current access request in the first level register of the target source unit. The second target interface refers to the bus interface that is in an idle state at the current time, in addition to the first target interface and not being locked by other high priority operations. The idle state can be determined by detecting the busy / idle signals of the target interfaces or the occupation mask of the arbiter.

[0063] For example, assume that the source unit 1 (Src 1) obtains the first level bus access right and is accessing the first target interface (dst 1). At this time, the states of the remaining interfaces (e.g., dst 2, dst 3 and dst 4) are checked. If the dst 3 and the dst 4 are not currently occupied by other source units, the dst 3 and the dst 4 are the second target interfaces in the idle state.

[0064] After the second target interface is determined, the target address of the subsequent access request stored in the second level register of the target source unit is checked. The target address is matched with the identifier of the second target interface, and then it can be determined whether the access request in the second level register is directed to the second target interface. If yes, it indicates that the current access request and the subsequent access request access different target interfaces and do not conflict with each other, and have the condition of parallel processing.

[0065] At this time, the second level bus access right is allocated to the second level register of the target source unit, and the target source unit is allowed to immediately start the access operation, so as to realize the parallel execution of the current access request and the subsequent access request.

[0066] Table 1 is a list of the access interfaces of the registers of the source units. As shown in Table 1, in the arbitration of the first level register, the first level registers of the source unit 1, the source unit 2 and the source unit 3 simultaneously compete for the interface 0, and the source unit 1 is selected as the target source unit by the random arbitration of the above embodiment. At this time, the first level register of the source unit 1 obtains the access right of the interface 0. Meanwhile, the first level register of the source unit 0 requests to apply for the access to the interface 1. At this time, there is no other competing source unit, and the first level register of the source unit 0 obtains the access right of the interface 1. At this time, the arbitration of the first level register ends, the interface 0 and the interface 1 are occupied, and the interface 2 is idle.

[0067] Next, the second level registers of the source unit 0 and the source unit 1 are checked. The second level register of the source unit 0 requests to access the interface 2, and the second level register of the source unit 1 requests to access the interface 1. The interface 1 is in the occupied state, and the interface 2 is in the idle state. Therefore, the second level bus access right is allocated to the second level register of the source unit 0.

[0068] After the above permission assignment, source unit 0 can send the current access request to interface 1 and the subsequent access request to interface 2 in the same pipeline cycle.

[0069] Table 1: List of access interfaces of each level of registers of source units

[0070] The embodiment realizes parallel requests within a single source unit by acquiring the second target interface in an idle state and assigning the second-level bus access permission to the second-level register in the case that the access request in the second-level register of the target source unit is directed to the second target interface, so that the access requests in the first-level register and the second-level register of the target source unit can be written or forwarded in parallel, greatly improving the utilization rate of the bus bandwidth and avoiding the problem that the subsequent request directed to the idle interface is unnecessarily blocked due to the occupation of a single interface by the previous request.

[0071] wherein, Figure 3 is a two-level arbitration flow diagram provided by the embodiment, as shown in Figure 3 First, each source unit (such as source unit 0, source unit 1, source unit 2, and source unit 3) is configured with a request queue, which includes a first-level register for storing a current access request and a second-level register for storing a subsequent access request. The first-level arbiter arbitrates the access requests in the first-level registers of each source unit, determines a target source unit that obtains the first-level bus access permission, and identifies a first target interface occupied by the first-level bus access permission, such as source unit 1 as the target source unit and access interface 0, which is the first target interface.

[0072] Then, according to the arbitration result of the first-level arbiter, a state mask is generated to determine a second target interface in an idle state other than the first target interface occupied by the first-level bus access permission.

[0073] Next, the second-level arbiter is controlled according to the state of the second target interface. If the subsequent access requests in the second-level register of the target source unit are directed to the second target interface, the second-level arbiter will arbitrate these requests and assign the second-level bus access permission to the winning second-level register.

[0074] Finally, the arbitration result is routed to the corresponding interface through the multiplexer of the output terminal. If the second-level bus access permission is assigned, the multiplexer allows the access request of the second-level register to be transmitted through the idle interface. In this way, when both the first-level register and the second-level register are authorized, two access requests can be written or processed simultaneously, thereby realizing parallel processing of the access requests in the first-level register and the second-level register and optimizing the bus performance.

[0075] Considering that after determining the second target interface in the idle state, there can be a concurrent conflict scenario, i.e., multiple different target source units in the second level register, which happen to request access to the same idle second target interface. Since a bus interface can only respond to the read-write operation of one source unit at the same time, if the permission is directly assigned without distinction, it will lead to data conflict or bus error. In order to effectively solve the conflict problem of multiple sources competing for the same idle resource while improving parallelism by using the idle interface, and ensure the orderliness of bus transmission.

[0076] Based on this, the embodiment further refines the step of assigning the second level bus access permission to the second level register, specifically comprising: In the case where the access requests of multiple target source units in the second level register all point to the same second target interface, arbitrating the multiple target source units, selecting one target source unit from the multiple target source units, and assigning the second level bus access permission to the second level register of the selected target source unit.

[0077] Specifically, the multiple target source units refer to the source unit set in which the second level register stores an effective access request, and the target address of the access request points to the same second target interface in the idle state within the current arbitration period.

[0078] For this specific second target interface, the corresponding arbiter logic is activated to select between the above multiple competing target source units. Specifically, the arbitration strategy can follow the random arbitration mechanism of steps 110-140, or other strategies, which are not specifically limited by the embodiment.

[0079] For example, after the first level arbitration ends, interface 0 and interface 1 are in the occupied state, and interface 2 is in the idle state. The second level register of source unit 0 requests to access interface 2, and the second level register of source unit 1 also requests to access interface 2. In this case, although interface 2 is idle, source unit 0 and source unit 1 both request access. The arbiter intervenes and arbitrates source unit 0 and source unit 1. Assuming that the arbitration result selects source unit 0, the arbiter only assigns the second level bus access permission to the second level register of source unit 0, allowing the access request of the second level register of source unit 0 to occupy interface 2, while the access request of the second level register of source unit 1, although pointing to interface 2, fails in arbitration and cannot obtain permission in this period, and needs to wait for the next period.

[0080] The embodiment introduces a secondary arbitration mechanism for the idle interface in the second level permission allocation stage, solves the conflict problem of multiple subsequent requests competing for the same idle resource. Since the competition source can be accurately identified and the arbitrator can be used to select a unique winner, the bus idle time slot is filled to the maximum extent under the premise of ensuring that the data transmission does not interfere with each other, safe and efficient instruction level parallel processing is realized, and the overall throughput performance of the multi-core processor under complex cooperative tasks is further improved.

[0081] Considering that under the architecture of two-level request queue, the request processing speed of the source unit directly affects the emptying efficiency of its internal queue. In order to ensure that the source unit can continuously initiate requests, and avoid blocking the upstream instruction stream due to full queue, the content in the register needs to be updated in time after the current request obtains arbitration and goes to the bus, so as to maintain the efficient operation of the pipeline. Especially when the source unit has higher bandwidth write capability, this capability should be fully utilized to match the parallel transmission efficiency of the bus end.

[0082] Based on this, the embodiment further includes register updating and pipeline management steps for different authorized situations after allocating bus access permission to the target source unit: In the case that the target source unit obtains the first level bus access permission and the second level bus access permission, the new access request is written to the first level register and the second level register of the target source unit in parallel; In the case that the target source unit only obtains the first level bus access permission, the access request in the second level register is moved to the first level register, and a new access request is written to the second level register.

[0083] Specifically, the target source unit obtaining bus access permission includes two cases: one is that the target source unit obtains the first level bus access permission and the second level bus access permission at the same time, that is, the access requests in the first level register and the second level register of the target unit are both approved to be sent in the same period. Two is that the target source unit only obtains the first level bus access permission, and the second level bus access permission is not allocated.

[0084] Specifically, when the target source unit can send requests with higher bandwidth, if it is detected that the first level and the second level register have been authorized, that is, the access requests in the two registers have been successfully transmitted to the bus, then the positions of the two registers will be idle after the current period ends.

[0085] At this time, the instruction distribution logic in the target source unit can take advantage of the high bandwidth characteristics to take out two new access requests from the instruction cache and write them to the first level register and the second level register respectively, realizing the double sending effect, so that the request queue always maintains a full state, maximizing the throughput of the source unit.

[0086] When only the access request in the first level register is granted to send, the first level register becomes idle, but the access request in the second level register is stranded due to the lack of right. In order to maintain the first-in first-out order and make room to receive new access requests, the access request stranded in the second level register is moved to the first level register, which becomes the first processing object in the next round of arbitration. At this time, the second level register is vacated, the control logic takes a new access request from the instruction cache and writes it into the second level register, maintaining the standard pipeline flow and ensuring that the request advances in order without causing the entire queue to stall due to the temporary blocking of the access request in the second level register.

[0087] Considering that in hardware circuit design, the implementation cost and generation speed of the random number generator directly affect the overall performance of the arbiter. If a complex true random number generation algorithm is used, although the randomness is better, it will consume a large number of logic gate resources and increase the clock delay, which may not meet the timing requirements of the GPU high-frequency bus access. The linear feedback shift register has the characteristics of simple structure, fast speed and small area occupation, and the pseudo-random sequence generated by it is sufficient to break the fixed dead loop of the polling arbitration in statistical characteristics.

[0088] Based on this, the embodiment further refines the steps of generating random numbers, specifically including: Generating an original random sequence using a linear feedback shift register; Truncating the original random sequence to a specified number of bits or performing a modulo operation to a specified range to generate a random number.

[0089] Specifically, the linear feedback shift register is a pseudo-random number generator composed of a shift register and an XOR logic gate. It uses a part of the current state of the register to perform an XOR operation and then feeds back to the input end, thereby generating a series of pseudo-random binary sequences.

[0090] The original random sequence refers to the binary value directly output by the linear feedback shift register. Since the bit width of the linear feedback shift register is usually fixed, the range of the generated value is usually [1, 2 k -1], k is the bit width.

[0091] Since the number of source units is dynamically changing and usually small, the range of the generated original random sequence is often much larger than the number of source units, and direct use will cause index out of bounds. Therefore, it is necessary to compress the value of the original random sequence to a value range determined by the number of source units.

[0092] Truncation to a specified number of bits means that when the number of source units is exactly a power of 2, several least significant bits of the binary representation of the original random sequence are directly selected as the result. Modulo to a specified range means dividing the value of the original random sequence by the number of source units and taking the remainder as the result. Performing truncation to a specified number of bits or modulo to a specified range operations on the original random sequence can map a large range of original random values ​​to a small interval [0, N-1], thereby generating random numbers that fall within the numerical range determined by the number of source units. Here, N represents the number of source units.

[0093] Table 2 lists the request completion times of each source unit during permission allocation in related technologies and the present invention. As shown in Table 2, the random arbitration mechanism in the present invention significantly reduces the request completion time of each source unit compared to the polling arbitration mechanism in related technologies. Specifically, for source unit 1, the request completion time in related technologies is 1500 units of time, while in the present invention it is 990 units of time, representing a significant performance improvement. This eliminates the long-tail latency phenomenon caused by specific access patterns, effectively avoiding the bottleneck effect from dragging down the overall system performance and achieving efficient parallel processing under multi-core collaborative tasks.

[0094] Table 2. List of request completion times for each source unit when allocating permissions for related technologies and this invention.

[0095] The bus access permission allocation device provided by the present invention is described below. The bus access permission allocation device described below can be referred to in correspondence with the bus access permission allocation method described above.

[0096] Based on any of the above embodiments Figure 4 This is a schematic diagram of the bus access permission allocation device provided by the present invention, as shown below. Figure 4 As shown, the device includes: Module 410 is used to obtain all source units that have initiated access requests to the target interface; The generation module 420 is used to generate random numbers that fall within a numerical range determined by the number of source units; Module 430 is established to establish the mapping relationship between the physical identifiers of each source unit and the continuous index values ​​within the numerical range; The allocation module 440 is used to find the mapping relationship based on the random number, select the source unit whose index value matches the random number as the target source unit, and allocate bus access permissions to the target source unit.

[0097] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 5As shown, the electronic device may include a processor 510, a communications interface 520, a memory 530, and a communication bus 540, wherein the processor 510, the communications interface 520, and the memory 530 communicate with each other through the communication bus 540. The processor 510 can call logical instructions in the memory 530 to execute a bus access permission allocation method.

[0098] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0099] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer is able to execute the bus access permission allocation method provided by the above methods.

[0100] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the bus access permission allocation methods provided by the methods described above.

[0101] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0102] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of allocating bus access rights, characterized by, The method comprises the following steps: acquiring all source units initiating access requests for a target interface; generating a random number, the random number falling within a numerical range determined by the number of source units; establishing a mapping relationship between the physical identifiers of the source units and the continuous index values within the numerical range; finding the mapping relationship according to the random number, selecting a source unit with a mapped index value consistent with the random number as a target source unit, and allocating bus access rights to the target source unit.

2. The bus access right allocation method according to claim 1, characterized by, Each source unit is configured with a request queue, the request queue comprising a first-level register for storing a current access request and a second-level register for storing a subsequent access request; allocating bus access rights to the target source unit comprises: allocating first-level bus access rights to the first-level register of the target source unit, and determining whether to allocate second-level bus access rights to the second-level register of the target source unit.

3. The bus access right allocation method according to claim 2, wherein The determination of whether to allocate second-level bus access rights to the second-level register of the target source unit comprises: determining a second target interface in an idle state other than a first target interface occupied by the first-level bus access rights; in the case where the access request in the second-level register of the target source unit is directed to the second target interface, allocating second-level bus access rights to the second-level register.

4. The bus access right allocation method according to claim 3, wherein The allocation of second-level bus access rights to the second-level register comprises: in the case where the access requests in the second-level registers of multiple target source units are all directed to the same second target interface, arbitrating the multiple target source units, selecting one target source unit from the multiple target source units, and allocating the second-level bus access rights to the second-level register of the selected target source unit.

5. The bus access right allocation method according to claim 2, wherein After allocating bus access rights to the target source unit, the method further comprises the following steps: in the case where the target source unit acquires the first-level bus access rights and the second-level bus access rights, writing a new access request into the first-level register and the second-level register of the target source unit in parallel; in the case where the target source unit only acquires the first-level bus access rights, moving the access request in the second-level register into the first-level register, and writing a new access request into the second-level register.

6. The bus access right allocation method according to any one of claims 1 to 5, characterized by, The generation of the random number comprises the following steps: generating an original random sequence by using a linear feedback shift register; performing a truncation operation to a specified number of bits or a modulo operation to a specified range on the original random sequence to generate the random number.

7. A bus access right allocation apparatus characterized by comprising: The method comprises the following steps: an acquiring module, configured to acquire all source units initiating access requests for a target interface; a generating module, configured to generate a random number, the random number falling within a numerical range determined by the number of source units; an establishing module, configured to establish a mapping relationship between the physical identifiers of the source units and the continuous index values within the numerical range; an allocating module, configured to find the mapping relationship according to the random number, select a source unit with a mapped index value consistent with the random number as a target source unit, and allocate bus access rights to the target source unit.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, The computer program is executed by the processor to implement the bus access right allocation method according to any one of claims 1 to 6. 9.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the bus access right allocation method according to any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the bus access right allocation method according to any one of claims 1 to 6.

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