Communication method of processor and retimer, electronic equipment and readable storage medium

Abstract

The invention discloses a communication method of a processor and a retimer, an electronic device and a readable storage medium, and relates to the technical field of communication, and the method comprises the steps: disassembling a bidirectional link establishment process of a processor receiving end and the retimer into two independent stages: the retimer sends a first signal, and the processor sends a second signal, each stage has a clear transmission direction and a detection main body, the signal receiving state can be detected in real time, and an abnormal link can be accurately positioned. Respectively designing repair measures for the two-stage abnormity: resetting and re-initializing the signal if the signal receiving end of the processor cannot receive the first signal; and if the retimer cannot receive the second signal, the substrate management controller restarts the system side receiving end of the substrate management controller. Therefore, interference to normal components is reduced, the problems of rough exception handling and high recovery cost of related methods are solved, and the link establishment efficiency and the system resource utilization rate are improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication method between a processor and a retimer, an electronic device, and a readable storage medium. Background Technology

[0002] With the rapid development of fields such as artificial intelligence, high-performance computing, and data centers, the Graphics Processing Unit (GPU) has become a core computing device due to its powerful parallel computing capabilities. In practical applications, the GPU needs to perform a large amount of high-frequency data interaction with external devices such as storage devices and other computing nodes. Currently, data transmission between the GPU and external devices is mainly achieved through a reliable interconnect architecture between the GPU and the physical layer timer. The efficiency and stability of the bidirectional interconnect between the GPU and the physical layer timer affect the overall system performance.

[0003] Mainstream bidirectional link establishment methods generally employ simple sequential execution logic, which lacks a flexible error handling mechanism in its process design. When problems such as signal lock timeout or link negotiation anomalies occur during link establishment, the entire link establishment process must be restarted, significantly extending the total link establishment time. This is especially problematic in complex electromagnetic environments or multi-device interconnection scenarios, where frequent restarts can severely slow down system startup speed. Summary of the Invention

[0004] This application provides a communication method, electronic device, and readable storage medium between a processor and a retimer, to at least solve the problem that the bidirectional link establishment method between the GPU and the physical layer retimer in the related art adopts a simple sequential execution mechanism, lacks a flexible and efficient error handling mechanism, and can only restart the entire link establishment process in case of an exception, resulting in prolonged link establishment time and reduced resource utilization during the system link establishment phase, which restricts the overall operating efficiency of the data transmission system between the GPU and external devices.

[0005] This application provides a communication method between a processor and a retimer, including:

[0006] When the server is powered on, a first signal is sent to the processor through the first transmitting port of the retimer; wherein, the first transmitting port is the port on the server side where the retimer is responsible for sending signals, and the first receiving port is the port on the server side where the retimer is responsible for receiving signals.

[0007] If the second receiving port of the processor does not receive the first signal within a first preset time period, the processor is reset and powered on again to initialize the processor; wherein, the second receiving port is the port of the processor responsible for receiving signals on the server side, and the second transmitting port is the interface of the processor responsible for sending signals on the server side.

[0008] If the second receiving end of the processor receives the first signal within the first preset time period, then the second transmitting end sends a second signal to the re-timer.

[0009] If the first receiving terminal does not receive the second signal within a second preset time period, the first receiving terminal will be restarted through the baseboard management controller;

[0010] If the first receiving end receives the second signal within the second preset time period, it is determined that the bidirectional communication link between the processor and the retimer has been established.

[0011] This application also provides a communication device between a processor and a retimer, comprising:

[0012] A sending module is configured to send a first signal to the processor via a first transmitting port of a re-timer when the server is powered on; wherein the first transmitting port is the port on the server side where the re-timer is responsible for sending signals, and the first receiving port is the port on the server side where the re-timer is responsible for receiving signals; if the processor's second receiving port does not receive the first signal within a first preset duration, the processor is reset and powered on again to initialize the processor; wherein the second receiving port is the port on the server side where the processor is responsible for receiving signals, and the second transmitting port is the interface on the server side where the processor is responsible for sending signals; if the processor's second receiving port receives the first signal within the first preset duration, a second signal is sent to the re-timer via the second transmitting port;

[0013] The receiving module is configured to restart the first receiving terminal via the baseboard management controller if the first receiving terminal does not receive the second signal within a second preset time period; and to determine that the bidirectional communication link between the processor and the retimer has been established if the first receiving terminal receives the second signal within the second preset time period.

[0014] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the communication method between the processor and the timer when executing the computer program.

[0015] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the above-described communication method between the processor and the timer.

[0016] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the communication method between the processor and the timer described above.

[0017] This application decomposes the bidirectional link establishment between the processor receiver and the re-timer into two independent stages: the re-timer sends a first signal to the processor receiver, and the processor sends a second signal to the re-timer. Each stage corresponds to a clear signal transmission direction and detection subject. The processor receiver detects the first signal, and the re-timer detects the second signal. This allows for real-time detection of the signal reception status at each stage, accurately pinpointing the specific point where an anomaly occurs, avoiding the drawback of having to restart the entire receiver process due to vague anomalies at the receiver. Furthermore, targeted repair measures are designed for anomalies in both stages: if the processor receiver does not receive the first signal from the re-timer within a first preset duration, the processor receiver is reset and re-initialized by power-on, without needing to restart the re-timer or the entire link establishment process; if the re-timer does not receive the second signal from the processor receiver within a second preset duration, the system-side receiver of the re-timer is restarted via the baseboard management controller, without needing to restart the entire re-timer or reset the processor, minimizing interference with normally functioning components. This solution addresses the technical pain points of related chain-building methods, such as crude handling of receiver anomalies and high recovery costs, ultimately improving chain-building efficiency and optimizing system resource utilization. Attached Figure Description

[0018] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A topology diagram of the hardware links on which the communication method between a processor and a retimer provided in this application depends;

[0020] Figure 2 A topology diagram of the management link on which the communication method between a processor and a retimer provided in this application depends;

[0021] Figure 3 A flowchart illustrating a communication method between a processor and a retimer provided in an embodiment of this application;

[0022] Figure 4 A flowchart illustrating another communication method between a processor and a retimer provided in an embodiment of this application;

[0023] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0025] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0026] To more clearly illustrate the embodiments of this application, the technical terms used in the embodiments will be briefly introduced below:

[0027] A graphics processing unit (GPU) is a programmable microprocessor specifically designed for efficient processing of graphics rendering and parallel computing tasks. Through massively parallel computing units, dedicated graphics pipelines, and high-speed video memory interfaces, it enables rapid processing of graphics data and supports general-purpose parallel computing. It provides computing power support for outputting images to display devices or for scientific computing, AI training, etc., complementing and expanding the computing power of the central processing unit (CPU).

[0028] A Baseboard Management Controller (BMC) is a dedicated embedded microcontroller that resides on hardware baseboards such as servers and industrial motherboards. Through hardware and software independent of the main CPU, it enables remote monitoring, fault diagnosis, power management, firmware upgrades, and other functions of server hardware. It can still work normally when the main system is powered off or malfunctions, and is the core component of server "out-of-band management".

[0029] Complex Programmable Logic Devices (CPLDs) are programmable logic devices based on AND-OR arrays and macrocell architectures. Users can define their logic functions through hardware description languages ​​or graphical tools to implement custom combinational and sequential logic. They are characterized by non-volatile memory, predictable latency, and high stability, and are often used in the control logic, interface adaptation, and signal processing of digital systems.

[0030] The physical layer retimer (Retimer) is a physical layer protocol-aware relay device used to restore clock and data in high-speed serial links, suppress jitter and loss, and retime the output with a local clock on the transmitting side, transparent to the data link layer and transaction layer.

[0031] Management Data Input / Output (MDIO) is a two-wire serial management bus defined by IEEE 802.3. It is used for Ethernet Media Access Control (MAC) to read and write registers and monitor the status of the physical layer and other manageable devices. It is typically used to connect the MAC and the physical layer. It consists of two signals: a management data clock and a management data input / output signal. It adopts a master-slave architecture, with the MAC acting as the master initiating read / write operations, and the physical layer responding as slave devices.

[0032] A serializer / deserializer (Serdes) is an integrated circuit technology or module used for high-speed data transmission. It converts parallel data into serial data, which is then transmitted through one or a few high-speed serial links. At the receiving end, the serial data is restored to parallel data. At the transmitting end, the serializer combines multiple parallel low-speed data streams into a single high-speed serial data stream according to a specific clock cycle, transmitting it using differential signaling to reduce electromagnetic interference and improve signal integrity. At the receiving end, the deserializer recovers the original clock signal from the high-speed serial data stream and uses this clock to convert the serial data back to parallel data for subsequent circuit processing.

[0033] Inter-Integrated Circuit (I2C) is a simple, bidirectional two-wire synchronous serial bus standard used to connect microcontrollers and their peripheral devices.

[0034] A Peripheral Component Interconnect Express Switch (PCIe Switch) is a chip or device based on the PCI Express standard used to expand the number of PCIe interfaces and connection topology.

[0035] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] like Figure 1 As shown, Figure 1The topology of the hardware link on which the communication method between the processor and the retimer provided in this application depends is shown.

[0037] The central processing unit (CPU), as the core processing unit, connects to two PCIe switches via a high-speed interface interconnected with peripheral components. These PCIe switches expand the PCIe lanes, and each switch connects to multiple graphics processors (GPUs). Each GPU is bidirectionally connected to its corresponding physical layer retimer via a serializer / deserializer. Simultaneously, each physical layer retimer is also bidirectionally connected to a high-density connector via a serializer / deserializer. This high-density connector is used for subsequent high-speed data exchange with other external devices or systems. Based on this hardware connection, the components work together to complete signal transmission, verification, and link configuration operations, thereby ensuring stable high-speed data transmission between the CPU, GPUs, retimers, and external connections.

[0038] like Figure 2 As shown, Figure 2 The topology of the management link on which the communication method between the processor and the retimer provided in this application depends is shown.

[0039] As the core computing unit, the CPU expands to multiple PCIe lanes through the PCIe switch, connecting multiple graphics processors and providing a basic path for data interaction between the graphics processors.

[0040] At the management and control level, complex programmable logic devices (CPLs) and the baseboard management controller (BMDC) play crucial roles. The BMDC communicates with the CPLs via an integrated circuit (IC) bus, allowing it to issue control commands or retrieve status information. Simultaneously, the BMDC configures and manages multiple physical layer retimers via a management data input / output bus, setting retimer mappings, communication rates, and equalizer parameters.

[0041] It should be emphasized that complex programmable logic devices (CPLDs) can be replaced by other logic devices such as microcontroller units (MCUs) and field-programmable gate arrays (FPGAs).

[0042] Multiple graphics processors are connected to complex programmable logic devices (CPUs) via the integrated circuit's built-in bus. The CPUs can operate on the configuration registers of the graphics processors via the integrated circuit's built-in bus. The CPUs set or rewrite the status values ​​of the physical layer timers and the graphics processor configuration registers to mark different working stages of the hardware, such as initialization complete, ready, and the receiver (RX) terminal started.

[0043] The connection relationships and communication methods between modules such as the central processing unit, graphics processing unit, complex programmable logic device, baseboard management controller, and physical layer retimer are the hardware connection foundation for the bidirectional communication link establishment process between the retimer and the graphics processing unit. Each module works together through the corresponding bus to ensure the orderly execution of server hardware initialization, configuration and link establishment operations.

[0044] like Figure 3 As shown, Figure 3 The following is a flowchart illustrating a communication method between a processor and a retimer, provided as an embodiment of this application. The method includes the following steps:

[0045] S301. When the server is powered on, a first signal is sent to the processor through the first transmitting terminal of the retimer.

[0046] The server includes a baseboard management controller (BMC), logic devices such as complex programmable logic devices (CPLDs), retimers, and a processor. In this application, the processor includes a graphics processing unit (GPU).

[0047] The first transmitting end is the system-side (SYS) transmit (TX) end of the retimer, which is the port on the server side where the retimer is responsible for sending signals. The first receiving end is the SYS-side RX end of the retimer, which is the port on the server side where the retimer is responsible for receiving signals. Additionally, the retimer may also have a device-side transmitting end and a device-side receiving end, but this application does not limit this.

[0048] This application involves sending a first signal from the system-side transmitter of the retimer to the system-side receiver of the processor when the server is powered on.

[0049] In some embodiments, when the server powers on, the re-timer is first initialized. After the re-timer initialization is complete, the first configuration register is set to a first state value via a complex programmable logic device (CPLD), and then the operating parameters of the re-timer are configured via a baseboard management controller (BMC). After the re-timer's operating parameters are configured, the first configuration register is rewritten to a second state value.

[0050] The first configuration register is the configuration register corresponding to the retimer, and can be labeled as the "Retimer configuration register". The CPLD sets the first configuration register to the first status value, such as 0x01, which indicates that the retimer initialization is complete.

[0051] After the server powers on, the re-timer needs to complete its own hardware initialization, such as the basic startup of the clock module, equalization circuit, and clock data recovery unit. However, the re-timer itself cannot actively report its initialization status to the system, so a CPLD is needed as an intermediary coordinator. After the re-timer initialization is complete, the CPLD will actively set the re-timer's dedicated configuration register (i.e., the first configuration register) to the preset first state value 0x01. This state value is equivalent to a ready signal, indicating that the re-timer is ready to receive parameter configuration and providing a clear basis for subsequent BMC operations. Subsequently, the BMC will read the state of the configuration register, confirm that the re-timer has been initialized and ready, and then write the specific working parameters to the re-timer through a dedicated communication link (such as I2C). After all working parameters are configured and verified to be correct, to avoid BMC reconfiguration or misoperation, the system will again rewrite the first configuration register to the second state value (such as 0x02) directly through the CPLD or BMC. This value represents configuration completion, indicating that the re-timer has entered normal working mode and can begin processing signals from the high-speed link.

[0052] From a technical perspective, the status flag in the first configuration register resolves the information synchronization issue among the retimer, CPLD, and BMC. Without this status flag, the BMC might force parameters to be written before the retimer has completed initialization, leading to configuration failure or retimer hardware malfunction. Furthermore, the status value switching clearly distinguishes between the initialization ready and configuration complete stages, ensuring that each operation is based on the success of the previous stage and avoiding instability caused by timing errors.

[0053] As a low-level hardware logic device, the CPLD excels at quickly responding to hardware states and completing simple register writes, ensuring the timeliness of initialization status marking. The BMC, as an out-of-band management controller, has more complex parameter calculation and verification capabilities and is responsible for accurately configuring the working parameters of the retimer. The division of labor between the two ensures the efficiency of the initialization process and improves the accuracy of parameter configuration.

[0054] Furthermore, writing the second status value also facilitates subsequent system maintenance. Maintenance personnel can quickly determine whether the retimer has been configured and is working properly by reading the register status. If a link failure occurs, the status value can also be used to trace back the configuration process to check for problems, reducing the difficulty of troubleshooting.

[0055] In some embodiments, the Baseboard Management Controller (BMC) configures the retimer's operating parameters via the MDIO bus. The retimer's operating parameters include, but are not limited to, at least one of mapping relationships, communication rates, and equalizer parameters. The CPLD rewrites the first status value 0x01 of the first configuration register to a second status value, such as 0x02, indicating that the retimer's operating parameter configuration is complete.

[0056] Among these, the mapping relationship refers to the correspondence between multi-channel signals, ensuring data transmission link matching and avoiding link confusion. The communication rate matches the system-side interface requirements, such as adapting to different rates like PCIe 5.0 / 6.0, ensuring synchronization with the system-side interface rate and preventing data packet loss or link interruption due to rate incompatibility. Equalizer parameters compensate for the loss of high-speed signals during transmission, optimizing signal integrity. The combination of these three elements fundamentally ensures that the retimer effectively extends link distance and optimizes signal quality.

[0057] As the core of server hardware management, the BMC does not directly configure the retimer through any arbitrary interface. Instead, it uses the standardized MDIO bus interface to write specific operating parameters to the retimer. These parameters cover the key settings for the normal operation of the retimer and encompass the core functional requirements for signal processing and link expansion implemented by the retimer.

[0058] The CPLD changes the first status value 0X01 of the first configuration register (Retimer configuration register) that was previously marked as having completed initialization to the second status value 0X02. This change in status value informs the system that the retimer has completed all parameter configurations and is ready to work normally.

[0059] From a technical perspective, configuring parameters via the MDIO bus avoids compatibility issues between BMCs from different vendors and retimers, reducing hardware design and debugging complexity. It also facilitates reading the retimer's configuration status using a unified protocol, improving maintenance convenience. The CPLD's status value rewriting solves the information synchronization problem between system modules: without this status flag, the system might not be able to determine if the retimer has completed parameter configuration, potentially leading to the wrong connection of an incompletely configured retimer and causing link failure. The explicit marking of the second status value, 0x02, not only allows upper-layer modules like the BMC to quickly identify the retimer's ready state, avoiding duplicate configurations or misoperations, but also provides a clear basis for subsequent troubleshooting. If a link is abnormal, reading the first configuration register status can quickly determine whether the problem is due to incomplete parameter configuration or other issues after configuration, shortening fault location time and improving system maintenance efficiency.

[0060] In some embodiments, after the first state value is rewritten to the second state value by the CPLD, the processor is also initialized. After the processor initialization is complete, the second configuration register is set to the third state value by the CPLD, and the first signal is further monitored by the second receiving terminal of the processor.

[0061] The second configuration register is the processor's configuration register, which can be simply referred to as the "GPU configuration register." It initializes the processor's basic modules, such as the core clock, memory interfaces, and PCIe links, to start up.

[0062] Specifically, after rewriting the first status value of the first configuration register to the second status value via the CPLD, the graphics processing unit (GPU) is initialized. Then, the second configuration register is set to the third status value, such as 0x01, via the CPLD, indicating that the GPU has started. Immediately afterwards, the first signal sent by the system-side transmitter of the retimer is monitored by the system-side receiver of the GPU.

[0063] After the retimer completes its parameter configuration and enters the GPU initialization phase, this step requires waiting for the retimer to be ready to prevent the GPU from receiving invalid signals due to the retimer not being ready if it starts prematurely. Once the GPU completes its hardware initialization, the CPLD sets the GPU's corresponding second configuration register (GPU configuration register) to a third status value. This value serves as a clear marker that the GPU has started, informing the system that the GPU is ready to operate and providing a status basis for subsequent signal monitoring. Finally, the GPU monitors the first signal sent by the retimer's TX terminal via its SYS-side RX terminal. This process essentially verifies the connectivity and signal quality of the link from the retimer to the GPU, ensuring that high-speed signals can be transmitted normally from the retimer to the GPU.

[0064] From a technical perspective, constraining the initialization order avoids timing conflicts between modules. If the GPU starts before the retimer is ready, it may experience hardware misjudgment or initialization failure due to receiving abnormal signals. Phased execution ensures that each module's operation is based on the fulfillment of preconditions, reducing startup failures at their source. The CPLD's status flags for the GPU configuration registers allow the system to quickly determine whether the GPU has completed startup by reading these registers. This facilitates management modules such as the BMC to grasp the global status and provides clear clues for troubleshooting. If a third status value is not present, GPU initialization anomalies can be located. Finally, monitoring the GPU's first signal can eliminate potential link risks before the system is officially put into operation, ensuring the stability of subsequent high-bandwidth data transmission.

[0065] In some embodiments, after the second configuration register is marked with the third state value by the logic device, the method further includes: shutting down the first receiver of the retimer after a third preset duration by the baseboard management controller, and then restarting the first receiver, thereby monitoring the second signal through the first receiver.

[0066] The third preset duration, such as 500ms, is set to avoid the unstable window when the module is first started. After the GPU starts, its link with the retimer may still be undergoing rate negotiation or equalization adjustment. Immediately operating the receiving end may easily cause the link to be interrupted. Delaying and waiting for the third preset duration can ensure that the link enters a stable state first, providing a reliable foundation for subsequent operations.

[0067] After the CPLD marks the GPU configuration register to the third state value (i.e., the GPU is started), the system does not directly enter the stable operation phase. Instead, it introduces delay control by the BMC. The BMC waits for a third preset duration. The purpose of this delay is to allow enough time for the link between the GPU and the retimer to complete initialization and synchronization, avoiding signal disturbances caused by operation immediately after startup. Subsequently, the BMC actively shuts down the first receiver of the retimer (the RX end on the SYS side) and then restarts it. This shutdown and restart operation is essentially a soft reset of the retimer receiver. Finally, the second signal is monitored by the restarted first receiver to verify whether the receiver can normally restore the signal reception function after the reset, and whether the link can still transmit data stably.

[0068] From a technical perspective, the soft reset operation of shutting down and restarting the receiver can effectively identify potential initialization residue issues. Some hardware modules may experience latent faults due to transient interference during initial startup, but appear normal on the surface. A soft reset can simulate a functional restart, verifying whether the receiver can complete signal reception preparation from its initial state. If it still works normally after the reset, it indicates that it has anti-interference and self-recovery capabilities, reducing the probability of sudden failures during long-term operation. After a soft reset, the link may experience parameter loss or state disorder. Verification through actual signal reception can confirm whether the link can still maintain signal integrity, ensuring that the retimer can continue to transmit high-quality signals to the GPU after a functional restart.

[0069] S302a. If the second receiving end of the processor does not receive the first signal within the first preset time period, the processor is reset and the processor is re-powered and initialized.

[0070] The second receiving end is the port on the server side where the processor receives signals; it is the processor's system-side receiving end. The first preset duration matches the link rate and hardware response characteristics, such as tens to hundreds of milliseconds.

[0071] After the system-side transmitter of the timer sends the first signal to the system-side receiver of the graphics processor (GPU), if the system-side receiver of the GPU does not receive the first signal within a first preset time period, it indicates that the timeout has occurred and the GPU has not been locked. In this case, the GPU is reset, restarted, and reinitialized.

[0072] When the TX pin of the re-timer on the SYS side sends the first signal to the RX pin of the GPU on the SYS side, the system will start a timing window of the first preset duration. If the GPU's receiving end fails to receive the first signal within this window, it is determined that the timeout has occurred and the device is not locked. At this time, the system will trigger a fault-tolerant operation: first, the GPU will be reset to clear the abnormal state of the GPU and the misconfiguration of the registers; then the GPU will be restarted and the initialization process will be re-executed to return the GPU to the initial state and re-monitor the first signal sent by the TX pin of the re-timer on the SYS side.

[0073] From a technical perspective, resetting and restarting the GPU clears errors generated during initialization, allowing the GPU to re-participate in link negotiation in a clean state, thus improving the automation and fault tolerance of the system startup. Timely GPU reset confines anomalies to the GPU itself, preventing faults from spreading to other hardware or software layers and ensuring an uninterrupted server startup process. The timeout retry mechanism provides a second or even multiple opportunities to establish a connection, reducing the probability of startup failures due to unforeseen factors and ensuring the server can stably complete the startup and coordination of core modules in complex hardware environments.

[0074] In some embodiments, after the system-side transmitter of the retimer sends the first signal to the system-side receiver of the graphics processing unit (GPU), if the system-side receiver of the GPU does not receive the first signal within a first preset time period, it means that there is an initialization anomaly in the link, and the error will be recorded by the CPLD. For example, the error type is "GPU receiver timed out and did not receive the first signal", the time of the anomaly, and the hardware state at that time (such as the retimer configuration register value, GPU configuration register value, etc.).

[0075] When the timer system-side transmitter sends the first signal to the GPU system-side receiver, the system starts a monitoring window of the first preset duration. If the GPU receiver fails to receive the first signal within the window, not only is a reset or other fault-tolerant operation triggered, but the CPLD also intervenes to record the error, converting the instantaneous abnormal event into a readable hardware record.

[0076] From a technical perspective, CPLD error logs act as snapshots of anomalies, preserving the critical context at the time of the fault. Maintenance personnel can quickly identify the anomaly type and associated status by reading relevant CPLD registers, avoiding blind troubleshooting. Directly obtaining information from hardware-level CPLD logs can quickly narrow down the investigation scope. For example, if the log shows the retimer configuration register was already in the second state value when the anomaly occurred, it indicates that the operating parameters were configured correctly, thus ruling out retimer configuration issues and allowing focus to be placed on the GPU receiver hardware or the physical connection of the link. Conversely, if the log shows the retimer parameter configuration process was not configured correctly, the fault location cycle should be shortened by prioritizing the investigation of the retimer parameter configuration process.

[0077] S302b: If the processor's second receiving end receives the first signal within a first preset time period, then the second transmitting end sends the second signal to the re-timer.

[0078] The second transmitting end is the interface on the server side where the processor is responsible for sending signals; it is the RX transmitting end on the processor's system (SYS) side.

[0079] After the system-side transmitter of the re-timer sends the first signal to the system-side receiver of the graphics processor (GPU), if the system-side receiver of the GPU receives the first signal within a first preset time period, it indicates that the first signal lock is successful. Then, the second signal is sent from the system-side transmitter of the GPU to the system-side receiver of the re-timer (i.e., the first receiver).

[0080] When the SYS-side TX pin of the retimer sends the first signal to the SYS-side RX pin of the GPU, if the GPU successfully receives and locks the signal within a first preset time period, it indicates that the downlink from the retimer to the GPU is working. This triggers reverse communication verification, and the GPU sends a second signal from its SYS-side TX pin to the SYS-side RX pin of the retimer. This process verifies the uplink; the first signal verifies the data transmission capability from the retimer to the GPU, and the second signal verifies the data feedback capability from the GPU to the retimer, forming a closed-loop test of the bidirectional link.

[0081] From a technical perspective, the transmission and reception of the second signal can directly verify the signal integrity of the uplink, avoid the half-connection state caused by normal one-way communication but reverse failure, and ensure that the link has full-duplex communication capability.

[0082] S303a. If the first receiving end does not receive the second signal within the second preset time period, the first receiving end is restarted through the baseboard management controller.

[0083] The second preset duration must match the signal transmission characteristics of the uplink to avoid misjudging instantaneous delay.

[0084] After the second signal is sent from the second transmitting end of the graphics processor to the first receiving end of the retimer, the first receiving end of the retimer monitors whether the second signal is received within a second preset duration.

[0085] If the first receiving terminal of the retimer does not receive the second signal within the second preset duration, it indicates that the second signal has not been locked due to timeout. In this case, the first receiving terminal of the retimer is restarted via the Baseboard Management Controller (BMC), i.e., the Sys-side RX terminal of the retimer is restarted. After restarting, the second signal is monitored again.

[0086] After the GPU sends the second signal to the SYS-side RX end of the retimer via the second transmitter, the system initiates a monitoring window of a second preset duration. If the first receiver of the retimer does not receive the second signal within this window (i.e., it times out and fails to lock), it indicates an anomaly in the uplink from the GPU to the retimer, such as GPU transmitter parameter deviation, unexpected link loss, or residual initialization issues at the retimer receiver. In this case, the BMC intervention is triggered. As the core of server hardware management, the BMC actively restarts the SYS-side RX end of the retimer, essentially performing a soft reset on the receiver to clear any abnormal states that could lead to reception failure. After the restart is complete, the system re-triggers the second signal monitoring process to verify whether the retimer receiver can resume normal reception.

[0087] From a technical perspective, restarting only the first receiver end of the retimer, rather than restarting the entire retimer or GPU, avoids the significant startup delays caused by a global restart. It also precisely addresses local anomalies at the receiver end by minimizing operations, balancing fault tolerance and startup efficiency. As an out-of-band management controller independent of the core computing module, the BMC can reliably execute control commands even if the core link fails, ensuring reliable triggering of the restart operation and preventing the fault tolerance mechanism from failing due to core module anomalies. Restarting the receiver end does not immediately confirm the link is normal; instead, it re-monitors the second signal. This verifies the effectiveness of the restart operation and distinguishes between a single anomaly and a persistent fault. If the retry succeeds, the anomaly is temporary, and the link can be used normally. If multiple retries fail, it indicates a potential hardware fault, providing a clear direction for subsequent maintenance and troubleshooting.

[0088] If the first receiving end of the retimer does not receive the second signal within the second preset duration, it indicates that the second signal was not locked within the timeout period. In this case, the timeout error is recorded by the baseboard management controller, and the first receiving end of the retimer is restarted. Specifically, the first receiving end of the retimer can be turned off after the third preset duration, and then restarted.

[0089] If the RX port on the SYS side of the re-timer does not receive the second signal sent by the GPU within the second preset time period, i.e., it times out and fails to lock, indicating an uplink anomaly, the system will first record this timeout error by the BMC. As the out-of-band management core, the BMC records information such as the error type "second signal timeout and failure to lock," the time of the anomaly, and the associated hardware status, enabling traceability of the abnormal event. Subsequently, the BMC will perform a delayed shutdown and restart operation: after waiting for a third preset time period, it will first shut down the first receiving port of the re-timer, and then restart the port. The delay design here is to avoid hardware impact caused by instantaneous operations, while shutting down and then restarting is to allow the receiving port to undergo a complete power-off and power-on initialization process, thoroughly clearing any possible abnormal states.

[0090] From a technical perspective, the BMC's recording of timeout errors can quickly narrow down the troubleshooting scope and reduce fault location costs. Secondly, the third preset delay design enhances the safety of the reset operation; the delay provides the receiving end with time to converge its state, allowing it to partially recover from the abnormal state before performing the reset operation, reducing the risk of hardware damage. The complete shutdown and restart process thoroughly eliminates deep-seated anomalies that could lead to reception failure, increasing the probability of successfully receiving a second signal after restarting.

[0091] S303b: If the first receiving end receives the second signal within the second preset time period, it is determined that the bidirectional communication link between the processor and the retimer has been established.

[0092] During the transmission of the first and second signals, the retimer and the GPU's equalizer and clock recovery unit dynamically adjust parameters (such as equalization level and de-emphasis value) according to the actual signal quality. If both signals are successfully received, it indicates that the parameter adaptation between the two sides has reached the optimal state. Successful verification of the two signals signifies that the bidirectional communication link between the retimer and the GPU is fully ready. The system can then trigger subsequent processes such as loading the GPU driver and starting the graphics rendering service, avoiding errors caused by premature use due to an incomplete link, and improving the orderliness and reliability of server startup.

[0093] In some embodiments, if the first receiving end of the retimer receives the second signal within a second preset duration, indicating that the second signal is locked, the Baseboard Management Controller (BMC) sets the second configuration register to a fourth state value, such as 0x02. Based on the aforementioned embodiments, this essentially rewrites the GPU configuration register from a third state value to a fourth state value to establish a bidirectional communication link between the processor and the retimer.

[0094] When the RX terminal on the SYS side of the retimer successfully receives the second signal sent by the GPU within the second preset time period (i.e., the second signal is locked), it means that the uplink from the GPU to the retimer and the downlink from the retimer to the GPU are both open. At this time, the BMC will intervene and change the status value of the GPU's corresponding second configuration register (i.e., the GPU configuration register) from the third status value 0X01, which previously marked "GPU started," to the fourth status value 0X02. This status value switch is not a simple parameter update, but a system-level confirmation signal, clearly informing all hardware modules on the server that the bidirectional communication link between the GPU and the retimer has been fully established, and the conditions for stable data transmission are met, allowing the subsequent business process to proceed.

[0095] From a technical perspective, the bidirectional communication capability of high-speed links requires dual verification through downlink and uplink signal reception. The previous third state value only represented the GPU's own startup completion, while the fourth state value integrates the link verification results, intuitively reflecting the overall status of GPU availability and link continuity. This avoids failures caused by premature GPU scheduling due to misjudgment of link status. Maintenance personnel can quickly determine the link status between the GPU and the retimer by reading the status value of the GPU configuration register. If it is the fourth state value, it indicates that the bidirectional link is normal; if it remains at the third state value, it indicates an uplink anomaly, such as the failure to receive the second signal. This narrows down the troubleshooting scope without requiring module-by-module testing, improving maintenance efficiency.

[0096] In summary, this application provides a communication method between a processor and a retimer. This method decomposes the bidirectional connection establishment between the GPU receiver and the retimer into two independent stages: the retimer sending a first signal to the GPU receiver, and the GPU transmitter sending a second signal to the retimer. Each stage corresponds to a clear signal transmission direction and detection subject. The GPU receiver detects the first signal, and the retimer receiver detects the second signal. This allows for real-time detection of the signal reception status at each stage, accurately pinpointing the specific point of failure—whether it's a problem with the retimer transmitter, the GPU receiver, or both—avoiding the drawback of requiring a complete restart due to ambiguity in the failure point.

[0097] Instead of the traditional approach of restarting the entire chain establishment process at the first sign of an anomaly, we have designed targeted remediation measures for anomalies in both stages. If the GPU receiver does not receive the first signal from the retimer within the first preset time period, we only reset the GPU receiver and power it back on to initialize the GPU. There is no need to restart the retimer or the entire chain establishment process, thus avoiding idle retimer resources due to GPU receiver-side anomalies. If the retimer receiver does not receive the second signal from the GPU receiver within the second preset time period, we only restart the system-side receiver of the retimer through the baseboard management controller. There is no need to restart the entire retimer or reset the GPU, thus minimizing interference with normally functioning components.

[0098] Since anomaly repair only performs local operations on faulty components / steps, rather than restarting the entire chain-building process, it shortens the time required for anomaly recovery. At the same time, non-faulty components do not need to participate in the restart waiting and can remain in a ready state, avoiding the problem of all related resources being idle due to a full restart in traditional methods, and significantly improving the system's resource utilization during the chain-building phase.

[0099] like Figure 4 As shown in the figure, this application embodiment provides a flowchart of another communication method between a processor and a retimer, which includes the following steps:

[0100] S401. When the server is powered on, initialize the Retimer.

[0101] S402, The first configuration register is set to the first state value by means of a complex programmable logic device.

[0102] The CPLD sets the Retimer configuration register to 0x01, indicating that the Retimer initialization is complete.

[0103] S403. Configure the operating parameters of the retimer through the baseboard management controller.

[0104] BMC configures the Retimer's mapping relationship, communication rate, equalizer parameters, and other operating parameters through the MDIO bus.

[0105] S404: The first state value is rewritten into the second state value using a complex programmable logic device.

[0106] The CPLD rewrites the Retimer configuration register to 0x02, indicating that the Retimer is ready.

[0107] S405: Send a first signal to the graphics processor through the first transmitter of the retimer.

[0108] The Retimer's SYS-side TX terminal sends the first signal to the GPU's SYS-side RX terminal.

[0109] S406. Initialize the graphics processor.

[0110] S407. The second configuration register is set to the third state value by means of a complex programmable logic device.

[0111] The CPLD sets the GPU configuration register to 0X01, indicating that the GPU's SYS side RX side has been started.

[0112] S408. Restart the first receiver via the baseboard management controller.

[0113] BMC polls the GPU configuration register via the I2C bus. When it is 0X01, it delays for 500ms and then shuts down and restarts the SYS-side RX terminal of the retimer via the MDIO bus to ensure stable signal detection.

[0114] S409, Monitor the first signal through the second receiver of the graphics processor.

[0115] The GPU's SYS side RX terminal monitors the first signal.

[0116] If the second receiving end does not receive the first signal within the first preset time period, it returns to S406.

[0117] If the GPU's SYS-side RX terminal fails to lock after a timeout, the CPLD records the timeout error, resets the graphics processor, and then powers on again to initialize the graphics processor.

[0118] S410. If the second receiving end receives the first signal within the first preset time period, then the second transmitting end sends the second signal to the re-timer.

[0119] If the GPU's SYS-side RX terminal successfully locks, the GPU's SYS-side TX terminal sends a second signal to the Retimer's SYS-side RX terminal.

[0120] S411, Monitor the second signal through the first receiving end of the retimer.

[0121] After the S408 is restarted, the Retimer's SYS-side RX terminal monitors the second signal sent by the GPU's SYS-side TX terminal.

[0122] If the first receiving end does not receive the second signal within the second preset time period, it returns to S408.

[0123] If the SYS-side RX terminal of the Retimer fails to lock after a timeout, the BMC records the timeout error and restarts the SYS-side RX terminal of the Retimer.

[0124] S412. If the first receiving end receives the second signal within the second preset time period, the second configuration register is rewritten from the third state value to the fourth state value.

[0125] If the SYS side RX terminal of the Retimer is successfully locked, the GPU configuration register will be rewritten to 0x02, confirming the establishment of a bidirectional communication link between the processor and the retimer.

[0126] From a technical perspective, the above-mentioned communication method between the processor and the retimer uses CPLD and BMC to rewrite the status of the Retimer configuration register and the GPU configuration register, transforming the abstract processes such as initialization completion, parameter configuration readiness, GPU startup, and bidirectional link establishment into explicit hardware register values. This allows each module of the system to quickly determine the current stage by reading the status values, avoiding operational timing disorder caused by information asymmetry and reducing startup failures at the root.

[0127] Secondly, the downlink from the Retimer to the GPU is verified using the first signal, and the uplink from the GPU to the Retimer is verified using the second signal, forming a complete bidirectional communication loop and avoiding the potential for partial failures due to normal one-way communication. Simultaneously, when the GPU fails to receive data, only the GPU is reset; when the Retimer fails to receive data, only its receiving end is restarted, rather than a global restart. This minimizes interference with the startup process and addresses occasional failures caused by momentary interference through retries, improving the success rate of link establishment.

[0128] Finally, hardware-level error logging and out-of-band management intervention improve system maintainability. The CPLD and BMC respectively log timeout errors of the GPU and Retimer, preserving key contexts at the time of failure, such as status values ​​and timing nodes, providing hardware-level logs for subsequent troubleshooting and preventing the loss of abnormal information due to software failure to start. Meanwhile, the BMC, as an independent out-of-band management unit, controls parameter configuration and receiver restart via MDIO and I2C buses, ensuring stable operation of management functions even if the core link fails. This not only relies on the MDIO bus to ensure standardized configuration processes but also improves the reliability of fault-tolerant operations, reducing maintenance difficulty and fault location time.

[0129] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0130] Embodiments of this application also provide a communication device between a processor and a retimer, the device comprising:

[0131] The transmitting module is used to send a first signal to the processor via the first transmitting port of the retimer when the server is powered on; wherein, the first transmitting port is the port on the server side where the retimer is responsible for sending signals, and the first receiving port is the port on the server side where the retimer is responsible for receiving signals; if the processor's second receiving port does not receive the first signal within a first preset duration, the processor is reset and powered on again to initialize the processor; wherein, the second receiving port is the port on the server side where the processor is responsible for receiving signals, and the second transmitting port is the interface on the server side where the processor is responsible for sending signals; if the processor's second receiving port receives the first signal within a first preset duration, a second signal is sent to the retimer via the second transmitting port;

[0132] The receiving module is used to restart the first receiving end through the baseboard management controller if the first receiving end does not receive the second signal within a second preset time period; and to determine that the bidirectional communication link between the processor and the retimer has been established if the first receiving end receives the second signal within the second preset time period.

[0133] As an optional implementation in this application, the device further includes an initialization module, used for: initializing the retimer when the server is powered on; after the retimer initialization is completed, setting the first configuration register to a first state value through a logic device, wherein the first configuration register is the configuration register corresponding to the retimer; configuring the operating parameters of the retimer through the baseboard management controller; and after the operating parameters are configured, rewriting the first state value to a second state value through a logic device.

[0134] As an optional implementation in this application, the initialization module is specifically used to: configure operating parameters via a management data input / output bus through a baseboard management controller; wherein the operating parameters include at least one of mapping relationship, communication rate, and equalizer parameters.

[0135] As an optional implementation in this application embodiment, the initialization module is further configured to: after the working parameters are configured, rewrite the first state value to the second state value through a logic device, and then initialize the processor; after the processor is initialized, mark the second configuration register as the third state value through a logic device, wherein the second configuration register is the configuration register corresponding to the processor; and monitor the first signal through the second receiving terminal of the processor.

[0136] As an optional implementation in this application, the initialization module is further configured to: after the processor initialization is completed, mark the second configuration register as the third state value through the logic device, close the first receiving end of the re-timer after a third preset time period through the baseboard management controller, and restart the first receiving end; monitor the second signal through the first receiving end.

[0137] As an optional implementation in this application embodiment, the sending module is further configured to: after the first transmitting end of the overload timer sends the first signal to the processor, if the second receiving end of the processor does not receive the first signal within a first preset time period, then record the timeout error through the logic device.

[0138] As an optional implementation in this application embodiment, the sending module is further configured to: after sending the second signal to the re-timer through the second transmitting end, if the first receiving end of the re-timer does not receive the second signal within a second preset duration, record a timeout error through the baseboard management controller.

[0139] As an optional implementation in this application embodiment, the receiving module is specifically used to: if the retimer receives the second signal within the second preset duration, set the second configuration register to the fourth state value to complete the establishment of a bidirectional communication link between the processor and the retimer.

[0140] For a description of the features in the embodiment corresponding to the communication device between the processor and the retimer, please refer to the relevant description in the embodiment corresponding to the communication method between the processor and the retimer, which will not be repeated here.

[0141] like Figure 5 As shown, embodiments of this application also provide an electronic device, including a memory 501 and a processor 502. The memory 501 stores a computer program, and the processor 502 is configured to run the computer program to perform the steps in any of the processor-timer communication method embodiments described above.

[0142] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the processor and timer communication method embodiments described above when running.

[0143] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0144] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the communication method between the processor and the retimer.

[0145] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the processor-timer communication method embodiments described above.

[0146] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0147] The foregoing has provided a detailed description of a communication method between a processor and a retimer, an electronic device, and a readable storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method of communication of a processor with a re-timer, the method comprising: The method comprises the following steps: sending a first signal to a processor through a first signaling end of a re-timer when a server is powered on; wherein the first signaling end is a port of the re-timer responsible for sending signals on the server side, and a first receiving end is a port of the re-timer responsible for receiving signals on the server side; if the second receiving end of the processor does not receive the first signal within a first preset time length, resetting the processor and re-powering to initialize the processor; wherein the second receiving end is a port of the processor responsible for receiving signals on the server side, and a second signaling end is an interface of the processor responsible for sending signals on the server side; if the second receiving end of the processor receives the first signal within the first preset time length, sending a second signal to the re-timer through the second signaling end; if the first receiving end does not receive the second signal within a second preset time length, restarting the first receiving end through a baseboard management controller; if the first receiving end receives the second signal within the second preset time length, determining that the establishment of a bidirectional communication link between the processor and the re-timer is completed.

2. The method of claim 1, wherein, Before sending the first signal to the processor through the first signaling end of the re-timer, the method further comprises: initializing the re-timer when the server is powered on; after the initialization of the re-timer is completed, setting a first configuration register to a first state value through a logic device, wherein the first configuration register is a configuration register corresponding to the re-timer; configuring working parameters of the re-timer through a baseboard management controller; after the configuration of the working parameters is completed, rewriting the first state value to a second state value through the logic device.

3. The method of claim 2, wherein, The configuration of the working parameters of the re-timer through the baseboard management controller comprises: configuring the working parameters through the baseboard management controller via a management data input / output bus; wherein the working parameters comprise at least one of a mapping relationship, a communication rate, and equalizer parameters.

4. The method of claim 2, wherein, After the configuration of the working parameters is completed and the first state value is rewritten to the second state value through the logic device, the method further comprises: initializing the processor; after the initialization of the processor is completed, marking a second configuration register to a third state value through a logic device, wherein the second configuration register is a configuration register corresponding to the processor; monitoring the first signal through the second receiving end of the processor.

5. The method of claim 4, wherein, After the initialization of the processor is completed and the second configuration register is marked to the third state value through the logic device, the method further comprises: turning off the first receiving end of the re-timer and restarting the first receiving end through the baseboard management controller after a third preset time length; monitoring the second signal through the first receiving end.

6. The method of claim 1, wherein, After the first signal is sent to the processor through the first signaling end of the re-timer, and before the processor is reset and re-powered to initialize the processor if the second receiving end of the processor does not receive the first signal within a first preset time length, the method further comprises: starting a timing window of the first preset time length; In the timing window, it is judged whether the second receiving end of the processor receives the first signal.

7. The method of claim 1, wherein, After the first signal is sent to the processor by the first signaling end of the re-timer, the method further comprises: If the second receiving end of the processor does not receive the first signal within the first preset time length, record a timeout error by the logic device.

8. The method of claim 1, wherein, After the second signal is sent to the re-timer by the second signaling end if the second receiving end of the processor receives the first signal within the first preset time length, the method further comprises: If the first receiving end of the re-timer does not receive the second signal within the second preset time length, record a timeout error by the baseboard management controller.

9. The method of claim 1, wherein, If the first receiving end receives the second signal within the second preset time length, it is determined that the establishment of the bidirectional communication link between the processor and the re-timer is completed, comprising: If the re-timer receives the second signal within the second preset time length, set the second configuration register to a fourth state value to complete the establishment of the bidirectional communication link between the processor and the re-timer.

10. An electronic device, comprising: Comprise: A memory for storing a computer program; A processor for executing the computer program to realize the steps of the communication method of the processor and the re-timer according to any one of claims 1 to 9.

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