Driving module and display device

Abstract

The application belongs to the field of display, and particularly relates to a driving module and a display device. The driving module comprises a plurality of source driving chips, a time sequence controller and at least one driving module. The driving module comprises a polarity partition control unit, a picture detection unit, a refresh rate detection unit and an inversion interval control unit. The refresh rate detection unit is used for detecting the refresh rate of a display partition. The inversion interval control unit is connected with the time sequence controller, the picture detection unit and the refresh rate detection unit. When the refresh rate of the display partition is high, the inversion interval control unit reduces the frequency of a first polarity inversion control signal, thereby improving or eliminating bright and dark lines and reducing the power consumption of the driving module. When the refresh rate of the display partition is low, the inversion interval control unit increases the frequency of the first polarity inversion control signal, thereby improving or eliminating bright and dark lines and reducing the risk of polarization of liquid crystal molecules, and improving the display effect of the display panel.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of display, and particularly relates to a driving module and a display device. BACKGROUND

[0002] When a liquid crystal display is displaying, a data line provides a data voltage for a pixel electrode, and polarity inversion makes the polarity of the data voltage alternate, that is, the data voltage is greater than or less than the voltage of a common electrode. A coupling capacitor (Cdc) formed between the data line and the pixel electrode will cause the data voltage to deviate, resulting in crosstalk, which affects the display effect of the liquid crystal display.

[0003] The source drive chip in the even column is pulled up, so that the display area controlled by the source drive chip in the even column and the display area controlled by the source drive chip in the odd column are polar symmetric, forming a polar symmetric mode, and the coupling directions of the data voltage and the common voltage of the adjacent display areas are opposite, which can offset the coupling and improve or eliminate the crosstalk. However, in the polar symmetric mode, the pixel column at the junction of the adjacent display areas will have all positive polarity or all negative polarity, while the polarities of the sub-pixels in the row direction and the column direction in other areas alternate, resulting in that the pixel column at the junction is brighter or darker than other areas, that is, a bright-dark line (bright line or dark line) is formed, which affects the display effect of the display panel.

[0004] In the prior art, the liquid crystal display performs polarity inversion once per frame. The degree of brightness of the bright-dark line is related to the interval time of polarity inversion. In the polar symmetric mode, the interval time of polarity inversion can be prolonged to improve or eliminate the bright-dark line. However, prolonging the interval time of polarity inversion at a low refresh rate may cause polarization of liquid crystal molecules, resulting in a decline in display effect, and even damage the liquid crystal material. SUMMARY

[0005] The present application aims to provide a driving module and a display device to reduce the risk of polarization of liquid crystal molecules and improve the display effect of the display panel.

[0006] To achieve the above-mentioned purpose, the present application provides a driving module, comprising a plurality of source drive chips, each of which is connected with a plurality of data lines of a display panel, and the source drive chips in the odd columns are connected with a pull-down power supply, the driving module further comprising a timing controller and at least one driving module, each of which controls a display sub-area of the display panel, and the driving module comprises:

[0007] a polarity sub-area control unit, which controls the source drive chips in the even columns to be connected with the pull-down power supply to form a normal polarity mode, or controls the source drive chips in the even columns to be connected with a pull-up power supply to form a polar symmetric mode;

[0008] A picture detection unit is connected with the display partition and the polarity partition control unit. When the crosstalk degree of the detected display picture exceeds a set value, the picture detection unit controls the polarity partition control unit to switch to the polarity symmetry mode.

[0009] A refresh rate detection unit is used to detect the refresh rate of the display partition.

[0010] A reversal interval control unit is connected with the timing controller, the picture detection unit and the refresh rate detection unit. In the normal polarity mode, the reversal interval control unit outputs the first polarity reversal control signal output by the timing controller to all the source drive chips controlled by the drive module. In the polarity symmetry mode, the reversal interval control unit increases or decreases the frequency of the first polarity reversal control signal to generate the second polarity reversal control signal output to all the source drive chips controlled by the drive module. The frequency of the second polarity reversal control signal is negatively related to the refresh rate of the display partition.

[0011] Optionally, the polarity partition control unit comprises a first transistor and a resistor. The first end of the first transistor is connected with the pull-up power supply. The second end of the first transistor is connected with the pull-down power supply through the resistor. The control end of the first transistor is connected with the picture detection unit.

[0012] Optionally, the picture detection unit is a waveform recognition unit. The waveform recognition unit is connected with the common electrode of the display partition, the polarity partition control unit and the reversal interval control unit. When the voltage of the common electrode exceeds a preset interval, the waveform recognition unit controls the polarity partition control unit to switch to the polarity symmetry mode and controls the reversal interval control unit to increase or decrease the frequency of the first polarity reversal control signal.

[0013] When the refresh rate of the display partition is greater than or equal to a first preset value, the refresh rate detection unit outputs a high-level control signal. When the refresh rate of the display partition is less than the first preset value, the refresh rate detection unit outputs a low-level control signal.

[0014] Optionally, the reversal interval control unit of each drive module is connected with all the source drive chips controlled by the drive module through a first signal line.

[0015] The reversal interval control unit comprises a first selector, a frequency converter and a second selector. The control end of the first selector is connected with the picture detection unit. The input end of the first selector is connected with the timing controller. The first output end of the first selector is connected with the input end of the frequency converter. The second output end of the first selector is connected with the first signal line.

[0016] The control terminal of the second selector is connected to the refresh rate detection unit, the first input terminal of the second selector is connected to the first output terminal of the frequency converter, the second input terminal of the second selector is connected to the second output terminal of the frequency converter, the output terminal of the second selector is connected to the first signal line, the first output terminal of the frequency converter outputs the first polarity reversal control signal to increase the frequency, and the second output terminal of the frequency converter outputs the first polarity reversal control signal to decrease the frequency.

[0017] Optionally, the frequency converter increases the frequency of the first polarity reversal control signal so that the polarity reversal interval of the display partition is two lines, or the frequency converter decreases the frequency of the first polarity reversal control signal so that the polarity reversal interval of the display partition is n frames, where n is an integer greater than or equal to 2.

[0018] Optionally, the first selector includes a second transistor and a third transistor, wherein the second transistor is an N-type field-effect transistor and the third transistor is a P-type field-effect transistor. The control terminals of the second transistor and the third transistor are the control terminals of the first selector. The first terminals of the second transistor and the third transistor are the input terminals of the first selector. The second terminal of the second transistor is the first input terminal of the first selector, and the second terminal of the third transistor is the second output terminal of the first selector.

[0019] The second selector includes a NOT gate, a first AND gate, a second AND gate, and a first OR gate. The first input terminal of the second selector is the first input terminal of the first AND gate, and the second input terminal of the second selector is the first input terminal of the second AND gate. The input terminal of the NOT gate and the second input terminal of the first AND gate are the control terminals of the second selector. The output terminal of the NOT gate is connected to the second input terminal of the second AND gate. The output terminals of the first AND gate and the second AND gate are respectively connected to the two input terminals of the first OR gate. The output terminal of the first OR gate is the output terminal of the second selector.

[0020] Optionally, the drive module includes multiple drive modules, and the inversion interval control unit of each drive module is connected to all the source drive chips it controls through a first signal line. The first polarity inversion control signal is output to the inversion interval control unit through a second signal line.

[0021] The driving module further includes a third selector and a selection controller. The third selector includes a fourth transistor and a fifth transistor. The fourth transistor is a P-type field-effect transistor, and the fifth transistor is an N-type field-effect transistor. The first and second terminals of the fourth transistor are respectively connected to the first signal lines of adjacent display zones. The first and second terminals of the fifth transistor are respectively connected to the second signal lines of adjacent display zones. One of the second signal lines is connected to the timing controller. The control terminals of the fourth transistor and the fifth transistor are connected to the selection controller.

[0022] The selection controller controls each display partition to be controlled separately by each of the driver modules or all display partitions to be controlled uniformly by one driver module, based on the refresh rate differences of the different display partitions.

[0023] Optionally, the drive module includes two drive modules. The selection controller includes a digital-to-analog converter, a difference calculation circuit, a judgment circuit, and an inverter. Each of the two input terminals of the difference calculation circuit is connected to one of the display zones through one of the digital-to-analog converters. The digital-to-analog converter is used to convert the refresh rate of the display zone into an analog signal. The difference calculation circuit is used to calculate the voltage difference between the two analog signals. The judgment circuit is used to determine the relationship between the voltage difference between the two analog signals and a preset range. The inverter is located between the output terminal of the judgment circuit and the control terminal of the third selector. When the voltage difference between the two analog signals is within the preset range, the judgment circuit controls the third selector to work, so that all the display zones are uniformly controlled by one drive module.

[0024] Optionally, the drive module includes three drive modules. The selection controller includes a second OR gate, a third OR gate, a third AND gate, and an inverter. The first input terminal of the second OR gate is connected to the refresh rate detection unit of the first drive module. The second input terminal of the second OR gate and the first input terminal of the third OR gate are connected to the refresh rate detection unit of the second drive module. The second input terminal of the third OR gate is connected to the refresh rate detection unit of the third drive module. The output terminals of the second OR gate and the third OR gate are connected to the two input terminals of the third AND gate. The output terminal of the third AND gate is connected to the control terminal of the third selector. The inverter is disposed between the output terminal of the third AND gate and the control terminal of the third selector.

[0025] This application also provides a display device, including:

[0026] Display panel;

[0027] The drive module is connected to the display panel.

[0028] The driving module and display device disclosed in this application have the following beneficial effects:

[0029] In this application, the driving module includes multiple source driver chips, a timing controller, and at least one driving module. The driving module includes a polarity partition control unit, a screen detection unit, a refresh rate detection unit, and an inversion interval control unit. The polarity partition control unit controls the even-numbered source driver chips to perform pull-up or pull-down to form a conventional polarity mode or a polarity symmetry mode. When the crosstalk level of the detected display screen exceeds a set value, the screen detection unit outputs a high-level control signal to control the polarity partition control unit to switch to the polarity symmetry mode. The refresh rate detection unit is used to detect the refresh rate of the display partition. The inversion interval control unit is connected to the timing controller, the screen detection unit, and the refresh rate detection unit. When the refresh rate of the display partition is high, the inversion interval control unit lowers the frequency of the first polarity inversion control signal, thereby improving or eliminating bright and dark lines while reducing the power consumption of the driving module. When the refresh rate of the display partition is low, the inversion interval control unit increases the frequency of the first polarity inversion control signal, thereby improving or eliminating bright and dark lines while reducing the risk of polarization of liquid crystal molecules and improving the display effect of the display panel.

[0030] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0033] Figure 1 This is a schematic diagram of the drive module in Embodiment 1 of this application.

[0034] Figure 2 This is a schematic diagram of the partition in the normal polarity mode in Embodiment 1 of this application.

[0035] Figure 3 This is a schematic diagram showing the polarity symmetry of the display panel in Embodiment 1 of this application.

[0036] Figure 4This is a schematic diagram of the partition in polar symmetry mode in Embodiment 1 of this application.

[0037] Figure 5 This is a schematic diagram of the voltage waveform of the common electrode in Embodiment 1 of this application.

[0038] Figure 6 This is a schematic diagram of the structure of the second selector in Embodiment 1 of this application.

[0039] Figure 7 This is a schematic diagram of the input and output of the second selector in Embodiment 1 of this application.

[0040] Figure 8 This is a schematic diagram of the inverted interval control unit including the sixth transistor in Embodiment 1 of this application.

[0041] Figure 9 This is a schematic diagram of the driving module including multiple driving modules in Embodiment 1 of this application.

[0042] Figure 10 This is a schematic diagram of adjacent driving modules connected by a third selector in Embodiment 1 of this application.

[0043] Figure 11 This is a schematic diagram of the structure of a selection controller in Embodiment 1 of this application.

[0044] Figure 12 This is a schematic diagram of another selection controller in Embodiment 1 of this application.

[0045] Figure 13 This is a schematic diagram showing the connection of three drive modules via a third selector in Embodiment 1 of this application.

[0046] Figure 14 This is a schematic diagram of the display device in Embodiment 2 of this application.

[0047] Explanation of reference numerals in the attached figures:

[0048] 10. Driver module; 100. Source driver chip; 200. Timing controller;

[0049] 300. Driver module; 310. Polarity partition control unit; 311. First transistor; 312. Resistor; 320. Screen detection unit; 330. Refresh rate detection unit; 340. Inversion interval control unit; 341. First selector; 3411. Second transistor; 3412. Third transistor; 342. Frequency converter; 343. Second selector; 3431. NOT gate; 3432. First AND gate; 3433. Second AND gate; 3434. First OR gate; 344. Sixth transistor; 350. Third selector; 351. Fourth transistor; 352. Fifth transistor; 360. Selection controller; 361. Digital-to-analog converter; 362. Difference calculation circuit; 363. Judgment circuit; 3631. Operational amplifier; 3632. Second OR gate; 3633. Third OR gate; 3634. Third AND gate;

[0050] 410 Pull-down power supply; 420 Pull-up power supply; 430 First signal line; 440 Second signal line;

[0051] 20. Display panel; 21. Display zone; 211. First display sub-zone; 212. Second display sub-zone; 213. Data cable; 214. Sub-pixel. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0053] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0054] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0055] Example 1

[0056] See Figures 1 to 4 As shown, in this embodiment, the drive module 10 includes multiple source drive chips 100 (including... Figure 1 The display panel 20 includes C1~C4), a timing controller 200 (TCON), and at least one drive module 300. Each drive module 300 controls one display partition 21 of the display panel 20. Each source driver chip 100 is connected to multiple rows of data lines 213 of the display panel 20, i.e., multiple source driver chips 100 form multiple rows.

[0057] The driver module 300 includes a polarity partition control unit 310, a screen detection unit 320, a refresh rate detection unit 330, and an inversion interval control unit 340. Odd-numbered source driver chips 100 are connected to a pull-down power supply 410, which includes a ground terminal. Even-numbered source driver chips 100 are connected to a pull-up power supply 420 via the polarity partition control unit 310, where the voltage of the pull-up power supply 420 is greater than the voltage of the pull-down power supply 410. The polarity partition control unit 310 controls the even-numbered source driver chips 100 to connect to the pull-down power supply 410 to form a normal polarity mode, or it controls the even-numbered source driver chips 100 to connect to the pull-up power supply 420 to form a symmetrical polarity mode.

[0058] Taking the "Zigzag" architecture display panel 20 as an example, the display panel 20 includes multiple columns of data lines 213 and multiple sub-pixels 214 arranged in an array. Each column of sub-pixels 214 is located between two adjacent data lines 213. That is, there is one more column of data lines 213 than sub-pixels 214. The sub-pixels 214 in odd-numbered rows are connected to the data lines 213 on the first side of the adjacent data lines 213 in their respective columns, and the sub-pixels 214 in even-numbered rows are connected to the data lines 213 on the second side of the adjacent data lines 213 in their respective columns. For example, the first side is the right side and the second side is the left side. The sub-pixels 214 in odd-numbered rows are connected to the data lines 213 on the right side of the adjacent data lines 213 in their respective columns, and the sub-pixels 214 in even-numbered rows are connected to the data lines 213 on the left side of the adjacent data lines 213 in their respective columns. The polarity inversion method of the display panel 20 is dot inversion, that is, the polarity of the sub-pixels 214 alternates between positive and negative in both the row and column directions.

[0059] The default state is the normal polarity mode. The pull-down power supply 410 outputs a low-level signal to the odd-numbered column source driver chips 100, and the polarity of the first display sub-area 211 controlled by the odd-numbered column source driver chips 100 is "+-+-". The polarity partition control unit 310 controls the even-numbered column source driver chips 100 to disconnect from the pull-up power supply 420, and the pull-down power supply 410 outputs a low-level signal to the even-numbered column source driver chips 100, and the polarity of the second display sub-area 212 controlled by the even-numbered column source driver chips 100 is "+-+-", such as... Figure 2 As shown.

[0060] In polarity symmetry mode, the polarity of the first display sub-area 211 controlled by the source driver chip 100 of the odd-numbered columns remains unchanged. The polarity partition control unit 310 controls the source driver chip 100 of the even-numbered columns to be connected to the pull-up power supply 420. The pull-up power supply 420 outputs a high-level signal to the source driver chip 100 of the even-numbered columns, and the polarity of the second display sub-area 212 controlled by the source driver chip 100 of the even-numbered columns becomes "-+-+". The adjacent display sub-areas of the display panel 20 are polarity symmetrical, such as... Figure 3 As shown. It should be understood that the adjacent first display sub-region 211 and second display sub-region 212 are polar symmetrical, and the data voltage and common voltage of the first display sub-region 211 and the second display sub-region 212 are coupled in opposite directions, which can cancel the coupling and improve or eliminate crosstalk.

[0061] The screen detection unit 320 is connected to the display partition 21 and the polarity partition control unit 310. When the crosstalk level of the detected display screen exceeds a set value, the screen detection unit 320 outputs a high-level control signal to control the polarity partition control unit 310 to switch to polarity symmetry mode. If the crosstalk level of the detected display screen does not exceed the set value, the screen detection unit 320 outputs a low-level control signal to control the polarity partition control unit 310 to switch to normal polarity mode.

[0062] The refresh rate detection unit 330 is used to detect the refresh rate of the display partition 21 and output a high-level control signal or a low-level control signal according to the refresh rate. For example, if the refresh rate of the display partition 21 is greater than or equal to 100Hz, the refresh rate detection unit 330 outputs a high-level control signal; if the refresh rate of the display partition 21 is less than 100Hz, the refresh rate detection unit 330 outputs a low-level control signal.

[0063] The inversion interval control unit 340 is connected to the timing controller 200, the screen detection unit 320, and the refresh rate detection unit 330. In normal polarity mode, the inversion interval control unit 340 outputs the first polarity inversion control signal from the timing controller 200 to all source driver chips 100 controlled by the drive module 300. In polarity symmetry mode, the inversion interval control unit 340 adjusts the frequency of the first polarity inversion control signal up or down to generate a second polarity inversion control signal, which is output to all source driver chips 100 controlled by the drive module 300. The frequency of the second polarity inversion control signal is negatively correlated with the refresh rate of the display partition 21.

[0064] In the normal polarity mode, the screen detection unit 320 outputs a low-level control signal, and the inversion interval control unit 340 directly outputs the first polarity inversion control signal output by the timing controller 200 to all source driver chips 100 controlled by the drive module 300, controlling the polarity inversion interval of the display partition 21 to be 1 frame. For example, the polarity of the data signals output by multiple data lines 213 in the current frame line direction is "+-+-" in sequence, and the polarity of the data signals output by multiple data lines 213 in the next frame line direction is "-+-+" in sequence.

[0065] See Figure 3 As shown, in the polarity symmetry mode, the pixel column at the junction of the first display sub-area 211 and the second display sub-area 212 will have the entire column being either positive or negative polarity. Meanwhile, the row and column direction sub-pixels 214 in other areas of the first display sub-area 211 and the second display sub-area 212 will have alternating positive and negative polarities, causing the pixel column at the junction to become brighter or darker than other areas, thus forming a bright-dark line, which affects the display effect of the display panel 20.

[0066] In order to reduce or eliminate bright and dark lines, this embodiment also provides a polarity reversal interval control unit 340, which is used to control the polarity reversal interval time of the display partition 21.

[0067] In polarity symmetry mode, the screen detection unit 320 outputs a high-level control signal. If the refresh rate detection unit 330 outputs a high-level control signal, the inversion interval control unit 340 lowers the frequency of the first polarity inversion control signal and generates a second polarity inversion control signal, which is output to all source driver chips 100 controlled by the driver module 300. Because the frequency of the second polarity inversion control signal is lower, the polarity inversion interval of the display partition 21 is longer. Since the visibility of bright and dark lines is related to the polarity inversion interval, extending the polarity inversion interval can improve or eliminate bright and dark lines.

[0068] In polarity symmetry mode, the screen detection unit 320 outputs a high-level control signal. If the refresh rate detection unit 330 outputs a low-level control signal, the inversion interval control unit 340 increases the frequency of the first polarity inversion control signal, generating a second polarity inversion control signal which is output to all source driver chips 100 controlled by the driver module 300. Because the frequency of the second polarity inversion control signal is lower, the polarity inversion interval of the display partition 21 is shorter and less than one frame, resulting in alternating positive and negative polarities in the pixel columns at the boundary, such as... Figure 4 As shown.

[0069] When the refresh rate of display zone 21 is high, lowering the frequency of the first polarity reversal control signal and extending the polarity reversal interval time can improve or eliminate bright and dark lines, thereby reducing the power consumption of the drive module. When the refresh rate of display zone 21 is low, increasing the frequency of the first polarity reversal control signal and shortening the polarity reversal interval time can improve or eliminate bright and dark lines, thereby reducing the risk of liquid crystal molecule polarization and improving the display effect of display panel 20.

[0070] It should be noted that although this embodiment uses a "Zigzag" architecture and a dot inversion method for polarity reversal in the display panel 20 for illustration, the driving module 10 in this embodiment can also be used to drive display panels 20 with other architectures and inversion methods. As long as there are display panels 20 with the same positive or negative polarity in the entire column of pixels at the boundary of adjacent display sub-areas in the polarity symmetry mode, the driving module 10 disclosed in this embodiment can be used for driving.

[0071] In this embodiment, the driving module 10 includes multiple source driver chips 100, a timing controller 200, and at least one driving module 300. The driving module 300 includes a polarity partition control unit 310, a screen detection unit 320, a refresh rate detection unit 330, and an inversion interval control unit 340. The polarity partition control unit 310 controls the even-numbered source driver chips 100 to perform pull-up or pull-down to form a conventional polarity mode or a polarity symmetrical mode. When the detected crosstalk level of the displayed screen exceeds a set value, the screen detection unit 320 outputs a high-level control signal to control the polarity partition control unit 310 to switch to the polarity symmetrical mode and refresh the screen. The refresh rate detection unit 330 is used to detect the refresh rate of the display partition 21. The inversion interval control unit 340 is connected to the timing controller 200, the screen detection unit 320 and the refresh rate detection unit 330. When the refresh rate of the display partition 21 is high, the inversion interval control unit 340 lowers the frequency of the first polarity inversion control signal, thereby improving or eliminating bright and dark lines while reducing the power consumption of the drive module. When the refresh rate of the display partition 21 is low, the inversion interval control unit 340 raises the frequency of the first polarity inversion control signal, thereby improving or eliminating bright and dark lines while reducing the risk of polarization of liquid crystal molecules and improving the display effect of the display panel 20.

[0072] In some embodiments, the polarity partition control unit 310 includes a first transistor 311 and a resistor 312. The first terminal of the first transistor 311 is connected to a pull-up power supply 420, and the second terminal of the first transistor 311 is connected to a pull-down power supply 410 through the resistor 312. The control terminal of the first transistor 311 is connected to the screen detection unit 320. The first transistor 311 may be an N-type field-effect transistor.

[0073] When the crosstalk level of the detected display screen exceeds a set value, the screen detection unit 320 outputs a high-level control signal, the first transistor 311 turns on, and the voltage output of the pull-up power supply 420 is sent to the even-numbered source driver chips 100, thus pulling up the even-numbered source driver chips 100; when the crosstalk level of the detected display screen does not exceed the set value, the screen detection unit 320 outputs a low-level control signal, the first transistor 311 turns off, and the voltage output of the pull-down power supply 410 is sent to the even-numbered source driver chips 100, thus pulling down the even-numbered source driver chips 100.

[0074] In some embodiments, the screen detection unit 320 is a waveform recognition unit. The waveform recognition unit is connected to the common electrode of the display partition 21, the polarity partition control unit 310, and the reversal interval control unit 340. The waveform recognition unit is used to control the polarity partition control unit 310 to switch to a polarity symmetry mode and control the reversal interval control unit 340 to increase or decrease the frequency of the first polarity reversal control signal when the voltage of the common electrode exceeds a preset range.

[0075] Crosstalk causes data voltage shifts, which can lead to voltage fluctuations in the common electrode (Vcom). The waveform recognition unit sets a range based on the common electrode voltage (Vcom), i.e., sets positive and negative trigger values ​​m1 and m2, respectively. Figure 5 As shown, when the voltage Vcom of the common electrode is detected to exceed the preset range (greater than m1 or less than m2, indicating severe crosstalk and poor image quality), a high-level control signal is output to the source driver chip 100 of the even-numbered column. Display partition 21 switches to polarity symmetry mode, and the data voltages of adjacent first display sub-regions 211 and second display sub-regions 212 are coupled in opposite directions to the common voltage, thereby canceling the coupling and improving or eliminating crosstalk. Conversely, when the voltage Vcom of the common electrode does not exceed the preset range, display partition 21 is in normal polarity mode.

[0076] When the display panel 20 displays special images, such as Excel images (images resembling Excel spreadsheets), alternating black and white columns, and TXT text documents, crosstalk can easily occur. The image detection unit 320 can also detect the severity of crosstalk based on parameters such as the type of image displayed and the area of ​​the image prone to crosstalk. Furthermore, the image detection unit 320 can be an additional detection unit, but it is not limited to this; the image detection unit 320 can also be integrated into the timing controller 200, depending on the specific circumstances.

[0077] The refresh rate detection unit 330 outputs a high-level control signal when the refresh rate of the display partition 21 is greater than or equal to a first preset value, and outputs a low-level control signal when the refresh rate of the display partition 21 is less than the first preset value. The first preset value is, for example, 90Hz, 100Hz, and 110Hz.

[0078] The image detection unit 320 is a waveform recognition unit. The waveform recognition unit judges the severity of crosstalk based on the voltage fluctuation of the common electrode, which reduces the difficulty of recognizing the severity of crosstalk.

[0079] In some embodiments, the inversion interval control unit 340 of each drive module 300 is connected to all the source drive chips 100 it controls via the first signal line 430. The inversion interval control unit 340 includes a first selector 341, a frequency converter 342, and a second selector 343. The control terminal of the first selector 341 is connected to the image detection unit 320, the input terminal of the first selector 341 is connected to the timing controller 200, the first output terminal of the first selector 341 is connected to the input terminal of the frequency converter 342, and the second output terminal of the first selector 341 is connected to the first signal line 430.

[0080] The control terminal of the second selector 343 is connected to the refresh rate detection unit 330. The first input terminal of the second selector 343 is connected to the first output terminal of the frequency converter 342, and the second input terminal of the second selector 343 is connected to the second output terminal of the frequency converter 342. The output terminal of the second selector 343 is connected to the first signal line 430. The first output terminal of the frequency converter 342 outputs a first polarity reversal control signal to increase the frequency, and the second output terminal of the frequency converter 342 outputs a first polarity reversal control signal to decrease the frequency.

[0081] The first selector 341 selects to output either a first polarity reversal control signal or a second polarity reversal control signal based on the control signal from the image detection unit 320. The second selector 343 selects whether the frequency of the second polarity reversal control signal is increased or decreased compared to the first polarity reversal control signal. By using two selectors to select and output three different signals, the structure of the reversal interval control unit 340 can be simplified.

[0082] In some embodiments, the frequency converter 342 increases the frequency of the first polarity inversion control signal, making the polarity inversion interval of display partition 21 two lines, three lines, etc., or alternating between different numbers of lines such as one, two, and three lines. The frequency converter 342 decreases the frequency of the first polarity inversion control signal, making the polarity inversion interval of display partition 21 n frames, where n is an integer greater than or equal to 2. For example, in the normal polarity mode, the polarity inversion interval of display partition 21 is 1 frame; when the frequency converter 342 decreases the frequency of the first polarity inversion control signal, the polarity inversion interval of display partition 21 becomes 2 frames, 3 frames, etc.

[0083] The frequency converter 342 can be connected to the display partition 21 and adjust the frequency of the first polarity inversion control signal by a multiple based on the refresh rate of the display partition 21. Furthermore, the multiple by which the frequency converter 342 adjusts the frequency of the first polarity inversion control signal can be a fixed value or adjustable according to the refresh rate of the display partition 21.

[0084] When the refresh rate of display zone 21 is high, the inversion interval control unit 340 lowers the frequency of the first polarity inversion control signal, thereby improving or eliminating bright and dark lines while reducing the power consumption of the drive module. When the refresh rate of display zone 21 is low, the inversion interval control unit 340 raises the frequency of the first polarity inversion control signal, thereby improving or eliminating bright and dark lines while reducing the risk of polarization of liquid crystal molecules and improving the display effect of display panel 20.

[0085] In some embodiments, the first selector 341 includes a second transistor 3411 and a third transistor 3412, wherein the second transistor 3411 is an N-type field-effect transistor and the third transistor 3412 is a P-type field-effect transistor. The control terminals of the second transistor 3411 and the third transistor 3412 are the control terminals of the first selector 341, the first terminals of the second transistor 3411 and the third transistor 3412 are the input terminals of the first selector 341, the second terminal of the second transistor 3411 is the first input terminal of the first selector 341, and the second terminal of the third transistor 3412 is the second output terminal of the first selector 341.

[0086] The second selector 343 includes a NOT gate 3431, a first AND gate 3432, a second AND gate 3433, and a first OR gate 3434. The first input terminal (D0) of the second selector 343 is the first input terminal of the first AND gate 3432, and the second input terminal (D1) of the second selector 343 is the first input terminal of the second AND gate 3433. The input terminals of the NOT gate 3431 and the second input terminal of the first AND gate 3432 are the control terminal (S) of the second selector 343. The output terminal of the NOT gate 3431 is connected to the second input terminal of the second AND gate 3433. The output terminals of the first AND gate 3432 and the second AND gate 3433 are respectively connected to the two input terminals of the first OR gate 3434. The output terminal (Y1) of the first OR gate 3434 is the output terminal of the second selector 343. Figure 6 As shown.

[0087] When the refresh rate of display partition 21 is high, the refresh rate detection unit 330 outputs a high-level control signal, and the frequency converter 342 lowers the frequency of the first polarity inversion control signal to generate a second polarity inversion control signal. The second polarity inversion control signal is output to the first signal line 430 through the first input terminal of the second AND gate circuit 3433 and the output terminal of the first OR gate circuit 3434. When the refresh rate of display partition 21 is low, the refresh rate detection unit 330 outputs a low-level control signal, and the frequency converter 342 raises the frequency of the first polarity inversion control signal to generate a second polarity inversion control signal. The second polarity inversion control signal is output to the first signal line 430 through the first input terminal of the first AND gate circuit 3432 and the output terminal of the first OR gate circuit 3434. Figure 7 As shown.

[0088] In some embodiments, see Figure 8 As shown, the inversion interval control unit 340 also includes a sixth transistor 344, which is an N-type field-effect transistor. The control terminal of the sixth transistor 344 is connected to the refresh rate detection unit 330, the first terminal of the sixth transistor 344 is connected to the screen detection unit 320, and the second terminal of the sixth transistor 344 is connected to the control terminal of the first selector 341. When the refresh rate of the display partition 21 is low, the refresh rate detection unit 330 outputs a low-level control signal, the sixth transistor 344 is turned off, the second transistor 3411 is turned off, and the third transistor 3412 is turned on. The first polarity inversion control signal is output to the first signal line 430 through the third transistor 3412.

[0089] Since the visibility of bright and dark lines is related to the refresh rate, it is less noticeable at low refresh rates. When the refresh rate detection unit 330 detects a low refresh rate, the sixth transistor 344 is turned off, and the first polarity reversal control signal does not pass through the second selector 343, which can reduce the power consumption of the drive module.

[0090] In some embodiments, see Figure 9 As shown, the drive module 10 includes multiple drive modules 300. The inversion interval control unit 340 of each drive module 300 is connected to all the source drive chips 100 controlled by it through the first signal line 430. The first polarity inversion control signal is output to the inversion interval control unit 340 through the second signal line 440. The inversion interval control unit 340 of each drive module 300 is connected to the timing controller 200 through the second signal line 440.

[0091] When the display panel 20 is divided into multiple display zones 21, each display zone 21 is controlled individually by a driver module 300, thereby determining whether to use the polar symmetry mode drive, instead of blindly turning on the entire screen.

[0092] In some embodiments, see Figure 10 and Figure 11 As shown, the drive module 10 also includes a third selector 350 and a selection controller 360. The third selector 350 includes a fourth transistor 351 and a fifth transistor 352. The fourth transistor 351 is a P-type field-effect transistor, and the fifth transistor 352 is an N-type field-effect transistor. The first and second terminals of the fourth transistor 351 are respectively connected to the first signal line 430 of the adjacent display partition 21, and the first and second terminals of the fifth transistor 352 are respectively connected to the second signal line 440 of the adjacent display partition 21. One of the second signal lines 440 is connected to the timing controller 200, for example, the leftmost second signal line 440 is connected to the timing controller 200. The control terminals of the fourth transistor 351 and the fifth transistor 352 are connected to the selection controller 360.

[0093] The controller 360 selects the refresh rate difference between different display zones 21 to control each display zone 21 individually by each driver module 300 or to control all display zones 21 uniformly by a single driver module 300. When the refresh rate difference between different display zones 21 is small, multiple display zones 21 of the entire display panel 20 can be uniformly controlled by a single driver module 300 to reduce the power consumption of the driver module 10; when the refresh rate difference between different display zones 21 is large, each display zone 21 is independently controlled by a separate driver module 300 to achieve a better display effect.

[0094] In some embodiments, the drive module 10 includes two drive modules 300. The selection controller 360 includes a digital-to-analog converter 361, a difference calculation circuit 362, a judgment circuit 363, and an inverter. The digital-to-analog converter 361 is used to convert the refresh rate of the display partition 21 into an analog signal, the voltage of which is positively correlated with the refresh rate of the display partition 21. The two input terminals of the difference calculation circuit 362 are each connected to a display partition 21 through a digital-to-analog converter 361. The difference calculation circuit 362 is used to calculate the voltage difference between the two analog signals, i.e., the voltage difference between the high-voltage analog signal and the low-voltage analog signal. The judgment circuit 363 is used to determine the relationship between the voltage difference between the two analog signals and a preset range. The inverter is located between the output terminal of the judgment circuit 363 and the control terminal of the third selector 350. When the voltage difference between the two analog signals is within the preset range, the judgment circuit 363 controls the third selector 350 to work, so that all display partitions 21 are uniformly controlled by one drive module 300. When the voltage difference between the two analog signals is outside the preset range, the judgment circuit 363 controls the third selector 350 to work, so that each display zone 21 is controlled by a single drive module 300.

[0095] The judgment circuit 363 may include an operational amplifier 3631. One input terminal of the operational amplifier 3631 is connected to the output terminal of the difference calculation circuit 362, and the voltage at the other input terminal of the operational amplifier 3631 is a second preset value Vmax. Figure 11 As shown. When the voltage difference between the two analog signals is less than the second preset value Vmax, the judgment circuit 363 controls the third selector 350 to work, so that all display zones 21 are uniformly controlled by a single drive module 300.

[0096] The judgment circuit 363 may include two operational amplifiers 3631. The voltage at the inverting input of the first operational amplifier 3631 is a third preset value Vmin. The voltage at the non-inverting input of the first operational amplifier 3631 is connected to the inverting input of the second operational amplifier 3631, and then connected to the output of the difference calculation circuit 362. The voltage at the non-inverting input of the second operational amplifier 3631 is a second preset value Vmax. Figure 12 As shown.

[0097] The drive module 10 includes two drive modules 300, which can compare the refresh rate difference between the two display partitions 21 and select to control the two display partitions 21 uniformly or individually based on the comparison result.

[0098] In some embodiments, see Figure 13As shown, the drive module 10 includes three drive modules 300. The selection controller 360 includes a second OR gate 3632, a third OR gate 3633, a third AND gate 3634, and an inverter. The first input terminal of the second OR gate 3632 is connected to the refresh rate detection unit 330 of the first drive module 300. The second input terminal of the second OR gate 3632 and the first input terminal of the third OR gate 3633 are connected to the refresh rate detection unit 330 of the second drive module 300. The second input terminal of the third OR gate 3633 is connected to the refresh rate detection unit 330 of the third drive module 300. The output terminals of the second OR gate 3632 and the third OR gate 3633 are connected to the two input terminals of the third AND gate 3634. The output terminal of the third AND gate 3634 is connected to the control terminal of the third selector 350, that is, the output terminal of the third AND gate 3634 is connected to the control terminal of the fourth transistor 351 and the control terminal of the fifth transistor 352. The inverter is positioned between the output of the third AND gate 3634 and the control terminal of the third selector 350.

[0099] If the third AND gate 3634 outputs a high-level signal, then both OR gates output high-level signals. One of the first and second driver modules 300 will control a display partition 21 with a high refresh rate (i.e., the control signal output by the refresh rate detection unit 330 is high-level). The high refresh rate display partition 21 occupies 2 / 3 of the space, and all three display partitions 21 are controlled uniformly. If the third AND gate 3634 outputs a low-level signal, then at least one OR gate will output a low-level signal, and at most only one display partition 21 will have a high refresh rate. The high refresh rate display partition 21 occupies 1 / 3 of the space, and each display partition 21 is controlled independently.

[0100] Furthermore, the drive module 10 includes three or more drive modules 300, which can count the proportion of display partitions 21 with high refresh rates. When the proportion of display partitions 21 with high refresh rates is relatively large (such as 2 / 3, 3 / 4, 4 / 5, etc.), all display partitions 21 are controlled uniformly; conversely, when the proportion of display partitions 21 with high refresh rates is relatively small, each display partition 21 is controlled separately.

[0101] Example 2

[0102] See Figure 14 As shown, the display device in this embodiment includes a display panel 20 and a driving module 10 disclosed in Embodiment 1, and the driving module 10 is connected to the display panel 20.

[0103] In this embodiment, the display device includes a driving module 10, which includes multiple source driver chips 100, a timing controller 200, and at least one driving module 300. The driving module 300 includes a polarity partition control unit 310, a screen detection unit 320, a refresh rate detection unit 330, and an inversion interval control unit 340. The polarity partition control unit 310 controls the even-numbered source driver chips 100 to perform pull-up or pull-down operations to form a conventional polarity mode or a polarity symmetrical mode. When the crosstalk level of the detected display screen exceeds a set value, the screen detection unit 320 outputs a high-level control signal to control the polarity partition control unit 310 to switch to polarity mode. In symmetrical mode, refresh rate detection unit 330 is used to detect the refresh rate of display zone 21. Inverting interval control unit 340 is connected to timing controller 200, screen detection unit 320 and refresh rate detection unit 330. When the refresh rate of display zone 21 is high, inverting interval control unit 340 lowers the frequency of the first polarity inversion control signal, thereby improving or eliminating bright and dark lines while reducing the power consumption of the drive module. When the refresh rate of display zone 21 is low, inverting interval control unit 340 raises the frequency of the first polarity inversion control signal, thereby improving or eliminating bright and dark lines while reducing the risk of polarization of liquid crystal molecules and improving the display effect of display panel 20.

[0104] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0105] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0106] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0107] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A driving module comprising a plurality of source driver chips, each of the source driver chips being connected to multiple rows of data lines of a display panel, characterized in that, The source driver chips of the odd-numbered columns are connected to a pull-down power supply. The driver module also includes a timing controller and at least one driver module. Each driver module controls a display zone of the display panel. The driver module includes: The polarity partition control unit controls the even-numbered source driver chips to connect with the pull-down power supply to form a normal polarity mode, or controls the even-numbered source driver chips to connect with the pull-up power supply to form a polarity symmetry mode. A screen detection unit is connected to the display partition and the polarity partition control unit. When the crosstalk level of the detected display screen exceeds a set value, the screen detection unit controls the polarity partition control unit to switch to the polarity symmetry mode. A refresh rate detection unit is used to detect the refresh rate of the display partition; The inversion interval control unit is connected to the timing controller, the screen detection unit, and the refresh rate detection unit. In the normal polarity mode, the inversion interval control unit outputs the first polarity inversion control signal output by the timing controller to all the source driver chips controlled by the drive module. In the polarity symmetry mode, the inversion interval control unit increases or decreases the frequency of the first polarity inversion control signal to generate a second polarity inversion control signal, which is output to all the source driver chips controlled by the drive module. The frequency of the second polarity inversion control signal is negatively correlated with the refresh rate of the display zone.

2. The drive module according to claim 1, characterized in that, The polarity partition control unit includes a first transistor and a resistor. The first terminal of the first transistor is connected to the pull-up power supply, and the second terminal of the first transistor is connected to the pull-down power supply through the resistor. The control terminal of the first transistor is connected to the screen detection unit.

3. The drive module according to claim 1, characterized in that, The screen detection unit is a waveform recognition unit. The waveform recognition unit is connected to the common electrode of the display partition, the polarity partition control unit and the inversion interval control unit. The waveform recognition unit is used to control the polarity partition control unit to switch to the polarity symmetry mode and control the inversion interval control unit to increase or decrease the frequency of the first polarity inversion control signal when the voltage of the common electrode exceeds the preset range. The refresh rate detection unit outputs a high-level control signal when the refresh rate of the display partition is greater than or equal to a first preset value, and outputs a low-level control signal when the refresh rate of the display partition is less than the first preset value.

4. The drive module according to claim 3, characterized in that, The inversion interval control unit of each drive module is connected to all the source drive chips it controls via a first signal line; The inversion interval control unit includes a first selector, a frequency converter, and a second selector. The control terminal of the first selector is connected to the image detection unit, the input terminal of the first selector is connected to the timing controller, the first output terminal of the first selector is connected to the input terminal of the frequency converter, and the second output terminal of the first selector is connected to the first signal line. The control terminal of the second selector is connected to the refresh rate detection unit, the first input terminal of the second selector is connected to the first output terminal of the frequency converter, the second input terminal of the second selector is connected to the second output terminal of the frequency converter, the output terminal of the second selector is connected to the first signal line, the first output terminal of the frequency converter outputs the first polarity reversal control signal to increase the frequency, and the second output terminal of the frequency converter outputs the first polarity reversal control signal to decrease the frequency.

5. The drive module according to claim 4, characterized in that, The frequency converter increases the frequency of the first polarity reversal control signal so that the polarity reversal interval of the display partition is two lines, or the frequency converter decreases the frequency of the first polarity reversal control signal so that the polarity reversal interval of the display partition is n frames, where n is an integer greater than or equal to 2.

6. The drive module according to claim 4, characterized in that, The first selector includes a second transistor and a third transistor. The second transistor is an N-type field-effect transistor, and the third transistor is a P-type field-effect transistor. The control terminals of the second transistor and the third transistor are the control terminals of the first selector. The first terminals of the second transistor and the third transistor are the input terminals of the first selector. The second terminal of the second transistor is the first input terminal of the first selector, and the second terminal of the third transistor is the second output terminal of the first selector. The second selector includes a NOT gate, a first AND gate, a second AND gate, and a first OR gate. The first input terminal of the second selector is the first input terminal of the first AND gate, and the second input terminal of the second selector is the first input terminal of the second AND gate. The input terminal of the NOT gate and the second input terminal of the first AND gate are the control terminals of the second selector. The output terminal of the NOT gate is connected to the second input terminal of the second AND gate. The output terminals of the first AND gate and the second AND gate are respectively connected to the two input terminals of the first OR gate. The output terminal of the first OR gate is the output terminal of the second selector.

7. The drive module according to claim 1, characterized in that, The drive module includes multiple drive modules. The inversion interval control unit of each drive module is connected to all the source drive chips it controls via a first signal line. The first polarity inversion control signal is output to the inversion interval control unit via a second signal line. The driving module further includes a third selector and a selection controller. The third selector includes a fourth transistor and a fifth transistor. The fourth transistor is a P-type field-effect transistor, and the fifth transistor is an N-type field-effect transistor. The first and second terminals of the fourth transistor are respectively connected to the first signal lines of adjacent display zones. The first and second terminals of the fifth transistor are respectively connected to the second signal lines of adjacent display zones. One of the second signal lines is connected to the timing controller. The control terminals of the fourth transistor and the fifth transistor are connected to the selection controller. The selection controller controls each display partition to be controlled separately by each of the driver modules or all display partitions to be controlled uniformly by one driver module, based on the refresh rate differences of the different display partitions.

8. The drive module according to claim 7, characterized in that, The driving module includes two driving modules. The selection controller includes a digital-to-analog converter, a difference calculation circuit, a judgment circuit, and an inverter. Each of the two input terminals of the difference calculation circuit is connected to one of the display zones through one of the digital-to-analog converters. The digital-to-analog converter is used to convert the refresh rate of the display zone into an analog signal. The difference calculation circuit is used to calculate the voltage difference between the two analog signals. The judgment circuit is used to determine the relationship between the voltage difference between the two analog signals and a preset range. The inverter is located between the output terminal of the judgment circuit and the control terminal of the third selector. When the voltage difference between the two analog signals is within the preset range, the judgment circuit controls the third selector to work, so that all the display zones are uniformly controlled by one driving module.

9. The drive module according to claim 7, characterized in that, The drive module includes three drive modules. The selection controller includes a second OR gate, a third OR gate, a third AND gate, and an inverter. The first input terminal of the second OR gate is connected to the refresh rate detection unit of the first drive module. The second input terminal of the second OR gate and the first input terminal of the third OR gate are connected to the refresh rate detection unit of the second drive module. The second input terminal of the third OR gate is connected to the refresh rate detection unit of the third drive module. The output terminals of the second OR gate and the third OR gate are connected to the two input terminals of the third AND gate. The output terminal of the third AND gate is connected to the control terminal of the third selector. The inverter is disposed between the output terminal of the third AND gate and the control terminal of the third selector.

10. A display device, characterized in that, include: Display panel; The driving module as described in any one of claims 1 to 9 is connected to the display panel.

Images