Dram device with a layout of a 3.5 f2 structure

Abstract

The invention discloses a DRAM (Dynamic Random Access Memory) element with a layout of a 3.5 F2 structure. The DRAM element comprises a substrate; a plurality of bit lines located on the substrate and arranged parallel to each other in a first horizontal direction at predetermined intervals; a plurality of word lines located on the bit lines and arranged parallel to each other at predetermined intervals in a second horizontal direction substantially perpendicular to the first horizontal direction; a plurality of channel patterns disposed on the bit lines in a honeycomb structure, each of the channel patterns extending in a vertical direction, each of the channel patterns including an upper electrode and a lower electrode, a region between the upper electrode and the lower electrode being a body region; and a gate insulating pattern between the plurality of channel patterns and the plurality of word lines, the plurality of word lines including first and second word lines arranged at different heights from each other, the first and second word lines being alternately arranged in a first horizontal direction, the plurality of channel patterns in contact with a single word line being arranged on the same straight line, and the first and second word lines being alternately arranged in a second horizontal direction. A plurality of channel patterns on a single bit line are arranged in a zigzag shape along both side edges of the single bit line.

Description

TECHNICAL FIELD

[0001] The present application relates to a DRAM element, and more particularly to a DRAM element having a layout of 3.5F2 structure (e.g., sub-4F2 structure). BACKGROUND

[0002] A DRAM cell has a one transistor-one capacitor (1T1C) structure, which is composed of a capacitor and a transistor, for storing and reading data (Non-Patent Literature 1). In the DRAM cell, the capacitor stores electric charges to hold logical information, and the transistor is controlled to be turned on / off by a word line and provides a data path between the capacitor and a bit line. The bit line is a transmission path for data, and the word line functions as a signal line for activating or deactivating the transistor as a gate of the transistor. In such a structure, the operation of the DRAM cell is divided into a write operation, a read operation, and a refresh operation, and weak signal amplification and periodic data recharging are achieved by a sense amplifier and a refresh circuitry, etc.

[0003] In addition, the main operation processes of the DRAM cell can be divided into a write operation, a read operation, and a refresh operation.

[0004] The write operation is an operation for storing data, the word line is activated to turn on the access transistor, and input data is transmitted to the capacitor through the bit line (in the case of logical "1", the capacitor is charged with positive electric charges, and in the case of logical "0", the capacitor is charged with negative electric charges), the word line is deactivated to turn off the access transistor, and the data is stored in the capacitor.

[0005] The read operation is an operation for reading data, the word line is activated to turn on the access transistor, and the charge state of the capacitor is transmitted through the bit line (in the case where positive electric charges exist in the capacitor, a certain voltage rise is sensed in the bit line, and in the case where negative electric charges exist in the capacitor, a certain voltage drop is sensed in the bit line), and the data of the bit line is amplified by a sense amplifier and converted into a readable signal.

[0006] Since the capacitor of the DRAM naturally discharges over time, it is necessary to periodically perform refresh to prevent loss of data, which is called a refresh operation. The period of refresh generally consists of several milliseconds (ms) units, and the same data is written again after reading the data of the cell to replenish the electric charges.

[0007] As main features of the DRAM cell, there are, for example, that it is a volatile memory in which data disappears as the charge of the capacitor is discharged when the power is turned off, that it can achieve high integration and fast access with a simple structure of 1T1C and can be driven at low power, that a refresh cycle is required periodically in order to retain data, thereby consuming additional power, and the like.

[0008] Main considerations when the DRAM cell is in operation are that as the DRAM cell is miniaturized, the capacitor capacity becomes low and it is difficult to store sufficient charge, and thus data stability can be reduced, that coupling noise between adjacent bit lines can occur, and that a margin value (detection margin) that can distinguish a signal from noise is required in a read operation.

[0009] The DRAM cell stores, reads, and retains data by such operation and functions as a high-density and high-performance memory.

[0010] As the integration of semiconductor memory devices increases, in order to reduce the area occupied by each unit memory cell on a plane, the cell structure is continuously reduced from 8F 2 to 6F 2 to 4F 2 . In correspondence therewith, various technologies for implementing a transistor, a bit line, a word line, a capacitor, and the like within a 4F 2 cell structure have been proposed. In particular, as one solution for reducing the area of a unit cell, a DRAM element including a vertical channel transistor in which a source and a drain region are arranged vertically to guide a vertical channel has been studied. Chung et al. proposed a new DRAM cell of a 4F 2 structure using a vertical pillar transistor (Non-Patent Literature 2). When such a vertical channel transistor is used, it is expected that the cell area efficiency can be improved.

[0011] However, in the vertical channel transistor of Non-Patent Literature 2, since the channel pillar directly contacts the cell capacitor, a leakage current flows during data storage, as a result, there is a limitation in that the retention time becomes short and frequent refresh is required, and power consumption increases. In addition, in the field of semiconductor elements, in order to increase the capacity per unit area, reduction of the minimum feature size F and a smaller cell layout are continuously pursued. However, the minimum spacing of a wiring line formed on the same plane like a word line faces a physical limit in the manufacturing process, and thus, it is currently difficult to further increase the capacity per unit area only by the element of Non-Patent Literature 2.

[0012] Existing technical documents

[0013] Non-patent literature

[0014] Non-patent literature 1: Robert H. Dennard, “Operation of a One-Transistor Cell Used in a High-Density DRAM”, IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 5, Oct. 1974

[0015] Non-patent literature 2: Chung et al., “4F2 DRAM Cell with Vertical Pillar Transistor (VPT)”, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011 Summary of the Invention

[0016] The technical problem that the invention aims to solve

[0017] One of the many objects of the present invention is to provide a vertical columnar transistor and a DRAM element including the thereof, wherein the vertical columnar transistor can increase the capacity per unit area by forming a multilayer word line structure at different heights to each other.

[0018] Furthermore, another object of the present invention is to provide a vertical channel transistor and a DRAM element including the same, wherein by forming the bit lines with a conductive material such as metal or silicide in the vertical channel transistor, the resistance and RC delay of the bit lines can be reduced and the detection margin can be improved.

[0019] Technical solutions for solving technical problems

[0020] According to one embodiment, the present invention provides a DRAM device with a 3.5F2 structure layout, comprising: a substrate; a plurality of bit lines located on the substrate and arranged parallel to each other in a first horizontal direction at predetermined intervals; a plurality of word lines located on the bit lines and arranged parallel to each other in a second horizontal direction substantially perpendicular to the first horizontal direction at predetermined intervals; a plurality of channel patterns arranged in a honeycomb structure on the bit lines and extending in a vertical direction, each of the channel patterns including an upper electrode and a lower electrode, the region between the upper electrode and the lower electrode being a main region; and a gate insulating pattern located between the plurality of channel patterns and the plurality of word lines, the plurality of word lines including a first word line and a second word line arranged at different heights, the first word line and the second word line being alternately arranged in the first horizontal direction, the plurality of channel patterns in contact with a single word line being arranged in a straight line, and the plurality of channel patterns located on a single bit line being arranged in a zigzag pattern along the two side edges of the single bit line.

[0021] According to one embodiment, at least a portion of each of the channel patterns can be in direct contact with the substrate.

[0022] According to another embodiment, the present invention provides a DRAM device with a 3.5F2 structure layout, comprising: a substrate; a plurality of channel patterns disposed on the substrate in a honeycomb structure and extending in a vertical direction, each of the channel patterns including an upper electrode and a lower electrode, the region between the upper electrode and the lower electrode being a main region; a plurality of bit lines contacting one side of the lower electrode, oriented in a first horizontal direction and arranged parallel to each other at predetermined intervals; a plurality of word lines contacting the main region, oriented in a second horizontal direction perpendicular to the first horizontal direction and arranged parallel to each other at predetermined intervals; and a gate insulating pattern located between the plurality of channel patterns and the plurality of word lines, the plurality of word lines including first word lines and second word lines disposed at different heights, the first word lines and the second word lines being alternately arranged in the first horizontal direction, the plurality of channel patterns contacting a single word line being arranged in a straight line, and the plurality of channel patterns contacting a single bit line being arranged in a zigzag pattern.

[0023] According to one embodiment, the bit line may contain a metal or silicide material.

[0024] Invention Effects

[0025] According to the DRAM element of the present invention, the advantage of the present invention is that by forming adjacent word lines at different heights, the minimum spacing between word lines can be reduced, thereby increasing the cell capacity per unit area and improving the integration density.

[0026] According to the DRAM element of the present invention, the advantage of the present invention is that by forming the bit lines with conductive materials such as metals or silicides, the bit line resistance can be reduced.

[0027] Furthermore, the present invention has the advantage that the parasitic capacitance of the bit line is reduced, thereby improving the detection margin of the cell.

[0028] Meanwhile, the present invention has the advantage that by using a deposition process instead of ion implantation to form the bit lines, the process difficulty can be alleviated and the manufacturing uniformity can be improved.

[0029] Furthermore, the present invention has the advantage that by applying a feedback bias voltage to the substrate in the main region of the channel pattern, the floating body effect is suppressed, thereby increasing the stability of the unit operation.

[0030] Furthermore, the present invention has the advantage that the RC delay is reduced due to the decrease in bit line resistance and the increase in the contact area between the bit line and the lower electrode, thereby improving the operating speed of the component.

[0031] The effects of one aspect of the present invention are not limited to those described above, but should be understood to include all effects that can be derived from the specific embodiments described in this specification or the technical features set forth in the appended claims. Attached Figure Description

[0032] Figure 1 This is a perspective view of a vertical columnar transistor manufactured according to a first embodiment of the present invention.

[0033] Figure 2 It is along Figure 1 A sectional view taken along line A-A'.

[0034] Figure 3 It is along Figure 1 A sectional view taken along line B-B'.

[0035] Figure 4 yes Figure 1 A schematic top view of a vertical columnar transistor.

[0036] Figure 5 It includes Figure 1 A three-dimensional view of a DRAM element with vertical columnar transistors.

[0037] Figure 6 This is a perspective view of a vertical channel transistor according to a second embodiment of the present invention.

[0038] Figure 7 It is along Figure 6A sectional view taken along line A-A'.

[0039] Figure 8 It is along Figure 6 A sectional view taken along line B-B'.

[0040] Figure 9 Part (a) is a top view of a prior art DRAM element including a vertical columnar transistor with a 4F2 structure. Figure 9 Part (b) is a top view of a DRAM element including vertical columnar transistors, wherein in the DRAM element including vertical columnar transistors, the vertical columnar transistors are fabricated such that the spacing between adjacent word lines (3) is reduced to half (1 / 2) compared to the width of (1) word lines, the width of (2) bit lines, and the spacing between adjacent bit lines (4).

[0041] Explanation of reference numerals in the attached figures

[0042] 10: Substrate 20: Bit Line

[0043] 30: Character line 30u: First character line

[0044] 30l: Second letter line; 40: Groove pattern

[0045] 40l: Lower electrode; 40u: Upper electrode

[0046] 50: Gate electrode; 52: Gate insulating film

[0047] 54: Gate conductive film; 60: Contact plug

[0048] 70: Capacitor; 100: Vertical columnar transistor

[0049] 200: DRAM components Detailed Implementation

[0050] The present specification will now be described in one manner with reference to the accompanying drawings. However, the contents of this specification can be implemented in many different forms, and therefore are not limited to the embodiments described herein.

[0051] Throughout this specification, when a part is described as being "connected" to other parts, it includes not only the case of "direct connection" but also the case of "indirect connection" with another component between them. Furthermore, when a component is described as being "above," "upper," "upper end," "below," "lower," or "lower end" of another component, it includes not only the case of one component being in contact with the other component but also the case of another component existing between the two components.

[0052] Throughout this specification, when a part is described as "including" a constituent element, it means, unless specifically stated to the contrary, that other constituent elements may also be present, rather than excluding other constituent elements.

[0053] The embodiments described in this specification will be illustrated with reference to cross-sectional views and / or schematic diagrams, which are ideal schematic representations of the invention. Throughout the specification, the same reference numerals refer to the same constituent elements. Detailed descriptions of well-known functions and technical features that may obscure the essence of the invention are omitted. Furthermore, the constituent elements illustrated in the figures of this invention may be shown slightly enlarged or reduced for ease of description.

[0054] Furthermore, the embodiments of the present invention are not limited to the specific form shown in the figure, but also include variations in form generated according to the manufacturing process.

[0055] Figure 1 This is a perspective view schematically illustrating a vertical columnar transistor manufactured according to a first embodiment of the present invention.

[0056] Reference Figure 1 A vertical columnar transistor 100 manufactured according to a first embodiment of the present invention includes: a substrate 10; a plurality of bit lines 20 located on the substrate 10 and arranged parallel to each other in a first horizontal direction at predetermined intervals; a plurality of word lines 30u, 30l located on the bit lines 20 and arranged parallel to each other in a second horizontal direction substantially perpendicular to the first horizontal direction at predetermined intervals; a plurality of channel patterns 40 arranged in a honeycomb structure on the bit lines 20 and extending in a vertical direction respectively; and a gate insulating pattern (not shown) located between the plurality of channel patterns 40 and the plurality of word lines 30u, 30l.

[0057] The vertical channel transistor 100 corresponds to the transistor portion of a DRAM cell consisting of a transistor and a capacitor. The DRAM element 200 is realized by arranging multiple vertical channel transistors 100 in a matrix configuration.

[0058] Multiple channel patterns 40 are arranged at the positions where multiple bit lines 20 intersect with multiple word lines 30u and 30l.

[0059] Electrodes (not shown) are formed at the upper and lower portions of multiple channel patterns 40. The region between the upper electrode 40u and the lower electrode 40l is a main region (not shown), which has the same polarity as the substrate 10, while the upper electrode 40u and the lower electrode 40l have different polarities than the substrate 10. For example, if the substrate 10 is a p-type semiconductor substrate, the main region has p-type polarity, and the upper electrode 40u and the lower electrode 40l have n-type polarity. In this case, the upper electrode 40u and the lower electrode 40l can be formed by implanting n-type impurity ions into the upper and lower ends of the channel pattern 40, respectively, and then performing drive-in diffusion.

[0060] A gate 50 is formed between the upper electrode and the lower electrode in such a way that it covers the side of the channel pattern 40. The gate 50 may include a gate insulating pattern 52 and a gate conductive pattern 54.

[0061] The plurality of word lines 30u, 30l include the first word line 30u and the second word line 30l configured at different heights from each other, the first and second word lines being alternately configured in the first horizontal direction (e.g., the x-axis direction).

[0062] In existing vertical channel transistors, there are physical limitations in increasing the capacity per unit area because multiple word lines are arranged flush at essentially the same height.

[0063] However, by arranging adjacent word lines at different heights, the minimum feature size F can be easily reduced in this invention, resulting in the advantages of increasing capacity per unit area and improving integration.

[0064] The first and second letter lines 30u and 30l can be formed independently of each other from at least one of the following substances: metal, semiconductor and alloy. They can be formed from the same substance or from different substances.

[0065] Spacers (not shown) may be provided on the sidewalls of the first and second letter lines 30u and 30l. The spacers can prevent the first and second letter lines 30u and 30l from contacting other unconnected channel patterns 40.

[0066] Figure 2 It is along Figure 1 A sectional view taken along line A-A'.

[0067] The substrate 10 may include, for example, group IV semiconductor materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), and silicon carbide (SiC); group III-V semiconductor materials such as gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); oxide semiconductors; nitride semiconductors; and oxynitride semiconductors. Specifically, the substrate may be a silicon substrate doped with p-type impurities, but is not limited thereto.

[0068] Multiple channel patterns 40 are formed extending substantially perpendicularly from the substrate 10. In other words, the channel patterns 40 can be configured as pillar shapes protruding from the upper surface of the substrate 10 in a vertical direction (e.g., the z-axis direction). Each channel pattern 40 can be integrally formed with the substrate 10, thereby it can be made of the same semiconductor material as the substrate 10.

[0069] Multiple channel patterns 40 are arranged in a honeycomb structure on the plane (i.e., the XY plane) of the substrate 10. A honeycomb structure refers to a pattern shape arranged at the center and vertices of a hexagon, whereby the arrangement between adjacent channel patterns will form a zigzag shape.

[0070] Each channel pattern 40, in order to perform the functions of the source / drain and channel of a transistor, includes impurity-doped regions at its upper and lower ends. More specifically, an upper electrode 40u is formed at the upper part of the channel pattern 40, and a lower electrode 40l is formed at the lower part of the channel pattern 40. The upper electrode 40u and the lower electrode 40l can be formed by implanting n-type impurity ions at the upper and lower ends of the channel pattern 40, respectively, and performing a thermal diffusion process. At this time, an additional masking process can be used for the positioning of the upper electrode 40u and the lower electrode 40l. After the upper / lower electrode is formed, the residual impurity diffusion region is controlled to exclude the main body region located in the middle of the channel pattern 40. The region between the upper electrode 40u and the lower electrode 40l corresponds to the body region of the transistor, which has the same polarity (p-type) as the substrate 10, while the upper electrode 40u and the lower electrode 40l have the opposite polarity (n-type) to the substrate 10. Depending on the requirements, the functions of the upper electrode 40u and the lower electrode 40l can be interchanged. For example, depending on the operating mode, the upper electrode 40u can be used as the source or drain, while the lower electrode 40l performs the opposite function. The lower electrode 40l is electrically connected to the bit line 20, and the upper electrode 40u is electrically connected to a capacitor (not shown) described later.

[0071] A gate 50 is formed between the upper electrode 40u and the lower electrode 40l of the channel pattern 40, that is, over the entire side surface of the channel pattern. The gate 50 corresponds to the gate electrode of a transistor surrounding the main region of the channel pattern, and may include a gate insulating pattern 52 and a gate conductive pattern 54. The gate insulating pattern 52 is an insulating film formed along the side surface of the channel pattern 40, and may be made of dielectric materials such as silicon oxide (SiO2) or silicon nitride (Si3N4). The gate conductive pattern 54 is a conductive film formed outside the gate insulating pattern 52, and may be made of conductive materials such as polysilicon, metal, or metal silicide. The gate 50 extends vertically around the main region of the channel pattern 40, and its height is preferably greater than the sum of the heights of the first and second word lines 30u and 30l, described later. This is to allow the overall height of the gate 50 to simultaneously encompass two word line layers, such that the word lines are connected to the gate 50 at different heights. As one example, by extending the gate 50 over the entire height of the channel pattern, the gate conductive pattern 54 can have a continuous structure without vertical division. Alternatively, the gate conductive pattern 54 can be divided into two parts in the vertical direction and formed at heights corresponding to the first and second word lines, respectively. In the latter case, the gate 50 has two gate electrodes connected in series vertically, and an appropriate structure can be selected based on the manufacturing process and driving method.

[0072] A portion of each channel pattern 40 may contact the p-type region of the substrate 10. For example, at least a portion of the base or outline of the channel pattern 40 may be continuously connected to the substrate 10. By applying a predetermined bias voltage to the substrate 10 through such a structure, a back bias is applied to the main body region of the channel pattern 40, thereby maintaining the transistor's body at a stable potential and preventing floating. As a result, unwanted floating effects are suppressed, thereby reducing the likelihood of transistor threshold voltage fluctuations or leakage paths.

[0073] Bit lines 20 are wirings used in a vertical channel transistor to connect the lower electrodes 401 of each memory cell to each other. They are provided extending along a first horizontal direction (e.g., the x-axis direction) at the lower part of the lower electrodes 401, and each bit line 20 can electrically connect the lower electrodes 401 arranged along the first horizontal direction. The bit lines 20 are formed inside the substrate 10, so that they can contain the same semiconductor material as the substrate 10.

[0074] Multiple word lines 30u and 30l constitute the gate signal lines of the memory cell transistor and extend along a second horizontal direction (e.g., the y-axis direction). In this invention, the word lines are not formed on a single plane, but rather implemented as a first word line 30u and a second word line 30l formed at two different heights. (See also...) Figure 2 and Figure 3 The second word line 30l is formed in such a way that it surrounds the lower region of the gate 50 formed on the side of the channel pattern 40, and the first word line 30u is formed in such a way that it surrounds the upper region of the gate 50. That is, in the portion of the gate 50 surrounding each channel pattern 40, the second word line 30l is arranged on the lower side and the first word line 30u is arranged on the slightly upper side, and they are respectively connected to the gate 50 of the channel pattern. As described above, by forming the first word line 30u and the second word line 30l at different heights, adjacent word lines will alternately have different heights along the first horizontal direction. As a result, the minimum spacing required between word lines on the same plane can be alleviated, thereby enabling a reduction in word line pitch in the cell layout.

[0075] The first word line 30u and the second word line 30l are electrically independent separate lines. Each word line 30u, 30l can be formed of a conductive material, such as polysilicon, tungsten, copper, aluminum, molybdenum, titanium, or other metals or silicides, or alloys thereof. However, since the two word line layers are formed at different process stages, they do not necessarily have to be formed of the same material. According to embodiments, the first word line 30u and the second word line 30l can be formed of the same material, or they can be formed of different materials. For example, the second word line 30l, as the lower layer, can be formed of polysilicon, and the first word line 30u, as the upper layer, can be formed of metal.

[0076] The first and second word lines 30u and 30l are arranged in contact with the gate 50 of the channel pattern 40. To prevent unintentional interference with other channels, spacer insulating films (not shown) can be provided on the sidewalls of the word lines. For example, by forming insulating spacers on the sidewalls of the first word line 30u and the second word line 30l, they can be physically separated from the gate 50 of adjacent channel patterns 40 that are not connected to the corresponding word lines. With such a structure, the channel pattern to which each word line belongs can be selectively controlled without affecting the channels of adjacent cells.

[0077] Figure 4 yes Figure 1 A schematic top view of a vertical channel transistor. Figure 4 The illustrations of capacitors and wiring connected to the upper part of the channel pattern 40 are omitted, and the illustration focuses on the arrangement structure of the channel pattern 40.

[0078] Reference Figure 4 The plurality of channel patterns 40 are arranged in a honeycomb structure on the bit line 20. A honeycomb structure refers to a structure in which channel patterns are arranged at the center point and six vertices of a hexagon, and the channel patterns at the six vertices respectively become the center points of six adjacent hexagons. In the honeycomb structure, the hexagons can be regular hexagons, and the six triangles sharing the center point can all be equilateral triangles.

[0079] exist Figure 4 In this configuration, each bit line 20 extends in a row along the x-axis, and channel patterns 40 are alternately arranged along its two side edges. Multiple channel patterns 40 connected to a bit line 20 are arranged in a zigzag pattern by crossing left and right along the bit line's direction of travel. On the other hand, multiple channel patterns 40 connected to a word line (30u or 30l) are arranged in a row along the y-axis direction where the word line extends. For example, the channel patterns driving the gate 50 via the first word line 30u are aligned on the same straight line along the y-axis, and the channel patterns driven by the adjacent second word line 30l are located between them. This arrangement efficiently reduces the spacing between adjacent cells, thereby achieving a cell area of ​​4F. 2 The following sub-4F 2 (sub 4F 2 The layout of the structure (e.g., 3.5F2) is such that, with multiple channel patterns 40 configured in a honeycomb structure, a 3.5F2 structure can be achieved without adjusting the widths of the first conductive lines 20l and 20u, the widths of the second conductive lines 30, and the spacing between adjacent first conductive lines 20. For example, when the diameter of each channel pattern 40, the width of the bit line 20, the width of the word lines 30u and 30l, and the spacing between adjacent bit lines 20 are all the same F, the area of ​​the parallelogram connecting the four channel patterns will be approximately 3.464F2 (=2F×2Fsin60°). As a result, it has the advantage of being able to easily achieve a 3.5F2 structure without increasing the inter-bit line capacitance, the inter-bit line-word line capacitance, or the inter-bit line-substrate capacitance, i.e., while keeping the ratio (Cb / Cs) of the bit line capacitance Cb to the unit capacitance Cs at the same level as in the prior art.

[0080] When the diameter of each channel pattern 40, the width of the bit line 20, and the spacing between adjacent bit lines 20 are all the same F, the inner half of each channel pattern 40 will be located on the bit line 20.

[0081] Figure 5 It is a general description including Figure 1 A three-dimensional view of a DRAM element with vertical columnar transistors.

[0082] Reference Figure 5A capacitor 70 is connected to the upper part of each vertical channel transistor 100. The capacitor 70 is a component used to ensure the data storage capacity of the memory cell, and it is electrically connected to the upper electrode 40u of the channel pattern 40. The capacitor 70 can be, for example, a stacked capacitor consisting of a cylinder-shaped lower electrode, a dielectric layer, and an upper electrode. Although not shown, the upper electrodes of multiple memory cell capacitors can be connected by a common potential. The lower electrode of the capacitor 70 is connected to the upper electrode 40u of the channel pattern 40 to form a storage node, and the upper electrode of the capacitor 70 operates as a common plate. Additionally, the lower electrode 40l of the channel pattern 40 is connected to the bit line 20 as described above. As described above, the vertical channel transistor 100 and the capacitor 70 combine to form a memory cell, and such memory cells are arranged in an XY matrix to form a DRAM element 200. DRAM element 200 is addressed by multiple bit lines 20 and multiple word lines 30u, 30l. Data stored in capacitor 70 can be read through bit lines 20 by turning on the transistor of the selected cell, or conversely, data can be stored in capacitors through bit lines.

[0083] A contact plug 60 may also be provided between the capacitor 70 and the channel pattern 40. With this structure, a DRAM element 200 is constructed that uses the vertical channel transistor 100 as a memory cell. Such a vertical channel transistor 100 is not only applicable to the aforementioned memory elements, but also, due to its versatility, to transistors in non-memory elements such as central processing units (CPUs).

[0084] The following is for reference Figures 6 to 8 The second embodiment of the present invention will be described. Since the second embodiment shares many structural elements with the first embodiment, the following description will focus on their differences.

[0085] The main feature of the second embodiment lies in the structure and material of the bit line 20. Figure 6 This is a perspective view of a vertical channel transistor according to the second embodiment. Figure 7 and Figure 8 The cross-sectional views are shown in the figures.

[0086] Unlike the first embodiment, in the second embodiment, the bit line 20 is not formed as a diffusion region inside the substrate 10, but rather as an additional conductive layer within a trench formed on the upper surface of the substrate 10. Specifically, the bit line 20 may have a structure that contacts the side of the lower electrode 40l of the channel pattern 40 and is physically separated from the substrate 10.

[0087] Bit lines 20 can be formed by depositing metal within a semiconductor substrate, instead of by implanting impurities into the semiconductor substrate. For example, bit lines 20 can be formed from metals such as tungsten (W), aluminum (Al), and copper (Cu), or from silicide materials. In such a metal bit line structure, the line resistance can be significantly reduced compared to diffused bit lines formed within the semiconductor substrate. Furthermore, since the bit lines are insulated from the substrate, the parasitic capacitance of the bit lines can be reduced. Therefore, it has the effect of improving signal transmission delay (RC delay) via bit lines and increasing the signal strength of the unit at the sense amplifier side. Additionally, using a deposition process instead of ion implantation offers the added advantages of reducing process difficulty and improving manufacturing uniformity.

[0088] Furthermore, the bit line 20 can be formed by finely patterning a conductive layer made of metal or its alloy. For example, the bit line 20 can be a metal wiring formed by depositing a metal such as tungsten or aluminum and etching it after forming an insulating film as a liner in a trench provided on the substrate 10. Since such a metal bit line 20 has lower resistance and less capacitance compared to the prior art bit lines formed as diffusion regions inside the substrate 10, it has excellent signal transmission characteristics. In addition, although the bit line 20 is formed on the same plane as the substrate 10, it can be electrically isolated from the substrate 10 by means of insulation separation through the trench or by diode insulation through the pn junction. That is, since the lower electrode 40l contacted by the bit line 20 is an n-type semiconductor and the substrate 10 is a p-type semiconductor, unless the pn junction between them is forward biased, current can be prevented from flowing between the bit line and the substrate. Therefore, the bit line 20 is designed to be electrically connected only to the lower electrode 40l and not to affect the surrounding substrate area. This structure effectively achieves electrical separation by utilizing the rectification characteristics of the pn junction formed between bit line 20 and substrate 10. Therefore, it can reduce parasitic capacitance and reliably ensure detection margin without the need for additional complex insulation structures.

[0089] The following explains in more detail the technical reasons why the minimum wiring width F can be easily reduced by placing adjacent word lines at different heights.

[0090] In the field of DRAM devices, the minimum wiring width F is an important factor in determining the integration level and performance of the device. The minimum wiring width F refers to the smallest line width that can be drawn in a semiconductor circuit. Generally speaking, it is the smallest of (1) the width of the word line, (2) the width of the bit line, (3) the spacing between adjacent word lines, and (4) the spacing between adjacent bit lines.

[0091] Because a smaller minimum wiring width F results in higher transistor density, smaller chip size, and reduced power consumption in semiconductor chips, the technology in the DRAM device field is developing towards using the smallest possible minimum wiring width F.

[0092] However, this minimum wiring width cannot be arbitrarily reduced; rather, it is usually determined based on the level of technological development at the time of manufacturing. Specifically, it is determined based on the resolution of the photolithography equipment and the quality and performance of the photoresist.

[0093] Figure 9 Part (a) is a top view of a prior art DRAM element including a vertical columnar transistor with a 4F2 structure. Figure 9 In part (a), (1) the width of the word line, (2) the width of the bit line, (3) the spacing between adjacent word lines, and (4) the spacing between adjacent bit lines are all set to F, thus giving it a 4F2 structure.

[0094] Figure 9 Part (b) is a top view of a DRAM element including vertical columnar transistors, wherein the vertical columnar transistors are fabricated such that the spacing between adjacent word lines (3) is reduced to half (1 / 2) compared to the width of the word line (1), the width of the bit line (2), and the spacing between adjacent bit lines (4). In this case, the spacing between adjacent word lines (3) will reach the minimum wiring width F, and since this minimum wiring width F is determined according to the level of technological development at the time of manufacturing, the result will be an increase in the area of ​​the unit cell (12F2 = 4F × 3F). That is, the method of adjusting the spacing between adjacent word lines in order to reduce the area of ​​the unit cell is not preferred.

[0095] However, in this invention, the horizontal spacing between adjacent first and second character lines can be adjusted arbitrarily as long as the interval between adjacent first character lines and the interval between adjacent second character lines are both greater than or equal to the minimum wiring width F. This is because character lines formed on different planes (at different heights) are formed at different stages of the manufacturing process, and therefore are not affected by the minimum wiring width determined by the technological level at the manufacturing time. Theoretically, the horizontal spacing between adjacent first and second character lines can be adjusted to 1 / 2F.

[0096] Therefore, a DRAM element manufactured according to one aspect of the present invention has the advantage of increased capacity per unit area compared to the capacity per unit area typically achievable at the level of technological advancement at the manufacturing time.

[0097] The foregoing description in this specification is merely illustrative. Those skilled in the art to which this specification pertains should understand that other specific forms can be readily derived without altering the technical concepts or essential technical features described herein. Therefore, the embodiments described above are illustrative in all respects and should not be construed as limiting. For example, constituent elements described as single can also be implemented in a distributed form; similarly, constituent elements described as distributed can also be implemented in a combined form.

[0098] The scope of this specification is set forth in the appended claims, and the meaning, scope, and all variations or modifications derived therefrom of the appended claims shall be construed as falling within the scope of this specification.

Claims

1. A DRAM cell having a layout with a 3.5F2 structure, wherein, Comprising: a substrate; a plurality of bit lines disposed on the substrate in parallel with each other at a prescribed interval in a first horizontal direction; a plurality of word lines disposed on the bit lines in parallel with each other at a prescribed interval in a second horizontal direction substantially perpendicular to the first horizontal direction; a plurality of channel patterns disposed in a honeycomb structure on the bit lines and extending in a vertical direction each, each of the channel patterns including an upper electrode and a lower electrode, a region between the upper electrode and the lower electrode being a body region; and a gate insulating pattern disposed between the plurality of channel patterns and the plurality of word lines, the plurality of word lines including first word lines and second word lines disposed at different heights from each other, the first word lines and the second word lines being alternately disposed with each other in the first horizontal direction, a plurality of channel patterns in contact with a single word line being arranged in a straight line, a plurality of channel patterns on a single bit line being arranged in a zigzag along both side edges of the single bit line.

2. The DRAM element having a layout of a 3.5F2 structure according to claim 1, wherein at least a portion of each of the channel patterns is in direct contact with the substrate. Comprising:

3. A DRAM cell having a layout with a 3.5F2 structure, wherein, a substrate; a plurality of channel patterns disposed in a honeycomb structure on the substrate and extending in a vertical direction each, each of the channel patterns including an upper electrode and a lower electrode, a region between the upper electrode and the lower electrode being a body region; a plurality of bit lines in contact with one side of the lower electrode, oriented in a first horizontal direction, and disposed in parallel with each other at a prescribed interval; a plurality of word lines in contact with the body region, oriented in a second horizontal direction perpendicular to the first horizontal direction, and disposed in parallel with each other at a prescribed interval; a gate insulating pattern disposed between the plurality of channel patterns and the plurality of word lines, the plurality of word lines including first word lines and second word lines disposed at different heights from each other, the first word lines and the second word lines being alternately disposed with each other in the first horizontal direction, a plurality of channel patterns in contact with a single word line being arranged in a straight line, a plurality of channel patterns on a single bit line being arranged in a zigzag.

4. The DRAM element having a layout of a 3.5F2 structure according to claim 3, wherein the bit lines contain a metal or a silicide substance. ​ ​

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