Method for integrating three-dimensionally stackable nonvolatile memories

Abstract

According to the three-dimensional stackable nonvolatile memory integration method, a prepared memory is formed by stacking a plurality of units from bottom to top, each unit comprises a selection tube and a nonvolatile storage medium, a source and a drain of the selection tube are provided by a channel layer of the selection tube, and a gate end of the selection tube is composed of gate metal and gate dielectric. The source ends of the selection tubes serve as bottom electrodes of the nonvolatile storage media at the same time, the drain ends of the selection tubes serve as top electrodes of the nonvolatile storage media at the same time, and the sources and the drains of the adjacent selection tubes are connected together. In the direction perpendicular to the paper surface, the gate ends of the selection tubes of the same row of units are connected together through gate metal to form a word line, the drain ends of the selection tubes of the uppermost layer of units form a bit line through source-drain metal, and the source ends of the selection tubes of the lowermost layer of units form a plate line through source-drain metal. The process steps of photoetching, etching, channel layer deposition, nonvolatile dielectric layer deposition and the like are shared by a plurality of memory units, so that the cost of each bit of the memory is reduced, and the high-reliability and high-density nonvolatile memory is prepared.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, in particular to a three-dimensionally stackable non-volatile memory integration method. BACKGROUND

[0002] With the development of artificial intelligence and Internet of Things technology, there is a surge in demand for high-speed, high-density, low-power storage. Existing storage needs to be compromised between reliability and storage density. Therefore, a new type of high-density, high-reliability storage is needed. SUMMARY

[0003] The purpose of the present application is to design a three-dimensionally stackable non-volatile memory integration method. The memory prepared by the integration method includes a low-off-state current conduction device as a selection tube of the memory and a non-volatile storage medium, thereby achieving high-density storage while ensuring high reliability.

[0004] The technical solution of the present application is as follows: By designing an integration method, a three-dimensionally stackable non-volatile memory can be prepared. The memory is composed of multiple units stacked from bottom to top, each unit including a selection tube and a non-volatile storage medium. The source and drain of the selection tube are provided by the channel layer, the gate end of the selection tube is composed of gate metal and gate dielectric, the source end of the selection tube simultaneously serves as the bottom electrode of the non-volatile storage medium, the drain end of the selection tube simultaneously serves as the top electrode of the non-volatile storage medium, and the source and drain of adjacent selection tubes are connected together. Along the direction perpendicular to the paper, the gate ends of the selection tubes of the same row of units are connected together by the gate metal to form a word line WL, and in the direction parallel to the paper, different units are located on different word lines WL. The drain end of the selection tube of the uppermost layer of units forms a bit line BL through the source-drain metal, and the source end of the selection tube of the lowermost layer of units forms a plate line PL through the source-drain metal.

[0005] The specific steps include: Step 1: depositing source-drain metal material, isolation layer material and gate metal material on the substrate in sequence, the specific method being depositing a layer of source-drain metal material as a plate line PL, then depositing a layer of isolation layer material, then depositing a layer of gate metal material as a word line WL, then repeating the deposition of isolation layer material and gate metal material, and then depositing a layer of isolation layer material, then depositing a layer of source-drain metal material as a bit line BL, the number of layers of gate metal material being the number of repetitions of the unit structure in the above-mentioned memory structure; Step 2: defining an active region, the specific method being patterning the active region by lithography, and then etching the isolation layer material, source-drain metal material and gate metal material outside the active region to form the active region; Step 3: Form the memory cell region. The specific method is to pattern the memory cell region using photolithography, and then etch the gate metal material and source / drain metal material laterally. Step 4: Form the gate dielectric layer. The specific method is to anneal in an oxygen atmosphere to form an oxide layer on the gate metal surface as the gate dielectric. Step 5: Form the channel layer, specifically by depositing channel material; Step 6: Form a non-volatile dielectric layer, specifically by depositing a non-volatile dielectric material; Specifically, the substrate in step 1 can be a bare silicon wafer or a silicon wafer on which front-end devices and circuits have already been fabricated. The isolation layer material can be a dielectric material such as silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, or porous silicon dioxide. The thickness of the deposited monolayer isolation layer material is between 10 nm and 500 nm, and the deposition method can be PVD, CVD, or epitaxy. The source / drain metal material can be a metal such as titanium nitride or tungsten. The thickness of the deposited monolayer source / drain metal material is between 10 nm and 500 nm. The gate metal material can be a metal such as tantalum or titanium. The thickness of the deposited monolayer gate metal material is between 1 nm and 500 nm.

[0006] The etching method in step 2 can be reactive ion etching (RIE), ion beam etching (IBE), inductively coupled plasma (ICP), etc.

[0007] The etching method in step 3 can be wet etching, and the etching reagent can be hot phosphoric acid, dilute nitric acid, hydrogen peroxide, etc.

[0008] The channel layer material in step 5 can be an oxide semiconductor material such as indium gallium zinc oxide, indium tin oxide, or tin suboxide, or a two-dimensional material such as molybdenum disulfide or black phosphorus, or a semiconductor material such as amorphous silicon or polycrystalline silicon. The thickness of the channel layer material is between 1 nm and 500 nm.

[0009] The non-volatile dielectric layer material in step 6 can be a ferroelectric material such as hafnium zirconium oxide, hafnium lanthanum oxide, or hafnium aluminum oxide, or a resistive switching material such as hafnium oxide or tungsten oxide, or a phase change material such as GeSbTe. The thickness of the non-volatile dielectric layer material is between 1 nm and 100 nm.

[0010] The specific technical effects of the three-dimensionally stackable non-volatile memory integration method of the present invention are as follows: 1. The proposed integration method can enable multiple memory cells to share process steps such as photolithography, etching, trench layer deposition, and non-volatile dielectric layer deposition, thereby reducing the cost per bit of memory; 2. The proposed integration method can fabricate highly reliable, high-density non-volatile memories that can be integrated in three dimensions. Attached Figure Description

[0011] Figure 1 This is a schematic diagram showing the effect of the memory obtained by the memory integration method proposed in this invention; Figures 2-7 This is a schematic diagram of the preparation steps using the integrated method proposed in this invention, wherein: Figure 2 This is an image showing the effect after depositing multiple layers of material; Figure 3 This is a diagram showing the effect after the active region is formed; Figure 4 This is a diagram showing the effect after the storage unit area is formed; Figure 5 This is a diagram showing the effect after the gate dielectric layer is formed; Figure 6 This is a rendering showing the effect after the channel layer is formed; Figure 7 This is a diagram showing the effect after the formation of a non-volatile dielectric layer; In the picture: 1 — Source / Drain Metal 2 — Isolation Layer 3 — Gate metal 4 — Gate dielectric layer 5 — Channel layer; 6 — Non-volatile medium layer Detailed Implementation

[0012] The present invention will be further illustrated below with examples. It should be noted that the purpose of disclosing the embodiments is to aid in further understanding the present invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection claimed by the present invention shall be determined by the scope defined in the claims.

[0013] Figure 1This is a schematic diagram illustrating one possible effect of the integration method proposed in this invention. The integrated memory has the following characteristics: The memory is composed of multiple cells stacked from bottom to top. Each cell includes a select transistor and a non-volatile storage medium 6. The source and drain of the select transistor are provided by its channel layer 5. The gate of the select transistor is composed of a gate metal 3 and a gate medium 4. The source of the select transistor also serves as the bottom electrode of the non-volatile storage medium, and the drain of the select transistor also serves as the top electrode of the non-volatile storage medium. The sources and drains of adjacent select transistors are connected together. Along the direction perpendicular to the paper, the gates of the select transistors in the same row are connected together through the gate metal 3 to form a word line WL. In the direction parallel to the paper, different cells are located on different word lines WL. The drain of the select transistor in the uppermost cell structure forms a bit line BL through the source-drain metal 1, and the source of the select transistor in the lowermost cell structure forms a plate line PL through the source-drain metal 1. The left and right columns of memory cells in the figure (each column is a memory composed of multiple memory cells) are respectively connected to different bit lines BL and different PL.

[0014] Figure 1 The memory shown can be fabricated using the integration method proposed in this invention. A detailed method diagram is shown below. Figures 2 to 7 The steps are as follows: First, a 50nm titanium nitride layer is deposited on the substrate as the board line (PL), then a 70nm silicon dioxide layer is deposited, followed by a 30nm tantalum layer as the word line (WL). This process of depositing silicon dioxide and tantalum is repeated seven times, followed by another 70nm silicon dioxide layer, and finally a 50nm titanium nitride layer as the bit line (BL). Figure 2 As shown.

[0015] Next, the active region is patterned using photolithography, and then the silicon dioxide, titanium nitride, and tantalum outside the active region are etched; such as Figure 3 As shown.

[0016] Next, the memory cell regions are patterned using photolithography, and then titanium nitride and tantalum are selectively etched laterally using dilute nitric acid and hydrogen peroxide; for example... Figure 4 As shown.

[0017] Next, annealing is performed in an oxygen atmosphere at a temperature of 350°C for half an hour, thereby forming tantalum oxide on the surface of the tantalum as the gate dielectric; Figure 5 As shown.

[0018] Next, 10nm indium tin oxide is deposited as the channel material; such as... Figure 6 As shown.

[0019] Next, 10nm hafnium zirconium oxide is deposited as a non-volatile dielectric material; such as... Figure 7 As shown.

[0020] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A three-dimensionally stackable nonvolatile memory integration method, the memory prepared by the integration method is composed of a plurality of cells stacked from bottom to top, each cell comprising a select transistor and a nonvolatile storage medium, the source and drain of the select transistor are both provided by the channel layer thereof, the gate end of the select transistor is composed of a gate metal and a gate dielectric, the source end of the select transistor simultaneously serves as the bottom electrode of the nonvolatile storage medium, the drain end of the select transistor simultaneously serves as the top electrode of the nonvolatile storage medium, and the source and drain of adjacent select transistors are connected together; along the direction perpendicular to the paper plane, the gate ends of the select transistors of the same row of cells are connected together through the gate metal to form a word line WL, in the direction parallel to the paper plane, different cells are located on different word lines WL; the drain end of the select transistor of the uppermost layer of cells forms a bit line BL through a source-drain metal, and the source end of the select transistor of the lowermost layer of cells forms a plate line PL through the source-drain metal; characterized in that, The specific steps of the integration method include: Step 1: sequentially depositing source-drain metal material, isolation layer material and gate metal material on the substrate, specifically, depositing a layer of source-drain metal material as a plate line PL, then depositing a layer of isolation layer material, then depositing a layer of gate metal material as a word line WL, then repeatedly depositing isolation layer material and gate metal material, and again depositing a layer of isolation layer material, then depositing a layer of source-drain metal material as a bit line BL, the number of layers of gate metal material is the number of repetitions of the unit structure in the memory structure; Step 2: defining an active region, specifically, patterning the active region by lithography, and then etching the isolation layer material, source-drain metal material and gate metal material outside the active region to form the active region; Step 3: forming a memory cell region, specifically, patterning the memory cell region by lithography, and then etching the gate metal material and source-drain metal material laterally; Step 4: forming a gate dielectric layer, specifically, annealing in an oxygen atmosphere to form an oxide layer on the surface of the gate metal as the gate dielectric; Step 5: forming a channel layer, specifically, depositing channel material; Step 6: forming a non-volatile dielectric layer, specifically, depositing non-volatile dielectric material.

2. The integration method of claim 1, wherein, The substrate in step 1 is a bare silicon wafer, or a silicon wafer on which front-end devices and circuits have been prepared; the isolation layer material is a dielectric material: silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide or porous silicon dioxide, the thickness of the deposited single layer of isolation layer material is between 10 nm and 500 nm, and the deposition method of the isolation layer material is PVD, CVD or epitaxy; the source-drain metal material is titanium nitride or tungsten, the thickness of the deposited single layer of source-drain metal material is between 10 nm and 500 nm; the gate metal material is tantalum or titanium, the thickness of the deposited single layer of gate metal material is between 1 nm and 500 nm.

3. The integration method of claim 1, wherein, The etching method in step 2 is reactive ion etching, ion beam etching or inductively coupled plasma.

4. The integration method of claim 1, wherein, The etching method in step 3 is wet etching, and the etching reagent is one or more of hot phosphoric acid, dilute nitric acid and hydrogen peroxide.

5. The integration method of claim 1, wherein, The channel layer material in step 5 is an oxide semiconductor material: indium-gallium-zinc oxide, indium tin oxide or stannous oxide, or a two-dimensional material: molybdenum disulfide or black phosphorus, and a semiconductor material: amorphous silicon or polycrystalline silicon, and the thickness of the channel layer material is between 1 nm and 500 nm.

6. The integration method of claim 1, wherein, The non-volatile dielectric layer material in step 6 is a ferroelectric material: hafnium-zirconium oxide, hafnium-lanthanum oxide or hafnium-aluminum oxide, or a resistive material: hafnium oxide or tungsten oxide, and a phase change material: GeSbTe, and the thickness of the non-volatile dielectric layer material is between 1 nm and 100 nm.

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