Resistor structure of semiconductor device and semiconductor device including resistor structure

Abstract

The invention relates to a resistor structure of a semiconductor device and a semiconductor device including the resistor structure. A resistor structure of a semiconductor device according to an embodiment may include: a semiconductor substrate including a device semiconductor layer and a resistor semiconductor layer; first and second device isolation regions disposed on the device semiconductor layer and the resistor semiconductor layer, respectively; and a resistor polysilicon layer disposed on the first resistor trench in which a portion of the second device isolation region is removed.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a resistor structure of a semiconductor device, a semiconductor device including the same, and a method of manufacturing the same. For example, embodiments relate to a polysilicon resistor structure of a semiconductor device, a semiconductor device including the same, and a method of manufacturing the same. BACKGROUND

[0002] An integrated circuit device is a functional device having a complete circuit function by integrating a large number of active devices and passive devices in a super small size into a single semiconductor substrate, and has a non-detachable structure, and is used in various industrial fields.

[0003] These integrated circuit devices are circuit devices in which transistors, diodes, capacitors, and resistors are densely integrated, and various sizes of resistors are required according to the purpose of electronic equipment in which the integrated circuit device is used.

[0004] Since a resistor device requires a greater resistance than a wiring structure of an integrated circuit device, the resistor device is generally formed on a device isolation film while a gate structure of a transistor is formed in an active region of a semiconductor substrate. For example, since a polysilicon material used in a manufacturing process of a semiconductor device can be doped with various impurities to control resistance, a gate electrode of a transistor and a resistor device can be simultaneously formed using polysilicon.

[0005] On the other hand, since resistance is proportional to the length of polysilicon, a certain length must be secured to implement a high-resistance polysilicon resistor. For example, in the related art, a polysilicon resistor structure having a length of about 1.4 μm and a thickness of about 0.2 μm is inevitably required to implement a high-resistance polysilicon resistor.

[0006] Therefore, in the related art, there is a technical contradiction problem in that it is difficult to implement a super miniaturization of a semiconductor device to implement a high-resistance polysilicon resistor. SUMMARY

[0007] Therefore, the disclosure relates to a resistor structure of a semiconductor device, a semiconductor device including the same, and a method of manufacturing the same, which substantially obviates one or more problems due to limitations and disadvantages of the above-described background art.

[0008] One of the technical problems of the embodiments is to solve the technical problem in that it is difficult to implement a super miniaturization of a semiconductor device when implementing a high-resistance polysilicon resistor. The technical problem of the embodiments is not limited to the technical problem described in this section but includes a technical problem understood from the specification of the disclosure.

[0009] The resistor structure of the semiconductor device according to the embodiment can include a semiconductor substrate including a device semiconductor layer and a resistor semiconductor layer, first and second device isolation regions disposed on the device semiconductor layer and the resistor semiconductor layer, respectively, and a resistor polysilicon layer disposed on a first resistor trench in which a portion of the second device isolation region is removed.

[0010] In addition, the embodiment can further include a resistor insulating layer disposed under the resistor polysilicon layer on the first resistor trench.

[0011] The resistor polysilicon layer can include a trench polysilicon layer disposed inside the first resistor trench and first and second polysilicon layers disposed on the second device isolation region, respectively.

[0012] A first depth of the first resistor trench can be at least 1 / 2 of a depth of the second device isolation region.

[0013] The resistor polysilicon layer can include a resistor ion implant region.

[0014] The resistor ion implant region can be in contact with the resistor insulating layer.

[0015] In addition, a horizontal width of the second device isolation region can be greater than a horizontal width of the first device isolation region.

[0016] In addition, a depth of the first device isolation region can be the same as a depth of the second device isolation region.

[0017] In addition, a material of the resistor insulating layer can be the same as a material of a gate insulating layer.

[0018] In addition, the resistor insulating layer can be spaced apart from the resistor semiconductor layer.

[0019] In addition, the resistor structure of the semiconductor device according to the embodiment can include a semiconductor substrate including a device semiconductor layer and a resistor semiconductor layer, first and second device isolation regions disposed on the device semiconductor layer and the resistor semiconductor layer, respectively, a resistor insulating layer disposed on a second resistor trench in which a portion of the second device isolation region is removed to expose a portion of the resistor semiconductor layer, and a resistor polysilicon layer disposed on the resistor insulating layer.

[0020] The resistor polysilicon layer can include a trench polysilicon layer disposed inside the second resistor trench and first and second polysilicon layers disposed on the second device isolation region, respectively.

[0021] A second depth of the second resistor trench can be equal to a depth of the second device isolation region.

[0022] The resistor polysilicon layer can include a resistor ion implantation region.

[0023] The resistor ion implantation region can be in contact with the resistor insulating layer.

[0024] Further, a horizontal width of the second device isolation region can be greater than a horizontal width of the first device isolation region.

[0025] Further, a depth of the first device isolation region can be the same as a depth of the second device isolation region.

[0026] Further, a material of the resistor insulating layer can be the same as a material of the gate insulating layer.

[0027] In addition, a second depth of the second resistor trench can be greater than a thickness of the second device isolation region.

[0028] In addition, the semiconductor device according to the embodiment can include the resistor device structure of any one of the semiconductor devices.

[0029] According to the embodiment, there is a technical effect of implementing a high-resistance polysilicon resistor while being able to implement a super-fine semiconductor device.

[0030] For example, according to the embodiment, after the first resistor trench having a depth of at least 1 / 2 of a depth L of the second device isolation region is formed, the resistor insulating layer and the resistor polysilicon layer can be formed on the first resistor trench (see FIG. 1A and FIG. 1B ).

[0031] Accordingly, according to the embodiment, by forming the resistor polysilicon layer on the first resistor trench formed to a depth of at least 1 / 2 of the depth L of the second device isolation region, it is possible to maximize a length of the resistor polysilicon layer without enlarging a size of the semiconductor device. Accordingly, there is a technical effect of implementing a high-resistance polysilicon resistor while being able to implement a super-fine semiconductor device.

[0032] In addition, according to the embodiment, after the first resistor trench is formed, it is possible to improve a surface roughness of the first resistor trench through a process of forming the resistor insulating layer, thereby preventing roughness from occurring in the resistor polysilicon layer formed later, thereby providing a technical effect of securing a stable resistance value of the resistor device.

[0033] In addition, according to the second embodiment, after a portion of the resistor semiconductor layer is exposed through the second resistor trench by etching, the resistor insulating layer and the resistor polysilicon layer can be formed on the second resistor trench (see FIG. 2A and FIG. 2B ).

[0034] Accordingly, according to the second embodiment, after the resistor insulating layer is formed on the second resistor trench formed to a depth sufficient to expose a portion of the resistor semiconductor layer, the resistor polysilicon layer can be formed on the resistor insulating layer.

[0035] According to the second embodiment, the length of the resistor polysilicon layer can be maximized without causing an electrical short due to the resistor insulating layer. Accordingly, there is a special technical effect in that a super-fine semiconductor device can be implemented while implementing a high-resistance polysilicon resistor.

[0036] In addition, according to the embodiment, when forming a polysilicon resistor pattern having the same resistance length, there is an effect in that a chip area of a semiconductor device can be reduced when the embodiment is applied.

[0037] Technical effects of the embodiments are not limited to the technical effects described in this section, and include technical effects understood from the description of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this disclosure, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0039] In the drawings:

[0040] FIG. 1A is a cross-sectional view of a semiconductor device 1001 including a polysilicon resistor structure according to the first embodiment.

[0041] FIG. 1B is a cross-sectional view of a portion of a manufacturing process of a semiconductor device 1001 including a polysilicon resistor structure according to the first embodiment.

[0042] FIG. 2A is a cross-sectional view of a semiconductor device 1002 including a polysilicon resistor structure according to the second embodiment.

[0043] FIG. 2B is a cross-sectional view of a portion of a manufacturing process of a semiconductor device 1002 including a polysilicon resistor structure according to the second embodiment.

[0044] FIG. 3 、 FIG. 4A and FIG. 4B 、 FIG. 5 to FIG. 8 is a cross-sectional view of a manufacturing process of a semiconductor device including a polysilicon resistor structure according to the embodiment. DETAILED DESCRIPTION

[0045] Hereinafter, aspects disclosed in the specification will be described in detail with reference to the accompanying drawings. In the following description of the aspects disclosed in the specification, the suffix "module" or "part" is used to give a name to a component of a description, and does not have a different meaning or role from the other components. Also, the accompanying drawings are intended to facilitate the easy understanding of aspects disclosed in the specification, and the technical idea disclosed in the specification is not limited to the accompanying drawings. Also, when an element such as a layer, an area, or a substrate is present "on" another element, it includes that the element can be directly on the other element, or that there can be another intervening element therebetween.

[0046] In the specification or claims, the meaning of "the element A includes at least one of a, b, and / or c" can include ① when the element A includes the element a, ② when the element A includes the element b, ③ when the element A includes the element c, ④ when the element A includes the elements a and b, ⑤ when the element A includes the elements b and c, ⑥ when the element A includes the elements a and c, and ⑦ when the element A includes all of the elements a, b, and c.

[0047] Unless the context clearly indicates otherwise, the singular expression includes the plural expression as well as the singular expression. For example, the meaning of "the element A includes one structure" can include the meaning of "the element A includes one or more structures".

[0048] (Embodiment)

[0049] FIG. 1A is a cross-sectional view of a semiconductor device 1001 including a polysilicon resistor structure according to a first embodiment. FIG. 1B is a cross-sectional view of a part of a manufacturing process of a semiconductor device 1001 including a polysilicon resistor structure according to a first embodiment. Hereinafter, the "first embodiment" can be abbreviated as "example".

[0050] The semiconductor device 1001 including a polysilicon resistor structure according to the first embodiment can include a semiconductor substrate including a device semiconductor layer 110 and a resistor semiconductor layer 210.

[0051] The device semiconductor layer 110 can be a semiconductor layer on which an active device such as a transistor is formed, and the resistor semiconductor layer 210 can be a semiconductor layer on which a passive device such as a resistor is formed.

[0052] In addition, the embodiment can include a first device isolation region 120 and a second device isolation region 220 disposed on the device semiconductor layer 110 and the resistor semiconductor layer 210 of the semiconductor substrate, respectively.

[0053] The horizontal width of the second device isolation region 220 can be greater than the horizontal width of the first device isolation region 120, but is not limited thereto.

[0054] In addition, the first device isolation region 120 and the second device isolation region 220 can have the same depth, but are not limited thereto.

[0055] For example, the first device isolation region 120 and the second device isolation region 220 can be formed with a predetermined depth L, but are not limited thereto.

[0056] For example, referring to FIG. 1B , the embodiment can include a first resistor trench RT1 formed by partially removing the second device isolation region 220.

[0057] In the first embodiment, the first depth L1 of the first resistor trench RT1 can be at least 1 / 2 of the depth L of the second device isolation region 220.

[0058] Again referring to FIG. 1A , the embodiment can form the first resistor trench RT1 at at least 1 / 2 of the depth L of the second device isolation region 220, and then form the resistor insulating layer 230 and the resistor polysilicon layer 240 on the first resistor trench RT1.

[0059] Accordingly, according to the embodiment, by forming the resistor polysilicon layer 240 on the first resistor trench RT1 formed with a depth of at least half of the depth L of the second device isolation region 220, it is possible to maximize the length of the resistor polysilicon layer 240 without expanding the size of the semiconductor device, and thus, has the technical effect of realizing a high-resistance polysilicon resistor while being able to realize a super-fine semiconductor device.

[0060] In addition, according to internal research, it has been researched that the surface of the first resistor trench RT1 can be roughened by etching the second device isolation region 220 with a deep depth to form the first resistor trench RT1. It has been researched that roughness can be transferred to the resistor polysilicon layer 240 formed later and cause a resistance change of the resistor device.

[0061] According to the embodiment, after the first resistor trench RT1 is formed, the surface roughness of the first resistor trench RT1 can be improved by a process of forming the resistor insulating layer 230. Accordingly, has the technical effect of preventing roughness from occurring in the resistor polysilicon layer 240 formed thereafter, thereby securing a stable resistance value of the resistor device.

[0062] In addition, the embodiment can include a gate insulating layer 130 and a gate electrode 140 disposed on the device semiconductor layer 110 between the first device isolation regions 120.

[0063] The gate insulating layer 130 can be formed of a thermal oxide layer or a deposited oxide layer, but is not limited thereto. The gate electrode 140 can be formed of polysilicon, but is not limited thereto.

[0064] In addition, the embodiment can form the resistor insulating layer 230 and the resistor polysilicon layer 240 on the first resistor trench RT1 of the resistor semiconductor layer 210. The resistor insulating layer 230 can be formed of the same material as the gate insulating layer 130, but is not limited thereto.

[0065] The resistor polysilicon layer 240 can include a trench polysilicon layer 242 disposed within the first resistor trench RT1, and a first polysilicon layer 241 and a second polysilicon layer 243 disposed on the second device isolation region 220, respectively.

[0066] In addition, the embodiment can include the first ion implantation region 160 on the device semiconductor layer 110 on both sides of the gate electrode 140.

[0067] The device semiconductor layer 110 can be formed as an N-MOS region or a P-MOS region.

[0068] For example, after forming a p-type well (not shown) in the device semiconductor layer 110, n-type dopant ions can be implanted into the p-type well to form the first ion implantation region 160. At this time, LDD ion implantation can also be performed on the resistor polysilicon layer 240.

[0069] In addition, the embodiment can include the first spacer 150 disposed on the gate electrode 140 side of the device semiconductor layer 110, and a source region 170 and a drain region 170 formed on the device semiconductor layer 110.

[0070] In addition, the embodiment can include a third resistor insulating layer 255 and a second spacer 250 in the resistor polysilicon layer 240 on the resistor semiconductor layer 210, and a resistor ion implantation region 270 formed in a predetermined second ion implantation SD.

[0071] For example, the second spacer 250 can be formed on the first polysilicon layer 241 and the second polysilicon layer 243 of the resistor polysilicon layer 240, and the third resistor insulating layer 255 can be formed on the trench polysilicon layer 242, after which the resistor ion implantation region 270 can be formed on the first polysilicon layer 241 and the second polysilicon layer 243 by the second ion implantation SD (see FIG. 7 ).

[0072] Further, the embodiments can include a first silicide 181 disposed on the source region 170 and the drain region 170 of the device region and a second silicide 182 disposed on the gate electrode 140. Further, a third silicide 283 can be formed on the resistor ion implant region 270 of the resistor polysilicon layer 240. The first silicide 181 to the third silicide 283 can be, but are not limited to, NiSi or CoSi2.

[0073] Further, after forming the interlayer insulating layer 310, an opening process is performed to remove a portion of the interlayer insulating layer, and a first wiring 191 and a first metal electrode 192 can be sequentially formed on the exposed first silicide 181. Further, a second wiring (not shown) and a second metal electrode (not shown) can be sequentially formed on the second silicide 182. Further, a third wiring 291 and a third metal electrode 292 can be sequentially formed on the third silicide 283.

[0074] According to the embodiments, there is a technical effect of being able to realize a super-fine semiconductor device while realizing a high-resistance polysilicon resistor.

[0075] For example, according to the embodiments, after forming the first resistor trench RT1 having a depth of at least 1 / 2 of the depth L of the second device isolation region 220, a resistor insulating layer 230 and a resistor polysilicon layer 240 can be formed on the first resistor trench RT1 (see FIG. 4B). FIG. 1A and FIG. 1B ).

[0076] Accordingly, according to the embodiments, by forming the resistor polysilicon layer 240 on the first resistor trench RT1 formed to a depth of at least 1 / 2 of the depth L of the second device isolation region 220, it is possible to maximize the length of the resistor polysilicon layer 240 without enlarging the size of the semiconductor device, and thus, there is a technical effect of being able to realize a super-fine semiconductor device while realizing a high-resistance polysilicon resistor.

[0077] Further, according to the present embodiments, after forming the first resistor trench RT1, by the process of forming the resistor insulating layer 230, it is possible to improve the roughness of the surface of the first resistor trench RT1, thereby preventing the occurrence of roughness in the resistor polysilicon layer 240 formed subsequently, thereby providing a technical effect of securing a stable resistance value of the resistor device.

[0078] Next, FIG. 2A is a cross-sectional view of a semiconductor device 1002 including a polysilicon resistor structure according to a second embodiment. FIG. 2B is a cross-sectional view of a part of a manufacturing process of a semiconductor device 1002 including a polysilicon resistor structure according to a second embodiment.

[0079] The second embodiment can employ the technical features of the first embodiment, and the main features of the second embodiment will be described below.

[0080] First, referring to FIG. 2B In the second embodiment, after etching to expose a portion 210B of the resistor semiconductor layer through the second resistor trench RT2, a resistor insulating layer 230 and a resistor polysilicon layer 240 can be formed on the second resistor trench RT2 (see FIG. 2A ).

[0081] Accordingly, according to the second embodiment, the resistor polysilicon layer 240 can be formed on the resistor insulating layer 230 after the resistor insulating layer 230 is formed on the second resistor trench RT2 formed to a depth capable of exposing the portion 210B of the resistor semiconductor layer.

[0082] According to the second embodiment, the length of the resistor polysilicon layer 240 can be maximized without causing an electrical short due to the resistor insulating layer 230. Accordingly, there is a special technical effect capable of implementing a high-resistance polysilicon resistor while also implementing an ultra-fine semiconductor device.

[0083] Further, through the process of forming the second resistor trench RT2 by etching the second device isolation region 220 to a deep depth, the surface of the second resistor trench RT2 can become rough, and a problem of roughness being transferred to the resistor polysilicon layer 240 formed later and causing resistance fluctuation of the resistor device has been researched.

[0084] According to the embodiment, after the second resistor trench RT2 is formed, the roughness of the surface of the second resistor trench RT2 can be improved through the process of forming the resistor insulating layer 230, and thus roughness can be prevented in the resistor polysilicon layer 240 formed later, thereby providing a special technical effect capable of securing a stable resistance value of the resistor device.

[0085] FIG. 3 to FIG. 8 is a cross-sectional view of a manufacturing process of a semiconductor device including a polysilicon resistor structure according to an embodiment.

[0086] First, referring to FIG. 3 A predetermined semiconductor substrate can be prepared. The semiconductor substrate can include a device semiconductor layer 110 and a resistor semiconductor layer 210. For example, the semiconductor substrate can include the device semiconductor layer 110 and the resistor semiconductor layer 210, but is not limited thereto. The device semiconductor layer 110 can be a semiconductor layer on which an active device such as a transistor is formed, and the resistor semiconductor layer 210 can be a semiconductor layer on which a passive device such as a resistor device is formed.

[0087] The first device isolation region 120 and the second device isolation region 220 can be formed on the device semiconductor layer 110 and the resistor semiconductor layer 210 of the semiconductor substrate, respectively.

[0088] The first device isolation region 120 and the second device isolation region 220 can form STI (Shallow Trench Isolation), but are not limited thereto.

[0089] For example, the first trench (not shown) and the second trench (not shown) can be formed by removing a portion of the device semiconductor layer 110 and a portion of the resistor semiconductor layer 210, respectively, and then the first trench and the second trench can be deposited with an oxide layer or the like to form the first device isolation region 120 and the second device isolation region 220, but are not limited thereto.

[0090] The horizontal width of the second device isolation region 220 can be greater than the horizontal width of the first device isolation region 120, but is not limited thereto.

[0091] The depths of the first device isolation region 120 and the second device isolation region 220 can be the same, but are not limited thereto.

[0092] For example, the first device isolation region 120 and the second device isolation region 220 can be formed with a predetermined depth L, but are not limited thereto.

[0093] Next, referring to FIG. 4A A portion of the second device isolation region 220 can be removed to form the first resistor trench RT1. FIG. 4A The first resistor trench RT1 can correspond to FIG. 1A of the first embodiment.

[0094] In the first embodiment, the first depth L1 of the first resistor trench RT1 can be at least 1 / 2 of the depth L of the second device isolation region 220.

[0095] According to the embodiment, after the first resistor trench RT1 is formed to at least 1 / 2 of the depth L of the second device isolation region 220, the resistor insulating layer 230 and the resistor polysilicon layer 240 can be formed on the first resistor trench RT1 (see FIG. 1A ).

[0096] Accordingly, according to the embodiment, by forming the resistor polysilicon layer 240 on the first resistor trench RT1 having a depth of at least 1 / 2 of the depth L of the second device isolation region 220, the length of the resistor polysilicon layer 240 can be maximized without expanding the size of the semiconductor device, and thus, has the technical effect of realizing a high-resistance polysilicon resistor while being able to realize a super-fine semiconductor device.

[0097] In addition, according to internal research, the surface of the first resistor trench RT1 can be roughened by a process of etching the second device isolation region 220 at a deep depth to form the first resistor trench RT1, and it has been researched that the roughness is transferred to the resistor polysilicon layer 240 formed later, thereby causing a resistance variation of the resistor device.

[0098] According to the present embodiment, after the first resistor trench RT1 is formed, the surface roughness of the first resistor trench RT1 can be improved by a process of forming the resistor insulating layer 230, thereby preventing the roughness from occurring in the resistor polysilicon layer 240 formed later, thereby providing a technical effect of securing a stable resistance value of the resistor device.

[0099] Next, referring to FIG. 4B , the second device isolation region 220 can be partially removed to form the second resistor trench RT2. FIG. 4B The second resistor trench RT2 can correspond to FIG. 2A the second embodiment illustrated in FIG. 2B.

[0100] In the second embodiment, the second depth L2 of the second resistor trench RT2 can be equal to the depth L of the second device isolation region 220.

[0101] In the second embodiment, a portion 210B of the resistor semiconductor layer can be exposed through the second resistor trench RT2.

[0102] According to the second embodiment, after the etching to expose the portion 210B of the resistor semiconductor layer through the second resistor trench RT2, the resistor insulating layer 230 and the resistor polysilicon layer 240 can be formed on the second resistor trench RT2 (see FIG. 2A ).

[0103] Accordingly, according to the second embodiment, after the resistor insulating layer 230 is formed on the second resistor trench RT2 formed at a depth capable of exposing the portion 210B of the resistor semiconductor layer, the resistor polysilicon layer 240 can be formed on the resistor insulating layer 230.

[0104] According to the second embodiment, the length of the resistor polysilicon layer 240 can be maximized without causing an electrical short circuit due to the resistor insulating layer 230. Accordingly, there is a special technical effect capable of implementing a high-resistance polysilicon resistor while implementing a super-fine semiconductor device.

[0105] Hereinafter, a manufacturing process will be described based on the structure of FIG. 4B the second embodiment, but the embodiments are not limited thereto.

[0106] Referring to FIG. 5The gate insulating layer 130 and the gate electrode 140 can be formed on the device semiconductor layer 110 located between the first device isolation regions 120.

[0107] The gate insulating layer 130 can be formed as a thermal oxide layer or a deposited oxide layer, but is not limited thereto. The gate electrode 140 can be formed as polysilicon, but is not limited thereto.

[0108] The gate insulating layer 130 can be formed with a thickness of about to , but is not limited thereto.

[0109] At this time, the resistor insulating layer 230 and the resistor polysilicon layer 240 can be formed on the second resistor trench RT2 of the resistor semiconductor layer 210. The resistor insulating layer 230 can be formed of the same material as the gate insulating layer 130, but is not limited thereto.

[0110] The resistor polysilicon layer 240 can include a trench polysilicon layer 242 disposed within the second resistor trench RT2, and a first polysilicon layer 241 and a second polysilicon layer 243 disposed on the second device isolation region 220, respectively.

[0111] According to the second embodiment, after etching to expose a portion 210B of the resistor semiconductor layer through the second resistor trench RT2, the resistor insulating layer 230 and the resistor polysilicon layer 240 can be formed on the second resistor trench RT2.

[0112] Accordingly, according to the second embodiment, after the resistor insulating layer 230 is formed on the second resistor trench RT2 formed to a depth exposing the portion 210B of the resistor semiconductor layer, the resistor polysilicon layer 240 can be formed on the resistor insulating layer 230.

[0113] According to the second embodiment, the length of the resistor polysilicon layer 240 can be maximized without causing an electrical short due to the resistor insulating layer 230. Accordingly, there is a special technical effect capable of implementing a high-resistance polysilicon resistor while implementing a super-fine semiconductor device.

[0114] In addition, a problem was studied in which a process of forming the second resistor trench RT2 by etching the second device isolation region 220 to a deep depth can roughen the surface of the second resistor trench RT2, and the roughness can be transferred to the resistor polysilicon layer 240 formed thereafter, thereby causing a resistance change of the resistor device.

[0115] According to embodiments, after the second resistor trench RT2 is formed, the roughness of the surface of the second resistor trench RT2 can be improved by a process of forming the resistor insulating layer 230, thus having a special technical effect of preventing the occurrence of roughness in the resistor polysilicon layer 240 formed thereafter, thereby ensuring a stable resistance value of the resistor device.

[0116] Next, referring to FIG. 2B, FIG. 6 A first ion implantation LDD can be performed on the device semiconductor layer 110 on both sides of the gate electrode 140 to form a first ion implantation region 160.

[0117] The device semiconductor layer 110 can be formed as an N-MOS region or a P-MOS region.

[0118] For example, after a p-type well (not shown) is formed in the device semiconductor layer 110, n-type dopant ions can be implanted into the p-type well to form the first ion implantation region 160. At this time, LDD ion implantation can also be performed on the resistor polysilicon layer 240.

[0119] Next, referring to FIG. 2B, FIG. 7 After the first spacer 150 as an insulating layer or the like is formed on the side of the gate electrode 140 of the device semiconductor layer 110, a second ion implantation SD can be performed to form a source region 170 and a drain region 170.

[0120] The doping concentration of the second ion implantation SD can be higher than the doping concentration of the first ion implantation LDD, but is not limited thereto.

[0121] For example, the doping of the second ion implantation SD can be a high-concentration n-type dopant ion implantation process, and the high-concentration n-type dopant can be doped at a concentration of 5E15 / cm 2 to 8E15 / cm 2 with an energy of about 50 keV to 80 keV, but is not limited thereto.

[0122] Further, after the second spacer 250 and the third resistor insulating layer 255 are formed on the resistor polysilicon layer 240 on the resistor semiconductor layer 210, a resistor ion implantation region 270 can be formed by the second ion implantation SD.

[0123] For example, after the second spacer 250 is formed on the first and second polysilicon layers 241 and 243 of the resistor polysilicon layer 240 and the third resistor insulating layer 255 is formed on the trench polysilicon layer 242, the resistor ion implantation region 270 can be formed on the first and second polysilicon layers 241 and 243 by the second ion implantation SD.

[0124] The resistor ion implantation region 270 can be in contact with the resistor insulating layer 230, but is not limited thereto.

[0125] Next, as shown in FIG. 1C, a first silicide 181 can be formed on the source region 170 and the drain region 170 of the device region. A second silicide 182 can be formed on the gate electrode 140. FIG. 8

[0126] A third silicide 283 can be formed on the resistor ion implantation region 270 of the resistor polysilicon layer 240. The first silicide 181 to the third silicide 283 can be NiSi or CoSi2, but are not limited thereto.

[0127] After the interlayer insulating layer 310 is formed, an opening process is performed to remove a portion of the interlayer insulating layer, and a first wiring 191 and a first metal electrode 192 are sequentially formed on the exposed first silicide 181. Further, a second wiring (not shown) and a second metal electrode (not shown) are sequentially formed on the second silicide 182.

[0128] Further, a third wiring 291 and a third metal electrode 292 are sequentially formed on the third silicide 283, thereby forming a semiconductor device having a resistor device according to the embodiment.

[0129] Although the above description focuses on the embodiment, this is merely an example and does not limit the embodiment, and a person having ordinary knowledge in the field to which the embodiment belongs will be able to understand that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiment. For example, each of the constituent elements specifically shown in the embodiment can be modified to be implemented. And the differences related to these modifications and applications should be interpreted as being included in the scope of the embodiment set forth in the appended claims.​

Claims

1. A resistor structure of a semiconductor device, the resistor structure of a semiconductor device comprising: a semiconductor substrate including a device semiconductor layer and a resistor semiconductor layer; a first device isolation region and a second device isolation region disposed on the device semiconductor layer and the resistor semiconductor layer, respectively; and a resistor polysilicon layer disposed on a first resistor trench in which a portion of the second device isolation region is removed.

2. The resistor structure of a semiconductor device according to claim 1, further comprising a resistor insulating layer disposed below the resistor polysilicon layer on the first resistor trench.

3. The resistor structure of a semiconductor device according to claim 1, wherein, the resistor polysilicon layer includes a trench polysilicon layer disposed within the first resistor trench and a first polysilicon layer and a second polysilicon layer disposed on the second device isolation region, respectively.

4. The resistor structure of a semiconductor device according to claim 1, wherein, a first depth of the first resistor trench is at least 1 / 2 of a depth of the second device isolation region.

5. The resistor structure of a semiconductor device according to claim 2, wherein, the resistor polysilicon layer includes a resistor ion implant region.

6. The resistor structure of a semiconductor device according to claim 5, wherein, the resistor ion implant region is in contact with the resistor insulating layer.

7. A resistor structure of a semiconductor device, the resistor structure of a semiconductor device comprising: a semiconductor substrate including a device semiconductor layer and a resistor semiconductor layer; a first device isolation region and a second device isolation region disposed on the device semiconductor layer and the resistor semiconductor layer, respectively; a resistor insulating layer disposed on a second resistor trench in which a portion of the second device isolation region is removed to expose a portion of the resistor semiconductor layer; and a resistor polysilicon layer disposed on the resistor insulating layer. the resistor polysilicon layer includes a trench polysilicon layer disposed within the second resistor trench and a first polysilicon layer and a second polysilicon layer disposed on the second device isolation region.

8. The resistor structure of a semiconductor device according to claim 7, wherein, the resistor polysilicon layer includes a resistor ion implant region, and 9. The resistor structure of a semiconductor device according to claim 7, wherein, wherein the resistor ion implant region is in contact with the resistor insulating layer.

10. A semiconductor device comprising the resistor structure of a semiconductor device according to any one of claims 1 to 9. ​

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