Memcapacitive device with multi-level capacitance conversion and preparation method thereof

Abstract

The application discloses a memcapacitive device with multi-stage capacitance conversion and a preparation method thereof, and belongs to the technical field of semiconductor devices. The memcapacitive device has an nn heterostructure, and comprises a bottom electrode layer, a wide-bandgap n-type semiconductor layer, an n-type metal oxide semiconductor layer and a plurality of top electrode layers which are sequentially grown on the surface of a substrate. The nn heterostructure constructed by the application reduces the dependence on the electrical conductivity of the material and increases the material selection of the memcapacitive device. The memcapacitive device can cause the change of the width of the potential barrier region of the memcapacitive device by adjusting the size and frequency of the scanning voltage, thereby realizing the memory function of multi-stage capacitance conversion, and solving the problems of power consumption and crosstalk that the two-terminal memory device faces in integration. The application also provides a preparation method which is simple in preparation process, low in cost and beneficial to batch production of the memcapacitive device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and specifically to a memory capacitor device with multi-level capacitance conversion and its fabrication method. Background Technology

[0002] Memristors, as an emerging storage device, possess dynamic resistance that adjusts with the flow of charge, inherent self-learning capabilities, and the ability to combine storage and computation. These characteristics make memristor-based computing networks poised to overcome the data transfer bottlenecks of traditional von Neumann architectures, potentially enabling high-efficiency, high-parallelism computing systems. Furthermore, current memristor integration densities have reached 10 GB / cm². 2 Its density is close to that of neurons in the human brain, and its operating frequency can reach 200MHz, far exceeding the frequency of human brain electrical activity, about 10 times faster. 6 Therefore, memristors are widely regarded as ideal candidate devices for building neuromorphic computing systems, promising to accomplish complex artificial intelligence computing tasks with fewer hardware resources and higher processing speeds.

[0003] However, numerous studies have revealed that the power consumption of individual memristors in practical applications is generally on the order of magnitude high. Neuromorphic computing, as a data-intensive computing paradigm, is extremely sensitive to system power consumption; therefore, achieving ultra-low power consumption has become one of the core research goals in this field. Based on this, another type of memory element—the memcell—through a capacitance control mechanism, exhibits unique advantages. It can achieve non-destructive reading of the capacitance state under zero bias conditions, possessing extremely low static power consumption and good signal retention capabilities. Simultaneously, utilizing the open-circuit characteristics of the capacitor itself under DC conditions, the memcell can effectively alleviate crosstalk problems faced by two-terminal structure devices during integration, which is beneficial for constructing high-density, low-power neuromorphic computing networks. Currently, most memcells rely on the polarization reversal of ferroelectric materials to control the capacitance state, resulting in relatively limited material systems. To address this, Chinese patent application CN19677186A designed and developed a PN structure memcell device, and Chinese patent application CN11857407A designed and developed a MIS structure memcell device, achieving continuous control of the device capacitance by the electric field. However, the electric field of these two structures has a small range of regulation over the capacitor and a relaxation process, which makes it impossible for the electric field to effectively regulate the capacitance state of the device. It can only be used to regulate the analog signal of the capacitor.

[0004] Therefore, developing a novel memory capacitor structure and material capable of multi-level capacitance state transitions to ensure that the device exhibits multi-level transition characteristics under different electric field stimuli is of great significance for expanding the range of material choices and promoting the practical development of digital memory capacitor devices. Summary of the Invention

[0005] To address the shortcomings of existing memory capacitor devices, such as the limited range of electric field control over capacitance and the inability of the electric field to effectively regulate the capacitance state of the device, the first objective of this invention is to provide a memory capacitor device with multi-level capacitance conversion. This memory capacitor device constructs an n-level heterostructure between inert metal electrodes, and by adjusting the magnitude and frequency of the scanning voltage, the width of the barrier region of the memory capacitor device can be changed, thereby achieving effective and stable control of the electric field over the capacitance state of the device.

[0006] The second objective of this invention is to provide a method for fabricating a memory capacitor device with multi-level capacitance conversion, which is simple, low-cost, and highly reliable.

[0007] To achieve the above-mentioned technical objectives, the present invention provides a memory capacitor device with multi-level capacitance conversion, having an n-type heterostructure, including a bottom electrode layer, a wide bandgap n-type semiconductor layer, an n-type metal oxide semiconductor layer and several top electrode layers sequentially grown on the substrate surface.

[0008] The memory capacitor device of this invention can effectively control the capacitive state of the device through an electric field and has the advantage of multi-level and stable capacitance switching. The key lies in the construction of an n-type heterostructure by setting a wide-bandgap n-type semiconductor layer and an n-type metal-oxide-semiconductor layer between the bottom electrode layer and the top electrode layer. Specifically, the wide-bandgap n-type semiconductor layer serves as a barrier modulation layer, while the n-type metal-oxide-semiconductor layer serves as a charge storage and capacitance modulation layer. Due to the difference in their band structures, an n-type heterostructure is formed at the interface, which is beneficial for the directional migration and storage of charges under the influence of an electric field. Under the influence of an electric field, the migration of oxygen ions and electrons in the overall bilayer thin film can be efficiently excited, thereby adjusting the width, height, and capacitance of the barrier region formed on one side of the n-type metal-oxide-semiconductor layer, thus achieving effective control of the device's capacitive state.

[0009] As a preferred embodiment, the wide bandgap n-type semiconductor layer has a bandgap width of 4.8~4.9 eV, and the bandgap width between the n-type metal-oxide-semiconductor layers is 3.3~3.4 eV. Within the bandgap range of this invention, it is more advantageous to form an adjustable barrier region, enabling multi-level capacitance switching.

[0010] As a preferred embodiment, the wide-bandgap n-type oxide semiconductor layer material is Ga2O3, with a thickness of 50-100 nm. This thickness range effectively ensures electron transport between the bottom electrode and the n-type metal oxide semiconductor layer. Further, the thickness is 80-90 nm, and even further, it is 80 nm.

[0011] As a preferred embodiment, the n-type metal-oxide-semiconductor layer material is ZnO, with a thickness of 100-200 nm. This thickness range effectively ensures control over the width of the barrier region, thereby enabling a wide range of capacitance modulation by the electric field. Further, the thickness is 100-150 nm, and even further, it is 100 nm.

[0012] Experiments revealed that when the wide-bandgap n-type oxide semiconductor layer material is Ga2O3 and the n-type metal oxide semiconductor layer material is ZnO, due to the bandgap bandwidth of Ga2O3 (approximately 4.9 eV) and ZnO (approximately 3.37 eV), and their respective band structure characteristics, an n-type heterostructure is formed at their interface. An electron accumulation region forms on the Ga2O3 side, while an electron depletion region (barrier region) forms on the ZnO side, giving the device capacitive characteristics. Under a strong electric field, the bound charges in the barrier region can trap electrons or oxygen ions, completing the charge storage and release process, and achieving multi-level conversion of the device's barrier capacitance. Furthermore, Ga2O3 and ZnO possess good lattice compatibility, thus their combination can form a memory capacitor device with optimal overall performance.

[0013] The memory device of the present invention can change the width of the barrier region of the memory device by adjusting the magnitude and frequency of the scanning voltage during use, thereby realizing the memory function of multi-level capacitance conversion.

[0014] The memory capacitor of the present invention maintains stability in the low capacitance state and exhibits a stepped distribution in the high capacitance state within the voltage amplitude range of 3V to 5V and the frequency range of 30 to 300 kHz.

[0015] As a preferred embodiment, the substrate is any one of sapphire, quartz, copper foil, and silicon, with a thickness of 10~2000μm. The substrate material of this invention can be either rigid or flexible, offering broad applicability. Furthermore, by selecting appropriate substrate materials and thicknesses, the temperature resistance during photoelectric testing can be improved.

[0016] As a preferred embodiment, the bottom electrode layer material is metallic Ni or Au, and its thickness is 100~200 nm. Further, the bottom electrode layer material is metallic Ni.

[0017] As a preferred embodiment, the top electrode layer material is metallic Ni or Au, and is cylindrical with a diameter of 10~300μm and a thickness of 80~100nm. Further, the number of top electrode layer materials is greater than or equal to 3, and the multiple top electrode layer materials are distributed in a circular array.

[0018] Furthermore, the bottom electrode layer material and the top electrode layer material are the same.

[0019] This invention also provides a method for fabricating a memory capacitor device with multi-level capacitance conversion, comprising the following steps:

[0020] S1 is deposited on the cleaned and pretreated substrate surface using magnetron sputtering to obtain the bottom electrode layer;

[0021] S2 continues to deposit upwards on the surface of the bottom electrode layer using magnetron sputtering to obtain a wide bandgap n-type semiconductor layer;

[0022] S3. Continue to deposit upwards on the surface of the wide bandgap n-type semiconductor layer using magnetron sputtering to obtain an n-type metal oxide semiconductor layer;

[0023] S4 Continue to deposit upwards on the surface of the n-type metal oxide semiconductor layer using magnetron sputtering to obtain the top electrode layer.

[0024] The fabrication process of this invention is simple, and the resulting memory capacitors exhibit stable and uniform capacitance conversion, high reliability, and are beneficial for the mass production and application of memory capacitors. The thickness of each layer is controlled by adjusting the deposition time of the magnetron sputtering.

[0025] As a preferred embodiment, in steps S1 and S4, the conditions for the magnetron sputtering method are: DC power supply sputtering power of 60~80W, and back-side vacuum ≤5.0×10⁻⁶. -4 The growth pressure is 1.5~5 Pa, the growth temperature is 300~600℃, the sputtering gas is argon, and the sputtering target is an inert metal target.

[0026] As a preferred embodiment, in step S2, the conditions for the magnetron sputtering method are as follows: the sputtering atmosphere is a mixture of oxygen and argon, the total flow rate is 19~21ccm, wherein the oxygen:argon ratio is ≥1:19, the AC power supply sputtering power is 80~120W, and the background vacuum is ≤2.0×10⁻⁶. -4 Pa, growth pressure is 1.5~5 Pa, growth temperature is 300~600℃, sputtering target is metal oxide ceramic target;

[0027] As a preferred embodiment, in step S3, the conditions for the magnetron sputtering method are as follows: the sputtering atmosphere is a mixture of oxygen and argon, the total flow rate is 19~21ccm, the AC power supply sputtering power is 80~120W, and the background vacuum is ≤2.0×10⁻⁶. -4 Pa, growth pressure is 1.5~5 Pa, growth temperature is 300~600℃, and sputtering target is metal oxide ceramic target.

[0028] As a preferred embodiment, in steps S1 and S4, the sputtering target is a Ni or Au target;

[0029] As a preferred embodiment, in step S2, the sputtering target is a Ga2O3 ceramic target;

[0030] As a preferred embodiment, in step S3, the sputtering target is a ZnO ceramic target.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] (1) The memory capacitor device with multi-level capacitance conversion provided by the present invention is based on the difference in band structure between the wide bandgap n-type oxide semiconductor layer material and the n-type metal oxide material, forming an n-type heterostructure at the interface. A barrier region is formed on the n-type metal oxide material side. Under the action of an electric field, the overall migration of oxygen ions in the thin film can be excited, and the width / height of the barrier region and the capacitance of the barrier region can be adjusted. In this way, the electric field can effectively and stably control the capacitance state of the device, effectively solving the problem that the existing structure electric field has a small range of capacitance control and a relaxation process.

[0033] (2) The memory container device with a heterostructure constructed by the present invention can reduce the dependence on the electrical conductivity of the material and increase the material selection of the memory container device.

[0034] (3) The preparation methods provided by the present invention all adopt magnetron sputtering technology. The preparation process is simple and low cost. The prepared memory capacitors have stable and uniform capacitance conversion and high reliability, which is conducive to the mass production and application of memory capacitors.

[0035] (4) The preparation method provided by the present invention allows for the use of diverse substrate materials for bottom electrode deposition. In addition to rigid materials such as sapphire, quartz, and silicon, flexible materials such as copper foil can also be selected to realize flexible memory devices, which has strong applicability.

[0036] (5) During use, the memory device of the present invention can change the width of the barrier region of the memory device by adjusting the magnitude and frequency of the scanning voltage, thereby realizing the memory function of multi-level capacitance conversion.

[0037] (6) When the combination of n-Ga2O3 and n-ZnO is further preferred, the memory device obtained has a non-volatile memory effect. When the scanning voltage is greater than 3.5V, there are multiple physical mechanisms in the memory device that participate in capacitance regulation and memory retention. In addition, the non-volatile memory effect of the memory device can remain stable within the frequency range of 30~300kHz. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of a memory capacitor device with multi-level capacitance conversion provided by the present invention, wherein the n-type semiconductor layer refers to the n-type metal oxide semiconductor layer.

[0039] Figure 2This is a schematic diagram of the structure of the memory capacitor device with multi-stage capacitance conversion prepared in Embodiment 1 of the present invention.

[0040] Figure 3 A schematic diagram of the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 1 of the present invention under the conditions of scanning voltage from -3V to 3V and then back to -3V, and frequency of 100kHz.

[0041] Figure 4 This is a schematic diagram showing the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 1 of the present invention under the conditions of scanning voltage from -3.5V to 3.5V and then back to -3.5V, and frequency of 100kHz.

[0042] Figure 5 A schematic diagram of the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 1 of the present invention under the conditions of scanning voltage from -4V to 4V and then back to -4V, and frequency of 100kHz.

[0043] Figure 6 This is a schematic diagram showing the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 1 of the present invention under the conditions of scanning voltage from -4.5V to 4.5V and then back to -4.5V, and frequency of 100kHz.

[0044] Figure 7 A schematic diagram of the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 1 of the present invention under the conditions of scanning voltage from -5V to 5V and then back to -5V, and frequency of 100kHz.

[0045] Figure 8 A schematic diagram of the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 1 of the present invention under the conditions of scanning voltage from -4V to 4V and then back to -4V and frequency of 30kHz.

[0046] Figure 9 A schematic diagram of the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 1 of the present invention under the conditions of scanning voltage from -4V to 4V and then back to -4V, and frequency of 50kHz.

[0047] Figure 10 A schematic diagram of the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 1 of the present invention under the conditions of scanning voltage from -4V to 4V and then back to -4V, and frequency of 200kHz.

[0048] Figure 11 A schematic diagram of the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 1 of the present invention under the conditions of scanning voltage from -4V to 4V and then back to -4V, and frequency of 300kHz.

[0049] Figure 12 The capacitance statistics of the memory capacitor device prepared in Embodiment 1 of the present invention at the time when the voltage is 0V under different amplitude scanning voltage conditions.

[0050] Figure 13 The image shows the average values ​​of the high and low capacitance states of the memory capacitor device prepared in Embodiment 1 of the present invention under different amplitude scanning voltages.

[0051] Figure 14 The capacitance statistics of the memory capacitor device prepared in Example 1 of the present invention at the moment when the device voltage is 0V under different amplitude frequencies.

[0052] Figure 15 The image shows the average values ​​of the high and low capacitance states of the memory capacitor device prepared in Example 1 of this invention under different amplitude and frequency conditions.

[0053] Figure 16 This is a schematic diagram showing the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 2 of the present invention under the conditions of scanning voltage from -3V to 3V and then back to -3V, and frequency of 30kHz.

[0054] Figure 17 This is a schematic diagram showing the capacitor voltage relationship of the memory capacitor device prepared in Embodiment 2 of the present invention under the conditions of scanning voltage from -4V to 4V and then back to -4V, and frequency of 30kHz. Detailed Implementation

[0055] To better illustrate the content of this invention, the following description is provided in conjunction with specific embodiments.

[0056] This invention provides a memory capacitor device with multi-stage capacitance conversion, the structure of which is as follows: Figure 1 As shown, it includes a bottom electrode layer, a wide bandgap n-type semiconductor layer, an n-type metal oxide semiconductor layer, and three top electrode layers that are sequentially grown on the substrate surface.

[0057] In specific embodiments, the substrate can be any one of sapphire, quartz, copper foil, and silicon, and the substrate thickness can be 10~2000μm. This invention, by selecting appropriate substrate materials and thicknesses, can improve the temperature resistance in optoelectronic testing.

[0058] In a specific embodiment, the bottom electrode layer is an inert metal layer with a thickness of 100-200 nm. Specifically, the inert metal layer is selected from either Ni or Au, and more preferably, the inert metal layer is a Ni layer.

[0059] In a specific embodiment, the thickness of the wide-bandgap n-type Ga2O3 semiconductor layer is 50~100nm. Setting it within this range effectively ensures electron transport between the Ni bottom electrode and ZnO. More preferably, the thickness of the wide-bandgap n-type Ga2O3 semiconductor layer is 80nm.

[0060] In a specific embodiment, the thickness of the n-type ZnO semiconductor layer is 100~200nm. Setting it within this range ensures control over the width of the barrier region. More preferably, the thickness of the n-type ZnO semiconductor layer is 100nm.

[0061] In a specific embodiment, the top electrode layer has a cylindrical point electrode structure with a diameter of 10~300μm and a thickness of 80~100nm. The material of the top electrode layer is the same as that of the bottom electrode layer.

[0062] The memory device with multi-level capacitance conversion provided by this invention constructs an n-level heterostructure device based on the energy band characteristics of the material. By adjusting the magnitude and frequency of the bias voltage, the width of the device barrier region can be changed, thereby realizing the memory function of the variable capacitance storage device. The technical solution of this invention can solve the crosstalk problem faced by two-terminal memory devices during integration and improve the application prospects of memory in the field of ultra-low power consumption and high-density neuromorphic computing networks.

[0063] The growth method of each layer in the memory container of the present invention is as follows:

[0064] S1 is cleaned with acetone, alcohol and deionized water, and then dried with nitrogen to perform surface cleaning of the substrate;

[0065] S2 employs magnetron sputtering to deposit an inert metal layer on a pre-cleaned substrate. Specifically, the sputtering gas is high-purity argon, the DC sputtering power is 60~80W, and the background vacuum is ≤5.0×10⁻⁶. -4 Pa, growth pressure is 1.5~5 Pa, growth temperature is 300~600℃, and sputtering target is an inert metal target;

[0066] S3 employs magnetron sputtering to deposit a wide-bandgap n-type semiconductor layer onto the surface of an inert metal layer. Specifically, the sputtering atmosphere is a mixture of oxygen and argon with a total flow rate of 20 ccm, where the oxygen:argon ratio is ≥1:19. The AC power supply sputtering power is 80~120W, and the background vacuum is ≤2.0×10⁻⁶. -4 Pa, growth pressure is 1.5~5 Pa, growth temperature is 300~600℃, sputtering target is metal oxide ceramic target;

[0067] S4 employs magnetron sputtering to deposit an n-type metal-oxide-semiconductor layer upwards on the surface of a wide-bandgap n-type semiconductor layer. Specifically, the sputtering atmosphere is a mixture of oxygen and argon with a total flow rate of 20 ccm, where the oxygen:argon ratio is 10:10. The AC power supply sputtering power is 80~120W, and the background vacuum is ≤2.0×10⁻⁶. -4 Pa, growth pressure is 1.5~5 Pa, growth temperature is 300~600℃, sputtering target is metal oxide ceramic target;

[0068] S5 employs magnetron sputtering to deposit the top electrode layer upwards on the surface of the n-type metal-oxide-semiconductor layer. Specifically, the sputtering atmosphere is high-purity argon, the DC sputtering power is 60~80W, and the background vacuum is ≤5.0×10⁻⁶. -4 Pa, growth pressure is 1.5~5 Pa, growth temperature is 300~600℃, and sputtering target is an inert metal target.

[0069] The thickness of each layer is controlled by adjusting the deposition time of the magnetron sputtering.

[0070] The memory capacitor device with multi-stage capacitance conversion of the present invention will be further described below with reference to specific embodiments.

[0071] Example 1

[0072] A memory capacitor device with multi-stage capacitance conversion is shown in the schematic diagram below. Figure 2 As shown, it includes a sapphire substrate with a thickness of 500 μm, and a Ni bottom electrode layer with a thickness of 100 nm, a wide bandgap n-type Ga2O3 semiconductor layer with a thickness of 80 nm, an n-type ZnO semiconductor layer with a thickness of 100 nm, and three cylindrical Ni top electrode layers with a thickness of 100 nm and a diameter of 100 μm, which are sequentially deposited on the surface of the sapphire substrate. The three cylindrical Ni top electrode layers are distributed in a circular array.

[0073] The fabrication process of a memory capacitor device with multi-stage capacitance conversion is as follows:

[0074] S1 uses acetone, alcohol and deionized water to clean the sapphire substrate, and then dries the substrate with nitrogen gas.

[0075] S2 employs magnetron sputtering to deposit a 100nm thick Ni bottom electrode layer on a pre-treated clean sapphire substrate. Specific parameters are: high-purity argon as the sputtering gas, 80W DC sputtering power, and a back-floor vacuum of 5.0 × 10⁻⁶. - 4 Pa, growth pressure is 3 Pa, growth temperature is 500℃, and sputtering target is Ni metal ceramic target;

[0076] S3 uses magnetron sputtering to deposit a wide-bandgap n-type Ga2O3 semiconductor layer on the surface of the Ni bottom electrode layer, resulting in a layer with a thickness of 80 nm. Specific parameters are as follows: sputtering atmosphere is a mixture of oxygen and argon, with a total flow rate of 20 ccm (oxygen:argon = 1:19), AC sputtering power of 80 W, and background vacuum of 2.0 × 10⁻⁶. -4 Pa, growth pressure is 3 Pa, growth temperature is 300℃, sputtering target is Ga2O3 ceramic target;

[0077] S4 uses magnetron sputtering to deposit an n-type ZnO semiconductor layer with a thickness of 100 nm onto the surface of a wide-bandgap n-type Ga2O3 semiconductor layer. Specific parameters are as follows: sputtering atmosphere is a mixture of oxygen and argon, with a total flow rate of 20 ccm (oxygen:argon = 10:10), AC sputtering power of 80 W, and background vacuum of 2.0 × 10⁻⁶. -4 Pa, growth pressure is 3 Pa, growth temperature is 300℃, sputtering target is ZnO ceramic target;

[0078] S5 uses magnetron sputtering to deposit three cylindrical Ni electrode layers with a diameter of 100 μm and a thickness of 100 nm on the surface of an n-type ZnO semiconductor layer. Specific parameters are: high-purity argon sputtering atmosphere, DC sputtering power of 80 W, and background vacuum of 5.0 × 10⁻⁶. -4 The growth pressure is 3 Pa, the growth temperature is 500℃, and the sputtering target is a Ni metal ceramic target.

[0079] The memory container device prepared in Example 1 was tested:

[0080] according to Figures 3 to 7 It can be observed that under positive voltage scans of different amplitudes, the capacitance value is close to zero in the negative electrode region. As the voltage increases from negative to positive, the capacitance value increases significantly, showing a main peak between 3V and 4V, and then decreases with increasing positive scan voltage. Under negative voltage scans, the device still exhibits a trend of first increasing and then decreasing, with the peak capacitance appearing between 0V and 1V, indicating that the memory device in Example 1 has a non-volatile memory effect. With increasing scan voltage amplitude, the memory window of the device increases significantly, indicating that its non-volatile storage performance is enhanced. When the scan voltage is greater than 3.5V, the curve shows a bimodal structure, indicating that multiple physical mechanisms are involved in capacitance regulation and memory retention in the memory device.

[0081] according to Figures 8 to 11 It can be seen that the capacitance-voltage curves of the device at different frequencies all exhibit a distinct double-peak or single-peak + plateau structure, indicating that the non-volatile memory effect of the memory device remains stable over a wide frequency range. As the measurement frequency increases from 30kHz to 300kHz, the maximum capacitance peak value decreases sharply, and the height of the left-side peak or plateau also decreases accordingly, with the area of ​​the hysteresis loop (memory window) shrinking significantly. At 300kHz, the overall capacitance value of the curve is the lowest, and the hysteresis loop is the narrowest, indicating that the capacitance memory characteristic of the memory device has a strong frequency dependence.

[0082] according to Figure 12 and Figure 13It can be seen that throughout all the test cycles, the capacitance value of the bottom curve remains at a very low and stable level, approximately 10pF, indicating that the low capacitance state is stable. When the scanning voltage amplitude gradually increases from 3V to 5V, the high capacitance state read at 0V shows a clear step-like increase, indicating that the high capacitance state can be precisely controlled by the amplitude of the write voltage.

[0083] according to Figure 14 and Figure 15 It can be seen that the low capacitance value remains at an extremely low and stable level, approximately 10 pF, independent of the measurement frequency. The high capacitance state exhibits a clear stepwise decrease with increasing measurement frequency, indicating that the capacitance value of the high capacitance state is strongly dependent on the measurement frequency; the high capacitance storage state of a memory device is a slow memory state. Reliable reading requires a low measurement frequency to ensure that the contribution of the slow charge is fully captured. At high frequencies, the storage window shrinks sharply.

[0084] Example 2

[0085] A memory capacitor device with multi-stage capacitance conversion is shown in the schematic diagram below. Figure 2 As shown, it includes a sapphire substrate with a thickness of 500 μm, and a Ni bottom electrode layer with a thickness of 100 nm, a wide bandgap n-type Ga2O3 semiconductor layer with a thickness of 80 nm, an n-type ZnO semiconductor layer with a thickness of 100 nm, and three cylindrical Ni top electrode layers with a thickness of 100 nm and a diameter of 100 μm, which are sequentially deposited on the surface of the sapphire substrate. The three cylindrical Ni top electrode layers are distributed in a circular array.

[0086] The fabrication process of a memory capacitor device with multi-stage capacitance conversion is as follows:

[0087] S1 uses acetone, alcohol and deionized water to clean the sapphire substrate, and then dries the substrate with nitrogen gas.

[0088] S2 employs magnetron sputtering to deposit a 100nm thick Ni bottom electrode layer on a pre-treated clean sapphire substrate. Specific parameters are: high-purity argon as the sputtering gas, 80W DC sputtering power, and a back-floor vacuum of 5.0 × 10⁻⁶. - 4 Pa, growth pressure is 3 Pa, growth temperature is 500℃, and sputtering target is Ni metal ceramic target;

[0089] S3 uses magnetron sputtering to deposit a wide-bandgap n-type Ga2O3 semiconductor layer on the surface of the Ni bottom electrode layer, resulting in a layer with a thickness of 80 nm. Specific parameters are as follows: sputtering atmosphere is a mixture of oxygen and argon, with a total flow rate of 20 ccm (oxygen:argon = 18:2), AC sputtering power of 80 W, and background vacuum of 2.0 × 10⁻⁶. -4Pa, growth pressure is 3 Pa, growth temperature is 300℃, sputtering target is Ga2O3 ceramic target;

[0090] S4 uses magnetron sputtering to deposit an n-type ZnO semiconductor layer with a thickness of 100 nm onto the surface of a wide-bandgap n-type Ga2O3 semiconductor layer. Specific parameters are as follows: sputtering atmosphere is a mixture of oxygen and argon, with a total flow rate of 20 ccm (oxygen:argon = 18:2), AC sputtering power of 80 W, and background vacuum of 2.0 × 10⁻⁶. -4 Pa, growth pressure is 3 Pa, growth temperature is 300℃, sputtering target is ZnO ceramic target;

[0091] S5 uses magnetron sputtering to deposit three cylindrical Ni electrode layers with a diameter of 100 μm and a thickness of 100 nm on the surface of an n-type ZnO semiconductor layer. Specific parameters are: high-purity argon sputtering atmosphere, DC sputtering power of 80 W, and background vacuum of 5.0 × 10⁻⁶. -4 The growth pressure is 3 Pa, the growth temperature is 500℃, and the sputtering target is a Ni metal ceramic target.

[0092] The memory container device prepared in Example 2 was tested:

[0093] according to Figure 16 It can be seen that, under the condition of changing the oxygen partial pressure in the sputtering atmosphere to 18:2, the capacitance-voltage curve of the memory capacitor still exhibits a relatively clear and symmetrical multi-stage extension hysteresis loop. Near the maximum positive and negative voltage values, the capacitance value shows several stable steps. According to... Figure 17 It can be seen that when the scanning voltage range is expanded to ±4V, the amplitude of the overall capacitance change increases significantly. For the same voltage point, the capacitance value differs even more between forward and reverse scanning. This means that the device's memory capacity or state resolution capability increases with the increase of the operating voltage amplitude. As shown in the figure, the fabricated memory capacitor device can achieve multi-stage capacitance switching function under different oxygen partial pressure conditions.

[0094] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A memcapacitive device with multi-level capacitance conversion, characterized in that: The nn heterostructure comprises a bottom electrode layer, a wide-bandgap n-type semiconductor layer, an n-type metal oxide semiconductor layer and several top electrode layers grown on the surface of a substrate in sequence; The wide-bandgap n-type oxide semiconductor layer material is Ga2O3, and the thickness is 50-100 nm; The n-type metal oxide semiconductor layer material is ZnO, and the thickness is 100-200 nm; The memcapacitive device has stable low-capacitance state and ladder-shaped high-capacitance state at a voltage amplitude of 3-5 V and a frequency of 30-300 kHz.

2. The memcapacitive device with multi-level capacitance conversion according to claim 1, wherein: The substrate is any one of sapphire, quartz, copper foil and silicon, and the thickness is 10-2000 μm.

3. The memcapacitive device with multi-level capacitance conversion according to claim 2, wherein: The bottom electrode layer material is metal Ni or Au, and the thickness is 100-200 nm.

4. The memcapacitive device with multi-level capacitance conversion of claim 2, wherein: The top electrode layer material is metal Ni or Au, and is in a cylindrical shape with a diameter of 10-300 μm and a thickness of 80-100 nm.

5. The method of claim 1-4, wherein the method of fabricating a memcapacitive device with multi-level capacitance conversion comprises: The method comprises the following steps, S1: depositing a bottom electrode layer on the surface of a substrate subjected to cleaning pretreatment by using a magnetron sputtering method; S2: continuing to deposit a wide-bandgap n-type semiconductor layer on the surface of the bottom electrode layer by using the magnetron sputtering method; S3: continuing to deposit an n-type metal oxide semiconductor layer on the surface of the wide-bandgap n-type semiconductor layer by using the magnetron sputtering method; S4: continuing to deposit a top electrode layer on the surface of the n-type metal oxide semiconductor layer by using the magnetron sputtering method.

6. The method of claim 5, wherein: In step S1 and step S4, the conditions of the magnetron sputtering method are as follows: direct current power sputtering power is 60-80 W, background vacuum is ≤5.0*10 -4 Pa, growth pressure is 1.5-5 Pa, growth temperature is 300-600 DEG C, sputtering gas is argon, and the sputtering target is an inert metal target. In step S2, the conditions of the magnetron sputtering method are as follows: the sputtering atmosphere is a mixture of oxygen and argon, the total flow rate is 19-21 ccm, the oxygen:argon ratio is ≥1:19, the alternating current power sputtering power is 80-120 W, the background vacuum is ≤2.0*10 -4 Pa, the growth pressure is 1.5-5 Pa, the growth temperature is 300-600℃, and the sputtering target is a metal oxide ceramic target; In step S3, the conditions of the magnetron sputtering method are as follows: the sputtering atmosphere is a mixture of oxygen and argon, the total flow rate is 19-21 ccm, the AC power sputtering power is 80-120 W, the background vacuum is ≤2.0×10 -4 Pa, the growth pressure is 1.5-5 Pa, the growth temperature is 300-600℃, and the sputtering target is a metal oxide ceramic target.

7. The preparation method of the memcapacitive device with multi-stage capacitance conversion according to claim 6, characterized in that: In steps S1 and S4, the sputtering target is a Ni or Au target; In step S2, the sputtering target is a Ga2O3 ceramic target; In step S3, the sputtering target is a ZnO ceramic target.

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