Asymmetric transmission line power combiner

Abstract

The invention relates to an asymmetric transmission line power combiner. An example apparatus described herein includes a first pad (140A), a second pad (140H), and a transmission line (135) including a first end (155) configured to be coupled to monitoring circuitry (125), wherein the transmission line (135) includes a second end (150). The example apparatus also includes a first switch (145A) coupled to the first pad (140A), wherein the first switch (145A) is coupled to the transmission line (135) between the first end (155) and the second end (150). The example apparatus further includes a second switch (145H) coupled to the second pad (140H) and to the second end (150) of the transmission line (135), wherein an impedance of the first switch (145A) is higher than an impedance of the second switch (140H).

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims the benefit of and priority to Indian Provisional Patent Application No. 202441052853, filed July 10, 2024, which is hereby incorporated by reference in its entirety.

[0003] This patent application also incorporates by reference commonly-assigned U.S. Patent Application No. 18 / 813,868, filed August 23, 2024, entitled “Integration of Directional Couplers with Power Combiners.” TECHNICAL FIELD

[0004] This description relates generally to power combiners, and more particularly, to asymmetric transmission line power combiners. BACKGROUND

[0005] Millimeter wave (mmWave) radar sensors can include multiple-input multiple-output (MIMO) transceivers with internal loopback systems to support calibration, monitoring, and / or functional safety requirements. The loopback systems connect multiple transmit power outputs of the MIMO transceiver to receivers of the MIMO transceiver. Such loopback systems enable attenuated versions of output signals generated at the transmit power outputs to be fed back to the receivers. The receivers receive these feedback signals and provide them to one or more circuits for various purposes. For example, monitoring circuits coupled to or otherwise included in the receivers can use the feedback signals to check the functionality of individual transmitter power outputs in operation, and measure characteristics such as average power output, peak power output, gain mismatch between power outputs, phase mismatch between power outputs, and so on, to ensure reliable transmitter performance. Some of these loopback systems utilize a transmission line power combiner that collectively couples the multiple transmit power outputs of the MIMO transceiver to a transmission line that combines the power from the multiple transmit power outputs and feeds it back to the receivers of the MIMO transceiver. In some examples, the feedback signals can be used to generate local oscillator signals in the receivers. SUMMARY

[0006] For methods and apparatuses implementing an asymmetric transmission line power combiner, an example apparatus described herein includes a first pad, a second pad, and a transmission line including a first end configured to be coupled to monitoring circuitry, where the transmission line includes a second end. The example apparatus also includes a first switch coupled to the first pad, where the first switch is coupled to the transmission line between the first end and the second end. The example apparatus further includes a second switch coupled to the second pad and coupled to the second end of the transmission line, where an impedance of the first switch is higher than an impedance of the second switch.

[0007] For methods and apparatuses implementing an asymmetric transmission line power combiner, another example apparatus described herein includes a transmission line having a first end and a second end, the first end coupled to circuitry for monitoring a plurality of transmission power outputs of an apparatus. The example apparatus also includes switches coupling the transmission power outputs to the transmission line, a first one of the switches coupling a first one of the transmission power outputs to the transmission line between the first end and the second end of the transmission line, a second one of the switches coupling a second one of the transmission power outputs to the second end of the transmission line, and the second one of the switches having a lower impedance than the first one of the switches.

[0008] For methods and apparatuses implementing an asymmetric transmission line power combiner, an example non-transitory computer-readable medium described herein includes computer-readable instructions to cause at least one processor circuit to at least cause a plurality of transmission power outputs of an apparatus to be sequentially activated for respective time intervals in a monitoring period, the transmission power outputs respectively in communication with a plurality of switches coupled to a transmission line at respective locations spaced along the transmission line, the transmission line having a termination and an output, the output coupled to circuitry for monitoring the transmission power outputs. Further, for a first one of the transmission power outputs active and others of the transmission power outputs inactive in a time interval, the computer-readable instructions further cause one or more of the at least one processor circuit to (i) deactivate a first one of the switches in communication with the first one of the transmission power outputs, the first one of the switches coupled to the transmission line at a first one of the locations; and (ii) activate a second one of the switches coupled to the transmission line at a second one of the locations, the second one of the locations between the first one of the locations and the termination of the transmission line. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram of an example apparatus including an example transmission line power combiner.

[0010] Figure 2 shows Figure 1 a first example implementation of a transmission line power combiner.

[0011] Figure 3 shows Figure 1A second example implementation of a transmission line power combiner.

[0012] Figure 4 Show Figure 1 A third example implementation of a transmission line power combiner.

[0013] Figure 5 Show Figure 4 Example performance results of a third example implementation of the transmission line power combiner shown.

[0014] Figure 6 Show Figure 1 The fourth example implementation of the transmission line power combiner corresponds to the example low-area, loss-balanced asymmetric transmission line power combiner as described herein.

[0015] Figure 7 Show Figure 6 Example operation of an asymmetric transmission line power combiner.

[0016] Figure 8 Showing the use of Figure 6 An example equivalent circuit for modeling the impedance in an asymmetric transmission line power combiner.

[0017] Figure 9 Show Figure 6 Example performance results for an asymmetric transmission line power combiner.

[0018] Figures 10 to 11 Show Figure 6 Example performance results for alternative switch configurations used in asymmetric transmission line power combiners.

[0019] Figure 12 Show Figure 8 The equivalent circuit of Figure 6 An example is used to model the impedance of the transmission lines contained in the asymmetric transmission line power combiner.

[0020] Figure 13 To indicate that inclusion can be used Figure 6 Asymmetric transmission line power combiner Figure 1 The flowcharts of example machine-readable instructions or example operations of the device are used to implement, instantiate, or perform at least one of the example programmable circuit system implementations.

[0021] Figure 14 To include structured implementations, instantiations, or executions Figure 13 Example machine-readable instructions or example operations to implement the included Figure 6 Asymmetric transmission line power combiner Figure 1 A block diagram of an example processing platform for a programmable circuit system of a device.

[0022] Figure 15 for Figure 14 A block diagram of an example implementation of a programmable circuit system.

[0023] Figure 16 for Figure 14 A block diagram of another example implementation of a programmable circuit system.

[0024] Figure 17 This is a block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers), which is used to distribute software, instructions, or firmware (e.g., corresponding to...) Figure 13 Example machine-readable instructions) are distributed to client devices associated with end users or consumers (e.g., for licensing, selling, or using), retailers (e.g., for selling, reselling, licensing, or sublicensing), or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers or other end users (e.g., direct purchase customers).

[0025] The diagrams are not necessarily drawn to scale. Generally, the same reference numerals in one or more diagrams and in this description refer to features and / or parts that are (functionally and / or structurally) the same or similar. Although the diagrams show areas with clearly defined lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, boundaries or lines may be unobservable, mixed, or irregular. Detailed Implementation

[0026] This paper describes example techniques for implementing low-area, loss-equalized asymmetric transmission line power combiners. As mentioned above, some MIMO transceivers include a loopback system that utilizes a transmission line power combiner to couple multiple transmit power outputs of the MIMO transceiver to a transmission line. The transmission line combines the power from the multiple transmit power outputs and feeds it back to the receiver of the MIMO transceiver. These transmission line power combiners can utilize a symmetrical design such that the loopback paths for different transmit power outputs have similar lengths, resulting in similar attenuation for the different transmit power outputs. Symmetrical transmission line power combiners work well for a relatively low number of transmit power outputs (e.g., two to four transmitters). However, for MIMO transceivers with a larger number of transmit power outputs (e.g., eight or sixteen transmitters), such as those used in modern radar devices, the symmetrical combiner can occupy a relatively large die area due to the relatively large size of the transmission line. Furthermore, such MIMO transceivers may experience relatively high attenuation losses due to the relatively large size of the transmission line, and therefore require additional amplifier stages to compensate for the additional losses, resulting in increased power consumption.

[0027] Utilizing asymmetrically designed transmission line power combiners can substantially reduce the die area of the combiner relative to symmetric transmission line implementations. However, some asymmetric transmission line power combiners exhibit a considerable difference in attenuation loss across different transmission power outputs. In contrast, example asymmetric transmission line power combiners described herein equalize the attenuation loss between multiple transmission power outputs and thus provide a lower difference in attenuation relative to other asymmetric transmission line power combiners. Furthermore, example asymmetric transmission line power combiners described herein reduce the total attenuation loss relative to other symmetric transmission line power combiner implementations, thereby reducing the number of amplifiers and associated current consumption for amplifying feedback signals relative to those symmetric transmission line power combiners. For example, asymmetric transmission line power combiners described herein can exhibit a total attenuation loss of 7 to 9 dB lower relative to symmetric transmission line power combiners and thus save 20 to 40 milliamps of current consumption. Furthermore, asymmetric transmission line power combiners described herein have substantially reduced die area (e.g., at least four times smaller) relative to other symmetric transmission line power combiners because the total length of the transmission lines described herein is shorter.

[0028] Turning to the drawings, Figure 1 is a block diagram of an example apparatus 100 including an example transmission line power combiner 105. In Figure 1 In the illustrated example of FIG. 1, apparatus 100 can implement at least a portion of a MIMO transceiver of a mmWave radar sensor used in automotive applications, industrial applications, imaging radars, building automation, consumer electronics, etc. For example, apparatus 100 can be used to implement a front radar for a car used in an advanced driver assistance system (ADAS), a corner radar for a car, etc. However, in other examples, apparatus 100 can correspond to any apparatus including multiple transmitters. For example, apparatus 100 can correspond to a mobile communication apparatus having multiple transmit antennas (e.g., an antenna array), an industrial detection and imaging radar, etc. Although combiner 105 is described herein as a combiner in a transmitter system, the same techniques can be implemented in a splitter circuit.

[0029] Therefore, device 100 includes a plurality of example antennas 110A to H and corresponding example power amplifiers (PAs) 115A to H to generate a plurality of transmission signals to be output by device 100. Antennas 110A to H can be implemented using any suitable technology and can be external antennas, internal antennas, etc., or any combination thereof. Antennas 110A to H are coupled to corresponding example transmission power outputs 120A to H of PAs 115A to H. PAs 115A to H can be implemented using any suitable amplifier technology to generate output signals at transmission power outputs 120A to H, which drive the corresponding antennas 110A-H to generate the transmission signals to be output by device 100. In some examples, antennas 110A to 110H can be integrated into device 100, while in other examples, antennas 110A to 110H can be external to device 100.

[0030] exist Figure 1 In the illustrated example, the apparatus includes an example loopback system implemented by a transmission line power combiner 105, an example monitoring circuitry system 125, and an example control circuitry system 130. In some examples, Figure 1 The monitoring circuitry 125 and / or control circuitry 130 can be instantiated (e.g., instantiated, generated, implemented, etc. within any given time period) by a programmable circuitry system, such as a central processing unit (CPU) that executes the first instruction. Alternatively, Figure 1 The monitoring circuit system 125 and / or control circuit system 130 can be instantiated (e.g., created, generated, implemented, etc.) by (i) an application-specific integrated circuit (ASIC) or (ii) a field-programmable gate array (FPGA) that can be structured and / or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. Therefore, Figure 1 Some or all of the monitoring circuit system 125 and / or control circuit system 130 may be instantiated at the same or different times. Figure 1 Some or all of the monitoring circuitry 125 and / or control circuitry 130 may be instantiated, for example, in one or more threads that are implemented simultaneously or in series on hardware. Furthermore, in some examples, Figure 1 Some or all of the monitoring circuitry 125 and / or control circuitry 130 may be implemented by a microprocessor circuitry that executes instructions or an FPGA circuitry that performs operations to implement one or more virtual machines or containers.

[0031] In the illustrated example, the transmission line power combiner 105 of the apparatus 100 includes an example transmission line 135, example pads 140A-H, and example switches 145A-H. The transmission line power combiner 105 uses the pads 140A-H and the switches 145A-H to couple the transmission power outputs 120A-H of the PAs 115A-H to the transmission line 135. The transmission line 135 of the illustrated example has an example termination 150 and an example output 155. In the illustrated example, the output 155 of the transmission line 135 is coupled to the monitoring circuitry 125.

[0032] In the illustrated example, the transmission line power combiner 105 combines the power from the transmission power outputs 120A-H of the PAs 115A-H and feeds the combined power back to the monitoring circuit 125. The monitoring circuit 125 processes the feedback signal provided at the output 155 of the transmission line to check the functioning of the individual transmitter transmission power outputs 120A-H in operation and to measure characteristics such as average power output, peak power output, gain mismatch between the transmission power outputs 120A-H, phase mismatch between the transmission power outputs 120A-H, etc. In some examples, the monitoring circuit 125 uses the measured characteristics to ensure reliable transmitter performance, identify one or more faults, implement one or more safety operation modes, etc.

[0033] To facilitate monitoring the transmission power outputs 120A-H individually, the control circuitry 130 of the illustrated example defines a monitoring period that is triggered or otherwise activated, enabled, etc., intermittently (e.g., periodically, aperiodically, etc.) during operation of the apparatus 100. For example, the monitoring period can have a duration of 10 milliseconds (ms) or some other duration and be triggered at a periodic interval of 10 seconds (sec) or some other periodic interval. The control circuitry 130 further defines a plurality of time intervals within the monitoring period and allocates the time intervals to the transmission power outputs 120A-H individually. Thus, in some examples, the number of time intervals in the monitoring period is equal to the number of transmission power outputs 120A-H. For example, if there are eight (8) transmission power outputs 120A-H, the control circuitry 130 can define eight (8) time intervals within a given monitoring period.

[0034] In the illustrated example, the control circuitry 130 causes the transmit power outputs 120A-H of the PAs 115A-H to be sequentially activated within respective time intervals of the monitoring period. For example, in a first time interval of the monitoring period, the control circuitry 130 can cause the transmit power output 120A of the PA 115A to be active and another transmit power output 120B-H of the PAs 115B-H to be inactive. Then, in a second interval of the monitoring period, the control circuitry 130 can cause the transmit power output 120B of the PA 115B to be active and another transmit power output 120A-C of the PAs 115A-C to be inactive. In this example, the control circuitry 130 continues to perform similar operations until a last time interval of the monitoring period, during which the control circuitry 130 causes the transmit power output 120H of the PA 115H to be active and another transmit power output 120A-C of the PAs 115A-C to be inactive. In some examples, during normal operation outside of the monitoring period, the control circuitry 130 controls or otherwise causes one or more or all of the transmit power outputs 120A-H of the PAs 115A-H to be activated.

[0035] To facilitate control of the PAs 115A-H as described above, the control circuitry 130 of the illustrated example includes example transmit control outputs 160 coupled to respective control inputs 165A-H of the PAs 115A-H. In the illustrated example, the control circuitry 130 uses the transmit control outputs 160 to selectively set the control inputs 165A-H of the PAs 115A-H to individually activate (or enable, turn on, etc.) or deactivate (or disable, turn off, etc.) the PAs 115A-H and thus the transmit power outputs 120A-H of the PAs 115A-H. For example, the PAs 115A-H can be configured such that a first logic value (e.g., a logic- 1 value, a logic-0 value, a logic-high value, a logic-low value, etc.) applied to the control input 165A-H of a given PA 115A-H causes the transmit power output 120A-H of that PA to be activated (or enabled, turned on, etc.), while a different second logic value (e.g., a logic-0 value, a logic- 1 value, a logic-low value, a logic-high value, etc.) applied to the control input 165A-H of that given PA 115A-H causes the transmit power output 120A-H of the PA to be deactivated (or disabled, turned off, etc.). In some examples, the transmit control outputs 160 of the control circuitry 130 are implemented by one or more pins, lines, traces, buses, etc.

[0036] In the illustrated example, the control circuitry 130 also includes example switch control outputs 170 coupled to respective control inputs 175A-H of the switches 145A-H. The control circuitry 130 uses the switch control outputs 170 to selectively set the control inputs 175A-H of the switches 145A-H to individually couple (or connect, etc.) or decouple (or disconnect, etc.) respective pads 140A-H and thus respective transmission power outputs 120A-H to the transmission line 135. For example, the switches 145A-H can be configured such that a first logic value (e.g., a logic- 1 value, a logic-0 value, a logic-high value, a logic-low value, etc.) applied to the control input 175A-H of a given switch 145A-H causes the switch to activate (or enable, close, etc.), while a second, different logic value (e.g., a logic-0 value, a logic- 1 value, a logic-low value, a logic-high value, etc.) applied to the control input 175A-H of the given switch 145A-H causes the switch to deactivate (or disable, open, etc.). In some examples, the switch control outputs 170 of the control circuitry 130 are implemented by one or more pins, lines, traces, buses, etc. In some examples, during normal operation outside of the monitoring period, the control circuitry 130 controls or otherwise causes one or more or all of the switches 145A-H to activate (or enable, close, etc.) or otherwise decouple (e.g., disconnect) their respective transmission power outputs 120A-H from the transmission line 135. Further details regarding how the control circuitry 130 operates to selectively control the switches 145A-H during the monitoring period are provided below.

[0037] In the illustrated example, the pads 140A-H couple the transmission power outputs 120A-H of the PAs 115A-H to the switches 145A-H of the antenna 110A-H and the transmission line power combiner 105. The pads 140A-H can be implemented by any conductive material, structure, etc. in any suitable arrangement. In some examples, the pads 140A-H are implemented by ground-signal-ground (GSG) pads. In some examples, such as examples in which the antennas 110A-H are internal to the device 100, the pads 140A-H are omitted, as the transmission power outputs 120A-H of the PAs 115A-H can be coupled internally to the switches 145A-H of the antennas 110A-H and the transmission line power combiner 105.

[0038] In the illustrated examples, switches 145A to H can be implemented using any type of switching technology. In some examples, switches 145A to H can be implemented by one or more example transistor switches 145A to H. For example, transistor switches 145A to H can be n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). In some examples, one or more of transistor switches 145A to H can be n-channel field-effect transistors (FETs), n-channel insulated-gate bipolar transistors (IGBTs), n-channel junction field-effect transistors (JFETs), NPN bipolar junction transistors (BJTs), or, with slight modifications, p-type equivalent devices or any combination thereof. In some examples, one or more of transistor switches 145A to H can be p-channel MOSFETs. In some examples, one or more of transistor switches 145A to H can be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or, with slight modifications, N-type equivalent devices or any combination thereof. In some examples, one or more of transistor switches 145A to H may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. In some examples, one or more of transistor switches 145A to H may be implemented on / above a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs). In some examples, switches 145A to H are shunt switches.

[0039] In the example where switches 145A to H are transistor switches 145A to H, the impedance of a given transistor switch 145A to H is proportional to its channel length (also known as the length of the transistor switch) and inversely proportional to its channel width (also known as the width of the transistor switch). Furthermore, in some examples, the width of transistor switches 145A to H is limited to a set of available widths. For example, transistor switches 145A to H may have widths limited to a set of available widths, including 16 micrometers (μm), 32 μm, 50 μm, etc. In some examples, the widths of transistor switches 145A to H are the same. However, in some examples, one or more of transistor switches 145A to H may have a width different from the widths of the others.

[0040] Figure 2 Show Figure 1 A first example implementation 105A of the transmission line power combiner 105. Figure 2 The example transmission line power combiner 105A supports two (2) transmitters and therefore includes the two (2) pads 140A to B and the two (2) switches 145A to B described above. The transmission line power combiner 105A also includes... Figure 1A first example embodiment 135A of the transmission line 135 included in the transmission line power combiner 105. Figure 2 The example transmission line 135A is an example of a symmetrical transmission line 135A, and therefore the transmission line power combiner 105A is an example of a symmetrical transmission line power combiner 105A.

[0041] In the example shown, the pad 140A / switch 145A combination associated with the first transmitter is coupled to a first position 205 on the transmission line 135A. Figure 2 The pad 140B / switch 145B associated with the second transmitter (marked as "TX1") is coupled to the second position 210 on the transmission line 135A. Figure 2 (marked as "TX2"). Furthermore, the second position 210 (TX2) corresponds to the termination 150A of transmission line 135A. For example... Figure 2 As shown, transmission line 135A is structured such that the feedback path from the first position 205 associated with the first transmitter (TX1) to the output 155A of transmission line 135A and the feedback path from the second position 210 associated with the second transmitter (TX2) to the output 155A of transmission line 135A have the same length or substantially similar lengths. This structure results in the feedback signals associated with the first and second transmitters experiencing the same or substantially similar attenuation, thereby creating little to almost no mismatch between the two feedback signals. Therefore, the monitoring circuitry 125 can apply the same amplification factor to both feedback signals, and thus utilize the same number of one or more amplifiers for both feedback paths.

[0042] Figure 3 Show Figure 1 A second example implementation 105B of the transmission line power combiner 105. Figure 3 The example transmission line power combiner 105B supports eight (8) transmitters and therefore includes eight (8) pads 140A to H and eight (8) switches 145A to H as described above. The transmission line power combiner 105B also includes... Figure 1 A second example embodiment 135B of the transmission line 135 included in the transmission line power combiner 105. Figure 3 The example transmission line 135B is another example of a symmetrical transmission line 135B, and therefore the transmission line power combiner 105B is another example of a symmetrical transmission line power combiner 105B. Furthermore, relative to... Figure 2 The transmission line is 135A. Figure 3 The transmission line 135B demonstrates the potential disadvantages of using symmetrical transmission lines in power combiners.

[0043] exist Figure 3In the example shown, the pad 140A / switch 145A combination associated with the first transmitter is coupled to a first position 305 on the transmission line 135B. Figure 3 The pad 140B / switch 145B associated with the second transmitter is coupled to the second position 310 on the transmission line 135B (marked as "TX1"). Figure 3 (marked as "TX2"), etc., wherein the pad 140H / switch 145H associated with the eighth transmitter is coupled to the eighth position 340 on the transmission line 135B. Figure 3 (marked as "TX8"). Furthermore, position 340 (TX8) corresponds to terminal 150B of transmission line 135B. For example... Figure 3 As shown, transmission line 135B is structured such that the feedback paths from the different locations 305 to 340 associated with the first to eighth transmitters (TX1 to TX8) to the output 155B of transmission line 135B have the same or substantially similar lengths. This structure results in the feedback signals associated with the first to eighth transmitters experiencing the same or substantially similar attenuation, thereby creating little to almost no mismatch between the eight feedback signals. Therefore, the monitoring circuitry 125 can apply the same amplification factor to the different feedback signals.

[0044] However, as Figure 3 As shown, with Figure 2 Compared to the two layers used in transmission line 135A, transmission line 135B utilizes four (4) layers to implement its symmetrical structure. The increased number of layers is due to the increased number of transmitters coupled to transmission line 135B. In some examples, a symmetrical transmission line with a structure similar to transmission line 135B would require half the number of layers corresponding to the number of transmitters to be coupled to the transmission line.

[0045] In some examples, the layer width of transmission line 135B is 40 μm. Furthermore, in some examples, the total length of transmission line 135B increases with the number of transmitters because the width of pads 140A to H (e.g., which could be GSG pads) sets the minimum distance between adjacent transmitter connectors. Under these constraints, in some examples, transmission line 135B occupies approximately 4 (layers) × 40 μm (width) × 4 mm (length) = 0.64 square millimeters (mm). 2 The die area of ​​the transistor is relatively small, which consumes considerable die space in at least some embodiments. Furthermore, in some examples, the total length of the feedback path of transmission line 135B results in a total passive loss of combiner 105B, which can be approximately 29 to 32 dB. Therefore, in some of these examples, monitoring circuitry 125 may require additional amplifiers and thus additional power dissipation to amplify the feedback signal to a sufficient level for subsequent processing.

[0046] Figure 4 Show Figure 1 A third example implementation 105C of the transmission line power combiner 105. Figure 4 The example transmission line power combiner 105C supports eight (8) transmitters and therefore includes eight (8) pads 140A to H and eight (8) switches 145A to H as described above. The transmission line power combiner 105C also includes... Figure 1 A third example implementation 135C of the transmission line 135 included in the transmission line power combiner 105. Figure 4 The example transmission line 135C is an example of an asymmetric transmission line 135C, and therefore the transmission line power combiner 105B is an example of an asymmetric transmission line power combiner 105C.

[0047] exist Figure 4 In the example shown, the pad 140A / switch 145A combination associated with the first transmitter is coupled to a first position 405 on the transmission line 135C. Figure 4 The pad 140B / switch 145B associated with the second transmitter is coupled to the second position 410 on the transmission line 135C (marked as "TX1"). Figure 4 (marked as "TX2"), etc., wherein the pad 140H / switch 145H combination associated with the eighth transmitter is coupled to the eighth position 440 on the transmission line 135C. Figure 4 (marked as "TX8"). Furthermore, the eighth position 440 (TX8) corresponds to the termination 150C of transmission line 135C. (As...) Figure 4 As shown, the asymmetric transmission line 135C is implemented using a single layer, and therefore its width is reduced by a factor of four (4) compared to the symmetric transmission line 135B, but both support eight (8) transmitters. Thus, the asymmetric transmission line 135C occupies 40 μm (width) × 4 mm (length) = 0.16 mm. 2 The die area is four times smaller than that of the symmetrical transmission line 135B.

[0048] However, as Figure 4As shown, transmission line 135C is structured such that the feedback paths from different locations 405 to 440 associated with the first to eighth transmitters (TX1 to TX8) to the output 155C of transmission line 135C have different lengths. For example, the feedback path from location 405 (TX1) to the output 155C of transmission line 135C may cover approximately 10 μm, while the feedback path from location 440 (TX8) to the output 155C of transmission line 135C may cover approximately 4 millimeters (mm). This structure results in the feedback signals associated with the first to eighth transmitters experiencing different attenuations, thereby potentially creating a considerable mismatch among the eight feedback signals.

[0049] For example, Figure 5 Show Figure 4 Example performance results 500 for the asymmetric transmission line power combiner 105C shown. Performance results 500 show that the loss difference between different feedback paths associated with different transmissions can be quite large, for example, approximately 36 dB in the example shown. In some examples, the monitoring circuitry system 125 may struggle to compensate for such a large range of dynamic losses.

[0050] Figure 6 Show Figure 1 The fourth example implementation 105D of the transmission line power combiner 105. Figure 6 The example transmission line power combiner 105D supports eight (8) transmitters and therefore includes eight (8) switches 145A to H coupled to eight (8) pads 140A to H (not shown), as described above. The transmission line power combiner 105D also includes... Figure 1 The fourth example implementation 135D of the transmission line 135 included in the transmission line power combiner 105. Figure 6 The example transmission line 135D is another example of an asymmetric transmission line 135D, and therefore the transmission line power combiner 105D is another example of an asymmetric transmission line power combiner 105D. However, with Figure 4 In contrast, the asymmetric transmission line power combiner 105B Figure 6 The 105D asymmetric transmission line power combiner is a low-area, loss-balanced asymmetric transmission line power combiner.

[0051] exist Figure 6 In the example shown, switch 145A associated with the first transmitter is coupled to a first position 605 on transmission line 135D. Figure 6 The switch 145B associated with the second transmitter (marked as "TX1") is coupled to the second position 610 on the transmission line 135D. Figure 6corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in Figure 6 corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in Figure 6 corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in Figure 4 corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in Figure 4 corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in Figure 6 corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in 2 corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in

[0052] corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in Figure 6 corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in Figure 4 corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in Figure 6 corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in

[0053] Figure 6 corresponds to the eighth position 640 (labeled "TX8") on the transmission line 135D. As shown in Figure 6As shown in the middle. Due to the inverse relationship between switch width and impedance described above, such progressive width scaling results in a progressive impedance scaling of the switches 140A-H coupled to the transmission line 135D from the output end 155D to the termination 150D of the transmission line 135D. For example, in the asymmetric transmission line power combiner 105D of Figure 6

[0054] ​In some examples, the channel width of switch 145H is at least two, three, or four times greater than the channel width of switch 145A (i.e., a ratio of at least 2, 3, or 4). Thus, the impedance of switch 145A is at least two, three, or four times greater than the channel width of switch 145H. The channel width of switch 145E can be at least 1.5, 2.0, or 2.5 times greater than the channel width of switch 145A (i.e., a ratio of at least 1.5, 2.0, or 2.5). The impedance of switch 145A is at least 1.5, 2.0, or 2.5 times greater than the channel width of switch 145E. And the channel width of switch 145H can be at least 1.2, 1.5, or 2.0 times greater than the channel width of switch 145E (i.e., a ratio of at least 1.2, 1.5, or 2.0). The impedance of switch 145E is at least 1.2, 1.5, or 2.0 times greater than the channel width of switch 145H. In some examples, all of switches 145A-H have the same channel length. These dimensions and parameters are merely examples of how to implement the techniques of the present disclosure.

[0055] Figure 6 The asymmetric transmission line power combiner 105D also achieves its reduction in overall attenuation / loss mismatch through the novel operation of switches 140A-H by control circuitry 130. Referring to Figure 1 Control circuitry 130 controls switches 140A-H to couple different combinations of transmission power outputs 120A-H to transmission line 135D depending on which transmission power outputs 120A-H are active during a particular time interval of a monitoring period. Figure 7 An example operation 700 of control circuitry 130 controlling switches 140A-H is shown in

[0056] Referring again to Figure 1 For an eight (8) transmitter implementation of device 100 corresponding to transmission line 135D, there will be eight (8) transmission power outputs 120A-H of PAs 115A-H coupled to transmission line 135D via eight (8) pads 140A-H and switches 145A-H at locations 605-640 (e.g., TX1-8). As described above, control circuitry 130 will operate to sequentially activate transmission power outputs 120A-H of PAs 115A-H for respective time intervals in a monitoring period. Further, referring to Figure 7The example operations 700 show that, during a given time interval in which a given one of the transmission power outputs 120A-H is active, the control circuitry 130 operates to cause the given switch 145A-H in communication with the active transmission power output 120A-H to couple the transmission power output 120A-H to the transmission line 135D. Further, the control circuitry 130 operates to cause any of the switches 145A-H coupled on the transmission line 135D at a position 605-640 between the output end 155D and the position of the switch 145A-H coupled to the active transmission power output 120A-H to couple its respective transmission power output 120A-H to the transmission line 135D. Further still, the control circuitry 130 operates to cause any of the switches 145A-H coupled on the transmission line 135D at a position 605-640 between the position of the switch 145A-H coupled to the active transmission power output 120A-H and the termination 150D to decouple its respective transmission power output 120A-H from the transmission line 135D.

[0057] For example, if the switches 145A-H are shunt switches, during a given time interval in which a given one of the transmission power outputs 120A-H is active, the control circuitry 130 operates to cause the given switch 145A-H in communication with the transmission power output 120A-H to deactivate (e.g., open), which couples the active transmission power output 120A-H to the transmission line 135D. Further, the control circuitry 130 operates to cause any of the switches 145A-H coupled on the transmission line 135D at a position 605-640 between the output end 155D and the position of the switch 145A-H coupled to the active transmission power output 120A-H to deactivate (e.g., open). Further still, the control circuitry 130 operates to cause any of the switches 145A-H coupled on the transmission line 135D at a position 605-640 between the position of the switch 145A-H coupled to the active transmission power output 120A-H and the termination 150D to activate (e.g., close), which decouples its respective transmission power output 120A-H from the transmission line 135D.

[0058] Figure 7 The example operations 700 show such operations for the control circuitry 130 in the case in which the transmission power output 120D corresponding to the switch 145D is active during a time interval of the monitoring period. In this example, the control circuitry 130 deactivates (e.g., opens) the switch 145D. The control circuitry 130 also deactivates (e.g., opens) the switches 145A-C between the output end 155D of the transmission line 135D and the switch 145D. The control circuitry 130 further activates (e.g., closes) the switches 145E-H between the switch 145D and the termination 150D of the transmission line 135D. More mathematically, when TXD= 1, the control circuitry 130 sets<n>(nth transmitter) is looping back (e.g., in Figure 7 TX<1:n-1> shunt switches are deactivated (e.g., open) and TX <n:8>The shunt switch is activated (e.g., closed). Such operation enables the given transmitter that is being looped back to experience a relatively low impedance in the direction towards the output 155D of the transmission line 135D, and a relatively high impedance in the direction towards the termination 150D of the transmission line 135D, which causes the feedback signal to flow towards the output 155D. Such operation also improves transmitter-to-transmitter isolation through the loopback path when the given transmitter is active.

[0059] Figure 8 An example equivalent circuit 800 is shown for modeling the impedances in the asymmetric transmission line power combiner 105D of Figure 6 The equivalent circuit 800 models the impedances at the particular switch coupling locations 605-640 in the direction towards the termination 150D of the transmission line 135D. In the equivalent circuit 800, the impedance of the transmission line 135D is represented by the variable Z0, and the impedance of the switches 145A-H at the particular switch coupling locations 605-640 is represented by the variable Z L As shown in Figure 8 , using the equivalent circuit 800, the impedance at the particular switch coupling locations 605-640 in the direction towards the termination 150D of the transmission line 135D is given by Equation 1:

[0060]

[0061] Figure 8 An evaluation of the equivalent circuit 800 for the example operation 700 of Figure 7 In the operation 700, the impedance of the transmission line 135D is 50 ohms, and the impedance of the switch 145D is 35 ohms. Thus, according to Equation 1, the impedance at the switch coupling location 620 (corresponding to the switch 145D) in the direction towards the termination 150D of the transmission line 135D is 71 ohms. Furthermore, the impedance towards the output 155D of the transmission line 135D is the line impedance of 50 ohms, which achieves a lower impedance towards the output 155D than towards the termination 150D.

[0062] Figure 9 An example performance result 900 is shown for the asymmetric transmission line power combiner 105D shown in Figure 6 The performance result 900 depicts the loss versus frequency distribution for different feedback paths from the locations 605-640 associated with the eight transmitters (TX1-TX8) to the output 155B of the transmission line 135B. The result 900 shows that the loss difference between the different feedback paths of the asymmetric transmission line power combiner 105D is approximately 5 dB, which is substantially less than the 10 dB loss difference of the symmetric transmission line power combiner 105A of Figure 4 Another asymmetric transmission line power combiner 105C as shown in the middle exhibits roughly 36 dB of loss. In some examples, the loss, e.g., of small dynamic range, can be handled by one of the amplifiers in the monitoring circuitry 125. Moreover, in this example, the absolute feedback path loss of the asymmetric transmission line power combiner 105D is 7-9 dB lower than the loss of the symmetric transmission line power combiner 105B described above. In some examples, the advantage of the asymmetric transmission line power combiner 105D is even more pronounced for a higher number of transmitters, e.g., sixteen transmitters, in an imaging radar, for example.

[0063] Figures 10 to 11 Example performance results for an alternative switch configuration used in the asymmetric transmission line power combiner 105D are shown. Figure 6 Example performance results 1000 for an example implementation in which all of the switches 145A-H have a width of 16 pm are shown. Figure 10 Example performance results 1100 for an example implementation in which all of the switches 145A-H have a width of 50 pm are shown. The performance results 1000 and 1100 show that using switches 145A-H with the same width creates a higher loss difference between the different feedback paths compared to the asymmetric transmission line power combiner 105D with a gradual scaling of the switch width. Figure 11 Example performance results 1100 for an example implementation in which all of the switches 145A-H have a width of 50 pm are shown. The performance results 1000 and 1100 show that using switches 145A-H with the same width creates a higher loss difference between the different feedback paths compared to the asymmetric transmission line power combiner 105D with a gradual scaling of the switch width.

[0064] For example, the performance results 1000 show that when the switches 145A-H have a width of 16 pm, TX7 exhibits ~2-2.7 dB higher loss than the rest of the transmitters. This is because TX7 sees a 50 ohm towards the output 155D and a 71 ohm towards the termination 150D, which is almost equal power splitting. A higher width switch can provide a lower “on” resistance (e.g., a 50 pm switch gives an “on” resistance of 10 ohms Ron, and a back impedance inversion of 250 ohms). The performance results 1100 show that when the switches 145A-H have a width of 50 pm, from TX4 onwards, there is roughly 4 dB higher loss than the first three transmitters TX1-3. This is because the 50 pm switches have a higher capacitance than the 16 pm switches, and this capacitance shunts the signal from the transmission line 135D. The feedback signal from the further transmitters TX4-8 passes through more switches and thus experiences more attenuation than the feedback signal from the closer transmitters TX1-3.

[0065] The aforementioned problem can be solved by progressively scaling the switch size. Transmitters closer to the output terminal 155D of transmission line 135D experience high impedance toward terminal 150D and therefore do not require large-sized switches. However, transmitters farther from the output terminal 155D benefit from larger switch sizes. In the example shown, transmitter TX7 experiences the worst signal splitting, and the 50μm switch at the location of TX8 solves this problem. Due to the capacitance of the 16μm shunt switches associated with transmitters TX1 to 4, signals from transmitters farther from the output terminal 155D experience less attenuation as they travel to the output terminal 155D. This scheme provides low loss for all transmitters and strives to equalize their losses, despite their signals traveling approximately four millimeters of different signal paths.

[0066] Figure 12 Show Figure 8 The equivalent circuit has 800 pairs. Figure 6 An example of impedance modeling in the 105D asymmetric transmission line power combiner uses 1200.

[0067] The table below compares Figure 6 The asymmetric transmission line power combiner 105D relative to Figure 3 Characteristics of the 105B symmetrical transmission line power combiner.

[0068] Parameter Symmetrical combiner 105B Asymmetrical combiner 105D Loss 29-32 dB 18-23 dB Area 0.64 mm 2 ]] 0.16 mm 2 ]] Additional amplifier 2-3 1-2

[0069] surface

[0070] Although the example transmission line power combiner 105D has been described in the context of a device containing eight (8) transmitters, the transmission line power combiner 105D is not limited thereto. Rather, the transmission line power combiner 105D can be used in devices containing fewer or more transmitters, such as four transmitters, twelve transmitters, sixteen transmitters, etc.

[0071] In some examples, device 100 includes components for controlling power output and switching. For example, the components for control may be implemented by control circuitry system 130. In some examples, control circuitry system 130 may be implemented by programmable circuitry system, such as… Figure 14 Example programmable circuit system 1412 can be instantiated. For example, control circuit system 130 can be instantiated via... Figure 15 The example microprocessor 1500 is instantiated to execute machine-executable instructions, such as at least those defined by... Figure 13 Those implemented in blocks 1305 to 1335. In some examples, the control circuitry system 130 may be instantiated by a hardware logic circuitry system, which may be an ASIC, XPU, or other system structured to perform operations corresponding to machine-readable instructions. Figure 16 FPGA circuitry 1600. Additionally or alternatively, control circuitry 130 can be instantiated by any other combination of hardware, software, or firmware. For example, control circuitry 130 can be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete or integrated analog or digital circuitry, FPGAs, ASICs, XPU, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured or structured to carry out some or all of machine-readable instructions or perform some or all of the operations corresponding to machine-readable instructions without carrying out software or firmware, although other structures are equally suitable.

[0072] Figure 13 To represent at least one of can be carried out, instantiated, or executed by programmable circuitry implementation to implement a device 100 having Figure 6 Figure 1 Example machine-readable instructions and / or example operations 1300 of control circuitry 130 included in an embodiment of device 100 of FIG. 1. Figure 13 Example machine-readable instructions and / or example operations 1300 begin at block 1305, where control circuitry 130 causes the device to sequentially activate the transmission power outputs 120A-H for respective time intervals in a monitoring period, as described above. Also as described above, the transmission power outputs 120A-H are coupled to the feedback transmission line 135D at respective locations 605-640 spaced along the transmission line 135D via switches 145A-H.

[0073] ​At block 1310, the control circuitry 130 cycles through the time intervals of the monitoring period, as described above. For example, at block 1315, the control circuitry 130 controls or otherwise causes the given transmission power output 120A-H associated with the current time interval to be active and the other of the transmission power outputs 120A-H to be inactive, as described above. At block 1320, the control circuitry 130 controls or otherwise causes the given switch 145A-H that is in communication with the active transmission power output 120A-H to be deactivated (e.g., opened), and the other switch 145A-H, if any, that is coupled to the transmission line 135D at the one or more locations 605-640 between the position 605-640 of the given switch 145A-H associated with the active transmission power output 120A-H and the output end 155D of the transmission line 135D to be deactivated (e.g., opened). At block 1325, the control circuitry 130 controls or otherwise causes the other switch 145A-H, if any, that is coupled to the transmission line 135D at the one or more locations 605-640 between the position of the given switch 145A-H associated with the active transmission power output 120A-H and the termination of the transmission line to be activated (e.g., closed).

[0074] At block 1330, the control circuitry 130 determines whether any time intervals remain in the current monitoring period. If any time intervals remain (corresponding to a “yes” output of block 1330), at block 1335, the control circuitry 130 sets the next time interval of the monitoring period to be the current time interval. Then, processing returns to block 1310 and the subsequent blocks at which the control circuitry 130 controls the power outputs 120A-H and the switches 145A-H for the next time interval of the monitoring period, as described above. However, if no time intervals remain (corresponding to a “no” output of block 1330), at block 1340, the control circuitry 130 deactivates (e.g., opens) the active transmission power output 120A-H and the active switch 145A-H, as described above. Figure 13 The example machine readable instructions of

[0075] Figure 14 to perform or instantiate (one or a combination thereof) Figure 13 one or more of the example machine readable instructions or example operations of Figure 1 and 6 A block diagram of an example programmable circuitry platform 1400 of the apparatus 100 of TM a tablet computer), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a head-mounted device (e.g., an augmented reality (AR) head-mounted device, a virtual reality (VR) head-mounted device, etc.), or other wearable device, or any other type of computing or electronic device.

[0076] The programmable circuitry platform 1400 of the illustrated example includes programmable circuitry 1412. The programmable circuitry 1412 of the illustrated example is hardware. For example, the programmable circuitry 1412 can be implemented by one or more integrated circuits from any desired family or manufacturer, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers. The programmable circuitry 1412 can be implemented by one or more semiconductor-based devices, e.g., semiconductor-based devices that include one or more processor cores, microprocessors, CPUs, GPUs, DSPs, or microcontrollers. In this example, the programmable circuitry 1412 implements the monitoring circuitry 125 and the control circuitry 130.

[0077] The programmable circuitry 1412 of the illustrated example includes local memory 1413 (e.g., cache, registers, etc.). The programmable circuitry 1412 of the illustrated example communicates with main memory 1414, 1416 over a bus 1418, which includes volatile memory 1414 and non-volatile memory 1416. The volatile memory 1414 can be implemented by one or more synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RAMBUS DRAM), double data rate (DDR) memory, or any other type of RAM device. The non-volatile memory 1416 can be implemented by flash memory or one or a combination of any other desired type of memory device. Access to the main memory 1414, 1416 of the illustrated example is controlled by a memory controller 1417. In some examples, the memory controller 1417 can be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuitry from any desired family or manufacturer to manage the flow of data to and from the main memory 1414, 1416. Dynamic random access memory or any other type of RAM device. The non-volatile memory 1416 can be implemented by flash memory or one or a combination of any other desired type of memory device. Access to the main memory 1414, 1416 of the illustrated example is controlled by a memory controller 1417. In some examples, the memory controller 1417 can be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuitry from any desired family or manufacturer to manage the flow of data to and from the main memory 1414, 1416.

[0078] The programmable circuitry platform 1400 of the illustrated example also includes interface circuitry 1420. The interface circuitry 1420 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a Wi-Fi® interface, a ZigBee® interface, a Near Field Communication (NFC) interface, a Global Positioning System (GPS) interface, a cellular interface, or any other type of interface. an interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, or a peripheral component interconnect express (PCIe) interface. In the illustrated example, the interface circuitry implements antennas 110A-H, PAs 115A-H, transmission lines 135D, pads 140A-H, and switches 145A-H.

[0079] In the illustrated example, one or more input devices 1422 are connected to the interface circuitry 1420. The one or more input devices 1422 permit a user (e.g., a human user, a machine user, etc.) to input one or a combination of data or commands into the programmable circuitry 1412. The one or more input devices 1422 can be implemented by, for example, one or a combination of an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, a pointing device, or a voice recognition system.

[0080] One or more output devices 1424 are also connected to the interface circuitry 1420 of the illustrated example. The one or more output devices 1424 can be implemented, for example, by one or a combination of a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, or a speaker. Thus, the interface circuitry 1420 of the illustrated example includes one or a combination of a graphics driver card, a graphics driver chip, or graphics processor circuitry such as a GPU.

[0081] The interface circuitry 1420 of the illustrated example also includes a communication device, such as one or a combination of a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, or a network interface, to facilitate exchange of data with external machines (e.g., computing devices of any kind) over a network 1426. The communication can occur via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-the-line-of-sight (beyond-line-of-sight) wireless system, a line-of-sight (line-of-sight) wireless system, a cellular telephone system, an optical connection, etc.

[0082] The programmable circuitry platform 1400 of the illustrated example also includes one or more mass storage disks or devices 1428 to store one or more of firmware, software, or data. Examples of these mass storage disks or devices 1428 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices such as flash memory devices and SSDs.

[0083] may be implemented by, for example, one or a combination of an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, a pointing device, or a voice recognition system. Figure 13 The machine-readable instructions 1432 implemented by the machine-readable instructions may be stored in one or a combination of mass storage device 1428, volatile memory 1414, and non-volatile memory 1416, or on at least one non-transitory computer-readable storage medium, such as a removable CD or DVD.

[0084] Figure 15 for Figure 14 A block diagram of an example implementation of the programmable circuit system 1412. In this example, Figure 14 The programmable circuit system 1412 is implemented by the microprocessor 1500. For example, the microprocessor 1500 may be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit system). The microprocessor 1500 implements... Figure 13 The flowchart contains some or all of the machine-readable instructions to effectively translate... Figure 1 The control circuit system 130 is instantiated as a logic circuit to perform operations corresponding to those machine-readable instructions. In some of these examples, Figure 1 The control circuitry system 130 is instantiated by the hardware circuitry of the microprocessor 1500 in conjunction with machine-readable instructions. For example, the microprocessor 1500 may be implemented by a multi-core hardware circuitry system such as a CPU, DSP, GPU, or XPU. Although the microprocessor may contain any number of example cores 1502 (e.g., one core), this example of a microprocessor 1500 is a multi-core semiconductor device containing N cores. The cores 1502 of the microprocessor 1500 may operate independently or collaboratively to execute machine-readable instructions. For example, machine code corresponding to firmware, embedded software, or software programs may be executed by one of the cores 1502, or by multiple cores 1502 at the same or different times. In some examples, the machine code corresponding to firmware, embedded software, or software programs is split into threads and executed in parallel by two or more of the cores 1502. Software programs may correspond to... Figure 13 A flowchart represents part or all of machine-readable instructions or operations.

[0085] The cores 1502 can communicate over a first example bus 1504. In some examples, the first bus 1504 can be implemented by a communication bus to enable communication associated with one or more of the cores 1502. For example, the first bus 1504 can be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1504 can be implemented by any other type of computing or electrical bus. The cores 1502 can obtain data, instructions, and signals from one or more external devices through example interface circuitry 1506. The cores 1502 can output data, instructions, and signals to one or more external devices through the interface circuitry 1506. Although the cores 1502 of this example include an example local memory 1520 (e.g., a level 1 (LI) cache, which can be split into an LI data cache and an LI instruction cache), the microprocessor 1500 also includes an example shared memory 1510 (e.g., a level 2 (L2) cache) that can be shared by the cores for high-speed access to data and instructions. Data and instructions can be transferred (e.g., shared) by one or a combination of writing to or reading from the shared memory 1510. The local memory 1520 of each of the cores 1502 and the shared memory 1510 can be part of a hierarchy of storage that includes multiple levels of cache memory and main memory (e.g., the main memory 1414, 1416 of Figure 14 Generally, higher level memories in the hierarchy exhibit shorter access times and have smaller storage capacities than lower level memories. Changes to the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

[0086] Each core 1502 can be referred to as a CPU, DSP, GPU, or any other type of hardware circuitry. Each core 1502 includes control unit circuitry 1514, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU) 1516, a plurality of registers 1518, local memory 1520, and a second bus 1522. Other structures can be present. For example, each core 1502 can include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load / store unit (LSU) circuitry, branch / fiop unit circuitry, floating point unit (FPU) circuitry, etc. Control unit circuitry 1514 includes semiconductor-based circuitry structured to control (e.g., coordinate) movement of data within corresponding core 1502. AL circuitry 1516 includes semiconductor-based circuitry structured to perform one or more mathematical or logical operations on data within corresponding core 1502. The AL circuitry 1516 of some examples performs integer-based operations. In other examples, the AL circuitry 1516 also performs floating point operations. In yet other examples, the AL circuitry 1516 can include first AL circuitry to perform integer-based operations and second AL circuitry to perform floating point operations. In some examples, the AL circuitry 1516 can be referred to as an arithmetic logic unit (ALU).

[0087] Registers 1518 are semiconductor-based structures used to store data and instructions, such as results of one or more of the operations performed by AL circuitry 1516 of corresponding core 1502. For example, registers 1518 can include one or more vector registers, one or more SIMD registers, one or more general purpose registers, one or more flag registers, one or more segment registers, one or more machine specific registers, one or more instruction pointer registers, one or more control registers, one or more debug registers, one or more memory management registers, one or more machine check registers, etc. Registers 1518 can be arranged in groups as shown in Figure 15 Alternatively, registers 1518 can be organized in any other arrangement, format, or structure, such as by being distributed throughout core 1502 to shorten access time. Second bus 1522 can be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0088] Each core 1502 or more generally, the microprocessor 1500 may include additional or alternative structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergent / common grid stoppers (CMS), one or more shifters (e.g., one or more barrel shifters) or other circuitry may be present. The microprocessor 1500 is a semiconductor device manufactured to include a number of transistors interconnected in one or more integrated circuits (ICs) contained in one or more packages, implementing the structures described above.

[0089] Microprocessor 1500 may include or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented by logic circuitry to perform certain tasks faster and more efficiently than a general-purpose processor can. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. GPUs, DSPs, or other programmable devices may also serve as accelerators. Accelerators may be mounted on microprocessor 1500, in the same chip package as microprocessor 1500, or in one or more separate packages with microprocessor 1500.

[0090] Figure 16 for Figure 14 A block diagram of another example embodiment of the programmable circuit system 1412 is shown. In this example, the programmable circuit system 1412 is implemented by an FPGA circuit system 1600. For example, the FPGA circuit system 1600 may be implemented by an FPGA. The FPGA circuit system 1600 can be used, for example, to execute machine-readable instructions that can be implemented by corresponding machine-readable instructions. Figure 15 The example microprocessor 1500 performs operations in other ways. However, once configured, the FPGA circuit system 1600 instantiates operations and functions corresponding to machine-readable instructions in hardware, and therefore can generally perform operations / functions faster than those that can be performed by a general-purpose microprocessor implementing the corresponding software.

[0091] More specifically, as described above Figure 15 The microprocessor 1500 (which is programmable and can be executed by...) Figure 13 Compared to a general-purpose device represented by one or more flowcharts in machine-readable instructions, but whose interconnection and logic circuitry system are fixed once manufactured, Figure 16 The example FPGA circuit system 1600 includes interconnect and logic circuit systems, which can be configured, structured, programmed, and interconnected in different ways or in combination after manufacturing to instantiate, for example, corresponding to those generated by... Figure 13 some or all of the operations / functions of machine-readable instructions of one or more flowchart representations of FIGS. 1-3. In particular, FPGA circuitry 1600 can be considered an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more special-purpose logic circuits (until and unless the FPGA circuitry 1600 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways for performing different operations on data received by the input circuitry. Those operations can correspond to some or all of the operations / functions of machine-readable instructions of one or more flowchart representations of FIGS. 1-3. Figure 13 some or all of the operations / functions of machine-readable instructions of one or more flowchart representations of FIGS. 1-3. In particular, FPGA circuitry 1600 can be considered an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more special-purpose logic circuits (until and unless the FPGA circuitry 1600 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways for performing different operations on data received by the input circuitry. Those operations can correspond to some or all of the operations / functions of machine-readable instructions of one or more flowchart representations of FIGS. 1-3. Figure 13 some or all of the operations / functions of machine-readable instructions of one or more flowchart representations of FIGS. 1-3. In particular, FPGA circuitry 1600 can be considered an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more special-purpose logic circuits (until and unless the FPGA circuitry 1600 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways for performing different operations on data received by the input circuitry. Those operations can correspond to some or all of the operations / functions of machine-readable instructions of one or more flowchart representations of FIGS. 1-3. Figure 13 some or all of the operations / functions of machine-readable instructions of one or more flowchart representations of FIGS. 1-3. In particular, FPGA circuitry 1600 can be considered an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more special-purpose logic circuits (until and unless the FPGA circuitry 1600 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways for performing different operations on data received by the input circuitry. Those operations can correspond to some or all of the operations / functions of machine-readable instructions of one or more flowchart representations of FIGS. 1-3.

[0092] In examples of Figure 16 FPGA circuitry 1600 is configured or structured at least one of in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file can be compiled or generated one or both of based on instructions in a hardware description language (HDL) such as Lucid, a very high speed integrated circuit (VHSIC) hardware description language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions in the HDL; the code / program can be translated into a lower-level language as needed; and the code / program (e.g., the code / program in the lower-level language) can be converted (e.g., by a compiler, a software application, etc.) into the binary file. In some examples, the binary file can be compiled or generated one or both of based on instructions in a hardware description language (HDL) such as Lucid, a very high speed integrated circuit (VHSIC) hardware description language (VHDL), or Verilog. Figure 16 FPGA circuitry 1600 of Figure 16 FPGA circuitry 1600 of Figure 16 FPGA circuitry 1600 of Figure 16 FPGA circuitry 1600 of

[0093] In some examples, the binary file is at least one of compiled, generated, converted, or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform can translate first instructions (e.g., code or programs) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) to second instructions corresponding to one or more operations / functions in an HDL. In some of these examples, the binary file is at least one of compiled, generated, or otherwise output from the unified software platform based on the second instructions. In some examples, Figure 16 FPGA circuitry 1600 of FIG. 1 can access or load at least one of the binary files to cause Figure 16 FPGA circuitry 1600 of FIG. 1 can be configured or structured to perform at least one of the one or more operations / functions. For example, the binary file can be implemented by Figure 16 FPGA circuitry 1600 of FIG. 1 can access a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), or machine-readable instructions, or a combination thereof, implemented to configure or structure Figure 16 FPGA circuitry 1600 of FIG. 1, or at least one of one or more portions thereof.

[0094] Figure 16 FPGA circuitry 1600 of FIG. 1 includes example input / output (I / O) circuitry 1602 to obtain data from, output data to, or at least one of at least one of example configuration circuitry 1604 or external hardware 1606. For example, configuration circuitry 1604 can be implemented by interface circuitry that can obtain a binary file that can be implemented by one or more of a bitstream, data, and or machine-readable instructions to configure FPGA circuitry 1600 or one or more portions thereof. In some of these examples, configuration circuitry 1604 can obtain the binary file from one or a combination of a user, a machine (e.g., hardware circuitry that can implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file, such as programmable or dedicated circuitry, etc., or any one or more combinations thereof). In some examples, external hardware 1606 can be implemented by external hardware circuitry. For example, external hardware 1606 can be implemented by Figure 15 microprocessor 1500 of FIG. 1.

[0095] The FPGA circuitry 1600 also includes an array of example logic gate circuitry 1608, a plurality of example configurable interconnects 1610, and example storage circuitry 1612. The logic gate circuitry 1608 and configurable interconnects 1610 are configurable to instantiate one or more operations / functions that can correspond to at least some of the machine-readable instructions of Figure 13 Figure 16 The logic gate circuitry 1608 shown in the example is fabricated in blocks or groups. Each block includes semiconductor-based electrical structures that are configurable into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOT gates, etc.) that provide the basic building blocks for logic circuits. Electrically controlled switches (e.g., transistors) are present within each of the logic gate circuitry 1608 to enable one or a combination of the electrical structures or logic gates to be configured to form circuits for performing desired operations / functions. The logic gate circuitry 1608 can include other electrical structures, such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0096] The configurable interconnects 1610 of the illustrated example are electrically conductive paths, traces, vias, etc. that can include electrically controlled switches (e.g., transistors), the state of which can be changed through programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuitry 1608 to program the desired logic circuits.

[0097] The storage circuitry 1612 of the illustrated example is structured to store one or more results of one or more of the operations performed by the corresponding logic gates. The storage circuitry 1612 can be implemented by registers or the like. In the illustrated example, the storage circuitry 1612 is distributed among the logic gate circuitry 1608 to facilitate access and improve execution speed.

[0098] Figure 16 ​The example FPGA circuit system 1600 also includes an example dedicated operating circuit system 1614. In this example, the dedicated operating circuit system 1614 includes a dedicated circuit system 1616 that can be invoked to implement common functions to avoid the need for field programming of those functions. Examples of such dedicated circuit systems 1616 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory and multiplier-accumulator circuit systems. Other types of dedicated circuit systems may be present. In some examples, the FPGA circuit system 1600 may also include an example general-purpose programmable circuit system 1618, such as an example CPU 1620 or an example DSP 1622. Additionally or alternatively, other general-purpose programmable circuit systems 1618, such as GPUs, XPUs, etc., may be present that can be programmed to perform other operations.

[0099] although Figure 15 and 16 Show Figure 14 Two example implementations of the programmable circuit system 1412 are provided, but many other approaches are envisioned. For example, the FPGA circuit system may include an onboard CPU, such as... Figure 15 One or more of the example CPUs 1620. Therefore, Figure 14 The programmable circuit system 1412 can also be configured by at least combining Figure 15 Example microprocessor 1500 and Figure 16 The example FPGA circuit system 1600 is used for implementation. In some of these hybrid examples, Figure 15 One or more core 1502 can be implemented by Figure 13 The first part of one or more flowcharts represents the machine-readable instructions to perform one or more first operations / functions. Figure 16 The FPGA circuit system 1600 can be configured or structured to perform operations corresponding to those performed by... Figure 13 The second part of one or more machine-readable instructions represented by one or more flowcharts, at least one of one or more second operations / functions, and / or the ASIC can be configured or structured to perform operations corresponding to those performed by the second part of the machine-readable instructions represented by one or more flowcharts. Figure 13 At least one of one or more third operations / functions in the third part of a machine-readable instruction represented by one or more flowcharts.

[0100] therefore, Figure 1 Some or all of the control circuitry in the control system 130 may be instantiated at the same or different times. For example, Figure 15 One or more identical and / or different parts of the microprocessor 1500 can be programmed to execute one or more parts of machine-readable instructions at the same and / or different times. In some examples, Figure 16 One or more identical and / or different parts of the FPGA circuit system 1600 may be configured or structured to perform at least one of the operations / functions corresponding to one or more parts of machine-readable instructions at the same and / or different times.

[0101] In some examples, Figure 1 Some or all of the control circuitry system 130 may be instantiated, for example, in one or more threads implemented in parallel and / or serially. For instance, Figure 15 The microprocessor 1500 can execute machine-readable instructions in one or more threads, in parallel and / or serial execution. In some examples, Figure 16 The FPGA circuit system 1600 can be configured or structured to operate / function in at least one of parallel and / or serial manner. Furthermore, in some examples, Figure 1 Some or all of the control circuit system 130 may be in the control circuit system 130 Figure 15 It is implemented within one or more virtual machines or containers on a microprocessor 1500.

[0102] In some examples, Figure 14 The programmable circuit system 1412 can be housed in one or more packages. For example, Figure 15 microprocessor 1500 or Figure 16 At least one of the FPGA circuitry systems 1600 may be housed in one or more packages. In some examples, the XPU may be derived from... Figure 14 The programmable circuit system 1412 is implemented, and the programmable circuit system may be in one or more packages. For example, the XPU may contain a CPU in one package (e.g., Figure 15 Microprocessor 1500, Figure 16 CPU 1620, etc.), and DSP in another package (e.g., Figure 16 DSP 1622), GPU in another package, and FPGA in yet another package (e.g., Figure 16 FPGA circuit system 1600).

[0103] Figure 17 The diagram shows a block diagram illustrating the methods for integrating software (e.g., Figure 14 Example software distribution platform 1705 distributes example machine-readable instructions (1432) to other hardware devices (e.g., one or more hardware devices owned or operated by a third party from the owner or operator of the software distribution platform). Example software distribution platform 1705 may be implemented by any computer server, data facility, cloud service, etc., capable of storing software and transferring software to other computing devices. The third party may be a customer of an entity that owns or operates at least one of the software distribution platforms 1705. For example, the entity that owns or operates at least one of the software distribution platforms 1705 may be a software (e.g., Figure 14 The third party can be a consumer, user, retailer, OEM, etc. that purchases or licenses one or a combination of the software for at least one of use, resale, or sub-license. In the illustrated example, the software distribution platform 1705 includes one or more servers and one or more storage devices. The storage devices store machine-readable instructions 1432, which can correspond to Figure 13 The one or more servers of the example software distribution platform 1705 communicate with the example network 1710, which can correspond to any one or more of the Internet or any of the example networks described above. In some examples, the one or more servers transmit software to a requesting party in response to a request that is part of a commercial transaction. Payment for at least one of delivery, sale, or license of the software can be handled by one or more servers of at least one of the software distribution platforms or by a third party payment entity. The servers enable one or more purchasers or licensees to download machine-readable instructions 1432 from the software distribution platform 1705. For example, the machine-readable instructions 1432 can correspond to Figure 13 The software of the example machine-readable instructions 1432 can be downloaded to the example programmable circuitry platform 1400, which will execute the machine-readable instructions 1432 to implement Figure 1 The control circuitry 130 of the example machine-readable instructions 1432 in some examples. In some examples, one or more servers of the software distribution platform 1705 periodically provide, transmit, or cause at least one of an update to ensure improvements, patches, updates, etc. are distributed and applied to the software at the end-user device. Although referred to as software above, the distributed "software" can instead be firmware. Figure 14 The example machine-readable instructions 1432 of the software to ensure improvements, patches, updates, etc. are distributed and applied to the software at the end-user device. Although referred to as software above, the distributed "software" can instead be firmware.

[0104] While example ways of implementing the apparatus 100 are shown in Figure 1 and 6 one or more of the elements, processes, and / or apparatus shown in Figure 1 and 6 may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Further, the monitoring circuitry 125, the control circuitry 130, or more generally the Figure 1 and 6 The example device 100 can be implemented solely by hardware or by hardware in combination with software and firmware. Thus, for example, any of the monitoring circuitry 125 or control circuitry 130 can be implemented by programmable circuitry in combination with one or more machine-readable instructions (e.g., firmware or software), processor circuitry, one or more analog circuits, one or more digital circuits, one or more logic circuits, one or more programmable processors, one or more programmable microcontrollers, one or more graphics processing units (GPU(s)), one or more digital signal processors (DSP(s)), one or more ASICs, one or more programmable logic devices (PLD(s)), or one or more field- programmable logic devices (FPLD(s)) (e.g., FPGA(s)). Still further, the example device 100 can include one or more elements, processes, or devices other than those shown in the device 100 of Figure 1 and 6 one or more elements, processes, or devices other than those shown in the device 100 of Figure 1 and 6 or in place of any or all of the elements, processes, and devices shown in the device 100 of

[0105] Figure 13 illustrate example machine-readable instructions (which can be executed by programmable circuitry to implement or instantiate at least one of the device 100 of Figure 1 and 6 illustrate one or more flow diagrams representing example machine-readable instructions (which can be executed by programmable circuitry to implement or instantiate at least one of the device 100 of Figure 1 and 6 illustrate one or more flow diagrams representing example machine-readable instructions (which can be executed by programmable circuitry to implement or instantiate at least one of the device 100 of Figure 14 and Figure 15 or 16) or one or more functions or portions of functions to be performed by example programmable circuitry (e.g., FPGA) discussed below in connection with the example processor platform 1400. In some examples, the machine-readable instructions cause operations, tasks, etc. to be performed or executed in the real world in an automated manner. As used herein, "automated" means without the need for human intervention.

[0106] The programs can be embodied in instructions stored on one or more non-transitory computer- and / or machine-readable storage media such as one or a combination of cache memory, magnetic storage, or disks (e.g., floppy disks, hard drives, etc.), optical storage (e.g., Blu-ray disks, compact disks, digital versatile disks, etc.), RAID, registers, ROM, SSDs, SSD memory, nonvolatile memory (e.g., EEPROM, flash memory, etc.), volatile memory (e.g., any type of RAM, etc.), or any other storage device or storage disk. The instructions of the non-transitory computer- and / or machine-readable media can be programmed into, or executed by, programmable circuitry located in one or more hardware devices, although the entire program or parts thereof can alternatively be implemented or instantiated in, or embodied in, special-purpose hardware. The machine-readable instructions can be distributed over multiple hardware devices or executed by two or more hardware devices (e.g., server and client hardware devices). For example, a client hardware device can be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediary client hardware device gateway (e.g., a radio access network (RAN)) that can facilitate communication between a server and an endpoint client hardware device. Similarly, the non-transitory computer-readable storage media can include one or more media. Moreover, although example programs are described with reference to one or more flow diagrams illustrated in the figures, other programs can alternatively be used (e.g., programs that are Figure 13 implemented in software, firmware, or hardware, or any combination thereof). Figure 1 and 6 Many other methods of the example device 100 are described herein. For example, the order of execution of the blocks in one or more flowcharts can be changed, or one or more of the blocks described can be changed, eliminated, or combined. Additionally or alternatively, any one or all of the blocks in a flowchart can be implemented by one or more hardware circuits (e.g., processor circuitry, discrete, integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) structured to perform the corresponding operation without executing software or firmware. Programmable circuitry can be distributed in different network locations or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPU, etc.)). For example, programmable circuitry can be one or a combination of: CPUs or FPGAs located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers of a server rack, multiple processors distributed across multiple server racks, etc., or any combination of one or more thereof.

[0107] The machine-readable instructions described herein can be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions as described herein can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or data structures (e.g., one or more portions of instructions, code, representations of code, etc.) that can be used to create, manufacture, or produce machine-executable instructions. For example, the machine-readable instructions can be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, in edge devices, etc.). The machine-readable instructions can require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decryption, decompression, unpackaging, distribution, redistribution, compilation, etc. in order to make them directly readable, interpretable, or executable by a computing device or other machine. For example, the machine-readable instructions can be stored in multiple portions that are individually compressed, encrypted, or stored on separate computing devices, where the portions, when decrypted, decompressed, or combined, form a set of one or more computer- or machine-executable instructions that perform one or more functions or operations that together can form a program as described herein.

[0108] In another example, machine-readable instructions can be stored in a state of a storage medium that can be read by programmable circuitry, but require addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc. in order to implement the machine-readable instructions on a particular computing device or another device. In another example, machine-readable instructions can require configuration (e.g., stored settings, data input, recorded network addresses, etc.) before the machine-readable instructions or one or more corresponding programs can be implemented in whole or in part. Thus, machine-readable, computer-readable, or machine-readable medium, as used herein, can include one or a combination of instructions and one or more programs in any format or state of being, regardless of specific format or state of the machine-readable instructions or one or more programs.

[0109] Machine-readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0110] As mentioned above, Figure 13 Example operations of the application can be implemented using executable instructions stored on one or more non-transitory computer-readable or machine-readable media (e.g., computer-readable and / or machine-readable instructions). As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and non-transitory machine-readable storage medium are expressly defined in terms of the express definition of the term computer-readable storage medium as including any type of computer-readable storage or storage disc, and excluding propagating signals and transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include one or more optical storage discs, magnetic storage discs, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, cache, any type of RAM, registers, or any other storage devices or storage discs where information is stored for any duration (e.g., for extended periods of time, permanently, for brief instances, temporarily as a buffer, cache, etc.). As used herein, the terms “non-transitory computer-readable storage device” and “non-transitory machine-readable storage device” are defined as including any physical (mechanical, magnetic, electro-mechanical, or electrical) hardware that stores information, but excludes propagating signals and transmission media. Examples of non-transitory computer-readable storage devices or non-transitory machine-readable storage devices include one or any combination of the following: random access memory (RAM), read only memory (ROM), solid state memory, flash memory, optical disc, magnetic disc, hard disk drive, or redundant array of independent discs (RAID) system. As used herein, the term “device” refers to a physical structure, such as one or any combination of the following: a mechanical, electro-mechanical, or electrical device, hardware, or circuitry, which can or can not be configured by, or manufactured to execute, computer-readable instructions, machine-readable instructions, etc.

[0111] "Including" and "comprises" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a technical solution uses any form of "including" or "comprises" (e.g., includes, encompassing, including, having, etc.) as a preposition or within any kind of technical solution description, additional elements, terms, etc., may be present without exceeding the scope of the corresponding technical solution or description. As used herein, when the phrase "at least" is used as a transitional term in, for example, a technical solution preposition, it is open-ended in the same way as the terms "including" and "comprises" are open-ended. The terms "and / or," when used in the form of, for example, A, B, and / or C, refer to any combination or subset of A, B, and C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A and B" means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A or B" means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase "at least one of A or B" means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0112] As used herein, singular references (e.g., "a(a)", "an(an)", "first", "second", etc.) do not exclude plurals. As used herein, the term "a(a)" or "an(an)" refers to one or more of the objects mentioned. The terms "a(a)" (or "an(an)"), "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed individually, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different examples or solutions, these features may be combined, and inclusion in different examples or solutions does not imply that the combination of features is infeasible or disadvantageous at least one of them.

[0113] As used herein, unless otherwise stated, the term "over" describes a relative position of one portion with respect to another when two portions are in face-sharing contact with each other. As such, a first portion is "over" a second portion when the first portion is closer to the earth than the second portion. Also, as used herein, a first portion is "under" a second portion when the first portion is closer to the earth than the second portion. As noted above, a first portion can be over or under a second portion with one or more of: having other portions therebetween, having no other portions therebetween, the first portion being in contact with the second portion, or the first and second portions not being in direct contact with each other.

[0114] Notwithstanding the foregoing, in reference to at least one of a semiconductor device (e.g., a transistor), a semiconductor die containing the semiconductor device, or an integrated circuit (IC) package containing the semiconductor die during fabrication or manufacturing, "over" does not refer to the earth, but rather to an underlying substrate on which the relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein, and unless the context otherwise dictates or implies, a first component is "over" a second component within a semiconductor die (e.g., a transistor or other semiconductor device) when the first component is further from the substrate (e.g., a semiconductor wafer) on which both components are fabricated or otherwise provided during fabrication / manufacturing than the second component. Similarly, and unless the context otherwise dictates or implies, a first component is "over" a second component within an IC package (e.g., a semiconductor die) during fabrication when the first component is further from a printed circuit board (PCB) on which the IC package is to be mounted or attached. Semiconductor devices are typically used in an orientation different from their orientation during fabrication. Thus, the definition of "over" in the preceding paragraph (i.e., the term "over" describes a relative position of one portion with respect to another when two portions are in face-sharing contact with each other) can govern based on the usage context when referring to one or a combination of a semiconductor device (e.g., a transistor), a semiconductor die containing the semiconductor device, or an integrated circuit (IC) package containing the semiconductor die during usage.

[0115] As used in this patent, stating that any portion (e.g., a layer, film, region, area, or plate) is on (e.g., positioned on, located on, disposed on, or formed on, etc.) another portion in any manner indicates that the referenced portion is in contact with the other portion, or that the referenced portion is over the other portion with one or more intervening portions therebetween.

[0116] As used herein, unless otherwise indicated, a connection reference (e.g., attached, coupled, connected, and joined) can include intermediate members between the elements referenced by the connection reference or relative movement therebetween. Thus, a connection reference does not necessarily infer that two elements are directly connected or in fixed relation to one another. As used herein, a statement that any portion is "contacted" with another portion is defined as meaning that there are no intermediate portions between the two portions.

[0117] Unless specifically stated otherwise, as used herein, the use of the description "first," "second," "third," etc., does not indicate a particular priority or order, but merely serves as a label for purposes of identification. In some examples, the description "first" can be used to refer to an element in the detailed description, while the same element can be referred to with a different description, such as "second" or "third," in the claims. In these instances, the description "first" is used merely for clarity in discussing the technical example, and does not indicate a particular priority or order in the technical example.

[0118] As used herein, "approximately" and "about" modify the meaning of its subject / value to recognize the potential existence of variations that occur in real-world applications. For example, "approximately" and "about" can modify dimensions that can not be exact due to at least one of manufacturing tolerances or other real-world imperfections. For example, unless otherwise specified herein, "approximately" and "about" can indicate that the dimensions can be within a + / - 10% tolerance range.

[0119] As used herein, "substantially real-time" refers to occurring in near-instantaneous fashion, recognizing that real-world delays in computation time, transmission, etc. can exist. Thus, unless otherwise specified, "substantially real-time" refers to real-time + / - 1 second.

[0120] As used herein, the phrase "communication," including variations thereof, covers one or a combination of direct communication or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication at least one of periodic intervals, predetermined intervals, non-periodic intervals, or one-time events.

[0121] As used herein, "programmable circuitry" is defined to include at least one of: (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) structured to perform one or more specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); or (ii) one or more general-purpose semiconductor-based circuits that are programmable with instructions to perform one or more specific functions or operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors, such as: central processing unit(s) (CPUs) that can execute first instructions to perform one or more operations or functions; field programmable gate arrays (FPGAs) that are programmable with second instructions to configure or structure at least one of the FPGAs to instantiate one or more operations or functions corresponding to the first instructions; graphics processing unit(s) (GPUs) that can execute first instructions to perform one or more operations or functions; digital signal processors (DSPs) that can execute first instructions to perform one or more operations or functions; XPU; network processing unit(s) (NPUs); one or more microcontrollers that can execute first instructions to perform one or more operations or functions; or integrated circuits, such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination(s) thereof) and orchestration technology (e.g., one or more application programming interfaces (API(s))), which can allocate one or more computing tasks to any one or more of the multiple types of programmable circuitry that are suitable and available to perform the one or more computing tasks.

[0122] As used herein, integrated circuit / circuitry is defined as one or more semiconductor packages that contain one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate that couples multiple circuit elements, a system on a chip (SoC), etc.

[0123] In this description, the term "coupled" can encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A produces a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B through intermediate component C, provided that intermediate component C does not alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal produced by device A.

[0124] A device "configured" to perform a task or function can be configured (e.g., programmed or hardwired), at a manufacturing or assembly facility, to perform that function, or can be configured (or reconfigured) by a user after manufacturing to perform the function and / or at least one other additional or alternative function. The configuration can be by at least one of firmware or software programming of the device, by at least one of construction or layout of hardware components and interconnects of the device, or by a combination thereof.

[0125] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" can be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnect or end thereof between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0126] In this description and the claims, "circuitry" described can include one or more circuits. A structure described herein as including certain components can actually be suitable for coupling to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., voltage and / or current sources) can actually include only the semiconductor elements within a single physical device (e.g., at least one of a semiconductor die or an integrated circuit (IC) package), and can be suitable for coupling to at least some of the passive elements or sources, e.g., by at least one of an end user or a third party, at the time of manufacture or after the time of manufacture, to form the described structure.

[0127] The circuits described herein can be reconfigurable to include alternative components to provide functionality at least somewhat similar to that available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in at least one of series or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors respectively coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors respectively coupled in series between the same two nodes as the single resistor or capacitor. While certain elements of the described examples are included in an integrated circuit and others are external to the integrated circuit, in other example embodiments additional or fewer features can be incorporated into the integrated circuit. In addition, some or all of the features shown as external to the integrated circuit can be included in the integrated circuit, and some features shown as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are at least one of: (i) incorporated in / over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; or (iv) incorporated in the same printed circuit board.

[0128] The use of the phrase "ground" in the foregoing description includes at least one of a chassis ground, an earth ground, a floating ground, a virtual ground, a digital ground, a common ground, or any other form of ground connection applicable to or suitable for use with the teachings described herein. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value, or if the value is zero, a reasonable range of values around zero.

[0129] In light of the foregoing, it should be appreciated that example systems, apparatus, articles of manufacture, and methods that implement asymmetric transmission line power combiners have been described. The described systems, apparatus, articles of manufacture, and methods improve the efficiency of devices, such as radar devices. For example, symmetric transmission line power combiners can be satisfactory for loopback systems with two transmitters. But some modern radar devices include eight or sixteen transmitters in a single die. A symmetric transmission line power combiner designed to support that number of transmitters can consume a considerable die area and exhibit high total losses due to the total length of the symmetric transmission line. In contrast, the example asymmetric transmission line power combiners described herein work well with a high number (e.g., eight or more) of transmitters and can be scaled to even higher numbers of transmitters while reducing the die area by at least a factor of four and reducing the total losses by 7 to 9 dB relative to other symmetric transmission line power combiners. Switches of appropriate size can also reduce the range of losses across the transmitter feedback paths of the asymmetric transmission line power combiner so that the paths have similar loss parameters. As such, the example asymmetric transmission line power combiners described herein can reduce the number of amplifiers needed to boost loopback signals and thus save 20 to 40 milliamps (mA) of current consumption relative to other symmetric transmission line power combiners. Moreover, such a reduction in die area can result in lower package size and total cost. Furthermore, the example asymmetric transmission line power combiners described herein are not limited to use in radar devices but can be used in any device with multiple transmitters that have signals to be looped back or otherwise transmitted in the device via a transmission line. Thus, the described systems, apparatus, articles of manufacture, and methods also relate to one or more improvements in the operation of machines, such as computers or other electronic or electromechanical devices.

[0130] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims. Additional examples and their combinations include the following. Example 1 includes a device comprising: a first pad; a second pad; a transmission line including a first end configured to be coupled to monitoring circuitry, wherein the transmission line includes a second end; a first switch coupled to the first pad, wherein the first switch is coupled to the transmission line between the first end and the second end; and a second switch coupled to the second pad and coupled to the second end of the transmission line, wherein an impedance of the first switch is higher than an impedance of the second switch.

[0131] Example 2 includes the device of Example 1, wherein the impedance of the first switch is at least twenty percent higher than the impedance of the second switch.

[0132] Example 3 includes the device of Example 1 or Example 2, wherein a channel width of the first switch is less than a channel width of the second switch.

[0133] Example 4 includes the apparatus of any of Examples 1-3, wherein a distance between the first switch and the first end of the transmission line is less than a distance between the second switch and the first end of the transmission line.

[0134] Example 5 includes the apparatus of any of Examples 1-4, comprising: a first transmission power output coupled to the first pad; a second transmission power output coupled to the second pad; and control circuitry to deactivate the first switch and activate the second switch during a first time interval, the first transmission power output active during the first time interval, the second transmission power output inactive during the first time interval.

[0135] Example 6 includes the apparatus of Example 5, wherein the control circuitry deactivates the first switch and deactivates the second switch during a second time interval, the first transmission power output inactive during the second time interval, the second transmission power output active during the second time interval.

[0136] Example 7 includes the apparatus of Example 6, comprising: a third pad; a third transmission power output coupled to the third pad; and a third switch coupled to the third pad, wherein the third switch is coupled to the transmission line between the first switch and the second switch, wherein the control circuitry: activates the third switch during a first time interval, the third transmission power output inactive during the first time interval; and deactivates the third switch during a second time interval, the third transmission power output inactive during the second time interval.

[0137] Example 8 includes the apparatus of Example 7, wherein the control circuitry deactivates the first switch, activates the second switch, and deactivates the third switch during a third time interval, the first transmission power output inactive during the third time interval, the second transmission power output inactive during the third time interval, and the third transmission power output active during the third time interval.

[0138] Example 9 includes the apparatus of Example 7, wherein an impedance of the third switch is lower than an impedance of the first switch and higher than an impedance of the second switch.

[0139] Example 10 includes the apparatus of any of Examples 1-9, wherein the first switch and the second switch are shunt switches.

[0140] Example 11 includes an apparatus comprising: a transmission line having a first end and a second end, the first end coupled to circuitry to monitor a plurality of transmission power outputs of the apparatus; and switches to couple the transmission power outputs with the transmission line, a first one of the switches to couple a first one of the transmission power outputs to the transmission line between the first end and the second end of the transmission line, a second one of the switches to couple a second one of the transmission power outputs to the second end of the transmission line, and the second one of the switches having a lower impedance than the first one of the switches.

[0141] Example 12 includes the apparatus of Example 11, wherein the circuitry is first circuitry, and the apparatus includes second circuitry to deactivate the first switch and activate the second switch during a first time interval, the first transmission power output active during the first time interval, the second transmission power output inactive during the first time interval.

[0142] Example 13 includes the apparatus of Example 12, wherein the second circuitry deactivates the first switch and deactivates the second switch during a second time interval, the first transmission power output inactive during the second time interval, the second transmission power output active during the second time interval.

[0143] Example 14 includes the apparatus of Example 13, wherein a third one of the switches couples a third one of the transmission power outputs to the transmission line between the first switch and the second switch, and the second circuitry: activates the third switch during the first time interval, the third transmission power output inactive during the first time interval; and deactivates the third switch during the second time interval, the third transmission power output inactive during the second time interval.

[0144] Example 15 includes the apparatus of Example 14, wherein the second circuitry deactivates the first switch, activates the second switch, and deactivates the third switch during a third time interval, the first transmission power output inactive during the third time interval, the second transmission power output inactive during the third time interval, and the third transmission power output active during the third time interval.

[0145] Example 16 includes the apparatus of Example 14 or Example 15, wherein the first switch has a first impedance, the second switch has a second impedance lower than the first impedance, and the third switch has a third impedance lower than the first impedance and higher than the second impedance.

[0146] Example 17 includes a non-transitory computer-readable medium comprising computer-readable instructions to cause at least one processor circuit to at least: cause a plurality of transmission power outputs of a device to be sequentially activated within respective time intervals in a monitoring period, the transmission power outputs respectively in communication with a plurality of switches, the plurality of switches coupled to a transmission line at respective locations spaced along the transmission line, the transmission line having a termination and an output, the output coupled to circuitry for monitoring the transmission power outputs; and within a first one of the time intervals in which a first one of the transmission power outputs is active and other ones of the transmission power outputs are inactive: cause a first one of the switches in communication with the first one of the transmission power outputs to be deactivated, the first one of the switches coupled to the transmission line at a first one of the locations; and cause a second one of the switches coupled to the transmission line at a second one of the locations, the second one of the locations between the first one of the locations and the termination of the transmission line.

[0147] Example 18 includes the non-transitory computer-readable medium of Example 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to, within the first one of the time intervals, deactivate a third one of the switches coupled to the transmission line at a third one of the locations, the third one of the locations between the first one of the locations and the output of the transmission line.

[0148] Example 19 includes the non-transitory computer-readable medium of Example 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to, within the first one of the time intervals: activate ones of the switches coupled to the transmission line between the first one of the locations and the termination of the transmission line; and deactivate ones of the switches coupled to the transmission line between the first one of the locations and the output of the transmission line.

[0149] Example 20 includes the non-transitory computer-readable medium of Example 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to, in time intervals outside the monitoring period, activate the switches.

[0150] The accompanying claims are hereby incorporated into the detailed description by this reference. While certain example systems, devices, articles, and methods have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods falling within the scope of the claims appended hereto. < / n>

Claims

1. An apparatus comprising: a first pad; a second pad; a transmission line including a first end configured to be coupled to monitoring circuitry, wherein the transmission line includes a second end; a first switch coupled to the first pad, wherein the first switch is coupled to the transmission line between the first end and the second end; and a second switch coupled to the second pad and coupled to the second end of the transmission line, wherein an impedance of the first switch is higher than an impedance of the second switch.

2. The apparatus of claim 1, wherein the impedance of the first switch is at least twenty percent higher than the impedance of the second switch.

3. The apparatus of claim 1, wherein a channel width of the first switch is less than a channel width of the second switch.

4. The apparatus of claim 1, wherein a distance between the first switch and the first end of the transmission line is less than a distance between the second switch and the first end of the transmission line.

5. The apparatus of claim 1, comprising: a first transmission power output coupled to the first pad; a second transmission power output coupled to the second pad; and control circuitry to deactivate the first switch and activate the second switch during a first time interval, the first transmission power output to be active during the first time interval, the second transmission power output to be inactive during the first time interval.

6. The apparatus of claim 5, wherein the control circuitry to deactivate the first switch and deactivate the second switch during a second time interval, the first transmission power output to be inactive during the second time interval, the second transmission power output to be active during the second time interval.

7. The apparatus of claim 6, comprising: a third pad; a third transmission power output coupled to the third pad; and a third switch coupled to the third pad, wherein the third switch is coupled to the transmission line between the first switch and the second switch, wherein the control circuitry to: activate the third switch during the first time interval, the third transmission power output to be inactive during the first time interval; and deactivate the third switch during the second time interval, the third transmission power output to be inactive during the second time interval.

8. The apparatus of claim 7, wherein the control circuitry to deactivate the first switch, activate the second switch, and deactivate the third switch during a third time interval, the first transmission power output to be inactive during the third time interval, the second transmission power output to be inactive during the third time interval, and the third transmission power output to be active during the third time interval.

9. The apparatus of claim 7, wherein an impedance of the third switch is lower than the impedance of the first switch and higher than the impedance of the second switch. ​ ​ 10. The apparatus of claim 1, wherein the first switch and the second switch are shunt switches.

11. An apparatus comprising: a transmission line having a first end and a second end, the first end coupled to circuitry for monitoring a plurality of transmission power outputs of the apparatus; and a switch coupling the transmission power outputs to the transmission line, a first one of the switch coupling a first one of the transmission power outputs to the transmission line between the first end and the second end of the transmission line, a second one of the switch coupling a second one of the transmission power outputs to the second end of the transmission line, and the second one of the switch having a lower impedance than the first one of the switch.

12. The apparatus of claim 11, wherein the circuitry is first circuitry, and the apparatus comprises second circuitry that deactivates the first one of the switch and activates the second one of the switch during a first time interval, the first one of the transmission power outputs active during the first time interval, the second one of the transmission power outputs inactive during the first time interval.

13. The apparatus of claim 12, wherein the second circuitry deactivates the first one of the switch and deactivates the second one of the switch during a second time interval, the first one of the transmission power outputs inactive during the second time interval, the second one of the transmission power outputs active during the second time interval.

14. The apparatus of claim 13, wherein a third one of the switch couples a third one of the transmission power outputs to the transmission line between the first one of the switch and the second one of the switch, and the second circuitry: activates the third one of the switch during the first time interval, the third one of the transmission power outputs inactive during the first time interval; and deactivates the third one of the switch during the second time interval, the third one of the transmission power outputs inactive during the second time interval.

15. The apparatus of claim 14, wherein the second circuitry deactivates the first one of the switch, activates the second one of the switch, and deactivates the third one of the switch during a third time interval, the first one of the transmission power outputs inactive during the third time interval, the second one of the transmission power outputs inactive during the third time interval, and the third one of the transmission power outputs active during the third time interval.

16. The apparatus of claim 14, wherein the first one of the switch has a first impedance, the second one of the switch has a second impedance lower than the first impedance, and the third one of the switch has a third impedance lower than the first impedance and higher than the second impedance.

17. A non-transitory computer-readable medium comprising computer-readable instructions to cause at least one processor circuit to at least: sequentially activating a plurality of transmission power outputs of a device within respective time intervals in a monitoring period, the transmission power outputs being in communication with a plurality of switches, respectively, the plurality of switches being coupled to a transmission line at respective locations spaced along the transmission line, the transmission line having a termination and an output, the output being coupled to circuitry for monitoring the transmission power outputs; and within a first one of the time intervals in which a first one of the transmission power outputs is active and others of the transmission power outputs are inactive: deactivating a first one of the switches that is coupled to the transmission line at a first one of the positions, the first one of the positions being between the first one of the positions and the termination of the transmission line; and activating a second one of the switches that is coupled to the transmission line at a second one of the positions, the second one of the positions being between the first one of the positions and the termination of the transmission line.

18. The non-transitory computer-readable medium of claim 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to deactivate, within the first one of the time intervals, a third one of the switches that is coupled to the transmission line at a third one of the positions, the third one of the positions being between the first one of the positions and the output of the transmission line.

19. The non-transitory computer-readable medium of claim 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to, within the first one of the time intervals: activate a plurality of the switches that are coupled to the transmission line between the first one of the positions and the termination of the transmission line; and deactivate a plurality of the switches that are coupled to the transmission line between the first one of the positions and the output of the transmission line.

20. The non-transitory computer-readable medium of claim 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to activate the switches in a time interval other than the monitoring period.

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