Millimeter wave CMOS power amplifier with packaging collaborative design

Abstract

The invention discloses a millimeter wave CMOS power amplifier based on packaging collaborative design, a plurality of amplifier units are arranged on a substrate, each amplifier unit comprises a first amplification assembly and a second amplification assembly, and the first amplification assembly and the second amplification assembly are used for receiving millimeter wave radio frequency signals and providing gain-amplified signals for a backward stage. The invention provides a millimeter wave CMOS (Complementary Metal-Oxide-Semiconductor Transistor) power amplifier with package collaborative design, aiming at overcoming the defects that in the prior art, under the 65nm CMOS process condition, the gain of a transistor is insufficient, the high-frequency interconnection loss is too large, and the high output power, high gain and high efficiency of a 94GHz power amplifier cannot be realized; the invention provides a millimeter wave CMOS (Complementary Metal-Oxide-Semiconductor Transistor) power amplifier based on package collaborative design, aiming at solving the problems that a conventional power combiner is large in insertion loss and package and a chip are lack of collaborative optimization, so that the requirements of millimeter wave communication and radar application on system-level performance are met.

Description

TECHNICAL FIELD

[0001] The application relates to a millimeter wave CMOS power amplifier for package co-design, and belongs to the field of radio frequency integrated circuits and millimeter wave packaging technology. BACKGROUND

[0002] Silicon-based millimeter wave integrated systems show significant potential in application fields such as high-speed wireless communication, automotive radar, security imaging, etc. Especially in the 90-100 GHz frequency band, with the rapid development of 5G / 6G and high-resolution radar, there is an urgent need for high-power, high-gain, and low-loss power amplifiers. However, how to realize high-performance millimeter wave power amplifiers on a low-cost, mass-producible CMOS process platform is still one of the key challenges of current research.

[0003] In the prior art, power amplifiers based on 65nm CMOS technology are often subject to the following limitations: first, the cutoff frequency of CMOS devices is limited, and the transconductance gain is insufficient, resulting in a significant decrease in output power and gain at 94GHz. Second, the metal interconnection has significant loss at high frequencies, further weakening the overall efficiency. These bottlenecks make it difficult for power amplifiers that simply rely on internal circuit optimization to meet the demand for high power in practical applications.

[0004] To solve the above problems, the industry has proposed various improvement schemes, mainly including:

[0005] (1) Circuit level optimization: by introducing multi-stage amplifier structures, linear embedding networks, and impedance matching networks to improve gain and bandwidth. However, limited by transistor performance and interconnection loss, single-chip circuit optimization is still limited in improving output power.

[0006] (2) Power combining structure: using a multi-path power combiner to combine the output signals of multiple amplification units to increase the overall output power. However, under the condition of 94GHz high frequency, the traditional combiner has the problems of large insertion loss and insufficient efficiency, resulting in limited actual combining gain.

[0007] (3) Package and interconnection improvement: by improving the packaging process (such as microstrip line, coplanar waveguide, low-loss substrate, etc.), the transmission loss between the chip and the external circuit can be reduced. However, if there is no co-optimization with the chip-end circuit, the effect of separate packaging improvement is limited.

[0008] Therefore, the following problems exist in the prior art:

[0009] 1) The gain of CMOS process devices is insufficient at 94GHz, limiting the single-chip power output.

[0010] 2) High frequency interconnection and power synthesis structure loss is large, and it is difficult to realize high efficiency synthesis.

[0011] 3) Single circuit optimization or package optimization is not enough to break through the system performance bottleneck.

[0012] 4) Lack of overall chip and package collaborative design method, resulting in difficulty in simultaneously improving system level output power, efficiency and bandwidth. SUMMARY

[0013] Object: In order to overcome the problems in the prior art that under the condition of 65nm CMOS process, the transistor gain is insufficient and the high frequency interconnection loss is too large, and the high output power, high gain and high efficiency of 94GHz power amplifier cannot be realized, and at the same time, the traditional power synthesizer has large insertion loss, and the package and chip lack collaborative optimization, the application provides a package collaborative design millimeter wave CMOS power amplifier, so as to meet the demand of millimeter wave communication and radar application on system level performance.

[0014] Technical scheme: In order to solve the above technical problems, the technical scheme adopted by the application is:

[0015] A package collaborative design millimeter wave CMOS power amplifier, comprising a substrate, a plurality of amplifier units are arranged on the substrate, each amplifier unit comprises: a first amplification component, a second amplification component, for receiving millimeter wave radio frequency signal and providing gain amplified signal to the rear stage.

[0016] Optionally, the first amplification component comprises a first gain amplification unit, a second gain amplification unit, a first inter-stage matching unit and a first driving output unit. The first input end of the first gain amplification unit is connected with a first series transmission line, and the second input end is connected with a second series transmission line. The first series transmission line and the second series transmission line are connected with a first parallel transmission line. The first input end of the second gain amplification unit is connected with a third series transmission line, and the second input end is connected with a fourth series transmission line. The third series transmission line and the fourth series transmission line are connected with a second parallel transmission line. The output end of the first gain amplification unit is connected with the first input end of the first inter-stage matching unit. The output end of the second gain amplification unit is connected with the second input end of the first inter-stage matching unit. The output end of the first inter-stage matching unit is connected with the input end of the first driving output unit. The first output end of the first driving output unit is connected with a fifth series transmission line, and the second output end is connected with a sixth series transmission line. The fifth series transmission line and the sixth series transmission line are connected with a third parallel transmission line. The other end of the first series transmission line and the third series transmission line is connected with a first ground end. The other end of the second series transmission line and the fourth series transmission line is connected with a first signal end. The first ground end and the first signal end are connected with a capacitor. The other end of the fifth series transmission line is connected with a second ground end, and the other end of the sixth series transmission line is connected with a second signal end. The second ground end and the second signal end are connected with a capacitor. The first parallel transmission line, the second parallel transmission line and the third parallel transmission line are connected with a power supply.

[0017] The second amplification component comprises a third gain amplification unit, a fourth gain amplification unit, a second interstage matching unit and a second driving output unit. The first input end of the third gain amplification unit is connected with the seventh series transmission line, and the second input end is connected with the eighth series transmission line. The fourth parallel transmission line is connected between the seventh series transmission line and the eighth series transmission line. The first input end of the fourth gain amplification unit is connected with the ninth series transmission line, and the second input end is connected with the tenth series transmission line. The fifth parallel transmission line is connected between the ninth series transmission line and the tenth series transmission line. The output end of the third gain amplification unit is connected with the first input end of the second interstage matching unit. The output end of the fourth gain amplification unit is connected with the second input end of the second interstage matching unit. The output end of the second interstage matching unit is connected with the input end of the second driving output unit. The first output end of the second driving output unit is connected with the eleventh series transmission line, and the second output end is connected with the twelfth series transmission line. The sixth parallel transmission line is connected between the eleventh series transmission line and the twelfth series transmission line. The other end of the seventh series transmission line and the ninth series transmission line is connected with the third signal end. The other end of the eighth series transmission line and the tenth series transmission line is connected with the third ground end. The capacitor is connected between the third signal end and the third ground end. The other end of the eleventh series transmission line is connected with the fourth signal end, and the other end of the twelfth series transmission line is connected with the fourth ground end. The capacitor is connected between the fourth signal end and the fourth ground end. The fourth parallel transmission line, the fifth parallel transmission line and the sixth parallel transmission line are connected with the power supply.

[0018] Optionally, the first ground end, the second ground end, the third ground end and the fourth ground end are connected with the ground layer of the PCB board.

[0019] Optionally, the first signal end, the second signal end, the third signal end and the fourth signal end are connected with the signal layer of the PCB board.

[0020] Optionally, the first gain amplification unit, the second gain amplification unit, the third gain amplification unit and the fourth gain amplification unit each comprise a first transistor group and a second transistor group. The source of the first transistor group and the source of the second transistor group are connected as a source port. The gate of the first transistor group is a first gate port. The drain of the first transistor group is a first drain port. The gate of the second transistor group is a second gate port. The drain of the second transistor group is a second drain port. The gate of the first transistor group is connected with a capacitor and an inductor in sequence and then connected with the drain of the second transistor group. The gate of the second transistor group is connected with a capacitor and an inductor in sequence and then connected with the drain of the first transistor group.

[0021] Optionally, the first transistor group and the second transistor group each include a plurality of cascaded transistors.

[0022] Optionally, the drain of the first transistor group and the second transistor group is led out through a top layer thick metal M9 layer terminal, the gate is connected to the top layer thick metal M9 layer through a bottom layer metal M1 and a multilayer via, and the source is grounded through a bottom layer metal M2 on both sides; the bottom layer metal M1 and the bottom layer metal M2 are arranged in a staggered manner.

[0023] Optionally, the two capacitors are symmetrically arranged on the left and right sides of the first transistor group and the second transistor group.

[0024] Optionally, the two inductors adopt a series inductance wiring structure.

[0025] Optionally, the first ground terminal, the second ground terminal, the third ground terminal and the fourth ground terminal are connected with the ground layer of the PCB board by using a Flip-chip flip-chip interconnection structure.

[0026] The first signal terminal, the second signal terminal, the third signal terminal and the fourth signal terminal are connected with the signal layer of the PCB board by using a Flip-chip flip-chip interconnection structure.

[0027] Beneficial effects: the packaged collaborative design millimeter wave CMOS power amplifier provided by the application brings the following remarkable effects through circuit optimization, power synthesizer design and joint simulation of packaging interconnection and PCB:

[0028] Firstly, at the circuit design level, the two-stage amplifier structure of the linear embedded network effectively improves the gain compensation capability of the circuit, ensuring that the CMOS device can still provide stable voltage gain and output power at 94GHz high frequency. The optimized impedance matching network reduces the reflection loss, so that the effective output power is significantly enhanced.

[0029] Secondly, in the power synthesizer part, the proposed four-way differential direct power synthesizer combined with the GSSG pad structure successfully realizes low insertion loss and high efficiency power synthesis. Simulation results show that the synthesizer has an insertion loss of less than 1 dB at 94GHz, which can ensure the superposition of multiple signals at the synthesis end, thereby improving the overall output power and stability.

[0030] Thirdly, in the packaging and interconnection design, Flip-chip packaging is used instead of traditional gold wire bonding, which greatly reduces the high-frequency loss caused by parasitic effects. At the same time, low-loss GCPW transmission lines and via arrays are introduced in the PCB part, which not only ensures good impedance matching, but also improves the ground integrity, thereby further reducing the power transmission loss in the system link.

[0031] Finally, in terms of system-level design and verification, through the joint simulation and co-optimization of circuit-package-PCB, the application ensures that the performance of the circuit end can be fully released at the system level. Simulation results show that at 94GHz, the power amplifier chip achieves a saturated output power of about 17.9dBm, a maximum gain of 11.48dB, and a peak power added efficiency (PAE) of 12%. At the same time, the overall system exhibits a stable working bandwidth of 28-106GHz, effectively covering the main application frequency bands of millimeter wave communication and radar.

[0032] In summary, through the co-design of chips and packages, the application breaks through the performance bottleneck of pure circuit optimization or pure package optimization while ensuring low cost and high integration of CMOS technology, achieving comprehensive performance advantages of high power, high gain, wide bandwidth, and high efficiency, and has important engineering application value and promotion significance. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A structure schematic diagram of a package co-design millimeter wave CMOS power amplifier of the application.

[0034] Figure 2 A structure schematic diagram of a gain amplification unit of the application.

[0035] Figure 3 A structure schematic diagram of an embodiment of a package co-design millimeter wave CMOS power amplifier of the application.

[0036] Figure 4 A structure schematic diagram of an embodiment of a gain amplification unit of the application.

[0037] Figure 5 An amplifier stability and maximum available gain result simulation diagram.

[0038] Figure 6 A power combiner circuit diagram and matching equivalent circuit diagram.

[0039] Figure 7 A power combiner model diagram.

[0040] Figure 8 A schematic diagram showing the superiority of GSSG over GSG in power combiner design.

[0041] Figure 9 A structure schematic diagram of a plate capacitor (MOM) and an interdigital capacitor (MIM).

[0042] Figure 10 A PCB package structure schematic diagram.

[0043] Figure 11 This is a schematic diagram showing the power and gain variations with input power in Example 2. Detailed Implementation

[0044] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0045] The present invention will be further described below with reference to specific embodiments.

[0046] Example 1:

[0047] This embodiment describes a millimeter-wave CMOS power amplifier with a co-package design, such as... Figure 1 As shown, the device includes a substrate on which a plurality of amplifier units 1 are disposed, each amplifier unit 1 including: a first amplification component 2 and a second amplification component 3.

[0048] The first amplification component 2 comprises a first gain amplification unit 201, a second gain amplification unit 202, a first inter-stage matching unit 203, and a first driving output unit 204. The first input end of the first gain amplification unit 201 is connected with a first series transmission line 205, and the second input end is connected with a second series transmission line 206. The first series transmission line 205 and the second series transmission line 206 are connected with a first parallel transmission line 207. The first input end of the second gain amplification unit 202 is connected with a third series transmission line 208, and the second input end is connected with a fourth series transmission line 209. The third series transmission line 208 and the fourth series transmission line 209 are connected with a second parallel transmission line 210. The output end of the first gain amplification unit 201 is connected with the first input end of the first inter-stage matching unit 203. The output end of the second gain amplification unit 202 is connected with the second input end of the first inter-stage matching unit 203. The output end of the first inter-stage matching unit 203 is connected with the input end of the first driving output unit 204. The first output end of the first driving output unit 204 is connected with a fifth series transmission line 211, and the second output end is connected with a sixth series transmission line 212. The fifth series transmission line 211 and the sixth series transmission line 212 are connected with a third parallel transmission line 213. The other end of the first series transmission line 205 and the third series transmission line 208 is connected with a first ground end 214. The other end of the second series transmission line 206 and the fourth series transmission line 209 is connected with a first signal end 215. The first ground end 214 and the first signal end 215 are connected with a capacitor. The other end of the fifth series transmission line 211 is connected with a second ground end 216, and the other end of the sixth series transmission line 212 is connected with a second signal end 217. The second ground end 216 and the second signal end 217 are connected with a capacitor. The first parallel transmission line 207, the second parallel transmission line 210, and the third parallel transmission line 213 are connected with a power supply.

[0049] The second amplification component 3 includes: a third gain amplification unit 301, a fourth gain amplification unit 302, a second interstage matching unit 303, and a second drive output unit 304. The first input terminal of the third gain amplification unit 301 is connected to a seventh series transmission line 305, and the second input terminal is connected to an eighth series transmission line 306. A fourth parallel transmission line 307 connects the seventh series transmission line 305 and the eighth series transmission line 306. The first input terminal of the fourth gain amplification unit 302 is connected to a ninth series transmission line 308, and the second input terminal is connected to a tenth series transmission line 309. A fifth parallel transmission line 310 connects the ninth series transmission line 308 and the tenth series transmission line 309. The output terminal of the third gain amplification unit 301 is connected to the first input terminal of the second interstage matching unit 303. The output terminal of the fourth gain amplification unit 302 is connected to the second input terminal of the second interstage matching unit 303. The output terminal of the second interstage matching unit 303 is connected to the input terminal of the second drive output unit 304. The first output terminal of the second drive output unit 304 is connected to the eleventh series transmission line 311, and the second output terminal of the second drive output unit 304 is connected to the twelfth series transmission line 312. A sixth parallel transmission line 313 is connected between the eleventh series transmission line 311 and the twelfth series transmission line 312. The other end of the seventh series transmission line 305 and the ninth series transmission line 308 is connected to the third signal terminal 314. The other end of the eighth series transmission line 306 and the tenth series transmission line 309 is connected to the third ground terminal 315. A capacitor is connected between the third signal terminal 314 and the third ground terminal 315. The other end of the eleventh series transmission line 311 is connected to the fourth signal terminal 316, and the other end of the twelfth series transmission line 312 is connected to the fourth ground terminal 317. A capacitor is connected between the fourth signal terminal 316 and the fourth ground terminal 317. The fourth parallel transmission line 307, the fifth parallel transmission line 310, and the sixth parallel transmission line 313 are respectively connected to the power supply.

[0050] Furthermore, the first grounding terminal 214, the second grounding terminal 216, the third grounding terminal 315, and the fourth grounding terminal 317 are all connected to the grounding layer of the PCB board.

[0051] Furthermore, the first signal terminal 215, the second signal terminal 217, the third signal terminal 314, and the fourth signal terminal 316 are all connected to the signal layer of the PCB board.

[0052] Furthermore, such as Figure 2As shown, the first gain amplification unit 201, the second gain amplification unit 202, the third gain amplification unit 301, and the fourth gain amplification unit 302 each include: a first transistor group 4 and a second transistor group 5. The sources of the first transistor group 4 and the second transistor group 5 are connected as source ports 6. The gate of the first transistor group 4 is a first gate port 7. The drain of the first transistor group 4 is a first drain port 8. The gate of the second transistor group 5 is a second gate port 9. The drain of the second transistor group 5 is a second drain port 10. The gate of the first transistor group 4 is connected to a capacitor 11 and an inductor 12 in sequence and then connected to the drain of the second transistor group 5. The gate of the second transistor group 5 is connected to a capacitor 11 and an inductor 12 in sequence and then connected to the drain of the first transistor group 4.

[0053] Furthermore, both the first transistor group 4 and the second transistor group 5 include a plurality of cascaded transistors.

[0054] Furthermore, the drains of the first transistor group 4 and the second transistor group 5 are led out through the terminals of the top thick metal M9 layer, the gates are connected to the top thick metal M9 layer through the bottom metal M1 and through multiple vias, and the sources are grounded on both sides through the bottom metal M2; the bottom metal M1 and the bottom metal M2 are arranged in a staggered manner.

[0055] Furthermore, two capacitors 11 are symmetrically arranged on the left and right sides of the first transistor group 4 and the second transistor group 5.

[0056] Furthermore, the two inductors 12 adopt a series inductor routing structure.

[0057] Furthermore, the first ground terminal 214, the second ground terminal 216, the third ground terminal 315, and the fourth ground terminal 317 are all connected to the ground layer of the PCB board using a flip-chip interconnect structure.

[0058] The first signal terminal 215, the second signal terminal 217, the third signal terminal 314, and the fourth signal terminal 316 are all connected to the signal layer of the PCB board using a flip-chip interconnect structure.

[0059] Example 2:

[0060] This embodiment describes a 94GHz millimeter-wave CMOS power amplifier with a co-designed package, such as... Figure 3As shown, an amplifier unit is provided on the substrate, including a first amplification component, a second amplification component consisting of a pre-amplification unit composed of a first gain amplification unit, a second gain amplification unit, a third gain amplification unit, and a fourth gain amplification unit; and a post-amplification unit consisting of a first drive output unit and a second drive output unit; the pre-amplification unit and the post-amplification unit are respectively connected through a first inter-stage matching unit and a second inter-stage matching unit.

[0061] The input terminal of the pre-amplifier unit is used to receive millimeter-wave radio frequency signals, and its output terminal is electrically connected to the input terminal of the subsequent drive output unit to provide the amplified signal to the subsequent stage.

[0062] The preamplifier unit incorporates a linear embedding network connected in parallel with the differential pair of amplifying transistors. This linear embedding network includes a series inductor and a series capacitor arranged between the input matching network and the intermediate stage coupling node, forming a compact embedding structure. This structure modulates the equivalent load of the differential pair in the 94 GHz band, maintaining the required voltage gain in the preamplifier stage. The linear embedding network and the preamplifier differential transistors are integrated into a single layout to control parasitic parameters at high frequencies.

[0063] The subsequent drive output unit has a similar structure to the preceding gain amplification unit, but its output stage transistors are constructed using parallel power units to improve the overall output drive capability. Preferably, as follows: Figure 4 As shown, the parallel power unit is a differential structure, with each side containing two pairs of parallel power transistors, totaling eight transistors. Each transistor is a large-size transistor with a gate width of 1.15 μm and 32 fingers, used to provide the required current capability in a 65 nm CMOS process with low breakdown voltage. The drain of each power transistor is led out through the terminal of the top thick metal M9 layer, and the gate is connected to the M9 layer through the bottom metal M1 and multiple vias to reduce the gate resistance. Both sides of the source are grounded through the bottom metal M2 to reduce the source resistance. The gate metal M1 and the source metal M2 are staggered to reduce the equivalent gate-source parasitic capacitance.

[0064] Unlike traditional differential amplifiers, the neutralizing capacitor units in this scheme are not located in the middle of the differential pair, but rather symmetrically arranged on the left and right sides of the amplifier. The neutralizing capacitor units are connected to the inverting signal terminals via traces of a certain length. These traces are designed on the layout as series inductors with a specific equivalent inductance, thus forming a series L-C structure with the neutralizing capacitors in the linear embedded network. By scanning the parameters of the series inductor traces and series capacitors, a combination that satisfies the target gain and stability can be obtained. The simulated electromagnetic model is as follows: Figure 5 As shown.

[0065] This power amplifier features power supply bias settings: the drain bias voltage of each amplification unit is 1 V, and the gate bias voltage is 0.6 V, to match the low breakdown characteristics of the 65 nm CMOS process, while ensuring that the output stage obtains sufficient saturated output power.

[0066] like Figure 6 As shown, the first amplification component and the second amplification component have multiple amplification channel outputs connected to a direct power combiner, which is used to perform in-phase power combining of the outputs of multiple differential power branches. The direct power combiner mainly consists of the following parts:

[0067] 1. Series transmission line segment: set between the output of each power amplifier branch and the combining node, used to transmit the radio frequency energy of each branch to the combining end.

[0068] 2. Input-side short-circuit stub: Connected in parallel to the input end of the series transmission line segment, with its short-circuit end serving as a virtual ground node.

[0069] 3. DC power supply node: Electrically connected to the virtual ground node, used to provide DC bias to each power amplifier branch;

[0070] 4. Output Matching Equivalent Network: Located between the synthesizer and the chip pads, it is used to match the single-ended impedance ZL seen by each branch with the optimal load impedance Zopt of the power amplifier to a consistent single-ended impedance value (half of the differential impedance) so as to connect to the external 50 Ω interface or the subsequent antenna unit.

[0071] In the above structure, the introduction of a short-circuit stub at the input end can provide bias for the power amplifier and form a reference point for the combining network without increasing the characteristic impedance of the series transmission line segment, thereby reducing the requirements for transmission line fabrication precision. The direct power combiner is suitable for combining four or more channels and features simple wiring, good scalability, and low insertion loss. To verify the electromagnetic coupling and matching, a system was established as follows... Figure 7 The HFSS full-wave electromagnetic simulation model shown in the figure has all synthesized branches, series transmission lines and short-circuit stubs built according to the actual chip size, and is used to obtain the synthesis efficiency and port isolation around 94 GHz.

[0072] like Figure 8As shown, to adapt to on-chip power combining in a low-cost, large-pitch PCB (class 6) process environment, this invention adopts a common-mode GSSG pad layout structure. The GSSG pad layout structure includes a first ground pad, a first signal pad, a second signal pad, and a second ground pad arranged sequentially. The spacing between the same pair of ground-signals is designed to be small to shorten the connection length from the amplifier output to the pad; the spacing between different ground-signal pairs is designed to be large to place more power amplification branch pads at the same chip edge, thereby increasing the number of synthesizable channels and reducing parasitic coupling between channels.

[0073] To further reduce the insertion loss of the chip-to-PCB transmission path, such as Figure 9 As shown, a matching capacitor unit is connected in parallel between the ground pad and the signal pad. This matching capacitor unit can be implemented using a MOM capacitor or a MIM capacitor, with a MIM capacitor being preferred. MIM capacitors are formed directly using the chip's metal layer, providing the required matching capacitance while reducing substrate loss and minimizing additional trace length. Co-simulation results with a 1400 μm PCB transmission line demonstrate that the GSSG layout with added MIM capacitors results in lower transmission loss and a port-visible impedance closer to the optimal load impedance of the power amplifier, thus effectively reducing the matching loss of the power combiner.

[0074] To eliminate the uncertain inductance and impedance transformations introduced by bonding wires in the millimeter-wave band, this invention employs a flip-chip interconnect structure between the chip output pads and the external PCB. This structure directly arranges solder ball interconnect units on the chip pads. The diameter and height of the solder balls are smaller than those of traditional gold wires, thereby reducing interconnect transmission losses and impedance shift. Simultaneously, the solder ball geometry is easily controlled during manufacturing, facilitating the establishment of accurate equivalent models in co-simulation, resulting in greater consistency between circuit-level simulation and system-level measurements.

[0075] like Figure 10 As shown, in a fan-out wafer-level package (FOWLP) structure suitable for multi-pad chips, a redistribution layer (RDL) is provided outside the chip and the fan-out area, and solder balls are formed on it. However, this method introduces additional parasitic and insertion losses. For applications where the number of solder pads for this power amplifier chip is small and high-frequency losses are required to be as low as possible, this invention preferably adopts a direct ball-mounted flip-chip package structure. That is, balls are directly placed on the chip pads and flip-chip soldered to the corresponding solder points on the PCB, eliminating the need for additional RDL traces and thus reducing the length of the high-frequency channel.

[0076] Example 3:

[0077] This embodiment describes the design of a first and second amplification components in an amplifier unit using a 65nm CMOS process. The front-end employs a linear embedded network to enhance gain, while the rear-end drives a power combiner. Simulation results show that the chip achieves an 11.48 dB gain and a saturated output power of 17.9 dBm at 94 GHz. The deviation between the actual load impedance at the pads and the ideal 50 Ω can be corrected in advance, avoiding matching degradation caused by the actual interconnect structure.

[0078] A four-channel differential direct power combiner is used, and the port matching is optimized using the GSSG pad structure. The insertion loss is less than 1 dB at 94 GHz, ensuring that the overall output power is not significantly attenuated.

[0079] The chip is packaged together with a low-loss GCPW PCB using a flip-chip interconnect, and a circuit-package-PCB co-simulation is performed. Simulation results show that the overall system achieves a peak PAE of 12% and a bandwidth range of 28–106 GHz, which can meet the requirements of millimeter-wave communication and radar applications.

[0080] This invention achieves the following Figure 11 The system-level performance shown is approximately 17.9 dBm saturated output power, approximately 11.48 dB maximum gain, approximately 12% peak power added efficiency, and an operating bandwidth covering 28–106 GHz, which can meet the application requirements of millimeter-wave high-power on-chip transmitter front-end.

[0081] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A millimeter-wave CMOS power amplifier with a co-packaged design, characterized in that: The system includes a substrate on which a plurality of amplifier units are disposed. Each amplifier unit includes a first amplification component and a second amplification component, for receiving millimeter-wave radio frequency signals and providing amplified signals to subsequent stages.

2. The millimeter-wave CMOS power amplifier with packaged co-design according to claim 1, characterized in that: The first amplification component includes: a first gain amplification unit, a second gain amplification unit, a first interstage matching unit, and a first drive output unit; the first input terminal of the first gain amplification unit is connected to a first series transmission line, and the second input terminal is connected to a second series transmission line, with a first parallel transmission line connecting the first and second series transmission lines; the first input terminal of the second gain amplification unit is connected to a third series transmission line, and the second input terminal is connected to a fourth series transmission line, with a second parallel transmission line connecting the third and fourth series transmission lines; the output terminal of the first gain amplification unit is connected to the first input terminal of the first interstage matching unit, and the output terminal of the second gain amplification unit is connected to the second input terminal of the first interstage matching unit. The first stage matching unit's output terminal is connected to the first drive output unit's input terminal. The first output terminal of the first drive output unit is connected to the fifth series transmission line, and the second output terminal of the first drive output unit is connected to the sixth series transmission line. A third parallel transmission line connects the fifth and sixth series transmission lines. The other ends of the first and third series transmission lines are connected to the first ground terminal. The other ends of the second and fourth series transmission lines are connected to the first signal terminal. A capacitor connects the first ground terminal and the first signal terminal. The other end of the fifth series transmission line is connected to the second ground terminal, and the other end of the sixth series transmission line is connected to the second signal terminal. A capacitor connects the second ground terminal and the second signal terminal. The first, second, and third parallel transmission lines are each connected to a power supply. The second amplification component includes: a third gain amplification unit, a fourth gain amplification unit, a second interstage matching unit, and a second drive output unit; the first input terminal of the third gain amplification unit is connected to a seventh series transmission line, and the second input terminal is connected to an eighth series transmission line, with a fourth parallel transmission line connecting the seventh and eighth series transmission lines; the first input terminal of the fourth gain amplification unit is connected to a ninth series transmission line, and the second input terminal is connected to a tenth series transmission line, with a fifth parallel transmission line connecting the ninth and tenth series transmission lines; the output terminal of the third gain amplification unit is connected to the first input terminal of the second interstage matching unit, and the output terminal of the fourth gain amplification unit is connected to the second input terminal of the second interstage matching unit, with the second input terminal of the second interstage matching unit connected to the second... The input terminals of the drive output units are connected together. The first output terminal of the second drive output unit is connected to the eleventh series transmission line, and the second output terminal of the second drive output unit is connected to the twelfth series transmission line. A sixth parallel transmission line is connected between the eleventh and twelfth series transmission lines. The other end of the seventh and ninth series transmission lines is connected to the third signal terminal. The other end of the eighth and tenth series transmission lines is connected to the third ground terminal. A capacitor is connected between the third signal terminal and the third ground terminal. The other end of the eleventh series transmission line is connected to the fourth signal terminal, and the other end of the twelfth series transmission line is connected to the fourth ground terminal. A capacitor is connected between the fourth signal terminal and the fourth ground terminal. The fourth, fifth, and sixth parallel transmission lines are connected to the power supply.

3. The millimeter-wave CMOS power amplifier with packaged co-design according to claim 2, characterized in that: The first grounding terminal, the second grounding terminal, the third grounding terminal, and the fourth grounding terminal are all connected to the grounding layer of the PCB board.

4. The millimeter-wave CMOS power amplifier with packaged co-design according to claim 2, characterized in that: The first signal terminal, the second signal terminal, the third signal terminal, and the fourth signal terminal are all connected to the signal layer of the PCB board.

5. A millimeter-wave CMOS power amplifier with a co-packaged design according to claim 2, characterized in that: The first gain amplification unit, the second gain amplification unit, the third gain amplification unit, and the fourth gain amplification unit each include: a first transistor group and a second transistor group. The sources of the first transistor group and the second transistor group are connected together as source ports. The gate of the first transistor group serves as a first gate port, and the drain of the first transistor group serves as a first drain port. The gate of the second transistor group serves as a second gate port, and the drain of the second transistor group serves as a second drain port. The gate of the first transistor group is connected to a capacitor and an inductor in sequence, and then connected to the drain of the second transistor group. The gate of the second transistor group is connected to a capacitor and an inductor in sequence, and then connected to the drain of the first transistor group.

6. A millimeter-wave CMOS power amplifier with a co-packaged design according to claim 5, characterized in that: Both the first transistor group and the second transistor group include a number of cascaded transistors.

7. A millimeter-wave CMOS power amplifier with a co-designed package according to claim 5, characterized in that: The drains of the first transistor group and the second transistor group are led out through the terminals of the top thick metal M9 layer, the gates are connected to the top thick metal M9 layer through the bottom metal M1 and through multiple vias, and the sources are grounded on both sides through the bottom metal M2; the bottom metal M1 and the bottom metal M2 are arranged in a staggered manner.

8. A millimeter-wave CMOS power amplifier with a co-packaged design according to claim 5, characterized in that: Two capacitors are symmetrically arranged on the left and right sides of the first transistor group and the second transistor group.

9. A millimeter-wave CMOS power amplifier with a co-packaged design according to claim 5, characterized in that: The two inductors use a series inductor routing structure.

10. A millimeter-wave CMOS power amplifier with a co-packaged design according to claim 2, characterized in that: The first grounding terminal, the second grounding terminal, the third grounding terminal, and the fourth grounding terminal are all connected to the grounding layer of the PCB board using a flip-chip interconnect structure. The first signal terminal, the second signal terminal, the third signal terminal, and the fourth signal terminal are all connected to the signal layer of the PCB board using a flip-chip interconnect structure.

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