Integrated chip and forming method thereof

Abstract

In some embodiments, embodiments of the present disclosure relate to an integrated chip. The integrated chip includes a substrate having a device region with one or more semiconductor devices. The substrate has one or more inner surfaces forming one or more trenches within the substrate along opposite sides of the device region. The multilayer film stack is disposed along one or more interior surfaces of the substrate. A core material is disposed within the one or more trenches and surrounded by a multilayer film stack. The multilayer film stack includes a plurality of dielectric materials having different electron affinity properties, respectively. A plurality of dielectric materials are arranged to form one or more potential wells within the multilayer film stack. The embodiment of the invention also relates to an integrated chip and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to integrated chips and methods of forming the same. Background Technology

[0002] Integrated circuits (ICs) with image sensors are widely used in modern electronic devices, such as cameras and mobile phones. In recent years, complementary metal-oxide-semiconductor (CMOS) image sensors have gained widespread use, largely replacing charge-coupled device (CCD) image sensors. Compared to CCD image sensors, CMOS image sensors are increasingly favored due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. Some types of CMOS image sensors include front-illuminated (FSI) image sensors and back-illuminated (BSI) image sensors. Summary of the Invention

[0003] Some embodiments of this application provide an integrated chip, comprising: a substrate having a device region including one or more semiconductor devices, wherein the substrate has one or more inner surfaces forming one or more trenches along opposite sides of the device region; a multilayer film stack disposed along the one or more inner surfaces of the substrate; a core material disposed within the one or more trenches and surrounded by the multilayer film stack; and wherein the multilayer film stack includes a plurality of dielectric materials having different electron affinities, the plurality of dielectric materials being arranged to form one or more potential wells within the multilayer film stack.

[0004] Other embodiments of this application provide an integrated chip, comprising: a substrate having a pixel region including an image sensing element configured to convert radiation into an electrical signal; one or more trench isolation structures disposed within the substrate along opposite sides of the pixel region, wherein the one or more trench isolation structures include: a first dielectric material having a first electron affinity; a second dielectric material disposed on the first dielectric material and having a second electron affinity; a third dielectric material disposed on the second dielectric material and having a third electron affinity; a fourth dielectric material disposed on the third dielectric material and having a fourth electron affinity; and a core material disposed on the fourth dielectric material; and wherein the second electron affinity is greater than the first electron affinity and the third electron affinity.

[0005] Further embodiments of this application provide a method for forming an integrated chip, comprising: forming a semiconductor device in a substrate having a first side and a second side; etching the second side of the substrate to form one or more trenches in the substrate along opposite sides of the semiconductor device; forming a multilayer film stack in the one or more trenches and along the second side of the substrate, wherein the multilayer film stack includes a plurality of dielectric materials having different electron affinities forming one or more potential wells; and forming a core material in the one or more trenches and on the multilayer film stack. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1A to 1B Some embodiments of an integrated chip are shown, including a trench isolation structure having a multilayer film stack configured to trap charge carriers.

[0008] Figures 2A to 2B Additional embodiments of an integrated chip are shown, including trench isolation structures having multilayer film stacks configured to trap charge carriers.

[0009] Figure 3A Additional embodiments of an integrated chip are shown, including trench isolation structures of multilayer film stacks configured to trap one or more potential wells for capturing charge carriers.

[0010] Figures 3B to 3C Some embodiments corresponding to example performance band diagrams of the disclosed multilayer film stacks are shown.

[0011] Figures 4A to 4B Cross-sectional views of some additional embodiments of an integrated chip including a trench isolation structure with the disclosed multilayer film stack are shown.

[0012] Figures 5A to 5B Some embodiments of an image sensor integrated chip including a trench isolation structure having the disclosed multilayer film stack are shown.

[0013] Figure 6 Additional embodiments of an image sensor integrated chip including a trench isolation structure with the disclosed multilayer film stack are shown.

[0014] Figures 7A to 7B Some embodiments of an image sensor integrated chip including a trench isolation structure having the disclosed multilayer film stack are shown.

[0015] Figures 8 to 11 Cross-sectional views of some additional embodiments of an image sensor integrated chip including a trench isolation structure with the disclosed multilayer film stack are shown.

[0016] Figures 12 to 26 Cross-sectional views of some embodiments of a method for forming an integrated chip including a trench isolation structure having a multilayer film stack configured to trap charge carriers are shown.

[0017] Figure 27 Flowcharts of some embodiments of a method for forming an integrated chip including a trench isolation structure having a multilayer film stack configured to trap charge carriers are shown. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] Many electronic devices (e.g., cameras, cell phones, computers, etc.) include one or more image sensor integrated circuits (ICs), including image sensing elements configured to capture images. The image sensor IC may comprise a large array of pixel regions, each comprising an image sensing element disposed within a semiconductor substrate. The pixel regions are typically electrically isolated from each other by trench isolation structures (e.g., deep trench isolation structures). The trench isolation structures may include insulating material disposed within trenches in the semiconductor substrate.

[0021] During the fabrication of trench isolation structures, a semiconductor substrate may be etched to form trenches that are subsequently filled with one or more dielectric materials. The etching process used to form the trenches may damage the semiconductor substrate, creating defects (e.g., dangling bonds, etc.) along the inner surface of the semiconductor substrate where the trenches are formed. These defects may trap electrons and cause unwanted leakage currents to flow between adjacent pixel regions, resulting in dark current and / or white pixel problems within the image sensor IC.

[0022] Some trench isolation structures may include a high-k dielectric material disposed along the inner surface of a semiconductor substrate forming the trench. The high-k dielectric material stores charge, which generates an electric field that accumulates holes along the inner surface of the semiconductor substrate. These accumulated holes are configured to passivate defects, thereby reducing dark current and / or white pixel issues. However, it has been recognized that the electric field provided by such a high-k dielectric material may not be strong enough to achieve a sufficient hole density to effectively passivate electrons trapped in defects. Therefore, image sensor ICs with high-k dielectric material along the sidewalls of the trenches formed during the fabrication of the trench isolation structure may still suffer performance degradation due to dark current and / or white pixel issues.

[0023] This disclosure relates to an integrated chip including a trench isolation structure having a multilayer film stack forming potential wells configured to trap charge carriers. In some embodiments, the integrated chip includes a substrate having device regions having one or more semiconductor devices (e.g., one or more image sensing elements). The substrate has one or more inner surfaces forming one or more trenches along opposite sides of the device regions. The trench isolation structure is disposed within the one or more trenches. The trench isolation structure includes a multilayer film stack and a core material. The multilayer film stack is disposed within the one or more trenches and along one or more inner surfaces of the substrate. The multilayer film stack includes a variety of dielectric materials, each having a different electron affinity. The various dielectric materials are arranged to form one or more potential wells within the multilayer film stack. The potential wells are capable of trapping charge carriers (e.g., electrons). By trapping charge carriers, the multilayer film stack is capable of increasing the total charge associated with the isolation structure and generating an electric field that attracts opposing charge carriers (e.g., holes) toward one or more inner surfaces of the substrate. Conversely, charge carriers can passivate defects (e.g., traps) along one or more inner surfaces of the substrate, thereby reducing unwanted currents (e.g., dark current, leakage current, etc.) and improving the performance of the integrated chip.

[0024] Figure 1A Cross-sectional views of some embodiments of an integrated chip 100 including a trench isolation structure having a multilayer film stack configured to trap charge carriers are shown.

[0025] The integrated chip 100 includes a substrate 102 having a first side 102a and a second side 102b opposite to the first side 102a. The substrate 102 includes a device region 106 having a semiconductor device. In some embodiments, the semiconductor device may include and / or a transistor device, such as a planar FET, FinFET, full-ring gate structure, nanowire structure, high-voltage device, etc. In other embodiments, the semiconductor device may include or be configured to convert incident radiation into an image sensing element. In some embodiments, the image sensing element may include a photodiode (e.g., a PN photodiode, a PIN photodiode, a Schottky photodiode, an avalanche photodiode, etc.).

[0026] Substrate 102 includes one or more inner surfaces (e.g., sidewalls) forming one or more trenches 104 disposed along opposite sides of device region 106. The one or more trenches 104 extend from a first side 102a of substrate 102 into the substrate 102. A trench isolation structure 111 is disposed within the one or more trenches 104. The trench isolation structure 111 includes a multilayer film stack 108 and a core material 110. The multilayer film stack 108 is disposed along one or more inner surfaces of substrate 102. The multilayer film stack 108 separates the core material 110 from the substrate 102. In some embodiments, the multilayer film stack 108 extends along opposite sidewalls and the bottom of the core material 110.

[0027] The multilayer film stack 108 includes multiple dielectric materials 108a-108d stacked on top of each other. In some embodiments, the multilayer film stack 108 may include a first dielectric material 108a, a second dielectric material 108b stacked on the first dielectric material 108a, a third dielectric material 108c stacked on the second dielectric material 108b, and a fourth dielectric material 108d stacked on the third dielectric material 108c. In some additional embodiments, the multilayer film stack 108 may include one or more additional dielectric materials. Two or more of the multiple dielectric materials 108a-108d have different electron affinities. The multiple dielectric materials 108a-108d are arranged to give the multilayer film stack 108 a conduction band having one or more potential wells (e.g., one potential well, two potential wells, three potential wells, etc.). In some embodiments, the conduction band of the multilayer film stack 108 is symmetrical. In some embodiments, the conduction band of the multilayer film stack 108 is asymmetrical.

[0028] Figure 1B Example performance band diagram 118 is shown in relation to the disclosed multilayer film stack 108. Example performance band diagram 118 is along... Figure 1A The line 112 was cut off.

[0029] As can be seen in band structure diagram 118, the various dielectric materials 108a-108d of the multilayer film stack 108 have different conduction band energies. These different conduction band energies form potential wells 120 within one of the dielectric materials of the multilayer film stack 108. The potential wells 120 are capable of trapping charge carriers (e.g., electrons 114 or holes) within the multilayer film stack 108. The trapped charge carriers enhance the isolation from the trench structure (e.g., ...). Figure 1A The total charge associated with 111) generates an electric field that attracts opposite charge carriers (e.g., holes 116 or electrons) toward one or more inner surfaces of the substrate 102 that form one or more trenches 104. Opposite charge carriers within the substrate 102 can passivate defects within the substrate 102 (e.g., traps 122 configured to trap electrons within the substrate), thereby reducing unwanted currents (e.g., dark currents) within the substrate 102 and thus improving isolation between device region 106 and adjacent device regions.

[0030] Figure 2A Cross-sectional views of some additional embodiments of an integrated chip 200 including a trench isolation structure having a multilayer film stack configured to trap charge carriers are shown.

[0031] The integrated chip 200 includes a substrate 102. The substrate 102 includes a device region 106 having a semiconductor device (e.g., a transistor device, an image sensing element, etc.). The substrate 102 also includes one or more inner surfaces (e.g., sidewalls) forming one or more trenches 104 along opposite sides of the device region 106. In some embodiments, the one or more trenches 104 may have a depth 202 in the range of about 100 nanometers (nm) to about 10 micrometers, between 200 nm and about 5 micrometers, and / or other similar values.

[0032] A trench isolation structure 111 is disposed within one or more trenches 104. The trench isolation structure 111 includes a multilayer film stack 108 laterally surrounding a core material 110. In some embodiments, the core material 110 may include a conductive material, such as aluminum, tungsten, doped polysilicon, etc. In other embodiments, the core material 110 may include a dielectric material, such as a high-k dielectric material or a low-k dielectric material. For example, the dielectric material may include alumina, hafnium oxide, silicon oxide, silicon nitride, etc.

[0033] The multilayer film stack 108 includes a variety of dielectric materials 108a-108d stacked on top of each other. For example, the multilayer film stack 108 may include a first dielectric material 108a disposed on one or more inner surfaces of a substrate 102, a second dielectric material 108b stacked on the first dielectric material 108a, a third dielectric material 108c stacked on the second dielectric material 108b, and a fourth dielectric material 108d stacked on the third dielectric material 108c. In some embodiments, the multilayer film stack 108, the core material 110, and the substrate 102 may have substantially coplanar horizontally extending surfaces (e.g., planes within the tolerances of a chemical mechanical planarization (CMP) process).

[0034] Figure 2B Example performance band diagram 206 is shown in relation to the disclosed multilayer film stack 108. Example performance band diagram 206 is along... Figure 2A The line 204 was cut off.

[0035] As shown in band structure diagram 206, multiple dielectric materials 108a-108d have different electron affinities 208-214 (e.g., different energy values ​​between the conduction band energy 207 and vacuum energy 216 of the respective dielectric materials). The multiple dielectric materials 108a-108d are arranged such that the different electron affinities 208-214 form a potential well 120 within the multilayer film stack 108. For example, in some embodiments, a first dielectric material 108a may have a first electron affinity 208, a second dielectric material 108b may have a second electron affinity 210, a third dielectric material 108c may have a third electron affinity 212, and a fourth dielectric material 108d may have a fourth electron affinity 214. In some embodiments, the first electron affinity 208 and the third electron affinity 212 are less than the second electron affinity 210 to form a potential well 120 at a location corresponding to the second dielectric material 108b. In various embodiments, the first electron affinity 208 may be greater than, less than, or substantially equal to the third electron affinity 212. In various embodiments, the fourth electron affinity 214 may be greater than, less than, or substantially equal to the first electron affinity 208, the second electron affinity 210, and / or the third electron affinity 212.

[0036] In some embodiments, during the fabrication of the multilayer film stack 108, one or more processes (e.g., thermal treatment, electrical treatment, etc.) may be applied to the multilayer film stack 108. One or more processes cause charge carriers (e.g., electrons 114) from the substrate 102 and / or core material 110 to tunnel through a potential energy barrier formed by the first dielectric material 108a and / or the third dielectric material 108c and enter the potential well 120. The charge carriers become trapped in the potential well 120 and increase the charge of the multilayer film stack 108. This is because once the charge carriers enter the potential well 120, the different electron affinities of the different dielectric materials form an energy barrier that prevents the charge carriers from leaving the potential well 120. For example, in some embodiments, the first difference 218 between the first electron affinity 208 and the second electron affinity 210, and the second difference 220 between the second electron affinity 210 and the third electron affinity 212, may be greater than about 0.001 electron volts (eV), greater than about 0.01 eV, less than about 1 eV, greater than about 1 eV, or other similar values.

[0037] Refer again Figure 2A In some embodiments, the plurality of dielectric materials 108a-108d may have a total thickness 205 ranging from about 50 nanometers (nm) to about 100 nm. If the total thickness 205 is less than about 50 nm, the amount of charge in the multilayer stack 108 is insufficient to provide a passivation effect on defects within the substrate 102. If the total thickness 205 is greater than about 100 nm, the tunneling effect of charge carriers (e.g., electrons) from the substrate 102 to the potential well formed by the second dielectric material 108b will be reduced, thereby reducing the passivation effect on defects within the substrate 102. In some embodiments, the plurality of dielectric materials 108a-108d may have different thicknesses T1-T4. In other embodiments, the plurality of dielectric materials 108a-108d may have substantially equal thicknesses T1-T4.

[0038] In some embodiments, two or more of the plurality of dielectric materials 108a-108d may also have different oxygen densities. For example, in some embodiments, the first dielectric material 108a may have a first oxygen density, the second dielectric material 108b may have a second oxygen density, the third dielectric material 108c may have a third oxygen density, and the fourth dielectric material 108d may have a fourth oxygen density. The fourth oxygen density is greater than the third oxygen density. The greater fourth oxygen density causes oxygen in the fourth dielectric material 108d to diffuse into the third dielectric material 108c and form a dipole within the third dielectric material 108c. The oxygen dipole enhances the electric field generated by charge carriers (e.g., electrons) trapped in the potential well and / or by opposite charge carriers (e.g., holes) accumulated in the substrate 102 along one or more inner surfaces forming one or more trenches 104.

[0039] In some embodiments, the various dielectric materials 108a-108d may respectively include oxides, nitrides, dielectric materials, high-k dielectric materials, etc. In some embodiments, the first dielectric material 108a may include one or more of zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, and silicon oxide. In some embodiments, the second dielectric material 108b may include one or more of strontium titanium oxide, tantalum oxide, barium zirconium oxide, zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, and silicon nitride. In some embodiments, the third dielectric material 108c may include one or more of zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, and silicon oxide. In some embodiments, the fourth dielectric material 108d may include one or more of aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, hafnium oxide, magnesium oxide, scandium oxide, and silicon oxide.

[0040] Figure 3A Additional embodiments of an integrated chip 300 are shown, including a trench isolation structure having a multilayer film stack configured to trap charge carriers.

[0041] The integrated chip 300 includes a substrate 102 having one or more trenches 104 disposed along opposite sides of a device region 106 including semiconductor devices (e.g., transistor devices, image sensor elements, etc.). A trench isolation structure 111 is disposed within the one or more trenches 104. The trench isolation structure 111 includes a multilayer film stack 108 laterally surrounding a core material 110. In various embodiments, the core material 110 may include a conductive material (e.g., aluminum, tungsten, doped polysilicon, etc.) or a dielectric material (e.g., alumina, hafnium oxide, silicon oxide, silicon nitride, etc.).

[0042] The multilayer film stack 108 includes multiple dielectric materials 108a-108e stacked on top of each other. For example, the multilayer film stack 108 may include a first dielectric material 108a disposed on one or more inner surfaces of a substrate 102 forming one or more trenches 104, a second dielectric material 108b stacked on the first dielectric material 108a, a third dielectric material 108c stacked on the second dielectric material 108b, a fourth dielectric material 108d stacked on the third dielectric material 108c, and a fifth dielectric material 108e stacked on the fourth dielectric material 108d. In some embodiments, the multiple dielectric materials 108a-108e may have a total thickness 205 in the range of about 50 nanometers (nm) and about 100 nm. In some embodiments, the multilayer film stack 108 may include one or more additional dielectric materials.

[0043] In some embodiments, the various dielectric materials 108a-108e may respectively include oxides, nitrides, dielectric materials, high-k dielectric materials, etc. In some embodiments, the first dielectric material 108a may include one or more of zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In some embodiments, the second dielectric material 108b may include one or more of strontium titanium oxide, tantalum oxide, barium zirconium oxide, zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, etc. In some embodiments, the third dielectric material 108c may include one or more of zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In some embodiments, the fourth dielectric material 108d may include one or more of the following: strontium titanium oxide, tantalum oxide, barium zirconium oxide, zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, and silicon nitride. In some embodiments, the fifth dielectric material 108e may include one or more of the following: zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, and silicon oxide.

[0044] Various dielectric materials 108a-108e have different electron affinities (e.g., different energy values ​​between conduction band energy and vacuum energy) forming one or more potential wells within a multilayer film stack 108. Figure 3B and Figure 3C Example performance band diagrams related to the disclosed multilayer film stack 108 are shown. It should be understood that... Figure 3B and Figure 3C The example performance band diagrams shown are not limiting examples, and the disclosed multilayer film stacks may have band diagrams of optional shapes.

[0045] Figure 3B It shows along Figure 3A The example performance of line 302 is shown in Figure 304.

[0046] As shown in band structure diagram 304, the first dielectric material 108a has a first electron affinity 208, the second dielectric material 108b has a second electron affinity 210, the third dielectric material 108c has a third electron affinity 212, the fourth dielectric material 108d has a fourth electron affinity 214, and the fifth dielectric material 108e has a fifth electron affinity 306. The first electron affinity 208, the third electron affinity 212, and the fifth electron affinity 306 are less than the second electron affinity 210 and the fourth electron affinity 214, thereby forming a first potential well 120a at the location of the second dielectric material 108b and a second potential well 120b at the location of the fourth dielectric material 108d. In various embodiments, the first electron affinity 208 may be greater than, less than, or substantially equal to the third electron affinity 212 and the fifth electron affinity 306. In various embodiments, the second electron affinity 210 may be greater than, less than, or substantially equal to the fourth electron affinity 214. In some embodiments, the first potential well 120a and the second potential well 120b may each have a depth 308 greater than about 0.001 eV, greater than about 0.01 eV, less than about 1 eV, greater than about 1 eV, or other similar values.

[0047] In some embodiments, a process (e.g., heat treatment, electrical treatment, etc.) may be applied during the fabrication of the multilayer film stack 108 to cause electrons 114 from the substrate 102 and / or the core material 110 to tunnel through the potential energy barriers of the first dielectric material 108a and / or the fifth dielectric material 108e and enter the first potential well 120a and the second potential well 120b. The electrons 114 become trapped in the first potential well 120a and the second potential well 120b, and increase the charge of the multilayer film stack 108.

[0048] Figure 3C It shows along Figure 3A The example performance of line 302 is shown in Figure 310.

[0049] As shown in band structure diagram 310, the first electron affinity 208 and the fifth electron affinity 306 are less than the second electron affinity 210 and the fourth electron affinity 214, and the second electron affinity 210 and the fourth electron affinity 214 are less than the third electron affinity 212, so as to form a potential well 120 with stepped sides within the multilayer film stack 108. The stepped sides of the potential well 120 allow more electrons 114 to tunnel into the potential well 120, thereby increasing the passivation effect of charge within the multilayer film stack 108 and the trapped electrons 114 within the potential well 120. This is because the stepped sides of the potential well 120 allow the energy barrier formed by the first dielectric material 108a and / or the fifth dielectric material 108e to be thinner, thereby increasing the tunneling probability of electrons entering the potential well 120. Furthermore, electrons stored in the third dielectric material 108c have a reduced escape probability due to the depth of the stepped potential well 120 (e.g., due to external noise).

[0050] In various embodiments, the first electron affinity 208 may be greater than, less than, or substantially equal to the fifth electron affinity 306. In various embodiments, the second electron affinity 210 may be greater than, less than, or substantially equal to the fourth electron affinity 214. In some embodiments, the first difference 312 between the first electron affinity 208 and the second electron affinity 210, the second difference 314 between the second electron affinity 210 and the third electron affinity 212, the third difference 316 between the third electron affinity 212 and the fourth electron affinity 214, and the fourth difference 318 between the fourth electron affinity 214 and the fifth electron affinity 306 may be greater than about 0.001 eV, greater than about 0.01 eV, less than about 1 eV, or other similar values.

[0051] Figure 4A Cross-sectional views of some additional embodiments of an integrated chip 400 including a trench isolation structure having the disclosed multilayer film stack are shown.

[0052] Integrated chip 400 includes a substrate 102 having one or more trenches 104 arranged along opposite sides of device region 106. Device region 106 includes transistor device 402. Transistor device 402 includes a gate electrode 404 separated from substrate 102 by a gate dielectric 406. Source / drain regions 408 are arranged along opposite sides of gate electrode 404. Trench isolation structure 111 is disposed within one or more trenches 104. Trench isolation structure 111 includes a multilayer film stack 108 laterally surrounding core material 110.

[0053] An interlayer dielectric (ILD) structure 410 is disposed on a substrate 102. In some embodiments, the ILD structure 410 includes one or more interlayer dielectric (ILD) layers stacked on top of each other. The ILD structure 410 surrounds one or more interconnects 412. In some embodiments, the one or more interconnects 412 may include conductive contacts, mid-processing (MEOL) interconnects, interconnects, and / or interconnect vias. In some embodiments, the ILD structure 410 may include a contact etch stop layer (CESL) 414 disposed on the substrate 102. In some embodiments, the ILD structure 410 (e.g., CESL 414) may contact the top surface of a first dielectric material 108a, a second dielectric material 108b, a third dielectric material 108c, a fourth dielectric material 108d, and a core material 110.

[0054] Figure 4B Cross-sectional views of some additional embodiments of an integrated chip 416 including a trench isolation structure with the disclosed multilayer film stack are shown.

[0055] The integrated chip 416 includes a substrate 102 having one or more trenches 104 disposed along opposite sides of a device region 106 including a transistor device 402. A trench isolation structure 111 is disposed within the one or more trenches 104. The trench isolation structure 111 includes a multilayer film stack 108 laterally surrounding a core material 110. The core material 110 is conductive.

[0056] An ILD structure 410 is disposed on a substrate 102. The ILD structure 410 surrounds one or more interconnects 412. The one or more interconnects 412 are electrically coupled to a core material 110. The one or more interconnects 412 are configured to provide a voltage to the core material 110. The voltage can cause an electric field to be formed between the core material 110 and the substrate 102. The electric field attracts charge carriers (e.g., electrons) toward the core material 110. In some embodiments, charge carriers can tunnel into one or more potential wells within a multilayer film stack 108. In some embodiments, the one or more interconnects 412 can be coupled through substrate vias (TSVs) to one or more additional interconnects disposed along opposite sides of the substrate 102.

[0057] Figures 5A to 5B Some embodiments of an image sensor integrated chip including a trench isolation structure having the disclosed multilayer film stack are shown.

[0058] Figure 5A A cross-sectional view 500 is shown of some embodiments of an image sensor integrated chip including a trench isolation structure having the disclosed multilayer film stack.

[0059] As shown in cross-sectional view 500, the image sensor integrated chip includes a substrate 102 having a device region comprising a plurality of pixel regions 502a-502b. Each of the plurality of pixel regions 502a-502b includes an image sensing element 504 configured to convert incident radiation (e.g., photons) into electrical signals (i.e., to generate electron-hole pairs from the incident radiation). In some embodiments, the image sensing element 504 may include a photodiode.

[0060] Multiple gate structures 506 are arranged along a first side 102a of substrate 102. A dielectric structure 508 is also arranged along the first side 102a of substrate 102. The dielectric structure 508 surrounds multiple conductive interconnects 510. In some embodiments, the dielectric structure 508 includes multiple stacked ILD layers, and the multiple conductive interconnects 510 include alternating layers of conductive vias and wires electrically coupled to the multiple gate structures 506. In some embodiments, the multiple gate structures 506 may include multiple transfer gates.

[0061] In some embodiments, the second substrate 512 is coupled to the dielectric structure 508. A plurality of transistor devices 514 are disposed on the second substrate 512. In some embodiments, the plurality of transistor devices 514 may include a first type of transistor device 514a (e.g., an NMOS transistor) and a second type of transistor device 514b (e.g., a PMOS transistor). In some embodiments, the plurality of transistor devices 514 may be separated by a shallow trench isolation structure 516. In some embodiments, the plurality of transistor devices 514 may include support circuitry. For example, the plurality of transistor devices 514 may include one or more of a row decoder, pixel support device, reset driver, select driver, column amplifier and / or capacitor, column decoder (e.g., a multiplexer), analog-to-digital converter, etc.

[0062] Multiple pixel regions 502a-502b are separated by one or more trench isolation structures 111 disposed within one or more trenches extending from the second side 102b of the substrate 102 into the substrate 102. The one or more trench isolation structures 111 include a multilayer film stack 108 and a core material 110. In some embodiments, the one or more trench isolation structures 111 extend vertically from the second side 102b of the substrate to the first side 102a of the substrate 102. In some additional embodiments (not shown), the one or more trench isolation structures 111 extend vertically from the second side 102b of the substrate into a dielectric structure 508.

[0063] Figure 5B It shows Figure 5A Some embodiments of the disclosed image sensor integrated chip structure top view 518 are shown. In some embodiments, Figure 5A The cross-sectional view is taken along line A-A' of top view 518.

[0064] As shown in top view 518, a plurality of pixel regions 502a-502b are arranged in rows and columns in the substrate. Rows extend in a first direction 520, and columns extend in a second direction 522 perpendicular to the first direction 520. One or more trench isolation structures 111 are arranged along opposite sides of the plurality of pixel regions 502a-502b. In some embodiments, the one or more trench isolation structures 111 surround the plurality of pixel regions 502a-502b along the first direction 520 and the second direction 522. In some embodiments, the one or more trench isolation structures 111 continuously wrap around multiple sides of the respective plurality of pixel regions 502a-502b, as seen in top view 518. In some embodiments, the one or more trench isolation structures 111 may wrap the plurality of pixel regions 502a-502b in a closed and uninterrupted loop.

[0065] Figure 6 Cross-sectional views of some embodiments of an image sensor integrated chip 600 including a trench isolation structure having a disclosed multilayer film stack configured to trap charge carriers are shown.

[0066] Image sensor integrated chip 600 includes a plurality of gate structures 506 disposed along a first side 102a (e.g., front side) of substrate 102. The plurality of gate structures 506 each include a gate dielectric layer 506d disposed along the first side 102a of substrate 102 and a gate electrode 506e disposed on the gate dielectric layer 506d. In some embodiments, sidewall spacers 506s are disposed on opposite sides of the gate electrode 506e. In some embodiments, the gate structure 506 corresponding to a transmission transistor is laterally disposed between a photodiode 602 and a floating diffusion well 604 within substrate 102. In such an embodiment, the photodiode 602 may include a first region 601 having a first doping type (e.g., n-type doping) and an adjacent second region 603 having a second doping type different from the first doping type (e.g., p-type doping). The gate structures 506 are configured to control charge transfer from the photodiode 602 to the floating diffusion well 604. If the charge level is sufficiently high within the floating diffusion well 604, the source follower transistor (not shown) is activated, and the charge is selectively output according to the operation of the row selection transistor (not shown) used for addressing. A reset transistor (not shown) is configured to reset photodiode 602 between exposure cycles.

[0067] The dielectric structure 508 is also disposed along a first side 102a (e.g., the front side) of the substrate 102. The dielectric structure 508 may include a plurality of stacked ILD layers. In various embodiments, the plurality of stacked ILD layers may include one or more of oxides (e.g., SiO2, SiCO, etc.), fluorosilicate glasses, phosphate glasses (e.g., borosilicate glasses), etc. The dielectric structure 508 surrounds a plurality of conductive interconnects 510 electrically coupled to the gate structure 506. In some embodiments, the plurality of conductive interconnects 510 may include one or more of copper, aluminum, tungsten, and carbon nanotubes, etc. In some embodiments, the dielectric structure 508 is coupled to a second substrate 512 (e.g., a carrier substrate). In some embodiments, the second substrate 512 may include silicon.

[0068] In some embodiments, a plurality of shallow trench isolation (STI) structures 606 are also disposed within a first side 102a of the substrate 102. The plurality of STI structures 606 include one or more dielectric materials (e.g., SiO2) disposed within trenches in the first side 102a of the substrate 102. A plurality of trench isolation structures 111 are disposed within one or more trenches in a second side 102b (e.g., the back side) of the substrate 102 above the plurality of STI structures 606. The plurality of trench isolation structures 111 include a multilayer film stack 108 surrounding a core material 110. In some embodiments, the plurality of trench isolation structures 111 may each have a width smaller than that of one of the plurality of STI structures 606. In some embodiments, one or more isolation well regions (not shown) may be disposed between the plurality of STI structures 606 and the plurality of trench isolation structures 111. The one or more isolation well regions may include doped regions that provide further isolation between adjacent plurality of pixel regions 502a-502b via junction isolation.

[0069] In some embodiments, the dielectric structure 609 is disposed along a second side 102b of the substrate 102. The dielectric structure 609 may include an anti-reflection structure 608 and a dielectric planarization structure 610 having a substantially flat surface facing away from the substrate 102. In some embodiments, the anti-reflection structure 608 may include a high-k dielectric layer, including hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), oxides (e.g., silicon oxide), TEOS, etc. In various embodiments, the dielectric planarization structure 610 may include oxides (e.g., SiO2) and / or nitrides.

[0070] A grid structure 612 is disposed on a dielectric structure 609. The grid structure 612 includes sidewalls forming openings located above a plurality of pixel regions 502a-502c. In various embodiments, the grid structure 612 may include a metal (e.g., aluminum, cobalt, copper, silver, gold, tungsten, etc.) and / or a dielectric material (e.g., SiO2, SiN, etc.). A plurality of color filters 614a-614c are arranged within the openings in the grid structure 612. The plurality of color filters 614a-614c are each configured to transmit incident radiation of a specific wavelength. For example, a first color filter 614a may transmit radiation having a wavelength within a first range (e.g., corresponding to green light), while a second color filter 614b may transmit radiation having a wavelength within a second range different from the first range (e.g., corresponding to red light), etc. A plurality of microlenses 616 are arranged above the plurality of color filters 614a-614c. A plurality of microlenses 616 are laterally aligned with a plurality of color filters 614a-614c and are located on a plurality of pixel regions 502a-502c. The plurality of microlenses 616 are configured to focus incident radiation (e.g., light) toward the plurality of pixel regions 502a-502c.

[0071] In some embodiments, one or more conductive wiring layers 618 may be disposed on or within the dielectric structure 609. The one or more conductive wiring layers 618 electrically couple the core material 110 to the bias source 620 (e.g., via a port located outside the pixel regions 502a-502c). In some embodiments, the one or more conductive wiring layers 618 may be disposed below the grid structure 612 so as not to obstruct incident radiation reaching the plurality of pixel regions 502a-502c.

[0072] Figures 7A to 7B Some embodiments of an image sensor integrated chip are shown, including a trench isolation structure having a disclosed multilayer film stack configured to trap charge carriers.

[0073] like Figure 7A As shown in cross-sectional view 700, the image sensor integrated chip includes a substrate 102 having a device region comprising a plurality of pixel regions 502a-502b. Each of the plurality of pixel regions 502a-502b includes an image sensing element 504 (e.g., a photodiode). In some embodiments, the plurality of pixel regions 502a-502b may be portions of a dual photodiode pixel region 502 configured to include a pair of photodiodes. A plurality of gate structures 506 are arranged along a first side 102a of the substrate 102. A dielectric structure 508 is also arranged along the first side 102a of the substrate 102. The dielectric structure 508 surrounds a plurality of conductive interconnects 510.

[0074] Multiple pixel regions 502a-502b are separated by trench isolation structures 111a-111b disposed within one or more trenches extending from the second side 102b of the substrate 102 into the substrate 102. The trench isolation structures 111a-111b include a multilayer film stack 108 and a core material 110. The trench isolation structures 111a-111b may include one or more first trench isolation structures 111a and one or more second trench isolation structures 111b. The one or more first trench isolation structures 111a extend vertically from the second side 102b of the substrate to the first side 102a of the substrate 102. In some embodiments, the one or more first trench isolation structures 111a extend vertically from the second side 102b of the substrate into a dielectric structure 508. The one or more second trench isolation structures 111b extend vertically from the second side 102b of the substrate to a non-zero distance from the first side 102a of the substrate 102.

[0075] Figure 7B It shows Figure 7A Some embodiments of the disclosed top view 702 of the image sensor integrated chip structure. In some embodiments, Figure 7A The cross-sectional view is taken along line A-A' of top view 702.

[0076] Top view 702 shows one or more first trench isolation structures 111a arranged around the periphery of a plurality of pixel regions 502a-502b, while one or more second trench isolation structures 111b separate adjacent plurality of pixel regions 502a-502b.

[0077] In various embodiments, the disclosed trench isolation structure may be disposed in one or more trenches arranged along different sides of the substrate and / or extending to different depths within the substrate. Figures 8 to 11 Additional embodiments of image sensor integrated chips with different configurations of trench isolation structures are shown.

[0078] Figure 8 Cross-sectional views of some embodiments of an image sensor integrated chip 800 including multiple trench isolation structures having disclosed multilayer film stacks are shown.

[0079] The image sensor integrated chip 800 includes a substrate 102 having multiple pixel regions 502a-502b, each including an image sensing element 504. Multiple gate structures 506 are disposed along a first side 102a (e.g., front side) of the substrate 102. A dielectric structure 508 is disposed on the first side 102a of the substrate 102 and around the multiple gate structures 506. Multiple color filters 614 are disposed on a second side 102b (e.g., back side) of the substrate 102 opposite to the first side 102a. Multiple microlenses 616 are arranged on the multiple color filters 614.

[0080] Multiple trench isolation structures 111 are disposed along opposite sides of multiple pixel regions 502a-502b. The multiple trench isolation structures 111 extend through a portion but not all of the substrate 102 (e.g., from a second side 102b of the substrate 102 to a non-zero distance from a first side 102a of the substrate 102). In some embodiments, the multiple trench isolation structures 111 have a width that decreases toward the first side 102a of the substrate 102. Each of the multiple trench isolation structures 111 includes a multilayer film stack 108 surrounding a core material 110. In some embodiments, the multilayer film stack 108 extends around the core material 110 and has an open end along the second side 102b of the substrate 102.

[0081] Figure 9 Cross-sectional views of some embodiments of an image sensor integrated chip 900 including multiple trench isolation structures having disclosed multilayer film stacks are shown.

[0082] The image sensor integrated chip 900 includes a substrate 102 having multiple pixel regions 502a-502b, each including an image sensing element 504. Multiple gate structures 506 are disposed along a first side 102a (e.g., front side) of the substrate 102. A dielectric structure 508 is disposed on the first side 102a of the substrate 102 and around the multiple gate structures 506. Multiple color filters 614 are disposed on a second side 102b (e.g., back side) of the substrate 102 opposite to the first side 102a. Multiple microlenses 616 are arranged on the multiple color filters 614.

[0083] Multiple trench isolation structures 111 are disposed along opposite sides of multiple pixel regions 502a-502b. The multiple trench isolation structures 111 extend completely through the substrate 102 (e.g., from a first side 102a of the substrate 102 to a second side 102b of the substrate 102). In some embodiments, the multiple trench isolation structures 111 have a width that decreases toward the second side 102b of the substrate 102. Each of the multiple trench isolation structures 111 includes a multilayer film stack 108 surrounding a core material 110. In some embodiments, the multilayer film stack 108 extends around the core material 110 and has an open end along the first side 102a of the substrate 102.

[0084] Figure 10 Cross-sectional views of some embodiments of an image sensor integrated chip 1000 including multiple trench isolation structures having disclosed multilayer film stacks are shown.

[0085] The image sensor integrated chip 1000 includes a substrate 102 having multiple pixel regions 502a-502b, each including an image sensing element 504. Multiple gate structures 506 are disposed along a first side 102a (e.g., front side) of the substrate 102. A dielectric structure 508 is disposed on the first side 102a of the substrate 102 and around the multiple gate structures 506. Multiple color filters 614 are disposed on a second side 102b (e.g., back side) of the substrate 102 opposite to the first side 102a. Multiple microlenses 616 are arranged on the multiple color filters 614.

[0086] Multiple trench isolation structures 111 are disposed along opposite sides of multiple pixel regions 502a-502b. The multiple trench isolation structures 111 include one or more first trench isolation structures 111a that extend completely through the substrate 102 (e.g., from a first side 102a of the substrate 102 to a second side 102b of the substrate 102) and one or more second trench isolation structures 111b that extend partially but not entirely through the substrate 102 (e.g., from the first side 102a of the substrate 102 to a non-zero distance from the second side 102b of the substrate 102). In some embodiments, the multiple trench isolation structures 111 have a width that decreases toward the second side 102b of the substrate 102. Each of the multiple trench isolation structures 111 includes a multilayer film stack 108 surrounding a core material 110. In some embodiments, the multilayer film stack 108 extends around the core material 110 and has an open end along the first side 102a of the substrate 102.

[0087] Figure 11 Cross-sectional views of some embodiments of an image sensor integrated chip 1100 including multiple trench isolation structures having disclosed multilayer film stacks are shown.

[0088] The image sensor integrated chip 1100 includes a substrate 102 having multiple pixel regions 502a-502b, each including an image sensing element 504. Multiple gate structures 506 are disposed along a first side 102a (e.g., front side) of the substrate 102. A dielectric structure 508 is disposed on the first side 102a of the substrate 102 and around the multiple gate structures 506. Multiple color filters 614 are disposed on a second side 102b (e.g., back side) of the substrate 102 opposite to the first side 102a. Multiple microlenses 616 are arranged on the multiple color filters 614.

[0089] Multiple trench isolation structures 111 are disposed along opposite sides of multiple pixel regions 502a-502b. The multiple trench isolation structures 111 extend through a portion but not all of the substrate 102 (e.g., from a first side 102a of the substrate 102 to a non-zero distance from a second side 102b of the substrate 102). In some embodiments, the multiple trench isolation structures 111 have a width that decreases toward the second side 102b of the substrate 102. Each of the multiple trench isolation structures 111 includes a multilayer film stack 108 surrounding a core material 110. In some embodiments, the multilayer film stack 108 extends around the core material 110 and has an open end along the first side 102a of the substrate 102.

[0090] Figures 12 to 26 Cross-sectional views 1200-2600 illustrate some embodiments of a method for forming an integrated chip including a trench isolation structure having a multilayer film stack configured to trap one or more potential wells for capturing charge carriers. Although Figures 12 to 26 The cross-sectional diagrams shown in Figures 1200-2600 are described using the reference method, but it should be understood that... Figures 12 to 26 The structures shown are not limited to the method of formation, but can exist independently of the method.

[0091] like Figure 12 As shown in cross-sectional view 1200, a substrate 102 is provided. In various embodiments, the substrate 102 can be any type of substrate, such as a semiconductor wafer (e.g., silicon, SiGe, SOI, etc.), and any other type of semiconductor and / or epitaxial layer associated therewith. The substrate 102 has a first side 102a and a second side 102b opposite to the first side 102a. In some embodiments, the substrate 102 can be coupled to a carrier substrate 1202 and then thinned to reduce the thickness of the substrate 102. In some embodiments, an etching process or a mechanical polishing process can be used to thin the substrate 102.

[0092] like Figure 13As shown in cross-sectional view 1300, an image sensing element 504 is formed within a plurality of pixel regions 502a-502b within a substrate 102. In some embodiments, the image sensing element 504 may comprise a photodiode formed by implanting one or more dopant materials into a first side 102a of the substrate 102. For example, the image sensing element 504 may be formed by selectively performing a first implantation process (e.g., according to a masking layer) to form a first region having a first doping type (e.g., n-type) and subsequently performing a second implantation process to form a second region adjacent to the first region and having a second doping type (e.g., p-type) different from the first doping type. In some embodiments, either the first implantation process or the second implantation process may also be used to form a floating diffusion well (not shown). In some embodiments, one or more shallow trench isolation (STI) structures 606 may be formed within the first side 102a of the substrate along opposite sides of the plurality of pixel regions 502a-502b.

[0093] like Figure 14 As shown in cross-sectional view 1400, a plurality of gate structures 506 are formed along a first side 102a of substrate 102. In some embodiments, the plurality of gate structures 506 may be formed by forming a gate dielectric layer on the first side 102a of substrate 102. In some embodiments, the gate dielectric layer may be deposited by a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), atomic layer deposition (ALD), sputtering deposition, etc.). One or more gate electrodes are formed over the gate dielectric layer. In some embodiments, the one or more gate electrodes are formed by depositing a gate electrode layer on the gate dielectric layer and a subsequent selective etching patterning process of the gate electrode layer and the gate dielectric layer.

[0094] like Figure 15As shown in cross-section 1500, one or more conductive interconnects 510 are formed within a dielectric structure 508 formed along a first side 102a of substrate 102. The dielectric structure 508 includes a plurality of stacked ILD layers, and the one or more conductive interconnects 510 include alternating layers of wires and vias. In some embodiments, one or more of the conductive interconnects 510 may be formed using a damascene process (e.g., a single damascene process or a double damascene process). The damascene process is implemented by: forming an ILD layer over the first side 102a of substrate 102; etching the ILD layer to form vias and / or trenches; and filling the vias and / or trenches with a conductive material. In some embodiments, the ILD layer may be deposited using physical vapor deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, etc.), and the conductive material may be formed using deposition processes and / or plating processes (e.g., electroplating, electroless plating, etc.). In various embodiments, the conductive material may include tungsten, copper, aluminum, copper, etc.

[0095] In some embodiments (not shown), the carrier substrate 1202 may be removed after the dielectric structure 508 is formed. In some embodiments, the substrate 102 may be thinned to reduce the thickness of the substrate 102 after the carrier substrate 1202 is removed. In some embodiments, the dielectric structure 508 may be bonded to an additional support substrate before the substrate 102 is thinned.

[0096] like Figure 16 As shown in cross-sectional view 1600, a mask 1602 is formed along a second side 102b (e.g., the back side) of a substrate 102. The mask 1602 includes sidewalls forming openings along the second side 102b of the substrate 102. In some embodiments, the mask 1602 can be formed by depositing a layer of photosensitive material (e.g., positive or negative photoresist) along the second side 102b of the substrate 102. Depending on the photomask, the photosensitive material layer is selectively exposed to electromagnetic radiation. The electromagnetic radiation modifies the solubility of the exposed regions within the photosensitive material to form soluble regions. The photosensitive material is then developed to form openings within the photosensitive material by removing the soluble regions.

[0097] A patterning process is performed on a second side 102b of substrate 102 according to mask 1602. The patterning process forms one or more trenches 104 within the second side 102b of substrate 102. The one or more trenches 104 extend vertically from the second side 102b of substrate 102 into the substrate 102 along opposite sides of a plurality of pixel regions 502a-502b. In some embodiments, the patterning process may selectively expose substrate 102 to one or more etchants 1604 (e.g., one or more dry etchants) according to mask 1602. In some embodiments, the one or more etchants 1604 may have an etching chemical substance including one or more of oxygen (O2), nitrogen (N2), hydrogen (H2), argon (Ar) and / or fluorine substances (e.g., CF4, CHF3, C4F8, etc.).

[0098] like Figure 17 As shown in cross-sectional view 1700, a first dielectric layer 1702 is formed on a second side 102b of a substrate 102 and within one or more trenches 104. The first dielectric layer 1702 may be formed conformally to line the sidewalls of the substrate 102. The first dielectric layer 1702 has a first electron affinity. In some embodiments, the first dielectric layer 1702 may include one or more of zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In various embodiments, the first dielectric layer 1702 may be deposited by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputtering deposition process, etc.).

[0099] like Figure 18 As shown in cross-sectional view 1800, a second dielectric layer 1802 is formed on the first dielectric layer 1702 and within one or more trenches 104. The second dielectric layer 1802 may be formed to conformally line the sidewalls of the first dielectric layer 1702. The second dielectric layer 1802 has a second electron affinity. In some embodiments, the second dielectric layer 1802 may include one or more of strontium titanium oxide, tantalum oxide, barium zirconium oxide, zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, etc. In various embodiments, the second dielectric layer 1802 may be deposited by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputtering deposition process, etc.).

[0100] like Figure 19As shown in cross-sectional view 1900, a third dielectric layer 1902 is formed on the second dielectric layer 1802 and within one or more trenches 104. The third dielectric layer 1902 may be formed conformally to line the sidewalls of the second dielectric layer 1802. The third dielectric layer 1902 has a third electron affinity. In some embodiments, the third dielectric layer 1902 may include one or more of zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In various embodiments, the third dielectric layer 1902 may be deposited by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputtering deposition process, etc.).

[0101] like Figure 20 As shown in cross-sectional view 2000, a fourth dielectric layer 2002 is formed on the third dielectric layer 1902 and within one or more trenches 104 to form a multilayer film stack 108 within the one or more trenches 104. The fourth dielectric layer 2002 may be formed conformally lining the sidewalls of the third dielectric layer 1902. The fourth dielectric layer 2002 has a fourth electron affinity. In some embodiments, the fourth dielectric layer 2002 may have a higher oxygen density than the third dielectric layer 1902. In some embodiments, the fourth dielectric layer 2002 may include one or more of aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, hafnium oxide, magnesium oxide, scandium oxide, silicon oxide, etc. In various embodiments, the fourth dielectric layer 2002 may be deposited by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputtering deposition process, etc.).

[0102] In some embodiments (not shown), one or more additional dielectric layers may be formed within one or more trenches to form a multilayer film stack 108. For example, in some embodiments, a fifth dielectric layer may be formed on the fourth dielectric layer and within one or more trenches 104 to form the multilayer film stack 108. The fifth dielectric layer may be formed to conformally line the sidewalls of the fourth dielectric layer 2002. The fifth dielectric layer has a fifth electron affinity. In some embodiments, the fifth dielectric layer may have a higher oxygen density than the fourth dielectric layer 2002. In some embodiments, the fifth dielectric layer may include one or more of zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In various embodiments, the fifth dielectric layer may be deposited by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputtering deposition process, etc.).

[0103] like Figure 21As shown in cross-sectional view 2100, a core layer 2102 is formed within one or more trenches 104 and between the sidewalls of the fourth dielectric layer 2002. In some embodiments, the core layer 2102 may include a conductive material, while in other embodiments, the core layer 2102 may include a dielectric material. In some embodiments, the core layer 2102 may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering deposition, etc.) and / or a plating process (e.g., electroplating, electroless plating, etc.).

[0104] like Figure 22 As shown in cross-sectional view 2200, a planarization process (along line 2202) is performed to remove portions of the multilayer film stack 108. The planarization process may remove the first dielectric layer (e.g., Figure 21 1702), the second dielectric layer (e.g., Figure 21 1802), the third dielectric layer (e.g., Figure 21 1902), the fourth dielectric layer (e.g., Figure 21 (2002) and core layer (e.g., Figure 21 The portion of 2102 located outside one or more trenches 104. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. In other embodiments, the planarization process may include an etching process, a grinding process, etc.

[0105] A planarization process forms one or more trench isolation structures 111 within one or more trenches 104 in a substrate 102. The one or more trench isolation structures 111 include a multilayer film stack 108 and a core material 110. The multilayer film stack 108 includes multiple dielectric materials 108a-108d stacked on top of each other. For example, the multilayer film stack 108 may include a first dielectric material 108a, a second dielectric material 108b stacked on the first dielectric material 108a, a third dielectric material 108c stacked on the second dielectric material 108b, and a fourth dielectric material 108d stacked on the third dielectric material 108c.

[0106] Two or more of the various dielectric materials 108a-108d have different electron affinities. The various dielectric materials 108a-108d are arranged to provide a conduction band for the multilayer film stack 108 having one or more potential wells. For example, in some embodiments, the second electron affinity is greater than the first and third electron affinity to form a potential well at a location corresponding to the second dielectric material 108b. In some embodiments, the second and fourth electron affinity are greater than the first, third, and fifth electron affinity to form potential wells at locations corresponding to the second and fourth dielectric materials 108b and 108d. In other embodiments, the second and fourth electron affinity are greater than the first and fifth electron affinity and less than the third electron affinity to form a stepped potential well.

[0107] A dielectric structure 609 is formed along the second side 102b of the substrate 102. In some embodiments, the dielectric structure 609 may physically contact the surfaces of the first dielectric material 108a, the second dielectric material 108b, the third dielectric material 108c, the fourth dielectric material 108d, and the core material 110.

[0108] like Figure 23A As shown in cross-sectional view 2300, a thermal process 2302 is performed on substrate 102. In some embodiments, thermal process 2302 may include furnace processing, rapid thermal annealing, etc. Thermal process 2302 causes charge carriers (e.g., electrons) from substrate 102 and / or core material 110 to tunnel into a potential well within multilayer film stack 108. In some embodiments, thermal process 2302 may be performed by exposing substrate 102 to a high temperature greater than about 100°C, greater than about 500°C, in the range between about 100°C and about 1000°C, or other similar values. In some embodiments, thermal process 2302 may expose substrate 203 to a high temperature for a time greater than about 1 minute, between about 1 minute and about 2 minutes, between about 1 minute and about 5 minutes, or other similar values.

[0109] In some alternative embodiments, Figure 23B As shown in cross-sectional view 2304, one or more conductive wiring layers 618 may be formed on or within the dielectric structure 609. The one or more conductive wiring layers 618 are electrically coupled to the core material 110. The one or more conductive wiring layers 618 may be used to apply a bias voltage to the core material 110. The voltage bias causes charge carriers (e.g., electrons or holes) to tunnel from the substrate 102 and / or the core material 110 into a potential well within the multilayer film stack 108. In some embodiments, the bias voltage may have a range between about -5 volts and about 5 volts.

[0110] like Figure 24As shown in cross-sectional view 2400, a grid structure 612 is formed on the dielectric structure 609. The grid structure 612 may include metal formed directly above one or more trench isolation structures 111. In some embodiments, the grid structure 612 may be formed by a deposition process and / or a plating process followed by an etching process.

[0111] like Figure 25 As shown in cross-sectional view 2500, a plurality of color filters 614a-614b are formed above dielectric structure 609 and between the sidewalls of grid structure 612. In some embodiments, the plurality of color filters 614a-614b are formed by depositing a light-filtering material on substrate 102 (e.g., via CVD, PVD, ALD, sputtering, spin coating, etc.). The light-filtering material is a material that allows the transmission of radiation (e.g., light) having a specific wavelength range while blocking light of wavelengths outside the specific range. In some embodiments, a planarization process (e.g., CMP) may then be performed on the plurality of color filters 614a-614b to planarize the upper surfaces of the plurality of color filters 614a-614b.

[0112] like Figure 26 As shown in cross-sectional view 2600, a plurality of microlenses 616 are formed above a plurality of color filters 614a-614b. In some embodiments, the plurality of microlenses 616 can be formed by depositing (e.g., via CVD, PVD, ALD, sputtering, spin coating, etc.) a microlens material on the plurality of color filters 614a-614b. A microlens template (not shown) having a curved upper surface is patterned on the microlens material. In some embodiments, the microlens template may include a photoresist material exposed using a distributed exposure light dose (e.g., for a negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed, and baked to form a circular shape. The plurality of microlenses 616 are then formed according to the microlens template by selectively etching the microlens material.

[0113] Figure 27 Flowcharts are shown of some embodiments of a method 2700 for forming an integrated chip including a trench isolation structure having a multilayer film stack configured to trap charge carriers.

[0114] Although method 2700 is shown and described herein as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events besides those shown and / or described herein. Furthermore, not all steps shown may be necessary to implement one or more aspects or embodiments described herein. Additionally, one or more of the steps depicted herein may be performed in one or more separate steps and / or stages.

[0115] In step 2702, one or more semiconductor devices are formed in the device region of the substrate. In some embodiments, the one or more semiconductor devices may include image sensing elements (e.g., photodiodes), transistor devices, etc. Figure 13 and / or Figure 14 Cross-sectional views 1300 and / or 1400 corresponding to some embodiments of step 2702 are shown.

[0116] In step 2704, one or more trenches are formed in the substrate. Figure 16 A cross-sectional view 1600 is shown, corresponding to some embodiments of step 2704.

[0117] In step 2706, a multilayer film stack is formed within one or more trenches. The multilayer film stack comprises multiple films with different electron affinities. The different electron affinities form one or more potential wells within the multilayer film stack. In some embodiments, the multilayer film stack can be formed according to steps 2708-2714.

[0118] In step 2708, a first dielectric layer having a first electron affinity is formed along the inner surface of the substrate and in one or more trenches. Figure 17 A cross-sectional view 1700 is shown, corresponding to some embodiments of step 2708.

[0119] In step 2710, a second dielectric layer having a second electron affinity is formed along the inner surface of the first dielectric layer and in one or more trenches. Figure 18 A cross-sectional view 1800 is shown corresponding to some embodiments of step 2710.

[0120] In step 2712, a third dielectric layer having a third electron affinity is formed along the inner surface of the second dielectric layer and in one or more trenches. Figure 19 A cross-sectional view 1900 is shown, corresponding to some embodiments of step 2712.

[0121] In step 2714, a fourth dielectric layer having a fourth electron affinity is formed along the inner surface of the third dielectric layer and in one or more trenches. Figure 20 Cross-sectional view 2000 is shown for some embodiments corresponding to step 2714.

[0122] In step 2716, a core material is formed along the inner surface of the fourth dielectric film and within one or more trenches. Figure 21 A cross-sectional view 2100 corresponding to some embodiments of step 2716 is shown.

[0123] In step 2718, a planarization process is performed to remove portions of the core material and multilayer film stack. Figure 22 A cross-sectional view 2200 is shown, corresponding to some embodiments of step 2718.

[0124] In step 2720, one or more processes are performed to drive charge carriers (e.g., electrons) into one or more potential wells within the multilayer film stack. In some embodiments, one or more processes may include one or more of thermal processes, the application of bias voltages, etc. Figure 23A Cross-sectional view 2300 is shown for some embodiments corresponding to step 2720. Figure 23B Cross-sectional view 2304 is shown, corresponding to some alternative embodiments of step 2720.

[0125] In step 2722, a plurality of color filters and microlenses are formed on the substrate. Figures 24 to 26 Cross-sectional views 2300-2500 are shown for some embodiments corresponding to step 2722.

[0126] Therefore, in some embodiments, this disclosure relates to an integrated chip including a trench isolation structure of a disclosed multilayer film stack having one or more potential wells configured to trap charge carriers (e.g., electrons).

[0127] In some embodiments, this disclosure relates to an integrated chip. The integrated chip includes: a substrate having a device region having one or more semiconductor devices, the substrate having one or more inner surfaces forming one or more trenches along opposite sides of the device region; a multilayer film stack disposed along one or more inner surfaces of the substrate; a core material disposed within the one or more trenches and surrounded by the multilayer film stack; and the multilayer film stack including multiple dielectric materials each having different electron affinities, the multiple dielectric materials being arranged to form one or more potential wells within the multilayer film stack. In some embodiments, the device region includes an image sensing element configured to convert radiation into an electrical signal. In some embodiments, the multilayer film stack includes: a first dielectric material having a first electron affinity; a second dielectric material having a second electron affinity greater than the first electron affinity; a third dielectric material having a third electron affinity less than the second electron affinity; and a fourth dielectric material having a fourth electron affinity. In some embodiments, the fourth dielectric material has a higher oxygen density than the third dielectric material. In some embodiments, the conductive bands of the multilayer film stack are symmetrical. In some embodiments, the conductive bands of the multilayer film stack are asymmetrical. In some embodiments, one or more potential wells include two potential wells. In some embodiments, the multilayer film stack has a thickness in the range of about 50 nanometers and about 100 nanometers.

[0128] In other embodiments, this disclosure relates to an integrated chip. The integrated chip includes: a substrate having pixel regions, the pixel regions having image sensing elements configured to convert radiation into electrical signals; one or more trench isolation structures disposed within the substrate along opposite sides of the pixel regions, the one or more trench isolation structures including: a first dielectric material having a first electron affinity; a second dielectric material disposed on the first dielectric material and having a second electron affinity; a third dielectric material disposed on the second dielectric material and having a third electron affinity; a fourth dielectric material disposed on the third dielectric material and having a fourth electron affinity; and a core material disposed on the fourth dielectric material; the second electron affinity is greater than the first electron affinity and the third electron affinity. In some embodiments, the difference between the first electron affinity and the second electron affinity is greater than 0.001 electron volts (eV). In some embodiments, the one or more trench isolation structures further include: a fifth dielectric material disposed on the fourth dielectric material, the fifth dielectric material having a fifth electron affinity less than the fourth electron affinity. In some embodiments, the integrated chip further includes: a dielectric structure disposed on a substrate and contacting the top surface of a first dielectric material, a second dielectric material, a third dielectric material, a fourth dielectric material, and a core material. In some embodiments, the integrated chip further includes: one or more conductive wiring layers located within the dielectric structure, the one or more conductive wiring layers contacting the core material, the core material being a conductive material.

[0129] In some other embodiments, this disclosure relates to a method of forming an integrated chip. The method includes: forming a semiconductor device within a substrate having a first side and a second side; etching the second side of the substrate to form one or more trenches within the substrate along opposite sides of the semiconductor device; forming a multilayer film stack within the one or more trenches and along the second side of the substrate, the multilayer film stack having multiple dielectric materials with different electron affinities forming one or more potential wells; and forming a core material within the one or more trenches and on the multilayer film stack. In some embodiments, forming the multilayer film stack includes: forming a first dielectric layer having a first electron affinity; forming a second dielectric layer having a second electron affinity greater than the first electron affinity; forming a third dielectric layer having a third electron affinity less than the second electron affinity; and forming a fourth dielectric layer having a fourth electron affinity. In some embodiments, the method further includes: performing a planarization process to remove portions of the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, and the core material from the second side of the substrate. In some embodiments, the one or more potential wells include a potential well located at a position corresponding to the second dielectric layer and surrounded by energy barriers corresponding to the first and third dielectric layers. In some embodiments, the fourth dielectric layer has a larger oxygen density than the third dielectric layer. In some embodiments, the method further includes performing a thermal process to cause charge carriers to tunnel through the one or more energy barriers and into the one or more potential wells. In some embodiments, the method further includes applying a bias voltage across the multilayer film stack to cause charge carriers to tunnel through the one or more energy barriers and into the one or more potential wells.

[0130] Some embodiments of this application provide an integrated chip, comprising: a substrate having a device region including one or more semiconductor devices, wherein the substrate has one or more inner surfaces forming one or more trenches along opposite sides of the device region; a multilayer film stack disposed along the one or more inner surfaces of the substrate; a core material disposed within the one or more trenches and surrounded by the multilayer film stack; and wherein the multilayer film stack includes a plurality of dielectric materials having different electron affinities, the plurality of dielectric materials being arranged to form one or more potential wells within the multilayer film stack.

[0131] In some embodiments, the device region includes an image sensing element configured to convert radiation into an electrical signal. In some embodiments, the multilayer film stack includes: a first dielectric material having a first electron affinity; a second dielectric material having a second electron affinity greater than the first electron affinity; a third dielectric material having a third electron affinity less than the second electron affinity; and a fourth dielectric material having a fourth electron affinity. In some embodiments, the fourth dielectric material has a greater oxygen density than the third dielectric material. In some embodiments, the conductive band structure of the multilayer film stack is symmetrical. In some embodiments, the conductive band structure of the multilayer film stack is asymmetrical. In some embodiments, the one or more potential wells include two potential wells. In some embodiments, the multilayer film stack has a thickness in the range of about 50 nanometers to about 100 nanometers.

[0132] Other embodiments of this application provide an integrated chip, comprising: a substrate having a pixel region including an image sensing element configured to convert radiation into an electrical signal; one or more trench isolation structures disposed within the substrate along opposite sides of the pixel region, wherein the one or more trench isolation structures include: a first dielectric material having a first electron affinity; a second dielectric material disposed on the first dielectric material and having a second electron affinity; a third dielectric material disposed on the second dielectric material and having a third electron affinity; a fourth dielectric material disposed on the third dielectric material and having a fourth electron affinity; and a core material disposed on the fourth dielectric material; and wherein the second electron affinity is greater than the first electron affinity and the third electron affinity.

[0133] In some embodiments, the difference between the first electron affinity and the second electron affinity is greater than 0.001 electron volts (eV). In some embodiments, the one or more trench isolation structures further include: a fifth dielectric material disposed on the fourth dielectric material, wherein the fifth dielectric material has a fifth electron affinity less than the fourth electron affinity. In some embodiments, the integrated chip further includes: a dielectric structure disposed on the substrate and contacting the topmost surface of the first dielectric material, the second dielectric material, the third dielectric material, the fourth dielectric material, and the core material. In some embodiments, the integrated chip further includes: one or more conductive wiring layers located within the dielectric structure, the one or more conductive wiring layers contacting the core material, wherein the core material is a conductive material.

[0134] Further embodiments of this application provide a method for forming an integrated chip, comprising: forming a semiconductor device in a substrate having a first side and a second side; etching the second side of the substrate to form one or more trenches in the substrate along opposite sides of the semiconductor device; forming a multilayer film stack in the one or more trenches and along the second side of the substrate, wherein the multilayer film stack includes a plurality of dielectric materials having different electron affinities forming one or more potential wells; and forming a core material in the one or more trenches and on the multilayer film stack.

[0135] In some embodiments, forming the multilayer film stack includes: forming a first dielectric layer having a first electron affinity; forming a second dielectric layer having a second electron affinity greater than the first electron affinity; forming a third dielectric layer having a third electron affinity less than the second electron affinity; and forming a fourth dielectric layer having a fourth electron affinity. In some embodiments, the method further includes: performing a planarization process to remove portions of the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, and the core material from a second side of the substrate. In some embodiments, the one or more potential wells include a potential well located at a position corresponding to the second dielectric layer and surrounded by energy barriers corresponding to the first dielectric layer and the third dielectric layer. In some embodiments, the fourth dielectric layer has a larger oxygen density than the third dielectric layer. In some embodiments, the method further includes: performing a thermal process to cause charge carriers to tunnel through one or more energy barriers and into the one or more potential wells. In some embodiments, the method further includes applying a bias voltage across the multilayer film stack such that charge carriers tunnel through one or more energy barriers and into the one or more potential wells.

[0136] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. An integrated chip comprising: a substrate having a device region comprising one or more semiconductor devices, wherein the substrate has one or more interior surfaces forming one or more trenches within the substrate along opposite sides of the device region; a multilayer film stack disposed along the one or more interior surfaces of the substrate; a core material disposed within the one or more trenches and surrounded by the multilayer film stack; and wherein the multilayer film stack comprises a plurality of dielectric materials each having a different electron affinity energy, the plurality of dielectric materials arranged to form one or more potential wells within the multilayer film stack.

2. The integrated chip of claim 1, wherein, the device region comprises an image sensing element configured to convert radiation into an electrical signal.

3. The integrated chip of claim 1, wherein, the multilayer film stack comprises: a first dielectric material having a first electron affinity energy; a second dielectric material having a second electron affinity energy greater than the first electron affinity energy; a third dielectric material having a third electron affinity energy less than the second electron affinity energy; and a fourth dielectric material having a fourth electron affinity energy.

4. The integrated chip of claim 3, wherein, the fourth dielectric material has an oxygen density greater than the third dielectric material.

5. The integrated chip of claim 1, wherein, the multilayer film stack has a symmetric conduction band.

6. The integrated chip of claim 1, wherein, the multilayer film stack has an asymmetric conduction band.

7. The integrated chip of claim 1, wherein, the one or more potential wells comprise two potential wells.

8. The integrated chip of claim 1, wherein, the multilayer film stack has a thickness in a range between 50 nanometers and 100 nanometers.

9. An integrated chip comprising: a substrate having a pixel region comprising an image sensing element configured to convert radiation into an electrical signal; one or more trench isolation structures disposed within the substrate along opposite sides of the pixel region, wherein the one or more trench isolation structures comprise: a first dielectric material having a first electron affinity energy; a second dielectric material disposed on the first dielectric material and having a second electron affinity energy; a third dielectric material disposed on the second dielectric material and having a third electron affinity energy; a fourth dielectric material disposed on the third dielectric material and having a fourth electron affinity energy; and a core material disposed on the fourth dielectric material; and wherein the second electron affinity energy is greater than the first electron affinity energy and the third electron affinity energy.

10. A method of forming an integrated chip comprising: forming a semiconductor device within a substrate having a first side and a second side; etching the second side of the substrate to form one or more trenches within the substrate along opposite sides of the semiconductor device; forming a multilayer film stack within the one or more trenches and along the second side of the substrate, wherein the multilayer film stack comprises a plurality of dielectric materials having different electron affinity energies forming one or more potential wells; and forming a core material within the one or more trenches and on the multilayer film stack.

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