Low-current micro-led chip epitaxial structure, preparation method thereof and micro-led chip

Abstract

The application discloses a low-current Micro-LED chip epitaxial structure and a preparation method and a Micro-LED chip thereof, and relates to the field of semiconductor photoelectric devices. The low-current Micro-LED chip epitaxial structure comprises a substrate and a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially grown on the substrate; the active layer is a periodic structure, each period comprises an InGaN potential well layer and a GaN potential barrier layer which are sequentially stacked; the number of periods of the active layer is greater than or equal to 2; and an AlGaN layer is inserted into at least one GaN potential barrier layer. By implementing the application, the recombination of electrons and holes can be improved, and the light-emitting efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor optoelectronic devices, and in particular to a low-current Micro-LED chip epitaxial structure, a preparation method thereof and a Micro-LED chip. BACKGROUND

[0002] With the booming development of emerging wearable and portable technologies, micro-sized LED chips (Micro-LEDs) have attracted great attention and research from scientific research institutions and enterprises due to their application prospects in the fields of display, visible light communication and biomedicine. Moreover, Micro-LED display has nanosecond (ns) level high-speed response performance, stable characteristics of inorganic materials, high light efficiency, high reliability, high color purity and contrast, and transparency, and the combination of these excellent performances is beyond the reach of liquid crystal display (LCD) and organic LED (OLED).

[0003] Although Micro-LED has many excellent characteristics, it also faces challenges in manufacturing technology and material device physics. For example, the problem of peak EQE reduction and corresponding current density increase with the decrease of chip size has not been completely solved, and the working current density of Micro-LED is in the range of 0.01-0.5A / cm 2 The efficiency of Micro-LED in this current density range is still significantly insufficient. In fact, even for conventional size chips used in general lighting and backlight display applications, the efficiency at this current density is relatively low, because the working current density of conventional size chips is between 20A / cm 2 and 40A / cm 2 , and the target of the corresponding epitaxial structure design and material growth is to improve the efficiency at high current density, and the peak EQE is usually in the range of 1-4A / cm 2 current density. The dominant cause of the light emission mechanism of LED devices at different current densities is different, and the corresponding epitaxial layer structure should also be changed. For example, at a low current density of 0.01-0.5A / cm 2 , the carrier concentration in the quantum well is relatively low, the proportion of Auger recombination is small, and the recombination volume of the quantum well can be reduced, that is, the number of quantum wells can be reduced, the number of defects can be reduced, and the EQE of the device at low current density can be improved. At low current density, electron leakage has not occurred or the proportion is very low, and the electron blocking layer structure not only does not block electrons, but also blocks the injection of holes, reducing the quantum efficiency of the device. Therefore, the traditional epitaxial structure design of LED cannot meet the application requirements of Micro-LED. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a low-current Micro-LED chip epitaxial wafer which has high luminous efficiency under low working current.

[0005] The technical problem to be solved by the present application is to provide a Micro-LED chip which is small in size, low in working current density and high in luminous efficiency.

[0006] To solve the above problems, the present application discloses a low-current Micro-LED chip epitaxial structure, which comprises a substrate and a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer successively grown on the substrate; the active layer is a periodic structure, each period comprising an InGaN potential well layer and a GaN potential barrier layer successively stacked; the number of periods of the active layer is greater than or equal to 2.

[0007] Among at least one GaN potential barrier layer, an AlGaN layer is inserted.

[0008] As an improvement of the above technical solution, an AlGaN layer is inserted in each of the GaN potential barrier layers close to the P-type semiconductor layer, and the Al content of the plurality of AlGaN layers decreases along the growth direction of the epitaxial wafer.

[0009] As an improvement of the above technical solution, the number of periods of the active layer is 3-8.

[0010] As an improvement of the above technical solution, an AlGaN layer is inserted in each of the 2-4 periods of GaN potential barrier layers close to the P-type semiconductor layer, and the Al content of the plurality of AlGaN layers decreases along the growth direction of the epitaxial wafer.

[0011] As an improvement of the above technical solution, the In content of the plurality of InGaN potential well layers decreases first and then increases along the growth direction of the epitaxial wafer.

[0012] As an improvement of the above technical solution, the In content of the InGaN potential well layer is 0.1-0.4, and the Al content of the AlGaN layer is 0.1-0.8.

[0013] As an improvement of the above technical solution, the thickness of the AlGaN layer is 0.1-20 nm, the thickness of the InGaN potential well layer is 1-10 nm, and the thickness of the GaN potential barrier layer is 3-40 nm.

[0014] As an improvement of the above technical solution, the N-type semiconductor layer is an N-type Al x Ga 1-x N layer, and the doping concentration is 1x10 18 cm -3 -1x10 20cm -3 , thickness is 0.1-6 mu m;

[0015] The P-type semiconductor layer is P-type Al y Ga z In 1-y-z N layer, the doping concentration is 1*10 18 cm -3 -1*10 20 cm -3 , thickness is 0.1-2 mu m;

[0016] Wherein, x is 0-0.6, y is 0-0.6, z is 0-0.6.

[0017] Correspondingly, the application also discloses a preparation method of the low-current Micro-LED chip epitaxial structure.

[0018] A substrate is provided, and a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on the substrate; the active layer is a periodic structure, each period includes InGaN well layer and GaN barrier layer which are sequentially stacked; the number of periods of the active layer is greater than or equal to 2; and an AlGaN layer is inserted in at least one GaN barrier layer.

[0019] Correspondingly, the application also discloses a low-current Micro-LED chip including the low-current Micro-LED chip epitaxial structure.

[0020] The application has the following beneficial effects:

[0021] The Micro-LED chip epitaxial wafer includes a substrate and a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially grown on the substrate, and the active layer includes periodically stacked InGaN well layer and GaN barrier layer. In the epitaxial wafer, no electron blocking layer is arranged, and an AlGaN layer is inserted in at least one GaN barrier layer of the active layer. Based on the structure, the electrons can be effectively confined in the active layer, the blocking effect of the high barrier region on the holes can be sufficiently weakened, the injection efficiency of the holes is improved, the matching degree of the electrons and holes is increased, and the light-emitting efficiency of the Micro-LED chip is improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a structure schematic view of the low-current Micro-LED chip epitaxial structure in an embodiment of the application;

[0023] Figure 2 is a structure schematic view of the active layer in an embodiment of the application;

[0024] Figure 3 is a preparation method flow chart of a low-current Micro-LED chip epitaxial structure in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below.

[0026] REFERENCE Figure 1 and Figure 2 The present application discloses a low-current Micor-LED chip epitaxial wafer, comprising a substrate 1, a buffer layer 2, an N-type semiconductor layer 3, an active layer 4 and a P-type semiconductor layer 5 grown on the substrate 1 in sequence. The active layer 4 is a periodic structure, each period comprising an InGaN well layer 41 and a GaN barrier layer 42 stacked in sequence, and at least one GaN barrier layer 42 has an AlGaN layer 43 inserted therein. The epitaxial wafer structure of the present application does not set an electron blocking layer, reduces the blocking effect of holes, improves the injection efficiency of holes to the active layer 4, improves the recombination efficiency of electrons and holes, and improves the light-emitting efficiency. Further, by inserting the AlGaN layer 43 in at least one GaN barrier layer 42 of the active layer 4, the leakage of electrons in the active layer 4 can be reduced, the electrons can be prevented from entering the P-type semiconductor layer 5, the amount of holes can be reduced, and thus the light-emitting efficiency can be improved. Based on this structure, the Micro-LED chip has a relatively high light-emitting efficiency at a small current density of 0.01A / cm 2 ~ 5A / cm 2 .

[0027] The number of periods of the active layer 4 is ≥2, specifically 2-10, and preferably 3-8. Since the carrier concentration in the active layer of the Micro-LED chip in the present application is relatively low, the number of periods of the active layer 4 is also relatively small.

[0028] The AlGaN layer 43 is inserted at the middle position of the GaN barrier layer 42, which divides the GaN barrier layer 42 into two barrier sub-layers 42a and 42b of the same thickness, but is not limited thereto. The number of AlGaN layers 43 can be one or more, and multiple AlGaN layers 43 are inserted in different GaN barrier layers 42.

[0029] The insertion position of the AlGaN layer 43 is any one / multiple GaN barrier layer 42 of the period. Preferably, in an embodiment of the present application, the number of AlGaN layers 43 is multiple, which are inserted in multiple GaN barrier layers 42 close to the P-type semiconductor layer 5. Based on this setting, the function of blocking electrons can be achieved, and thus the Micro-LED chip can use a relatively high driving current (0.5A / cm2 ~ 6 A / cm 2 ), and further improve the light emitting efficiency. Further, the plurality of AlGaN layers 43 are inserted in the plurality of GaN barrier layers 42 close to the P-type semiconductor layer 5, and the Al component content in the plurality of AlGaN layers 43 decreases along the epitaxial growth direction, specifically, gradually decreases from 0.6-0.8 to 0-0.1. The Al component content in each AlGaN layer 43 is constant or decreases. Further preferably, one AlGaN layer 43 is inserted in each of the 2-4 periods of GaN barrier layers 42 close to the P-type semiconductor layer 5, and the Al component content in the plurality of AlGaN layers 43 decreases along the growth direction of the epitaxial wafer, and the Al component content in each AlGaN layer 43 remains constant.

[0030] The thickness of a single AlGaN layer 43 is 0.1 nm-20 nm, and is exemplarily 0.5 nm, 2 nm, 4 nm, 5 nm, 8 nm, 11 nm, 13 nm, 15 nm, 18 nm, or 19.5 nm, but is not limited thereto.

[0031] The thickness of a single GaN barrier layer 42 is 3 nm-40 nm, and is exemplarily 5 nm, 10 nm, 13 nm, 18 nm, 21 nm, 27 nm, 32 nm, 38 nm, 44 nm, 48 nm, or 49 nm, but is not limited thereto. When an AlGaN layer 43 is inserted in the GaN barrier layer 42, the thickness of each barrier sub-layer 42a, 42b obtained by division is the same, i.e., 1.5 nm-20 nm.

[0032] The thickness of a single InGaN well layer 41 is 1 nm-10 nm, and is exemplarily 2.5 nm, 4 nm, 5.5 nm, 7 nm, 8.5 nm, or 9 nm, but is not limited thereto. The In component content (molar ratio) in a single InGaN well layer 41 is 0.1-0.4, and is exemplarily 0.14, 0.18, 0.22, 0.26, 0.3, 0.34, or 0.38, but is not limited thereto.

[0033] Specifically, the In component content in each InGaN well layer 41 is the same, and the In component content in the plurality of InGaN well layers 41 decreases first and then increases along the growth direction of the epitaxial wafer. Specifically, in one embodiment, in the first 2-4 periods, the In component content in the InGaN well layer 41 decreases from 0.35-0.4 to 0.1-0.2, and in the last 4-6 periods, the In component content in the InGaN well layer 41 increases from 0.1-0.2 to 0.35-0.4, based on the above setting, the light emitting efficiency can be further improved.

[0034] Specifically, the active layer 4 structure of this application can be applied to common GaN-based Micro-LED chips, i.e., the N-type semiconductor layer 3 is an N-GaN layer and the P-type semiconductor layer 5 is a P-GaN layer; it can also be applied to AlGaN-based Micro-LED chips, and it can also be applied to AlGaInN-based Micro-LED chips, but is not limited to these.

[0035] Preferably, in one embodiment of the present invention, the N-type semiconductor layer is an N-type Al. x Ga 1-x N-layer (x = 0-0.6) with a doping concentration of 1 × 10⁻⁶. 18 cm -3 -1×10 20 cm -3 The thickness ranges from 0.1 μm to 6 μm. The 5th P-type semiconductor layer is a P-type Al... y Ga z In 1-y- z The N-layer (y = 0 - 0.6, z = 0 - 0.6) has a doping concentration of 1 × 10⁻⁶. 18 cm -3 -1×10 20 cm -3 The thickness is 0.1μm-2μm.

[0036] The substrate 1 can be a sapphire substrate, a silicon substrate, or a silicon carbide substrate, but is not limited to these.

[0037] The buffer layer 2 can be an AlN layer or an AlGaN layer, but is not limited to these. The thickness of the buffer layer 2 is 10nm-80nm, and exemplary thicknesses are 14nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm or 75nm, but are not limited to these.

[0038] In one embodiment of the present invention, an intrinsic semiconductor layer is further disposed between the buffer layer 2 and the N-type semiconductor layer 3. Specifically, when the Micro-LED chip is a GaN-based chip, it is a U-GaN layer; when the Micro-LED chip is an AlGaN-based chip, it is a U-AlGaN layer, but is not limited thereto. The thickness of the intrinsic semiconductor layer can be 0.5–5 μm.

[0039] Accordingly, refer to Figure 3 The present invention also discloses a method for fabricating a low-current Micro-LED chip, which includes the following steps:

[0040] S1: Provides epitaxial wafers;

[0041] Specifically, the substrate is a sapphire substrate, a silicon substrate, a silicon carbide substrate, but is not limited thereto. Preferably, the substrate is a patterned sapphire substrate.

[0042] S2: sequentially growing a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate;

[0043] Specifically, S2 comprises:

[0044] S21: growing a buffer layer on the substrate;

[0045] Specifically, the AlN layer can be grown by PVD as the buffer layer, or the AlGaN layer can be grown by MOCVD as the buffer layer, but is not limited thereto. When the AlGaN layer is grown by MOCVD, the growth temperature is 500-700°C, and the growth pressure is 100-500 torr.

[0046] S22: growing an N-type semiconductor layer on the buffer layer;

[0047] In one embodiment of the present application, the N-type semiconductor layer is grown in MOCVD. The growth temperature is 1000-1200°C, and the growth pressure is 100-400 torr.

[0048] S23: growing an active layer on the N-type semiconductor layer;

[0049] Specifically, S23 comprises:

[0050] S231: growing an InGaN well layer;

[0051] In one embodiment of the present application, the InGaN well layer is grown in MOCVD. The growth temperature is 700-800°C, and the growth pressure is 100-500 torr.

[0052] S232: growing a GaN barrier layer;

[0053] In one embodiment of the present application, the GaN barrier layer is grown in MOCVD. The growth temperature is 800-900°C, and the growth pressure is 100-500 torr.

[0054] Preferably, in one embodiment of the present application, an AlGaN layer is grown during the growth of the GaN barrier layer. The growth temperature is 900-1000°C, and the growth pressure is 100-500 torr.

[0055] S233: periodically repeating steps S231 and S232 until the active layer is obtained.

[0056] S24: growing a P-type semiconductor layer on the active layer;

[0057] In one embodiment of the present invention, a P-type GaN layer is grown in MOCVD at a growth temperature of 800-1000℃ and a growth pressure of 100-500 torr.

[0058] The present invention will be further described below with reference to specific embodiments:

[0059] Example 1

[0060] This embodiment provides a low-current Micro-LED chip epitaxial structure, referenced... Figure 1 and Figure 2 It includes a substrate 1 and a buffer layer 2, an N-type semiconductor layer 3, an active layer 4, and a P-type semiconductor layer 5 sequentially grown on the substrate 1. The active layer 4 has a periodic structure with 8 periods. Each period includes an InGaN well layer 41 and a GaN barrier layer 42 stacked sequentially; wherein an AlGaN layer 43 is inserted into the GaN barrier layer 42 in the third period.

[0061] The thickness of a single InGaN well layer 41 is 3 nm, and the In content is 0.25%. The In content in multiple InGaN well layers 41 is the same. The thickness of a single GaN barrier layer 42 is 10 nm, and the thickness of a single AlGaN layer 43 is 5 nm, with an Al content of 0.6%.

[0062] In this design, substrate 1 is a sapphire substrate. Buffer layer 2 is an AlN layer with a thickness of 25 nm, and N-type semiconductor layer 3 is an N-type AlN layer. x Ga 1-x The N-layer (x = 0.3) is doped with Si at a concentration of 5 × 10⁻⁶. 19 cm -3 The thickness is 3.5 μm. P-type semiconductor layer 5 is P-type Al. y Ga z In 1-y-z The N-layer is doped with Mg at a concentration of 8 × 10⁻⁶. 18 cm -3 The thickness is 0.8μm.

[0063] The method for fabricating the epitaxial wafer of the light-emitting diode in this embodiment includes the following steps:

[0064] (1) Provide a substrate;

[0065] (2) Grow a buffer layer on the substrate;

[0066] Specifically, an AlN layer is deposited using PVD as a buffer layer.

[0067] (3) Grow an N-type semiconductor layer on the buffer layer;

[0068] Specifically, the N-type Al x Ga 1-x N layer is grown as the N-type semiconductor layer in MOCVD. The growth temperature is 1100℃, and the growth pressure is 220 torr.

[0069] (4) growing an InGaN potential well layer on the substrate obtained in step (3);

[0070] Specifically, the InGaN potential well layer is grown in MOCVD. The growth temperature is 720℃, and the growth pressure is 300 torr.

[0071] (5) growing a GaN potential barrier layer on the InGaN potential well layer;

[0072] Specifically, the GaN potential barrier layer is grown in MOCVD. The growth temperature is 880℃, and the growth pressure is 300 torr.

[0073] (6) periodically repeating step (4) and step (5) until an active layer is obtained;

[0074] In the growth of the GaN potential barrier layer in the 3rd cycle, an AlGaN layer is grown, the growth temperature is 920℃, and the growth pressure is 350 torr.

[0075] (7) growing a P-type semiconductor layer on the active layer;

[0076] Specifically, the P-type Al y Ga z In 1-y-z N layer is grown as the P-type semiconductor layer in MOCVD. The growth temperature is 350℃, and the growth pressure is 300 torr.

[0077] Embodiment 2

[0078] This embodiment provides a low-current Micro-LED chip epitaxial structure, which refers to Figure 1 and Figure 2 which comprises a substrate 1 and a buffer layer 2, an N-type semiconductor layer 3, an active layer 4, and a P-type semiconductor layer 5 grown on the substrate 1 in sequence. The active layer 4 is a periodic structure with a period number of 8. Each period comprises an InGaN potential well layer 41 and a GaN potential barrier layer 42 stacked in sequence; and in the GaN potential barrier layers 42 in the 5th to 8th periods, an AlGaN layer 43 is inserted.

[0079] The thickness of the single InGaN well layer 41 is 3 nm, the In content is 0.25, and the In contents in the plurality of InGaN well layers 41 are the same. The thickness of the single GaN barrier layer 42 is 10 nm, the thickness of the single AlGaN layer 43 is 5 nm, the Al content is 0.4, and the Al contents in the plurality of AlGaN layers 43 are the same.

[0080] The substrate 1 is a sapphire substrate. The buffer layer 2 is an AlN layer with a thickness of 25 nm. The N-type semiconductor layer 3 is an N-type Al x Ga 1-x N layer (x = 0.3) doped with Si at a doping concentration of 5 x 1018cm-3 and having a thickness of 3.5 μm. The P-type semiconductor layer 5 is a P-type Al 19 Ga -3 In y N layer doped with Mg at a doping concentration of 8 x 1018cm-3 and having a thickness of 0.8 μm. z 1-y-z 18 -3

[0081] The method for preparing the light emitting diode epitaxial wafer in the embodiment includes the following steps:

[0082] (1) providing a substrate;

[0083] (2) growing a buffer layer on the substrate;

[0084] Specifically, an AlN layer is deposited by PVD to serve as the buffer layer.

[0085] (3) growing an N-type semiconductor layer on the buffer layer;

[0086] Specifically, an N-type Al x Ga 1-x N layer is grown in MOCVD to serve as the N-type semiconductor layer. The growth temperature is 1100°C, and the growth pressure is 220 torr.

[0087] (4) growing an InGaN well layer on the substrate obtained in step (3);

[0088] Specifically, an InGaN well layer is grown in MOCVD. The growth temperature is 720°C, and the growth pressure is 300 torr.

[0089] (5) growing a GaN barrier layer on the InGaN well layer;

[0090] Specifically, a GaN barrier layer is grown in MOCVD. The growth temperature is 880°C, and the growth pressure is 300 torr.

[0091] ​​​​(6) Repeat steps (4) and (5) periodically until an active layer is obtained;

[0092] During the growth of the GaN barrier layer in the 5th to 8th cycles, the AlGaN layer is grown at a growth temperature of 920℃ and a growth pressure of 350 torr.

[0093] (7) Grow a P-type semiconductor layer on the active layer;

[0094] Specifically, growing P-type Al in MOCVD y Ga z In 1-y-z The N-layer, as a P-type semiconductor layer, is grown at a temperature of 350°C and a growth pressure of 300 torr.

[0095] Example 3

[0096] This embodiment provides a low-current Micro-LED chip epitaxial structure, referenced... Figure 1 and Figure 2 It includes a substrate 1 and a buffer layer 2, an N-type semiconductor layer 3, an active layer 4, and a P-type semiconductor layer 5 sequentially grown on the substrate 1. The active layer 4 has a periodic structure with 8 periods. Each period includes an InGaN well layer 41 and a GaN barrier layer 42 stacked sequentially; wherein an AlGaN layer 43 is inserted into the GaN barrier layer 42 in the 5th to 8th periods.

[0097] The thickness of a single InGaN well layer 41 is 3 nm, and the In content is 0.25%. The In content is the same in all InGaN well layers 41. The thickness of a single GaN barrier layer 42 is 10 nm, and the thickness of a single AlGaN layer 43 is 5 nm. The Al content of the multiple AlGaN layers 43 decreases from 0.6 to 0. Specifically, in the 5th period, the Al content of the AlGaN layer 43 is 0.6; in the 6th period, it is 0.4; in the 7th period, it is 0.2; and in the 8th period, it is 0.0%.

[0098] Substrate 1 is a sapphire substrate. Buffer layer 2 is an AlN layer with a thickness of 25 nm, and N-type semiconductor layer 3 is an N-type Al... x Ga 1-x The N-layer (x = 0.3) is doped with Si at a concentration of 5 × 10⁻⁶. 19 cm -3 The thickness is 3.5 μm. P-type semiconductor layer 5 is P-type Al. y Ga z In 1-y-zN layer, whose doping element is Mg, and doping concentration is 8*1018cm-3, and thickness is 0.8μm. 18 cm -3 .

[0099] The preparation method of the light emitting diode epitaxial wafer in the embodiment comprises the following steps:

[0100] (1) providing a substrate;

[0101] (2) growing a buffer layer on the substrate;

[0102] Specifically, an AlN layer is deposited by PVD as the buffer layer.

[0103] (3) growing an N-type semiconductor layer on the buffer layer;

[0104] Specifically, an N-type Al x Ga 1-x N layer is grown in MOCVD as the N-type semiconductor layer. The growth temperature is 1100℃, and the growth pressure is 220torr.

[0105] (4) growing an InGaN potential well layer on the substrate obtained in step (3);

[0106] Specifically, an InGaN potential well layer is grown in MOCVD. The growth temperature is 720℃, and the growth pressure is 300torr.

[0107] (5) growing a GaN potential barrier layer on the InGaN potential well layer;

[0108] Specifically, a GaN potential barrier layer is grown in MOCVD. The growth temperature is 880℃, and the growth pressure is 300torr.

[0109] (6) periodically repeating step (4) and step (5) until an active layer is obtained;

[0110] In the growth of the GaN potential barrier layer in the 5th to 8th periods, an AlGaN layer is grown, the growth temperature is 920℃, and the growth pressure is 350torr.

[0111] (7) growing a P-type semiconductor layer on the active layer;

[0112] Specifically, a P-type Al y Ga z In 1-y-z N layer is grown in MOCVD as the P-type semiconductor layer, the growth temperature is 350℃, and the growth pressure is 300torr.

[0113] Embodiment 4

[0114] The embodiment provides a low-current Micro-LED chip epitaxial structure, referring to Figure 1 and Figure 2 which comprises a substrate 1 and a buffer layer 2, an N-type semiconductor layer 3, an active layer 4 and a P-type semiconductor layer 5 grown on the substrate 1 in sequence. The active layer 4 is a periodic structure with a period number of 8. Each period comprises an InGaN well layer 41 and a GaN barrier layer 42 stacked in sequence; wherein an AlGaN layer 43 is inserted in the GaN barrier layer 42 of the 5th to 8th periods.

[0115] The thickness of a single InGaN well layer 41 is 3nm, and the In content in the plurality of InGaN well layers 41 decreases from 0.29 to 0.08, that is, the In content in the InGaN well layers 41 in the 1st to 8th periods is 0.29, 0.26, 0.23, 0.20, 0.17, 0.14, 0.11 and 0.08 respectively. The thickness of a single GaN barrier layer 42 is 10nm, the thickness of a single AlGaN layer 43 is 5nm, and the Al content in the plurality of AlGaN layers 43 decreases from 0.6 to 0. That is, the Al content in the AlGaN layer 43 in the 5th period is 0.6, the Al content in the AlGaN layer 43 in the 6th period is 0.4, the Al content in the AlGaN layer 43 in the 7th period is 0.2, and the Al content in the AlGaN layer 43 in the 8th period is 0.

[0116] The substrate 1 is a sapphire substrate. The buffer layer 2 is an AlN layer with a thickness of 25nm, the N-type semiconductor layer 3 is an N-type Al x Ga 1-x N layer (x=0.3) with a doping element of Si and a doping concentration of 5x10 19 cm -3 -3 and a thickness of 3.5μm. The P-type semiconductor layer 5 is a P-type Al y Ga z In 1-y-z N layer with a doping element of Mg and a doping concentration of 8x10 18 cm -3 -2 and a thickness of 0.8μm.

[0117] The preparation method of the light-emitting diode epitaxial wafer in the embodiment comprises the following steps:

[0118] (1) providing a substrate;

[0119] (2) growing a buffer layer on the substrate;

[0120] Specifically, an AlN layer is deposited by PVD to serve as the buffer layer.

[0121] (3) growing an N-type semiconductor layer on the buffer layer;

[0122] Specifically, the N-type Al x Ga 1-x N layer is grown in MOCVD as the N-type semiconductor layer. The growth temperature is 1100℃, and the growth pressure is 220 torr.

[0123] (4) growing an InGaN potential well layer on the substrate obtained in step (3);

[0124] Specifically, the InGaN potential well layer is grown in MOCVD. The growth temperature is 720℃, and the growth pressure is 300 torr.

[0125] (5) growing a GaN potential barrier layer on the InGaN potential well layer;

[0126] Specifically, the GaN potential barrier layer is grown in MOCVD. The growth temperature is 880℃, and the growth pressure is 300 torr.

[0127] (6) periodically repeating step (4) and step (5) until an active layer is obtained;

[0128] In the growth of the GaN potential barrier layer in the 5th to 8th periods, an AlGaN layer is grown, the growth temperature is 920℃, and the growth pressure is 350 torr.

[0129] (7) growing a P-type semiconductor layer on the active layer;

[0130] Specifically, the P-type Al y Ga z In 1-y-z N layer is grown in MOCVD as the P-type semiconductor layer, the growth temperature is 350℃, and the growth pressure is 300 torr.

[0131] Embodiment 5

[0132] This embodiment provides a low-current Micro-LED chip epitaxial structure, which refers to Figure 1 and Figure 2 which comprises a substrate 1 and a buffer layer 2, an N-type semiconductor layer 3, an active layer 4, and a P-type semiconductor layer 5 grown on the substrate 1 in sequence. The active layer 4 is a periodic structure with a period number of 8. Each period comprises an InGaN potential well layer 41 and a GaN potential barrier layer 42 stacked in sequence; and in the GaN potential barrier layer 42 in the 5th to 8th periods, an AlGaN layer 43 is inserted.

[0133] The thickness of a single InGaN well layer 41 is 3 nm. The In content of multiple InGaN well layers 41 decreases from 0.29 to 0.08, and then increases to 0.28; that is, the In content of the InGaN well layer 41 in the 1st to 8th periods are 0.29, 0.22, 0.15, 0.08, 0.08, 0.15, 0.55, and 0.29, respectively. The thickness of a single GaN barrier layer 42 is 10 nm, the thickness of a single AlGaN layer 43 is 5 nm, and the Al content of multiple AlGaN layers 43 decreases from 0.6 to 0. That is, in the 5th period, the Al content of Al GaN layer 43 is 0.6, in the 6th period, the Al content of Al GaN layer 43 is 0.4, in the 7th period, the Al content of Al GaN layer 43 is 0.2, and in the 8th period, the Al content of Al GaN layer 43 is 0.

[0134] In this design, substrate 1 is a sapphire substrate. Buffer layer 2 is an AlN layer with a thickness of 25 nm, and N-type semiconductor layer 3 is an N-type AlN layer. x Ga 1-x The N-layer (x = 0.3) is doped with Si at a concentration of 5 × 10⁻⁶. 19 cm -3 The thickness is 3.5 μm. P-type semiconductor layer 5 is P-type Al. y Ga z In 1-y-z The N-layer is doped with Mg at a concentration of 8 × 10⁻⁶. 18 cm -3 The thickness is 0.8μm.

[0135] The method for fabricating the epitaxial wafer of the light-emitting diode in this embodiment includes the following steps:

[0136] (1) Provide a substrate;

[0137] (2) Grow a buffer layer on the substrate;

[0138] Specifically, an AlN layer is deposited using PVD as a buffer layer.

[0139] (3) Grow an N-type semiconductor layer on the buffer layer;

[0140] Specifically, growing N-type Al in MOCVD x Ga 1-x The N-layer serves as an N-type semiconductor layer. The growth temperature is 1100℃, and the growth pressure is 220 torr.

[0141] (4) Grow an InGaN potential well layer on the substrate obtained in step (3);

[0142] Specifically, the InGaN well layer is grown in MOCVD. The growth temperature is 720°C, and the growth pressure is 300 torr.

[0143] (5) growing a GaN barrier layer on the InGaN well layer;

[0144] Specifically, the GaN barrier layer is grown in MOCVD. The growth temperature is 880°C, and the growth pressure is 300 torr.

[0145] (6) repeating steps (4) and (5) periodically until the active layer is obtained;

[0146] In the growth of the GaN barrier layer in the 5th to 8th periods, an AlGaN layer is grown, the growth temperature is 920°C, and the growth pressure is 350 torr.

[0147] (7) growing a P-type semiconductor layer on the active layer;

[0148] Specifically, the P-type Al y Ga z In 1-y-z N layer is grown in MOCVD as the P-type semiconductor layer, the growth temperature is 350°C, and the growth pressure is 300 torr.

[0149] Comparative Example 1

[0150] The difference between this comparative example and Example 1 is that the AlGaN layer 43 is not inserted in the GaN barrier layer 42, and correspondingly, the step of growing the AlGaN layer 43 is not provided in the preparation method.

[0151] In addition, an electron blocking layer is grown between the active layer 4 and the P-type semiconductor layer 5. Specifically, the electron blocking layer is an Al α Ga 1-α N layer (α = 0.8) with a thickness of 80 nm. The electron blocking layer is grown by MOCVD, the growth temperature is 940°C, and the growth pressure is 250 torr.

[0152] Comparative Example 2

[0153] The difference between this comparative example and Example 1 is that the AlGaN layer 43 is not inserted in the GaN barrier layer 42, and correspondingly, the step of growing the AlGaN layer 43 is not provided in the preparation method.

[0154] The epitaxial wafers obtained in Examples 1-5 and Comparative Examples 1-2 are processed to produce LED chips with a vertical structure with a size of 50 μm x 50 μm. The LED chips are tested at current densities of 0.2 A / cm 2 , 1 A / cm 2 , and 5 A / cm 2and 10 A / cm 2 The electroluminescent intensity of the device was tested under the following conditions:

[0155]

[0156]

[0157] The above described are preferred embodiments of the application, it should be noted that for those skilled in the art, without departing from the principles of the present application, can make a number of improvements and refinements, these improvements and refinements are also considered within the scope of the present application.

Claims

1. A low current Micro-LED chip epitaxial structure, characterized in that, The epitaxial wafer comprises a substrate and a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer grown on the substrate in sequence; the active layer is a periodic structure, each period comprising an InGaN well layer and a GaN barrier layer stacked in sequence; the active layer has a period number of 3-8; The In content of the plurality of InGaN well layers decreases first and then increases along the growth direction of the epitaxial wafer. An AlGaN layer is inserted in the 2-4 periods of GaN barrier layers close to the P-type semiconductor layer, and the Al content of the plurality of AlGaN layers decreases along the growth direction of the epitaxial wafer.

2. The low current Micro-LED chip epitaxial structure of claim 1, wherein, The In content of the InGaN well layer is 0.1-0.4, and the Al content of the AlGaN layer is 0.1-0.

8.

3. The low current Micro-LED chip epitaxial structure of claim 1, wherein, The thickness of the AlGaN layer is 0.1-20 nm, the thickness of the InGaN well layer is 1-10 nm, and the thickness of the GaN barrier layer is 3-40 nm.

4. The low current Micro-LED chip epitaxial structure of claim 1, wherein, The N-type semiconductor layer is an N-type Al x Ga 1-x N layer with a doping concentration of 1×10 18 cm -3 -1×10 20 cm -3 and a thickness of 0.1 μm-6 μm; The P-type semiconductor layer is P-type Al y Ga z In 1-y-z The N layer has a doping concentration of 1×10 18 cm -3 -1×10 20 cm -3 and a thickness of 0.1 μm-2 μm; x is 0-0.6, y is 0-0.6, and z is 0-0.

6.

5. A preparation method of a low-current Micro-LED chip epitaxial structure, for preparing the low-current Micro-LED chip epitaxial structure according to any one of claims 1-4, characterized in that, The epitaxial wafer comprises a substrate and a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer grown on the substrate in sequence; the active layer is a periodic structure, each period comprising an InGaN well layer and a GaN barrier layer stacked in sequence; the active layer has a period number of 3-8; The In content of the plurality of InGaN well layers decreases first and then increases along the growth direction of the epitaxial wafer. An AlGaN layer is inserted in the 2-4 periods of GaN barrier layers close to the P-type semiconductor layer, and the Al content of the plurality of AlGaN layers decreases along the growth direction of the epitaxial wafer. The epitaxial wafer comprises a substrate and a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer grown on the substrate in sequence; the active layer is a periodic structure, each period comprising an InGaN well layer and a GaN barrier layer stacked in sequence; the active layer has a period number of 3-8; 6. A low current Micro-LED chip, characterized in that, The In content of the plurality of InGaN well layers decreases first and then increases along the growth direction of the epitaxial wafer. An AlGaN layer is inserted in the 2-4 periods of GaN barrier layers close to the P-type semiconductor layer, and the Al content of the plurality of AlGaN layers decreases along the growth direction of the epitaxial wafer.

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