Display panel and electronic device including the same

Abstract

A display panel and an electronic device including the same are provided. The display panel includes a main display area and a component area including a transmissive area. The display panel includes: a substrate including a groove disposed in a transmissive region in a depth direction of the substrate; a main display element disposed over the substrate in the main display area; a main pixel circuit electrically connected to the main display element; an auxiliary display element disposed over the substrate in the component area; and an auxiliary pixel circuit electrically connected to the auxiliary display element.

Description

[0001] This application is a divisional application of the invention patent application "Display panel and display device including the thereof" filed on December 22, 2020, with application number 202011527361.3. Technical Field

[0002] One or more embodiments relate to a display panel and a display device including the display panel, and to a display panel and a display device including the display panel having an enlarged display area, such that one or more images can be displayed even in an area where components such as electronic components can be arranged or set. Background Technology

[0003] The applications of display devices have become increasingly diversified recently. Furthermore, their use has expanded as display devices have become thinner and lighter.

[0004] Given the various ways display devices can be utilized, the diverse methods available for designing their shapes, and the increasing number of functions that can be connected to or linked to them, the possibilities are vast.

[0005] It will be understood that this background section is partly intended to provide useful background for understanding the technology. However, this background section may also include ideas, concepts, or knowledge that were not part of what is known or understood by one of skill in the art prior to the corresponding valid date of submission of the subject matter disclosed herein. Summary of the Invention

[0006] One or more embodiments include a display panel and a display device including the display panel, the display panel having an enlarged display area, enabling images to be displayed even in areas where electronic components can be arranged or positioned. However, one or more embodiments are merely examples, and the scope of disclosure is not limited thereto.

[0007] Other aspects will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of the embodiments.

[0008] According to an embodiment, a display panel may include a main display area and a component area that may include a transmissive area. The display panel may include: a substrate, including a groove disposed in the transmissive area along the depth direction of the substrate; a main display element disposed above the substrate in the main display area; a main pixel circuit electrically connected to the main display element; an auxiliary display element disposed above the substrate in the component area; and an auxiliary pixel circuit electrically connected to the auxiliary display element.

[0009] The substrate may include a first substrate layer, a first inorganic barrier layer, a second substrate layer and a second inorganic barrier layer that can be stacked sequentially. The second inorganic barrier layer may include a first opening located in the transmission region. The second substrate layer may include a second opening that overlaps with the first opening. The groove may include the first opening, the second opening and the upper surface of the first inorganic barrier layer.

[0010] The main display element may include a main sub-pixel disposed in the main display area, and the main sub-pixel may have a first pixel arrangement structure. The auxiliary display element may include an auxiliary sub-pixel disposed in the component area, and the auxiliary sub-pixel may have a second pixel arrangement structure. The first pixel arrangement structure may be different from the second pixel arrangement structure.

[0011] The component region may include a first component region and a second component region. The auxiliary sub-pixels set in the first component region may have a third pixel arrangement structure, and the auxiliary sub-pixels set in the second component region may have a fourth pixel arrangement structure that may be different from the third pixel arrangement structure.

[0012] Multiple pixel groups corresponding to the auxiliary display element group can be arranged in the component area, multiple transmissive areas can be arranged in the component area, and the multiple pixel groups and the transmissive areas can alternate with each other.

[0013] The bottom metal layer can be disposed between the substrate and the auxiliary pixel circuit. The bottom metal layer may include a bottom hole located in the transmission region, and the bottom hole may have a polygonal shape or a circular shape. The polygonal shape has eight or more sides.

[0014] The upper layer can be disposed on the counter electrode, which can be disposed in the main display element and the auxiliary display element. The counter electrode can include a first opening located in the transmission region, and the upper layer can include a second opening located in the transmission region. The inner surfaces of the first opening and the second opening can be coplanar.

[0015] A weak adhesive layer can be disposed in the transmissive region; and a counter electrode can be disposed in the main display element and the auxiliary display element. The counter electrode may include a transmissive hole or a transmissive groove corresponding to the weak adhesive layer.

[0016] The functional layer can be disposed in the main display element and the auxiliary display element, and can include organic materials. The functional layer can be continuously disposed in the transmissive region, and the counter electrode can be disposed in the main display element and the auxiliary display element and can include a transmissive hole or transmissive groove corresponding to the weak adhesive layer.

[0017] The counter electrode can be disposed in the main display element and the auxiliary display element. The counter electrode may include: a first thickness at a portion of the counter electrode that can overlap with the pixel electrode of the auxiliary display element; and a second thickness at a portion of the counter electrode between the auxiliary display elements. The second thickness may be greater than the first thickness.

[0018] The auxiliary display element may include auxiliary sub-pixels, which may include auxiliary sub-pixels that emit a first color. The main display element may include main sub-pixels, which may include main sub-pixels that emit a first color. The size of the auxiliary sub-pixels that emit the first color may be larger than the size of the main sub-pixels that emit the first color.

[0019] At least one of the main pixel circuit and the auxiliary pixel circuit may include: a first thin-film transistor, which may include an oxide semiconductor layer; and a second thin-film transistor, which may include a polycrystalline silicon semiconductor layer.

[0020] The auxiliary display element may include a first auxiliary display element and a second auxiliary display element. The thickness of the first pixel electrode of the first auxiliary display element may be greater than the thickness of the second pixel electrode of the second auxiliary display element, and the first pixel electrode may include a reflective layer.

[0021] The auxiliary display element may include a first auxiliary display element. The pixel electrode of the first auxiliary display element may include a first pixel electrode unit and a second pixel electrode unit. The thickness of the first pixel electrode unit may be different from the thickness of the second pixel electrode unit. The first pixel electrode unit may be a stack of a first transparent electrode layer, a reflective layer and a second transparent electrode layer, and the second pixel electrode unit may extend from the first transparent electrode layer.

[0022] The wiring can be placed in the transmission area and can include transparent conductive material.

[0023] The first display driving unit can drive the main pixel circuit, and the second display driving unit can drive the auxiliary pixel circuit, wherein at least one of the driving voltage and the common voltage applied to the main pixel circuit can be different from at least one of the driving voltage and the common voltage applied to the auxiliary pixel circuit.

[0024] The first main data line can be electrically connected to the main pixel circuit, and the first auxiliary data line can be electrically connected to the auxiliary pixel circuit. The first main data line and the first auxiliary data line can be arranged in the same column, and the ends of the first main data line and the ends of the first auxiliary data line can be spaced apart from each other. The transmission area is arranged between the ends of the first main data line and the ends of the first auxiliary data line.

[0025] The first wiring can be electrically connected to a predetermined number of main pixel circuits and a predetermined number of auxiliary pixel circuits. The load matching unit can be electrically connected to the first wiring and can be disposed in a peripheral area adjacent to the component area. The first load connection line can electrically connect the first wiring to the load matching unit. The first load connection line can be disposed between the substrate and the main pixel circuit. The first wiring can electrically contact the first load connection line through a contact hole.

[0026] The thin-film encapsulation layer can be configured to correspond to the main display element and the auxiliary display element, and can include a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer, wherein the first inorganic encapsulation layer can be disposed in a groove of the substrate.

[0027] The encapsulation component can be configured to correspond to the main display element and the auxiliary display element; and the touchscreen layer can be disposed on the encapsulation component. The touchscreen layer can be stacked on the main display area and can include: sensing electrodes disposed in a first direction; driving electrodes disposed in a second direction intersecting the first direction; a first connecting electrode electrically connecting the sensing electrodes to each other; and a second connecting electrode electrically connecting the driving electrodes to each other. The touchscreen layer can be stacked on the component area and can include touch electrodes disposed in the first and second directions and spaced apart from each other.

[0028] The sensing electrode and the driving electrode can be driven using the mutual capacitance method, while the touch electrode can be driven using the self-capacitance method.

[0029] The touchscreen layer may include touch openings located in the transmissive area.

[0030] The encapsulation component can encapsulate the main display element and the auxiliary display element, and the mirror component can be disposed on the surface of the encapsulation component. At least one of the main display area and the component area can include a mirror area, and the mirror component can be disposed in the mirror area and can include: a first mirror layer, including a first mirror opening configured to correspond to the main display element and the auxiliary display element; and a second mirror layer disposed in the mirror area and the first mirror opening.

[0031] At least one of the first and second mirror layers can be a self-capacitive touch electrode.

[0032] The encapsulation component can be configured to correspond to the main display element and the auxiliary display element; the touch screen layer can be disposed on the encapsulation component; the filter can be disposed on the touch screen layer and can include a color filter and a black matrix, and the filter can include an opening located in the transmission region.

[0033] The substrate may include: an upper surface portion; a first side surface portion extending from one side of the upper surface portion and bendable with a first radius of curvature; and a second side surface portion extending from the other side of the upper surface portion and bendable with a second radius of curvature. Component regions may be disposed on the upper surface portion and the first side surface portion.

[0034] The first radius of curvature can be greater than the second radius of curvature.

[0035] According to an embodiment, a display panel may include a main display area and a component area including an auxiliary display area and an image sensor area. The display panel may include a substrate; a main display element disposed above the substrate in the main display area; a main pixel circuit electrically connected to the main display element; an auxiliary display element disposed above the substrate in the auxiliary display area; an auxiliary pixel circuit electrically connected to the auxiliary display element; a photodiode disposed above the substrate in the image sensor area; and a light-receiving pixel circuit electrically connected to the photodiode. The auxiliary display area and the image sensor area may alternate.

[0036] The packaging component can encapsulate the main display element, the auxiliary display element, and the photodiode; and the filter can be disposed on the packaging component and can include a color filter that can be configured to correspond to the main display element, the auxiliary display element, and the photodiode.

[0037] Microlenses can be positioned above the filter in the image sensor area.

[0038] The touchscreen layer can be positioned between the encapsulation component and the color filter.

[0039] The auxiliary display element may include auxiliary sub-pixels arranged in a pentile matrix structure, and the light-receiving pixels including photodiodes may be arranged in a Bayer pattern.

[0040] Each of the auxiliary display elements may be an organic light-emitting diode and may include a stack of pixel electrodes, an emitting layer and a counter electrode. Each of the photodiodes may be a PN diode or a PIN diode and may include a stack of a first electrode, an active layer and a second electrode. The active layer may include an amorphous silicon semiconductor, and the pixel electrode and the first electrode may be disposed on different layers.

[0041] According to an embodiment, a display device may include: a first display panel, which may include a first display element that emits light, a main display area, and a component area; a second display panel, which is disposed below the first display panel and includes a second display element that emits light and a second display area; and a lower cover that can accommodate the first display panel and the second display panel.

[0042] The component can be disposed below the first display panel and can receive light obtained from outside the display device; the motion drive unit can move the second display panel relative to the first display panel; and the controller can control the motion drive unit, wherein the component can be disposed on the second display panel and can be disposed on one side of the second display area.

[0043] When the component is in the first state, the motion driving unit can move the second display panel so that the component can correspond to the component area. And when the component is in the second state, the motion driving unit can move the second display panel so that the second display area can correspond to the component area.

[0044] The components may include a first component and a second component, and the first and second components may be selected from imaging devices, infrared sensors, solar cells, and flash lamps.

[0045] The first display element can be an organic light-emitting diode (OLED), and the second display element can be an inorganic light-emitting diode (LED).

[0046] The second display panel may include an image sensor area disposed on one side of the second display area, and light receiving pixels may be disposed in the image sensor area, and may include photodiodes disposed on a substrate on which the second display element is disposed.

[0047] The image sensor area of ​​the second display panel may include: a substrate, on which light-receiving pixels, including photodiodes, may be disposed in a two-dimensional array structure, wherein the substrate may include a first surface and a second surface opposite to the first surface; a multi-layer wiring layer disposed on the first surface; a color filter and microlens disposed on the second surface; and a pixel separation structure disposed in the substrate. The pixel separation structure can separate the light-receiving pixels from each other.

[0048] The second display element can be disposed on the second surface.

[0049] The second display element can be an inorganic light-emitting diode, and the inorganic light-emitting diode can be disposed between the first electrode and the second electrode, with the first electrode and the second electrode disposed on different layers.

[0050] The second display element can be an inorganic light-emitting diode, and the inorganic light-emitting diode can be disposed between the first electrode and the second electrode, with the first electrode and the second electrode disposed on the same layer.

[0051] The component area of ​​the first display panel may be a transmissive area, the second display panel may include a photodiode, and the second display element and the photodiode may be arranged alternately.

[0052] The component area of ​​the first display panel may be a transmissive area, the second display element may be a light-emitting and light-receiving element, and each of the second display elements may be electrically connected via a switching element to a first pixel circuit for displaying an image and a second pixel circuit for capturing an image.

[0053] The light-emitting and light-receiving elements can be PN diodes or PIN diodes.

[0054] The substrate of the first display panel may include through holes corresponding to the component area.

[0055] According to an embodiment, a display device may include: a display panel, which may include a display element that emits light in a first direction, a main display area, and a component area; a component, configured to face a direction opposite to the first direction; a light guide unit, which can guide light incident on the component area toward the component; and a lower cover, which may include holes corresponding to the component.

[0056] The light guiding unit may include: a light guide, including at least one curved portion; a first path changer capable of changing the path of light traveling along the light guide; and a path change driver connected to the first path changer. The path change driver can change the position of the first path changer.

[0057] The path change driver can change the position of the first path changer, allowing the first path changer to be stacked with or not stacked with the hole.

[0058] The light guide unit may include a second path changer that can alter the path of light traveling along the light guide, and the second path changer may be a mirror or a prism.

[0059] The component area of ​​the display panel may include a transmissive area, and the display panel may include: a substrate, which may include a groove disposed in the transmissive area in the depth direction of the substrate; a main display element disposed above the substrate in the main display area; a main pixel circuit electrically connected to the main display element; an auxiliary display element disposed above the substrate in the component area; and an auxiliary pixel circuit electrically connected to the auxiliary display element.

[0060] Details of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0061] The above and other aspects, features, and advantages of the described embodiments will become clearer from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a perspective view of a display device according to an embodiment; Figure 2 This is an exploded perspective view of a display device according to an embodiment; Figure 3This is a block diagram of a display device according to an embodiment; Figure 4 This is a plan view of the display panel according to an embodiment; Figure 5 yes Figure 4 A side view of an example of the display panel; Figure 6 This is a plan view of the display panel according to an embodiment; Figure 7 yes Figure 6 A side view of an example of the display panel; Figures 8A to 8I It is a layout diagram showing component areas having shapes and arrangements according to various embodiments; Figures 9A to 9E These are schematic cross-sectional views of corresponding portions of a display device according to an embodiment; Figure 10 This is a schematic plan view of the display panel according to an embodiment; Figure 11A and Figure 11B This is an equivalent circuit diagram of a pixel circuit for driving sub-pixels according to an embodiment; Figure 12 This is a schematic layout diagram illustrating the pixel arrangement structure in the main display area of ​​a display panel according to an embodiment; Figures 13A to 15 This is a schematic layout diagram illustrating the pixel arrangement structure in the component area of ​​a display panel according to various embodiments; Figures 16A to 16H This is a schematic plan view showing the shape of the bottom metal layer according to an embodiment; Figure 17 This is a schematic cross-sectional view of a portion of the display panel according to an embodiment; Figures 18A to 18C This is a schematic cross-sectional view illustrating a method for patterning counter electrodes according to an embodiment; Figures 19A to 19C This is a schematic cross-sectional view illustrating a method for patterning counter electrodes according to an embodiment and a display panel manufactured using the method; Figure 20A and Figure 20B This is a schematic cross-sectional view illustrating a method for patterning counter electrodes according to an embodiment; Figure 21A and Figure 21B This is a schematic cross-sectional view illustrating a method for patterning counter electrodes according to an embodiment; Figures 22A to 22C This is a plan view illustrating a method for patterning counter electrodes according to an embodiment; Figure 22D It is an application Figures 22A to 22CA schematic cross-sectional view of a portion of the display panel used in the manufacturing method; Figures 23A to 23E A method for patterning counter electrodes according to an embodiment is shown; Figure 24 This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 25 This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 26 This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 27A This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 27B This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 27C This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 27D This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 28 This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 29A and Figure 29B This is a schematic layout diagram illustrating the pixel arrangement structure in the component area according to an embodiment; Figure 30 It is along Figure 29A A schematic cross-sectional view taken from line II-II'; Figure 31 This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 32 It is a plan view of the display panel and the components arranged or disposed below the display panel according to an embodiment; Figure 33A and Figure 33B This is a schematic plan view illustrating the arrangement relationship between sub-pixels and wiring of a display panel according to an embodiment; Figure 34 This is a schematic cross-sectional view of a display panel according to an embodiment, and shows wiring arranged or disposed in the transmissive area; Figure 35 This is a schematic cross-sectional view of the display panel according to an embodiment, and shows the view along... Figure 33B A schematic cross-sectional view taken from lines III-III' and IV-IV'; Figure 36A and Figure 36BThis is a schematic plan view illustrating the arrangement relationship between sub-pixels and wiring of a display panel according to an embodiment; Figure 37 This is a schematic plan view illustrating the arrangement relationship between sub-pixels and wiring of a display panel according to an embodiment; Figure 38A and Figure 38B It is along Figure 37 A schematic cross-sectional view taken by line V-V'; Figures 39 to 41 This is a schematic plan view illustrating the arrangement relationship between sub-pixels and wiring of a display panel according to an embodiment; Figure 42 This is a schematic plan view of the display panel according to an embodiment; Figure 43 This is a schematic plan view illustrating the arrangement relationship between sub-pixels and wiring of a display panel according to an embodiment; Figure 44 This is a schematic plan view illustrating the arrangement relationship between sub-pixels and wiring of a display panel according to an embodiment; Figure 45 This is a schematic plan view of the display panel according to an embodiment; Figure 46 This is a schematic plan view of the load matching unit of the display panel according to an embodiment; Figure 47 It is along Figure 46 A schematic cross-sectional view taken from line VI-VI'; Figure 48 This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 49 This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 50 This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 51A This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 51B This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 51C This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 52 This is a plan view of the touchscreen layer of the display panel according to an embodiment; Figure 53 An example of a touch sensor driver unit connected to touch electrodes is shown; Figure 54This is an enlarged plan view of the touch sensing area of ​​the touch screen layer according to an embodiment; Figure 55 This is a plan view of the touchscreen layer of the display panel according to an embodiment; Figure 56 It is connected to Figure 55 Circuit diagram of the touch sensor driving unit for each touch electrode; Figure 57 This is a plan view of the touchscreen layer of the display panel according to an embodiment; Figure 58 and Figure 59 This is an enlarged plan view of a corresponding portion of the touchscreen layer according to an embodiment; Figures 60 to 62 This is a schematic cross-sectional view of a corresponding portion of the display panel according to an embodiment; Figure 63 and Figure 64 This is a schematic cross-sectional view of a corresponding portion of the display panel according to an embodiment; Figure 65 This is a perspective view of the display panel according to an embodiment; Figure 66 This is an expanded view of the display panel according to an embodiment; Figure 67 yes Figure 65 A front view of an example of a display panel; Figure 68 yes Figure 65 A rear view of an example of the display panel; Figure 69 yes Figure 65 A side view of an example of the display panel; Figure 70A This is an expanded view of a portion or area of ​​the display panel according to an embodiment; Figure 70B This is an expanded view of a portion or area of ​​the display panel according to an embodiment; Figure 71 This is an expanded view of a portion or area of ​​the display panel according to an embodiment; Figure 72 This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figures 73A to 73C It is a schematic cross-sectional view showing the positional relationship between the display panel and components arranged or disposed below the display panel according to an embodiment; Figure 74 This is a schematic perspective view of a display device according to an embodiment; Figure 75 It shows that Figure 74 The folded state of the display device; Figure 76It is one of them Figure 75 A schematic cross-sectional view of the display device in a folded state; Figures 77A to 77C The first component region to the third component region according to an embodiment are shown; Figure 78 This is a schematic plan view of the component areas of the display panel according to an embodiment; Figure 79A and Figure 79B This illustrates an embodiment. Figure 78 Schematic cross-sectional views of different shapes of deformed display panels; Figure 80 yes Figure 78 A schematic cross-sectional view of a portion or area of ​​the display panel; Figure 81 and Figure 82 These are schematic cross-sectional views of corresponding portions of a display device according to an embodiment; Figure 83 This is a schematic plan view of a second display panel that can be included in a display device; Figure 84A and Figure 84B This is a schematic cross-sectional view of a portion or area of ​​a display device according to an embodiment; Figures 85A to 85B This is a schematic plan view of a second display panel that can be included in a display device; Figure 86A This is a schematic plan view of the second display panel according to an embodiment; Figure 86B yes Figure 86A A schematic cross-sectional view of an embodiment; Figure 87 It is a circuit diagram showing the arrangement or placement of light-receiving pixels in the image sensor area; Figure 88 This is a schematic cross-sectional view of the image sensor area of ​​the second display panel according to an embodiment; Figure 89 This is a perspective view of the light-emitting element of a display device according to an embodiment; Figure 90 This is a plan view of the second display area of ​​the second display panel according to an embodiment; Figure 91 It is along Figure 90 A schematic cross-sectional view taken from line VII-VII'; Figure 92 and Figure 93 This is a plan view of an example of the second display area of ​​the second display panel; Figure 94 It is along Figure 92A schematic cross-sectional view taken from line VIII-VIII'; Figure 95 This is a schematic cross-sectional view of a display device according to an embodiment; Figure 96 yes Figure 95 A schematic plan view of an embodiment of the second display panel; Figure 97 This is a schematic cross-sectional view of a portion or area of ​​a display device according to an embodiment; Figure 98 Is included Figure 97 A plan view of an example of a second display panel in a display device; Figure 99 This is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment; Figure 100 This is a schematic cross-sectional view of the component area of ​​the display panel according to an embodiment; Figures 101A to 101C It is applicable Figure 100 A schematic cross-sectional view of a photodiode; Figure 102A This is a schematic plan view of the component areas of the display panel according to an embodiment; Figure 102B yes Figure 102A A schematic cross-sectional view of an embodiment; Figure 103 A schematic cross-sectional view of a display device according to an embodiment; and Figure 104 It is a schematic cross-sectional view of a portion or area of ​​a display device according to an embodiment. Detailed Implementation

[0062] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the following description, with reference to the accompanying drawings, focuses solely on embodiments to explain the described aspects.

[0063] In order to describe the disclosed embodiments, some parts that are not related to the description may be omitted, and throughout the specification, the same reference numerals refer to the same elements.

[0064] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0065] The terms “and” and “or” can be used in a combined or separate sense and can be understood as equivalent to “and / or”. In the specification and claims, for the purposes of their meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0066] One or more embodiments disclosed will now be described in more detail with reference to the accompanying drawings. Components that are identical or corresponding to each other are given the same reference numerals, independent of the drawing numbers, and redundant descriptions are omitted.

[0067] It will be understood that although the terms “first,” “second,” etc., may be used here to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. For example, without departing from the publicly stated teachings, the first element or first component discussed below may be referred to as the second element or second component. Similarly, the second element or second component may also be referred to as the first element or first component.

[0068] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are also intended to include the plural forms.

[0069] It will also be understood that when the terms “comprising,” “including,” “having,” and / or variations thereof are used in this specification, they may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0070] When a layer, film, region, substrate, area, or element is referred to as being "on" another layer, film, region, substrate, area, or element, it may be directly on the other layer, film, region, substrate, area, or element, or there may be intermediate layers, films, regions, substrates, areas, or elements therein. In contrast, when a layer, film, region, substrate, or area, element is referred to as being "directly on" another layer, film, region, substrate, area, or element, there are no intermediate layers, films, regions, substrates, areas, or elements therein. Furthermore, when a layer, film, region, substrate, or area, element is referred to as being "below" another layer, film, region, substrate, area, or element, it may be directly below the other layer, film, region, substrate, area, or element, or there may be intermediate layers, films, regions, substrates, areas, or elements therein. In contrast, when a layer, membrane, region, substrate, or area or element is referred to as being "directly below" another layer, membrane, region, substrate, or area or element, there is no intermediate layer, membrane, region, substrate, or area or element in between. Furthermore, "above" or "on" can include being positioned on or below an object and does not necessarily imply a direction based on gravity.

[0071] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” are used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to encompass different orientations of the device in use or operation besides those depicted in the drawings. For example, if the device shown in the drawings is flipped, the device positioned “below” or “under” another device may be placed “above” said other device. Therefore, the descriptive term “below” can include both a lower and upper position. The device may also be positioned in other directions, and thus the spatial relative terms can be interpreted differently depending on the orientation.

[0072] In the accompanying drawings, the dimensions and thicknesses of the elements may be enlarged for better understanding, clarity, and ease of description. However, the disclosure is not limited to the dimensions and thicknesses shown. In the accompanying drawings, the thicknesses of layers, films, panels, areas, and other elements may be exaggerated for clarity. In the accompanying drawings, the thicknesses of some layers and areas may be exaggerated for better understanding and ease of description.

[0073] Furthermore, in the instruction manual, the phrase "in a plan view" indicates the view of the target portion from above, while the phrase "in a schematic sectional view" indicates the view of the target portion as a schematic cross-section taken by vertically cutting it from the side.

[0074] Additionally, the term "overlay" or variations thereof indicates that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlay" may include stacking, overlapping, facing, or variations thereof, extending over, covering, or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The term "facing" or variations thereof indicates that the first element may be directly or indirectly opposite the second element. Where a third element is situated between the first and second elements, although they still face each other, the first and second elements may be understood as indirectly opposite each other. When an element is described as "not" "overlayed" with another element or similarly described, this may include elements spaced apart from each other, offset from each other, or separated from each other, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art.

[0075] When embodiments can be implemented differently, the specific process sequence can be performed in a manner different from that described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0076] It will be understood that when a layer, region, or component is referred to as "connected" or "bonded" to another layer, region, or component, it may be "directly connected" or "directly bonded" to said other layer, region, or component and / or may be "indirectly connected" or "indirectly bonded" to said other layer, region, or component, with other layers, regions, or components situated therebetween. For example, it will be understood that when a layer, region, or component is referred to as "electrically connected" to another layer, region, or component, it may be "directly electrically connected" to said other layer, region, or component and / or may be "indirectly electrically connected" to said other layer, region, or component, with other layers, regions, or components situated therebetween.

[0077] Furthermore, when an element is referred to as being in “contact” with another element or is described similarly, the element may be in “electrical contact” or “physical contact” with the other element; or in “indirect contact” or “direct contact” with the other element.

[0078] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms “about” or “approximately” as used herein include the stated value and indicate an acceptable deviation from the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0079] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0080] As used herein, the term "unit" refers to a structure or element as shown in the accompanying drawings and described in the specification. However, the disclosure is not limited thereto. The term "unit" is not limited to the structures or elements shown in the accompanying drawings.

[0081] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Furthermore, it will be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0082] Figure 1 This is a perspective view of display device 1 according to an embodiment. Figure 2 This is an exploded perspective view of the display device 1 according to an embodiment. Figure 3 This is a block diagram of display device 1 according to an embodiment.

[0083] Reference Figure 1 and Figure 2 The display device 1 according to the embodiment displays moving or still images, and therefore can be used as a display screen for various products, such as not only portable electronic devices (e.g., mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs)) but also televisions, laptops, monitors, advertising panels, and Internet of Things (IoT) devices. The display device 1 according to the embodiment can also be used in wearable devices such as smartwatches, watch phones, glasses displays, and head-mounted displays (HMDs). The display device 1 according to the embodiment can also be used as a vehicle dashboard, a central information display (CID) of a vehicle's center fascia or dashboard, an interior mirror display replacing a vehicle's side mirrors, and a display arranged or mounted on the rear side of the front seats for use as an entertainment device for rear-seat passengers.

[0084] For ease of explanation, Figure 1 and Figure 2 The illustration shows a smartphone used as a display device 1 according to an embodiment. The display device 1 according to the embodiment may include a cover window 50, a display panel 10, a display circuit board 30, a display driving unit 32, a touch sensor driving unit 33, a bracket 60, a main circuit board 70, a battery 80, and a lower cover 90.

[0085] The term "above" can indicate the direction in which the cover 50 can be arranged or positioned relative to the display panel 10, i.e., the +z direction, and the term "below" can indicate the direction in which the lower cover 90 can be arranged or positioned relative to the display panel 10, i.e., the -z direction. The terms "left," "right," "up," and "down" can indicate directions in which the display panel 10 can be viewed from above. For example, "left" indicates the -x direction, "right" indicates the +x direction, "up" indicates the +y direction, and "down" indicates the -y direction. However, the disclosure is not limited thereto.

[0086] According to the floor plan, display device 1 can have a substantially rectangular shape. For example, as shown... Figure 1 As shown, the display device 1 may have a generally rectangular planar shape having a shorter side along a first direction (x-direction) and a longer side along a second direction (y-direction). The angle between the shorter side along the first direction (x-direction) and the longer side along the second direction (y-direction) may be rounded to have a specific or predetermined curvature, or it may be a right angle. The planar shape of the display device 1 is not limited to a rectangle, and may be any other polygonal, elliptical, or irregular shape within the spirit and scope of this disclosure.

[0087] The cover window 50 can be located above the display panel 10 to cover the upper surface of the display panel 10 or overlap with the upper surface of the display panel 10. Therefore, the cover window 50 can be used to protect the upper surface of the display panel 10.

[0088] The cover window 50 may include a transmissive cover unit DA50 corresponding to the display panel 10 and a light-shielding cover unit NDA50 corresponding to the area other than the display panel 10. The light-shielding cover unit NDA50 may include an opaque material that blocks light. The light-shielding cover unit NDA50 may include a pattern that can be displayed to the user when no image can be displayed.

[0089] The display panel 10 can be positioned below the cover window 50. The display panel 10 can be stacked with the transmission cover unit DA50 of the cover window 50.

[0090] The display panel 10 may include a main display area MDA and a component area CA. Both the main display area MDA and the component area CA are areas where images can be displayed, and the component area CA may be an area beneath which components 40, such as sensors for sensing visible light, infrared light, sound, etc., can be arranged or positioned. According to an embodiment, the component area CA may have a higher light transmittance and / or a higher sound transmittance than the main display area MDA. According to an embodiment, when light is transmitted through the component area CA, the light transmittance in the component area CA may be about 25% or greater, or about 30% or greater, for example, about 50% or greater, about 75% or greater, about 80% or greater, about 85% or greater, or about 90% or greater.

[0091] Display panel 10 may be a light-emitting display panel that includes light-emitting elements. For example, display panel 10 may be an organic light-emitting display panel that uses organic light-emitting diodes that include organic emission layers, a micro LED display panel that uses micro light-emitting diodes (LEDs), a quantum dot light-emitting display panel that uses quantum dot LEDs that include quantum dot emission layers, or an inorganic light-emitting display panel that uses inorganic light-emitting elements that include inorganic semiconductors.

[0092] The display panel 10 can be a rigid display panel that is rigid and therefore not easily bent, or a flexible display panel that is flexible and therefore easily bent, folded, or rolled. For example, the display panel 10 can be a foldable display panel, a curved display panel with a curved display surface, a curved display panel with areas other than the display surface bent, a rollable display panel, or a stretchable display panel.

[0093] The display panel 10 can be a transparent display panel, which can be made transparent so that objects or backgrounds arranged or disposed on the lower surface of the display panel 10 can be seen through the upper surface of the display panel 10. Alternatively, the display panel 10 can be a reflective display panel, which can reflect objects or backgrounds onto the upper surface of the display panel 10.

[0094] The first flexible film 34 can be attached to the edge of the display panel 10. One side of the first flexible film 34 can be attached to the edge of the display panel 10 using an anisotropic conductive film. The first flexible film 34 can be a flexible film, and the flexible film can be bendable.

[0095] The display driving unit 32 can be located on the first flexible film 34. The display driving unit 32 can receive control signals and power supply voltage, and generate and output signals and voltages for driving the display panel 10. The display driving unit 32 can be an integrated circuit (IC).

[0096] The display circuit board 30 can be attached to the other side of the first flexible film 34. The other side of the first flexible film 34 can be attached to the upper surface of the display circuit board 30 using an anisotropic conductive film. The display circuit board 30 can be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a composite PCB. The FPCB can be flexible, the rigid PCB is rigid and therefore not easily bent, and the composite PCB includes both rigid PCB and FPCB.

[0097] The touch sensor driving unit 33 can be located on the display circuit board 30. The touch sensor driving unit 33 can be implemented as an IC. The touch sensor driving unit 33 can be attached to the upper surface of the display circuit board 30. The touch sensor driving unit 33 can be electrically connected to the touch electrodes of the touch screen layer of the display panel 10 via the display circuit board 30.

[0098] The touchscreen layer of the display panel 10 can sense user touch input using at least one of several sensing methods, such as resistive film methods and capacitive methods. For example, when the touchscreen layer of the display panel 10 senses user touch input using a capacitive method, the touch sensor driving unit 33 can apply a driving signal to the driving electrode in the touch electrode and sense the voltage charged in the mutual capacitance between the sensing electrode and the driving electrode in the touch electrode via the sensing electrode, thereby determining whether a user touch exists. User touch can include contact touch and proximity touch. Contact touch means that the user's finger or an object such as a pen directly touches the cover window 50 arranged or disposed on the touchscreen layer. Proximity touch means that the user's finger or an object such as a pen can be positioned or disposed on the cover window 50 at a close distance (such as hovering). The touch sensor driving unit 33 can transmit sensor data to the main processor 710 according to the sensed voltage, and the main processor 710 can calculate the touch coordinates at the input touch location by analyzing the sensor data.

[0099] The power supply can be arranged separately or located on the display circuit board 30. The power supply can provide the driving voltage to drive the pixels of the display panel 10, the scan driving unit, and the display driving unit 32. Alternatively, the power supply can be integrated with the display driving unit 32. In this case, the display driving unit 32 and the power supply can be implemented as a single IC.

[0100] A bracket 60 for supporting the display panel 10 may be located below the display panel 10. The bracket 60 may include plastic, metal, or both. The bracket 60 may include a first camera hole CMH1 through which a camera 731 can be inserted, a battery hole BH in which a battery 80 can be disposed or located, and a cable hole CAH through which a cable 35 connected to the display circuit board 30 can pass. The bracket 60 may also include a component hole CPH that can be superimposed on the component area CA of the display panel 10. The component hole CPH may be superimposed on the component 40 of the main circuit board 70 in the third direction (z-direction). Therefore, the component area CA of the display panel 10 may be superimposed on the component 40 of the main circuit board 70 in the third direction (z-direction). The bracket 60 may not include the component hole CPH. In this case, the bracket 60 may be positioned or configured not to be superimposed on the component area CA of the display panel 10 in the third direction (z-direction).

[0101] The display panel 10 may include components 40 that can be superimposed on the component area CA. For example, a first component 41, a second component 42, a third component 43, and a fourth component 44 may be superimposed on the component area CA. The first component 41, the second component 42, the third component 43, and the fourth component 44 may be a proximity sensor, an illuminance sensor, an iris sensor, and a camera (or image sensor), respectively, but the disclosure is not limited thereto. Because the component area CA of the display panel 10 may include a specific or predetermined transmittance, a proximity sensor using infrared light can detect objects disposed near the upper surface of the display device 1, and an illuminance sensor can sense the brightness of light that can be incident on the upper surface of the display device 1. An iris sensor disposed or disposed on the upper surface of the display device 1 can image a person's iris, and a camera can capture images of objects disposed or disposed on the upper surface of the display device 1. The components 40 superimposed on the component area CA of the display panel 10 are not limited to proximity sensors, illuminance sensors, iris sensors, and cameras, but may be various other sensors described later.

[0102] The main circuit board 70 and the battery 80 can be located below the bracket 60. The main circuit board 70 can be a PCB or an FPCB.

[0103] The main circuit board 70 may include a main processor 710, a camera 731, a main connector 75, and component 40. The main processor 710 may be implemented as an IC. The camera 731 may be arranged or disposed on both the upper and lower surfaces of the main circuit board 70, and each of the main processor 710 and the main connector 75 may be arranged or disposed on one of the upper and lower surfaces of the main circuit board 70.

[0104] The main processor 710 can control all functions of the display device 1. For example, the main processor 710 can output digital video data to the display driver unit 32 via the display circuit board 30, causing the display panel 10 to display an image. The main processor 710 receives sensor data from the touch sensor driver unit 33. The main processor 710 can determine whether a user touch is present based on the sensor data and can perform operations corresponding to a direct or near touch by the user. For example, the main processor 710 can calculate the user's touch coordinates by analyzing the sensor data and then execute an application or operation indicated by an icon touched by the user. The main processor 710 can be an application processor, a central processing unit, or a system-on-a-chip (SoC) implemented as an IC.

[0105] Camera 731 processes image frames, such as still images or moving images, acquired through an image sensor in camera mode and outputs the processing results to main processor 710. Camera 731 may include at least one of a camera sensor (e.g., CCD or CMOS), a light sensor (or image sensor), and a laser sensor. Camera 731 may be connected to the image sensor in component 40 superimposed with component region CA and may process images input to the image sensor.

[0106] The cable 35, passing through the cable hole CAH of the bracket 60, can be connected to the main connector 75, so that the main circuit board 70 can be electrically connected to the display circuit board 30.

[0107] In addition to the main processor 710, camera 731, and main connector 75, the main circuit board 70 may also include at least one of the modules included in the wireless communication interface 720, at least one of the components included in the input interface 730, at least one of the components included in the sensor unit 740, at least one of the components included in the output interface 750, at least one of the components included in the interface unit 760, memory 770, and power supply 780.

[0108] The wireless communication interface 720 may include at least one of a broadcast receiving module 721, a mobile communication module 722, a wireless internet module 723, a short-range communication module 724, and a location information module 725.

[0109] The broadcast receiving module 721 can receive broadcast signals and / or broadcast-related information from an external broadcast management server via a broadcast channel. Within the spirit and scope of public disclosure, the broadcast channel can be a satellite channel, a ground wave channel, etc.

[0110] The mobile communication module 722 can transmit or receive wireless signals from at least one of a base station, an external terminal, and a server on a mobile communication network established according to technical standards or communication methods used for mobile communication (e.g., Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Code Division Multiple Access 2000 (CDMA2000), Enhanced Voice Data Optimized or Enhanced Voice Data Only (EV-DO), Wideband CDMA (WCDMA), High-Speed ​​Downlink Packet Access (HSDPA), High-Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), and LTE-A Advanced). Examples of wireless signals may include voice call signals, video call signals, and various types of data transmitted according to text / multimedia messages.

[0111] Wireless Internet Module 723 indicates a module for wireless Internet access. Wireless Internet Module 723 can transmit or receive wireless signals in a communication network based on wireless Internet technology. Wireless Internet technology can be, for example, Wireless LAN (WLAN), Wi-Fi, Wi-Fi Direct, and Digital Living Network Alliance (DLNA).

[0112] The short-range communication module 724 is used for short-range communication, and therefore can be used via Bluetooth. TM The short-range communication module 724 supports at least one of the following technologies: Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra Wideband (UWB), ZigBee, Near Field Communication (NFC), Wi-Fi, Wi-Fi Direct, and Wireless Universal Serial Bus (Wireless USB). The short-range communication module 724 can support wireless communication between the display device 1 and a wireless communication system, between the display device 1 and another electronic device, or between the display device 1 and a network that can locate or set up another electronic device (or an external server) via a wireless local area network. The wireless local area network can be a wireless personal area network. The other electronic device can be a wearable device capable of exchanging data with (or interacting with) the display device 1.

[0113] The location information module 725 is included to obtain the location (or current location) of the display device 1. Representative examples of the location information module 725 include a Global Positioning System (GPS) module and a WiFi module. For example, if a GPS module is available, the display device 1 can obtain its location using signals transmitted by GPS satellites. If a WiFi module is available, the display device 1 can obtain its location based on information from a wireless access point (AP) that can transmit or receive wireless signals to or from the WiFi module. Because the location information module 725 can be used to obtain the location (or current location) of the display device 1, it is not limited to modules that directly calculate or obtain the location of the display device 1.

[0114] The input interface 730 may include an image input interface (such as a camera 731) for inputting image signals, an audio input interface (such as a microphone 732) for inputting audio signals, and an input device 733 for receiving information from a user.

[0115] Camera 731 processes image frames, such as still images or moving images, obtained from the image sensor in video call mode or image capture mode. The processed image frames corresponding to the processing results can be displayed on display panel 10 or stored in memory 770.

[0116] Microphone 732 processes external audio signals into electrical audio data. The electrical audio data can be used in various ways depending on the function (or application) currently being executed on display device 1. Various noise removal algorithms can be implemented in microphone 732 to remove noise that may be generated while receiving external audio signals.

[0117] The main processor 710 can control the operation of the display device 1 to correspond to information that can be input via the input device 733. The input device 733 may include mechanical input units (such as buttons, dome switches, jog wheels, and jog switches that are positioned or disposed on the rear or side surfaces of the display device 1) or touch input units. The touch input unit may be implemented as a touch screen layer of the display panel 10.

[0118] Sensor unit 740 may include at least one sensor that senses at least one of information within display device 1, information about the surrounding environment of display device 1, and user information, and generates a sensing signal corresponding to the at least one type of information. Based on such sensing signals, main processor 710 may control the driving or operation of display device 1, or may perform data processing, functions, or operations associated with applications configured in display device 1. Sensor unit 740 may include at least one of proximity sensor, illuminance sensor, accelerometer, magnetic sensor, gravity (G) sensor, gyroscope sensor, motion sensor, RGB sensor, infrared (IR) sensor, finger scanning sensor, ultrasonic sensor, optical sensor, battery gauge, environmental sensor (e.g., barometer, hygrometer, thermometer, radiation sensor, thermal sensor, and gas sensor), and chemical sensor (e.g., electronic nose, medical sensor, and biosensor).

[0119] A proximity sensor can be a sensor that can detect the presence of an object approaching or existing near a predetermined sensing surface without mechanical contact using electromagnetic force or IR rays. Examples of proximity sensors include transmissive photoelectric sensors, direct reflective photoelectric sensors, specular reflective photoelectric sensors, high-frequency oscillation proximity sensors, capacitive proximity sensors, magnetic proximity sensors, and infrared proximity sensors. A proximity sensor can sense not only proximity touch operations but also proximity touch patterns, such as proximity touch distance, proximity touch direction, proximity touch speed, proximity touch time, proximity touch position, or proximity touch motion state. The main processor 710 can process the data (or information) corresponding to both the proximity touch operation and proximity touch pattern sensed by the proximity sensor, and can control the visual information corresponding to the processed data to be displayed on the display panel 10.

[0120] An ultrasonic sensor can identify the position information of an object by using ultrasonic waves. The main processor 710 can calculate the position of the object using information sensed by the optical sensor and the ultrasonic sensor. Because the speed of light is different from the speed of ultrasound, the position of the object can be calculated using the time it takes for light to reach the optical sensor and the time it takes for ultrasound to reach the ultrasonic sensor.

[0121] The output interface 750 produces outputs associated with vision, hearing, or touch, and may therefore include at least one of the display panel 10, audio output interface 751, haptic module 752, and optical output interface 753.

[0122] Display panel 10 can display (or output) information that can be processed by display device 1. For example, display panel 10 can display execution screen information of an application being driven by display device 1, or can display user interface (UI) and graphical user interface (GUI) information based on execution screen information. Display panel 10 may include a display layer for displaying images and a touch screen layer for sensing user touch input. Therefore, display panel 10 can be used as an input device 733 that provides an input interface between display device 1 and the user, and also as an output interface 750 that provides an output interface between display device 1 and the user.

[0123] The audio output interface 751 can output audio data received from the wireless communication interface 720 or stored in the memory 770 in modes such as call signal receiving mode, call or recording mode, voice recognition mode, and broadcast receiving mode. The audio output interface 751 also outputs audio signals related to functions performed by the display device 1 (e.g., call signal receiving sound or message receiving sound). The audio output interface 751 may include a receiver and a speaker. At least one of the receiver and speaker may be an audio generating device that can be attached to the lower part of the display panel 10 and vibrate the display panel 10 to output audio. The audio generating device may be a piezoelectric element or piezoelectric actuator that contracts and expands according to an electrical signal, or an exciter that generates magnetic force by using a voice coil to vibrate the display panel 10.

[0124] The haptic module 752 generates various tactile effects that the user can perceive. The haptic module 752 can provide vibrations as a tactile effect to the user. The intensity, mode, etc., of the vibrations generated by the haptic module 752 can be controlled according to the user's selection or the settings of the main processor 710. For example, the haptic module 752 can synthesize different vibrations and output the synthesized result, or it can output different vibrations sequentially. In addition to vibrations, the haptic module 752 can also generate various other tactile effects, such as the effects of needle arrangement moving vertically relative to the skin surface, the jetting or suction force of air through a nozzle or inlet, the gentle rubbing of the skin surface, the contact of electrodes, and stimulation effects such as electrostatic forces, as well as the effects of reproducing cold and heat sensations by using elements that can absorb and generate heat. The haptic module 752 can transmit tactile effects through direct contact, and within the spirit and scope of the disclosure, it can also be implemented so that the user can perceive the tactile effects through the muscle sensations of the fingers, arms, etc.

[0125] The optical output interface 753 outputs a signal to notify of an event by using light from a light source. Examples of events generated in the display device 1 may include message reception, call signal reception, missed call, alarm, calendar notification, email reception, and information reception via an application. The signal output by the optical output interface 753 can be realized when the display device 1 emits monochromatic or multicolor light to its front or rear surface. The output of the signal can be terminated when the display device 1 senses a user confirmation event.

[0126] Interface unit 760 serves as a channel for various types of external devices connected to display device 1. Interface unit 760 may include at least one of the following: a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device including an identification module, an audio input / output (I / O) port, a video I / O port, and an earphone port. When an external device is connected to interface unit 760, display device 1 can perform appropriate control related to the connected external device.

[0127] The memory 770 can store data supporting various functions of the display device 1. The memory 770 can store applications driven by the display device 1, multiple data entries for the operation of the display device 1, and instructions. At least some or a predetermined number of applications can be downloaded from an external server via wireless communication. The memory 770 can store applications for the operation of the main processor 710 and can temporarily store input / output data, such as phone books, messages, still images, and moving images. The memory 770 can also store tactile data for various vibration modes that can be provided to the tactile module 752, and audio data for various sounds that can be provided to the audio output interface 751. The memory 770 can include at least one type of storage medium selected from flash memory, hard disk, solid-state drive (SSD), silicon disk drive (SDD), multimedia card micro, card-type memory (e.g., Secure Digital (SD) or Extreme Digital (XD) memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), programmable ROM (PROM), magnetic storage, magnetic disk, and optical disk.

[0128] Under the control of the main processor 710, the power supply 780 can receive external and internal power, and can supply external and internal power to components included in the display device 1. The power supply 780 may include a battery 80. The power supply 780 may include a connection port, which may be an example of an interface unit 760, to which an external charger supplying power to charge the battery 80 can be electrically connected. Alternatively, the power supply 780 can wirelessly charge the battery 80 without using the connection port. The battery 80 can receive power from an external wireless power transmission device using at least one of an inductive coupling method based on magnetic induction and a magnetic resonance coupling method based on electromagnetic resonance. The battery 80 may be arranged or configured not to overlap with the main circuit board 70 in the third direction (z-direction). The battery 80 may overlap with the battery hole BH of the bracket 60.

[0129] The lower cover 90 may be located below the main circuit board 70 and the battery 80. The lower cover 90 may be fastened to the bracket 60 and fixed in place. The lower cover 90 may form the appearance of the lower surface of the display device 1. The lower cover 90 may include plastic, metal, or both plastic and metal.

[0130] The second camera aperture CMH2 can be provided or disposed in the lower cover 90, and the lower surface of the camera 731 can be exposed through the second camera aperture CMH2. The position of the camera 731 and the positions of the corresponding first camera aperture CMH1 and second camera aperture CMH2 are not limited to... Figure 1 and Figure 2 Examples of implementations.

[0131] Figure 4 This is a plan view of the display panel 10 according to an embodiment. Figure 5 yes Figure 4 A side view of an example of the display panel 10. Figure 4 A plan view of the display panel 10 with its first flexible film 34 unfolded is shown.

[0132] Reference Figure 4 and Figure 5 The display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, an optical functional layer OFL, and a panel protective component PB.

[0133] Substrate 100 may include insulating materials such as glass, quartz, and polymeric resins. Substrate 100 may be a rigid or flexible substrate; a flexible substrate may be bendable, foldable, or rollable. For example, substrate 100 may include polymeric resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Substrate 100 may have a multilayer structure comprising a layer containing the aforementioned polymeric resin and an inorganic layer (not shown). For example, substrate 100 may include two layers containing the aforementioned polymeric resin and an inorganic barrier layer located between the two layers.

[0134] The display layer DISL can be disposed on the substrate 100. The display layer DISL may include pixels and may be a layer capable of displaying images. The display layer DISL may include a circuit layer containing thin-film transistors, a display element layer in which display elements can be arranged or disposed, and a packaging component capable of encapsulating the display element layer.

[0135] The display layer DISL can be divided into a display area DA and a peripheral area DPA. The display area DA can be an area that includes pixels arranged or disposed therein and can display images. The peripheral area DPA can be an area outside or adjacent to the display area DA, and does not display images. The peripheral area DPA can be arranged or disposed around or adjacent to the display area DA. The peripheral area DPA can be a region extending from the outer edge of the display area DA to the edge of the display panel 10. In the display area DA, not only pixels but also pixel circuits driving the pixels, as well as scan lines, data lines, and power lines electrically connected to the pixel circuits, can be arranged or disposed. A scan drive unit that can apply scan signals to the scan lines and a fan-out line that can electrically connect the data lines to the display drive unit 32 can be arranged or disposed in the peripheral area DPA.

[0136] The touchscreen layer (TSL) can be located on the display layer (DISL). The touchscreen layer (TSL) may include touch electrodes and can sense the presence of a user touch. The touchscreen layer (TSL) may be located directly on the encapsulation component of the display layer (DISL). Alternatively, the touchscreen layer (TSL) may be provided separately and then bonded to the upper surface of the encapsulation component of the display layer (DISL) via an adhesive layer (such as optically clear adhesive (OCA)).

[0137] The optical functional layer OFL can be located on the touchscreen layer TSL. The optical functional layer OFL may include an anti-reflective layer. The anti-reflective layer can reduce the reflectivity of light (external light) incident from an external source toward the display device 1.

[0138] According to an embodiment, the anti-reflection layer may include a polarizing film. The polarizing film may include a linear polarizer and a phase retardation film such as a quarter-wave (λ / 4) plate. The phase retardation film may be located on the touchscreen layer TSL, and the linear polarizer may be located on the phase retardation film.

[0139] According to an embodiment, the anti-reflective layer may include a filter layer comprising a black matrix and color filters. The color filters can be arranged or configured taking into account the color of the light beam emitted by the pixels of display device 1. For example, the filter layer may include red, green, or blue color filters.

[0140] According to an embodiment, the antireflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, can destructively interfere with each other, thereby reducing the reflectivity of external light.

[0141] Cover window 50 can be arranged or disposed on the optical functional layer OFL. Cover window 50 can be attached to the upper surface of the optical functional layer OFL by means of a transparent adhesive member such as an OCA film.

[0142] The panel protection member PB can be located below the display panel 10. The panel protection member PB can be attached to the lower surface of the display panel 10 using an adhesive member. The adhesive member can be a pressure-sensitive adhesive (PSA). The panel protection member PB can include at least one of the following: a light-absorbing layer for absorbing external incident light, a cushioning layer for absorbing external impacts, and a heat sink layer for effectively dissipating heat from the display panel 10.

[0143] A light-absorbing layer may be disposed beneath the display panel 10. The light-absorbing layer blocks light transmission, preventing components arranged or disposed beneath the light-absorbing layer (e.g., display circuit board 30) from being visible from above the display panel 10. The light-absorbing layer may include a light-absorbing material, such as black pigment or black dye.

[0144] A buffer layer may be disposed below the light-absorbing layer. The buffer layer can absorb external impacts to prevent damage to the display panel 10. The buffer layer may be a single layer or multiple layers. For example, the buffer layer may include copolymer resins (such as polyurethane, polycarbonate, polypropylene, or polyethylene), or may include elastic materials (such as rubber, polyurethane-based materials, or sponges obtained by foaming acrylic materials).

[0145] The heat sink layer may be located below the buffer pad layer. The heat sink layer may include a first heat sink layer and a second heat sink layer. The first heat sink layer includes graphite or carbon nanotubes, and the second heat sink layer may shield electromagnetic waves and include a thin film of metal with high thermal conductivity, such as copper, nickel, ferrite, or silver.

[0146] The panel protection component PB may include an opening PB_OP corresponding to the component area CA. Including the opening PB_OP in the panel protection component PB can improve the light transmittance of the component area CA.

[0147] The component region CA can have an area larger than the area where the component 40 can be arranged or positioned. Therefore, the area of ​​the opening PB_OP included in the panel protection member PB can be different from the area of ​​the component region CA. The component 40 can be arranged or configured to overlap with the opening PB_OP. According to an embodiment, the component 40 can be arranged or configured to be inserted into the opening PB_OP.

[0148] The first flexible film 34 may be located in the peripheral region DPA of the edge of the display panel 10. The first flexible film 34 may be bent below the display panel 10, and the display circuit board 30 may be positioned or disposed on the lower surface of the panel protection member PB. The display circuit board 30 may be attached to and fixed to the lower surface of the panel protection member PB via a first adhesive member 39. The first adhesive member 39 may be a PSA.

[0149] The display area DA of the display panel 10 may include a component area CA and a main display area MDA, and the component 40 may be arranged or disposed below the component area CA. The component area CA may be arranged or disposed on one side of the main display area MDA. According to an embodiment, Figure 4 The diagram illustrates that the component region CA can be a strip-shaped component region with the same width as the main display region MDA in the x-direction. The component region CA can be positioned between the peripheral region DPA and the main display region MDA, such that the upper, right, and left edges of the component region CA can contact the peripheral region DPA, and its lower edge can contact the main display region MDA.

[0150] Figure 6 This is a plan view of the display panel 10 according to an embodiment. Figure 7 yes Figure 6 A side view of an example of the display panel 10. Figure 6 A plan view of the display panel 10 unfolded in its first curved region BA1 is shown.

[0151] Figure 6 and Figure 7 Implementation examples and Figure 4 and Figure 5 The difference in the embodiment is that the first bending region BA1 on one side of the display panel 10 can be bent, so that the first pad (or "soldering pad") region PDA1 can be positioned or disposed on the lower surface of the panel protection member PB. In other words, the display panel 10 can be a display panel whose one side is bendable.

[0152] Reference Figure 6 and Figure 7 The first curved region BA1 and the first pad region PDA1 can protrude from the peripheral region DPA on one side of the display panel 10 in the -y direction. For example... Figure 6 As shown, the corresponding lengths of the first curved region BA1 and the first pad region PDA1 in the x direction can both be smaller than the length of the display region DA in the x direction.

[0153] The display panel 10 can be bent at the first bending region BA1, and the first pad region PDA1 can be arranged or disposed on the lower surface of the panel protective member PB. The first pad region PDA1 can be superimposed on the display region DA in the thickness direction (z direction) of the display panel 10. The display driving unit 32 and the display circuit board 30 can be arranged or disposed in the first pad region PDA1.

[0154] Despite Figure 4 and Figure 6 The component area CA of the display area DA is included as a bar, but the embodiment is not limited thereto. For example, the shape of the component area CA can be circular, elliptical, or a polygon such as a triangle or pentagon, and the position of the component area CA can vary. The display device can have two or more component areas CA, and the component areas CA can have different shapes and different sizes.

[0155] Figures 8A to 8I The component region CA is shown, which has a shape and arrangement according to various embodiments.

[0156] Reference Figures 8A to 8F Each component region (CA) can be arranged or placed within the main display area (MDA), and can be surrounded by or adjacent to the main display area (MDA). The component region (CA) can have a substantially circular shape, and multiple component regions can be included. For example... Figure 8A As shown, the component area CA can be arranged or set in the upper right part of the display area DA. Figure 8B As shown, the component area CA can be arranged or positioned at the center of the upper part of the display area DA. Figure 8C As shown, the component area CA can be arranged or positioned at the center of the display area DA. When an image capturing device, such as a camera, can be arranged or positioned corresponding to the component area CA, this arrangement allows the user's eyes to be naturally captured during selfies or video calls.

[0157] like Figure 8D and Figure 8E As shown, the component region CA may include a first component region CA1 and a second component region CA2 arranged side-by-side in the y-direction. Alternatively, as... Figure 8F As shown, the component region CA may include a first component region CA1 and a second component region CA2 arranged side-by-side in the x-direction. In this case, the first component region CA1 and the second component region CA2 may be spaced apart from each other, and each of the first component region CA1 and the second component region CA2 may be surrounded by or adjacent to the main display region MDA. In this case, a first camera may be arranged or configured corresponding to the first component region CA1, and a second camera may be arranged or configured corresponding to the second component region CA2. Figure 8E As shown, the component area CA can be arranged or positioned at the center of the longer edge of the display area DA. This arrangement can be useful when the display device can be used in landscape mode.

[0158] like Figure 8G As shown, the display area DA may include three or more component regions CA. Component regions CA may include first component regions CA1 to fourth component regions CA4, located at the four corners of the display area DA, respectively. Component regions CA may also include a fifth component region CA5 located at the center of the display area DA. First to fifth cameras may be arranged or configured to correspond to first to fifth component regions CA1 to CA5, respectively. In this case, because images can be captured from various angles, image compensation can be achieved based on the images captured by the first to fifth cameras.

[0159] like Figure 8H and Figure 8I As shown, component regions CA can be arranged or configured such that one side of each component region CA contacts the peripheral region DPA. (Refer to...) Figure 8H and Figure 8I Each component area CA can be a notched component area that can be inserted from one side of the display area DA toward the center of the display area DA. The notch can be any shape of various shapes such as rectangle, semicircle, and semi-ellipse.

[0160] Figures 9A to 9E It is a schematic cross-sectional view of a portion or area of ​​the display device 1 according to an embodiment.

[0161] Reference Figures 9A to 9E The display device 1 may include a display panel 10 and a component 40 superimposed on the display panel 10. The display panel 10 may include a component area CA superimposed on the component 40 and a main display area MDA on which the main image is displayed.

[0162] The display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, and an optical functional layer OFL located on the substrate 100, and a panel protection member PB located below the substrate 100. The display layer DISL may include a circuit layer PCL, a display element layer EDL, and an encapsulation member ENCM (such as a thin film encapsulation layer TFEL or an encapsulation substrate ENS). The circuit layer PCL includes a main thin film transistor TFT and an auxiliary thin film transistor TFT'. The display element layer EDL includes a main light-emitting element (i.e., the main display element) ED and an auxiliary light-emitting element (i.e., the auxiliary display element) ED'. Insulating layers IL and IL' may be disposed or located between the substrate 100 and the display layer DISL, and within the display layer DISL.

[0163] As described above, substrate 100 may include an insulating material such as glass, quartz, or polymer resin. Substrate 100 may be a rigid substrate or a flexible substrate, and a flexible substrate may be bendable, foldable, or rollable.

[0164] The main thin-film transistor (TFT) and the main light-emitting element (ED) electrically connected thereto can be arranged or configured to realize or form a main sub-pixel Pm in the main display area MDA of the display panel 10. The auxiliary thin-film transistor (TFT) and the auxiliary light-emitting element (ED) electrically connected thereto can be arranged or configured to realize an auxiliary sub-pixel Pa in the component area CA of the display panel 10.

[0165] The transmissive region TA, which does not contain any display elements, can be arranged or positioned within the component region CA. The transmissive region TA can transmit light / signals emitted by the component 40 arranged or positioned corresponding to the component region CA, or light / signals incident on the component 40.

[0166] A bottom metal layer (BML) can be disposed or located within the component region CA. The bottom metal layer (BML) can be disposed or located below the auxiliary thin-film transistor (TFT) '. For example, the bottom metal layer (BML) can be located between the auxiliary thin-film transistor TFT ' and the substrate 100. The bottom metal layer (BML) can prevent external light from reaching the auxiliary thin-film transistor TFT '. According to an embodiment, a static voltage or signal can be applied to the bottom metal layer (BML), thus preventing damage to the pixel circuitry from electrostatic discharge. The bottom metal layer (BML) can be disposed or located within the component region CA. In some cases, different voltages can be applied to the bottom metal layer (BML). A single bottom metal layer (BML) including a hole corresponding to the transmission region TA can be positioned or located within the component region CA.

[0167] The display element layer (EDL) can be covered by a thin-film encapsulation layer (TFEL) or by an encapsulation substrate (ENS), or stacked with a thin-film encapsulation layer (TFEL) or an encapsulation substrate (ENS). According to an embodiment, such as... Figure 9A As shown, the thin-film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. According to an embodiment, the thin-film encapsulation layer TFEL may include a first inorganic encapsulation layer 131, a second inorganic encapsulation layer 133, and an organic encapsulation layer 132 located between the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133.

[0168] According to the embodiments, such as Figure 9B As shown, the encapsulation substrate ENS can be arranged or positioned facing the substrate 100, and the display element layer EDL is located between the encapsulation substrate ENS and the substrate 100. A gap may exist between the encapsulation substrate ENS and the display element layer EDL. The encapsulation substrate ENS may include glass. A sealant including glass frit, etc., can be arranged or disposed between the substrate 100 and the encapsulation substrate ENS, and can be arranged or disposed in the peripheral area DPA. The sealant arranged or disposed in the peripheral area DPA can surround the display area DA and can prevent moisture from penetrating through the side surface of the display panel 10.

[0169] A touchscreen layer (TSL) can obtain coordinate information based on external inputs (e.g., touch events). A TSL may include touch electrodes and touch wiring electrically connected to the touch electrodes. The TSL can sense external inputs using either self-capacitance or mutual capacitance methods.

[0170] The touchscreen layer TSL can be located on the encapsulation member ENCM. Alternatively, the touchscreen layer TSL can be provided separately or disposed on the touch substrate and then bonded to the upper surface of the encapsulation member ENCM via an adhesive layer (such as OCA). According to an embodiment, such as... Figures 9A to 9D As shown, the touchscreen layer TSL can be provided directly or disposed on the encapsulation component ENCM. In this case, there may be no adhesive layer between the touchscreen layer TSL and the encapsulation component ENCM.

[0171] The optical functional layer OFL may include an anti-reflective layer. The anti-reflective layer can reduce the reflectivity of light (external light) incident from an external source toward the display device 1.

[0172] According to an embodiment, the optical functional layer OFL can be a polarizing film. The optical functional layer OFL may include an opening OFL_OP corresponding to the transmission region TA. Therefore, the transmittance of the transmission region TA can be significantly improved. The opening OFL_OP may be filled with a transparent material, such as optically transparent resin (OCR).

[0173] According to the embodiments, such as Figure 9CAs shown, the optical functional layer OFL may include a filter 180 containing a black matrix and a color filter. The filter 180 may include a substrate layer 181, a color filter 182 located on the substrate layer 181, a black matrix 183, and an outer coating 184.

[0174] Color filters 182 can be arranged or configured to take into account the color of the light beam emitted by the pixels of display panel 10. For example, each color filter 182 may be red, green, or blue depending on the color of the light beam emitted by the main light-emitting element ED and the auxiliary light-emitting element ED'. Color filters 182 and black matrix 183 are not present in the transmission region TA. For example, the layer including color filters 182 and black matrix 183 may include apertures 183OP corresponding to the transmission region TA, and at least a portion of the apertures 183OP may be filled with a portion of the outer coating 184. The outer coating 184 may include an organic material such as resin, and the organic material may be transparent.

[0175] like Figure 9D As shown, a cover window 50 can be arranged or disposed above the display panel 10 to protect the display panel 10. The cover window 50 may include a lens member 50L embedded therein to correspond to the transmissive area TA of the display panel 10. The lens member 50L can be arranged or disposed when the component 40 arranged or disposed in the component area CA is a camera or image sensor. Due to the arrangement or disposal of the lens member 50L, external light can be focused onto the component 40, which may be a camera, thus improving the quality of the image captured by the camera.

[0176] like Figure 9E As shown, component 40 can be attached to the lower surface of display panel 10. The panel protection component PB may include a protective layer PY, a light-blocking layer LBY, a buffer layer CY, and a heat sink layer HSY. The protective layer PY can be attached to the lower surface of substrate 100 and protect substrate 100. For example, the protective layer PY can absorb external physical impacts or prevent foreign objects, moisture, etc., from penetrating into the display layer DISL. The protective layer PY can be coated on the lower surface of substrate 100 or can be attached to the lower surface of substrate 100 in the form of a film.

[0177] According to embodiments, the protective layer PY may include a material that blocks ultraviolet (UV) radiation. For example, the protective layer PY may include a matrix resin, a UV absorber, and inorganic particles. The UV absorber and inorganic particles may be dispersed and provided to the matrix resin. The matrix resin may be an acrylate resin, such as a polyurethane acrylate. However, the embodiments are not limited thereto. A matrix resin that is optically transparent and can disperse the UV absorber and inorganic particles may be used in the protective layer PY without limitation or restriction.

[0178] For example, UV absorbers may include at least one of benzotriazole compounds, benzophenone compounds, salicylic acid compounds, salicylic ester compounds, cyanoacrylate compounds, cinnamic ester compounds, oxaloaniline compounds, polystyrene compounds, methylimine compounds, and triazine compounds.

[0179] A light-blocking layer LBY may be located on the lower surface of the protective layer PY, and a cushioning layer CY may be located on the lower surface of the light-blocking layer LBY. The light-blocking layer LBY may be a double-sided adhesive between the protective layer PY and the cushioning layer CY. The light-blocking layer LBY may absorb external incident light. For example, the light-blocking layer LBY may be a black layer to absorb external light. However, the embodiments are not limited to this. The light-blocking layer LBY may include various materials capable of absorbing external light.

[0180] A cushioning layer CY can be attached to the lower surface of the light-blocking layer LBY to protect the display panel 10. The cushioning layer CY may include an elastic material and may be, for example, sponge or rubber.

[0181] The heat sink layer HSY can be located below the buffer pad layer CY. The heat sink layer HSY can include a first heat sink layer and a second heat sink layer. The first heat sink layer includes graphite or carbon nanotubes, and the second heat sink layer can shield electromagnetic waves and includes a thin metal film with high thermal conductivity, such as copper, nickel, ferrite, or silver.

[0182] The positions of the protective layer PY, light-blocking layer LBY, buffer layer CY, and heat sink layer HSY that make up the panel protection component PB can be varied.

[0183] As described above, the panel protection component PB may include an opening PB_OP corresponding to the component area CA, and the component 40 may be located within the opening PB_OP.

[0184] Component 40 can be mounted on package 40SP, and package 40SP can be attached to the lower surface of substrate 100 via adhesive member 40RS. Package 40SP may include control circuitry electrically connected to main circuit board 70 and component 40.

[0185] OCR can be filled between the lower surface of the component 40 and the substrate 100. The OCR can be optically transparent, thus minimizing the loss of light incident on the component 40.

[0186] The adhesive member 40RS can fix or bond the package 40SP to the lower surface of the substrate 100. The adhesive member 40RS may include resin. In other words, after the resin is arranged or positioned to contact the package 40SP and the lower surface of the substrate 100, it can be cured by UV. The adhesive member 40RS may include a light-absorbing material.

[0187] Figure 10 This is a schematic plan view of the display panel 10 according to an embodiment.

[0188] Reference Figure 10 Various components constituting the display panel 10 can be arranged or disposed on the substrate 100. The substrate 100 may include a display area DA and a peripheral area DPA surrounding or adjacent to the display area DA. The display area DA may include a main display area MDA on which a main image can be displayed and a component area CA that may contain a transmissive area TA on which an auxiliary image can be displayed. The auxiliary image may form a single overall image together with the main image, or it may be an image independent of the main image.

[0189] The main sub-pixel Pm can be arranged or set in the main display area MDA. Each main sub-pixel Pm can be implemented as a display element such as an organic light-emitting diode. Each main sub-pixel Pm can emit, for example, red, green, blue, or white light. Within the spirit and scope of the disclosure, the main display area MDA can be covered or stacked with a packaging component, and thus can be protected from the effects of ambient air, moisture, etc.

[0190] As described above, the component region CA can be positioned or disposed on one side of the main display region MDA, or it can be arranged or disposed within the display region DA and surrounded or adjacent to the main display region MDA. Auxiliary subpixels Pa can be arranged or disposed within the component region CA. Each auxiliary subpixel Pa can be implemented as a display element such as an organic light-emitting diode (OLED). Each auxiliary subpixel Pa can emit, for example, red, green, blue, or white light. Within the spirit and scope of this disclosure, the component region CA can be covered by or stacked with an encapsulation component, thus protecting it from ambient air, moisture, etc.

[0191] The component region CA may have a transmission region TA. The transmission region TA may be arranged or configured to surround or be adjacent to the auxiliary sub-pixel Pa. Alternatively, the transmission region TA may be arranged together with the auxiliary sub-pixel Pa or configured as a mesh structure.

[0192] Because the component area CA has a transmissive area TA, the resolution of the component area CA can be lower than the resolution of the main display area MDA. For example, the resolution of the component area CA can be approximately 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, or 1 / 16 of the resolution of the main display area MDA. For example, the resolution of the main display area MDA can be approximately 400 ppi or greater, and the resolution of the component area CA can be approximately 200 ppi or approximately 100 ppi.

[0193] The pixel circuits that can drive the main sub-pixel Pm and the auxiliary sub-pixel Pa can be electrically connected to external circuits arranged or disposed in the peripheral area DPA. The first scan drive circuit SDRV1, the second scan drive circuit SDRV2, the terminal unit PAD, the drive voltage supply line 11, and the common voltage supply line 13 can be arranged or disposed in the peripheral area DPA.

[0194] The first scan driving circuit SDRV1 can apply scan signals to each pixel circuit driving the main sub-pixel Pm and the auxiliary sub-pixel Pa via scan line SL. The first scan driving circuit SDRV1 can also apply light emission control signals to each pixel circuit via light emission control line EL. The second scan driving circuit SDRV2 can be positioned or disposed on a side of the main display area MDA opposite to the side where the first scan driving circuit SDRV1 can be positioned or disposed, and can be approximately parallel to the first scan driving circuit SDRV1. Some or a predetermined number of pixel circuits of the main sub-pixel Pm arranged or disposed in the main display area MDA can be electrically connected to the first scan driving circuit SDRV1, and the remaining pixel circuits can be electrically connected to the second scan driving circuit SDRV2. Some or a predetermined number of pixel circuits of the auxiliary sub-pixel Pa arranged or disposed in the component area CA can be electrically connected to the first scan driving circuit SDRV1, and the remaining pixel circuits can be electrically connected to the second scan driving circuit SDRV2. The second scan driving circuit SDRV2 may not be included.

[0195] Terminal unit PAD can be arranged or disposed on one side of substrate 100. Terminal unit PAD can be exposed without being covered by or superimposed on the insulating layer, and can be electrically connected to display circuit board 30. Display driving unit 32 can be disposed on display circuit board 30. Display driving unit 32 can generate control signals that can be transmitted to the first scan driving circuit SDRV1 and the second scan driving circuit SDRV2. Display driving unit 32 can drive voltage ELVDD (see...) Figure 11A ) is supplied to drive voltage supply line 11, and the common voltage ELVSS (see Figure 11A The driving voltage ELVDD can be applied to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa via the driving voltage line PL electrically connected to the driving voltage supply line 11, and the common voltage ELVSS can be applied to the counter electrode of each display element via the common voltage supply line 13. The display driving unit 32 can generate data signals, and the generated data signals can be transmitted to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa via the fan-out wiring FW and the data line DL electrically connected to the fan-out wiring FW.

[0196] The driving voltage supply line 11 may extend in the x-direction along the underside of the main display area MDA. The common voltage supply line 13 may have a substantially annular shape with one side open, and may surround or be adjacent to a portion of the main display area MDA.

[0197] Figure 11A and Figure 11B This is an equivalent circuit diagram of the pixel circuit for driving the main sub-pixel Pm and the auxiliary sub-pixel Pa according to an embodiment.

[0198] Reference Figure 11A The pixel circuit PC can be electrically connected to the light-emitting element ED and can realize the emission of sub-pixels. The pixel circuit PC can include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 can be electrically connected to the scan line SL and the data line DL, and can transmit the data signal Dm received via the data line DL to the driving thin-film transistor T1 according to the scan signal Sn received via the scan line SL.

[0199] The storage capacitor Cst can be electrically connected to the switching thin-film transistor T2 and the drive voltage line PL, and stores the voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the drive voltage ELVDD supplied to the drive voltage line PL.

[0200] The driving thin-film transistor T1 can be electrically connected to the driving voltage line PL and the storage capacitor Cst, and the driving current flowing from the driving voltage line PL to the light-emitting element ED can be controlled according to the voltage value stored in the storage capacitor Cst. The light-emitting element ED can emit light with a specific or predetermined brightness due to the driving current.

[0201] although Figure 11A The illustration shows a scenario where the pixel circuit PC may include two thin-film transistors and a storage capacitor, but the embodiments are not limited to this.

[0202] Reference Figure 11B The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, a light emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0203] Although the pixel circuit PC can include signal lines (i.e., Figure 11BThe signal lines (i.e., scan line SL, previous scan line SL-1, next scan line SL+1, light emission control line EL, and data line DL), initialization voltage line VL, and drive voltage line PL are included, but the embodiments are not limited thereto. According to the embodiments, at least one of the signal lines (i.e., scan line SL, previous scan line SL-1, next scan line SL+1, light emission control line EL, and data line DL) and / or the initialization voltage line VL can be shared by adjacent pixel circuits.

[0204] The drain electrode of the driving thin-film transistor T1 can be electrically connected to the light-emitting element ED via the light-emitting control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm according to the switching operation of the switching thin-film transistor T2 and supplies the driving current to the light-emitting element ED.

[0205] The gate electrode of the switching thin-film transistor T2 can be electrically connected to the scan line SL, and its source electrode can be electrically connected to the data line DL. The drain electrode of the switching thin-film transistor T2 can be electrically connected to the source electrode of the driving thin-film transistor T1, and can also be electrically connected to the driving voltage line PL via the operation control thin-film transistor T5.

[0206] The switching thin-film transistor T2 is turned on according to the scan signal Sn received via the scan line SL, and performs a switching operation to transmit the data signal Dm received from the data line DL to the source electrode of the driving thin-film transistor T1.

[0207] The gate electrode of the compensation thin-film transistor T3 can be electrically connected to the scan line SL. The source electrode of the compensation thin-film transistor T3 can be electrically connected to the drain electrode of the driving thin-film transistor T1, and simultaneously electrically connected to the pixel electrode of the light-emitting element ED via the light-emitting control thin-film transistor T6. The drain electrode of the compensation thin-film transistor T3 can be electrically connected to one electrode of the storage capacitor Cst, the source electrode of the first initialization thin-film transistor T4, and the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on according to the scan signal Sn received via the scan line SL, and electrically connects the gate electrode and drain electrode of the driving thin-film transistor T1 to each other, thus realizing the diode connection of the driving thin-film transistor T1.

[0208] The gate electrode of the first initialization thin-film transistor T4 can be electrically connected to the previous scan line SL-1. The drain electrode of the first initialization thin-film transistor T4 can be electrically connected to the initialization voltage line VL. The source electrode of the first initialization thin-film transistor T4 can be electrically connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation thin-film transistor T3, and the gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on according to the previous scan signal Sn-1 received via the previous scan line SL-1, and can transmit the initialization voltage Vint to the gate electrode of the driving thin-film transistor T1, thereby initializing the voltage of the gate electrode of the driving thin-film transistor T1.

[0209] The gate electrode of the operating control thin-film transistor T5 can be electrically connected to the light-emitting control line EL. The source electrode of the operating control thin-film transistor T5 can be electrically connected to the drive voltage line PL. The drain electrode of the operating control thin-film transistor T5 can be electrically connected to the source electrode of the driving thin-film transistor T1 and the drain electrode of the switching thin-film transistor T2.

[0210] The gate electrode of the light-emitting control thin-film transistor T6 can be electrically connected to the light-emitting control line EL. The source electrode of the light-emitting control thin-film transistor T6 can be electrically connected to the drain electrode of the driving thin-film transistor T1 and the source electrode of the compensation thin-film transistor T3. The drain electrode of the light-emitting control thin-film transistor T6 can be electrically connected to the pixel electrode of the light-emitting element ED. The operation control thin-film transistor T5 and the light-emitting control thin-film transistor T6 are simultaneously turned on according to the light-emitting control signal En received via the light-emitting control line EL, so the driving voltage ELVDD is transmitted to the light-emitting element ED, and the driving current flows in the light-emitting element ED.

[0211] The gate electrode of the second initialization thin-film transistor T7 can be electrically connected to the next scan line SL+1. The source electrode of the second initialization thin-film transistor T7 can be electrically connected to the pixel electrode of the light-emitting element ED. The drain electrode of the second initialization thin-film transistor T7 can be electrically connected to the initialization voltage line VL. The second initialization thin-film transistor T7 can be turned on according to the next scan signal Sn+1 received via the next scan line SL+1, and can initialize the pixel electrode of the light-emitting element ED.

[0212] Despite Figure 11B The first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can be electrically connected to the previous scan line SL-1 and the next scan line SL+1, respectively, but the embodiment is not limited thereto. According to the embodiment, both the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can be electrically connected to the previous scan line SL-1 and can be driven according to the previous scan signal Sn-1.

[0213] The other electrode of the storage capacitor Cst can be electrically connected to the drive voltage line PL. This electrode of the storage capacitor Cst can also be electrically connected to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensation thin-film transistor T3, and the source electrode of the first initialization thin-film transistor T4.

[0214] The counter electrode (e.g., cathode) of the light-emitting element ED is provided with a common voltage ELVSS. The light-emitting element ED receives a drive current from the driving thin-film transistor T1 and emits light.

[0215] Pixel circuit PCs are not limited to the above references Figure 11A and Figure 11B The description includes the number of thin-film transistors, the number of storage capacitors, and the complete circuit design. The number of thin-film transistors, the number of storage capacitors, and the circuit design can vary.

[0216] The pixel circuits PC that drive the primary sub-pixel Pm and the auxiliary sub-pixel Pa can be the same or different from each other. For example, Figure 11B The pixel circuit PC can be used as the pixel circuit PC to drive the main sub-pixel Pm and the auxiliary sub-pixel Pa. According to an embodiment, Figure 11B The pixel circuit PC can be used as the pixel circuit PC to drive the master sub-pixel Pm, and Figure 11A The pixel circuit PC can be used as the pixel circuit PC to drive the auxiliary sub-pixel Pa.

[0217] Figure 12 This is a schematic layout diagram illustrating the pixel arrangement structure in the main display area MDA according to an embodiment.

[0218] The master subpixel Pm can be arranged or set in the main display area MDA. As used herein, a subpixel can refer to a light-emitting region that is the smallest unit capable of realizing an image. In the case where an organic light-emitting diode is used as the display element, the light-emitting region can be defined by an opening in the pixel-defining layer. This will be described later.

[0219] like Figure 12 As shown, the main sub-pixel Pm arranged or set in the main display area MDA can have a pentile (or "five-tile") structure. The red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb can represent red, green, and blue, respectively.

[0220] Therefore, red sub-pixels Pr and blue sub-pixels Pb can alternate on the first row 1N, green sub-pixels Pg can be spaced apart by a predetermined distance on the second row 2N adjacent to the first row 1N, blue sub-pixels Pb and red sub-pixels Pr can alternate on the third row 3N adjacent to the second row 2N, and green sub-pixels Pg can be spaced apart by a predetermined distance on the fourth row 4N adjacent to the third row 3N. This pixel arrangement can be repeated up to the Nth row. In this case, blue sub-pixels Pb and red sub-pixels Pr can be larger than green sub-pixels Pg.

[0221] The red sub-pixels Pr and Pb located in the first row 1N and the green sub-pixel Pg located in the second row 2N can be arranged or configured in a zigzag pattern. Therefore, the red sub-pixels Pr and Pb can alternate with each other in the first column 1M, the green sub-pixels Pg can be arranged at predetermined distances in the second column 2M adjacent to the first column 1M, the blue sub-pixels Pb and Pr can alternate with each other in the third column 3M adjacent to the second column 2M, and the green sub-pixels Pg can be at predetermined distances in the fourth column 4M adjacent to the third column 3M. This pixel arrangement can be repeated up to the Mth column.

[0222] The pixel arrangement structure can be described differently. The red sub-pixel Pr can be arranged or placed at the first and third vertices facing each other diagonally among the four vertices of the imaginary quadrilateral VS. The imaginary quadrilateral VS takes the center point of the green sub-pixel Pg as its center point, and the blue sub-pixel Pb can be arranged or placed at the remaining vertices, namely the second and fourth vertices. Within the spirit and scope of the disclosure, the imaginary quadrilateral VS can be a rectangle, rhombus, square, etc.

[0223] This pixel arrangement structure can be called a pentile matrix structure or a pentile structure. By applying the rendering principle that the color of a pixel can be represented by sharing the colors of its neighboring pixels, high resolution can be achieved with a small number of pixels.

[0224] Despite Figure 12 The principal sub-pixels Pm can be arranged or configured in a pentile matrix structure, but the embodiments are not limited to this. For example, the principal sub-pixels Pm can be arranged or configured in various configurations such as strip structures, mosaic arrangements, and triangular arrangements.

[0225] Figures 13A to 15 This is a schematic layout diagram illustrating the pixel arrangement structure in the component region CA according to various embodiments.

[0226] Reference Figure 13AAuxiliary subpixels Pa can be arranged or set in the component area CA. Each auxiliary subpixel Pa can emit, for example, red, green, blue, or white light.

[0227] The component region CA may include a pixel group PG and a transmission region TA, wherein the pixel group PG includes at least one auxiliary sub-pixel Pa. The pixel group PG and the transmission region TA may alternate with each other in the x and y directions, and may be arranged or configured, for example, as a grid structure. In this case, the component region CA may have a pixel group PG and a transmission region TA.

[0228] A pixel group PG can be defined as a set of subpixels in which auxiliary subpixels Pa can be grouped into predetermined units. For example, ... Figure 13A As shown, a single pixel group PG may include eight auxiliary sub-pixels Pa arranged or configured in a pentile structure. In other words, a single pixel group PG may include two red sub-pixels Pr, four green sub-pixels Pg, and two blue sub-pixels Pb.

[0229] Within the component region CA, basic units U, including a specific or predetermined number of pixel groups PG and a specific or predetermined number of transmission regions TA, can be repeated in both the x and y directions. Figure 13A In this design, the basic unit U can have a quadrilateral shape, in which two pixel groups PG and two transmissive regions TA, which can be arranged or disposed around the pixel groups PG, can be grouped together. The basic unit U is a repeating structure and does not represent a broken construction.

[0230] In the main display area MDA, a corresponding unit U' with the same area as the basic unit U can be provided. In this case, the number of main sub-pixels Pm included in the corresponding unit U' can be greater than the number of auxiliary sub-pixels Pa included in the basic unit U. In other words, if the number of auxiliary sub-pixels Pa included in the basic unit U is 16 and the number of main sub-pixels Pm included in the corresponding unit U' is 32, then the ratio of the number of auxiliary sub-pixels Pa to the number of main sub-pixels Pm arranged or set on the same area can be 1:2.

[0231] The auxiliary sub-pixel Pa can be arranged or set as follows: Figure 13A The pentile structure shown, where the resolution of the component region CA is half the resolution of the main display region MDA, is called a 1 / 2 pentile structure. The number or arrangement of auxiliary sub-pixels Pa included in the pixel group PG can be modified according to the resolution of the component region CA.

[0232] Reference Figure 13BThe pixel arrangement structure of the component region CA can be a 1 / 4 pentile structure. According to an embodiment, a pixel group PG may include eight auxiliary sub-pixels Pa arranged or set in a pentile structure, but the basic unit U may include only one pixel group PG. The remaining area of ​​the basic unit U not occupied by the single pixel group PG can be filled with a transmission region TA. Therefore, the ratio of the number of auxiliary sub-pixels Pa to the number of main sub-pixels Pm arranged or set on the same area can be 1:4. In this case, the single pixel group PG can be surrounded by or adjacent to the transmission region TA.

[0233] Reference Figure 13C The pixel arrangement structure of the component region CA can be a 1 / 4 pentile dispersed structure. According to an embodiment, two pixel groups PG can be dispersed and arranged or set within the basic unit U. A single pixel group PG can be based on a pentile structure and can include a total of four auxiliary sub-pixels Pa, namely, one red sub-pixel Pr, two green sub-pixels Pg, and one blue sub-pixel Pb.

[0234] Four auxiliary sub-pixels Pa can be arranged or positioned at the four vertices of the imaginary quadrilateral VS'. According to an embodiment, the imaginary quadrilateral VS' can be a parallelogram. Red sub-pixels Pr and blue sub-pixels Pb can be arranged or positioned on the first row 1N, and two green sub-pixels Pg can be arranged or positioned on the second row 2N.

[0235] Because pixel groups PG and transmission regions TA can be arranged or set alternately, as the number of auxiliary subpixels Pa included in each pixel group PG decreases, the auxiliary subpixels Pa can be more dispersed within the basic unit U.

[0236] Reference Figure 13D The pixel arrangement structure of the component region CA can be a 3 / 16 pentile structure. According to an embodiment, two pixel groups PG can be dispersed and arranged or disposed within the basic unit U. A single pixel group PG can be based on a pentile structure and can include a total of three auxiliary sub-pixels Pa, namely, a red sub-pixel Pr, a green sub-pixel Pg, and a blue sub-pixel Pb. In the arrangement of the auxiliary sub-pixels Pa in a single pixel group PG, the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb can be arranged or disposed at the three vertices of an imaginary triangle VT, respectively.

[0237] and Figure 12Compared to the basic pentile structure in the main display area MDA, the pixel arrangement structure according to the embodiment may not include sub-pixels in the third row 3N and the fourth row 4N, and may also not include sub-pixels in the fourth column 4M. Therefore, the number of auxiliary sub-pixels Pa included in the basic unit U is 6, and the number of main sub-pixels Pm included in the corresponding unit U' is 32. Thus, the ratio of the number of auxiliary sub-pixels Pa to the number of main sub-pixels Pm arranged or set on the same area can be 3:16.

[0238] Reference Figure 13E The pixel arrangement structure of the component region CA can be an S-strip structure. According to an embodiment, a single pixel group PG can include a total of three auxiliary sub-pixels Pa, namely, a red sub-pixel Pr, a green sub-pixel Pg, and a blue sub-pixel Pb.

[0239] According to an embodiment, a red sub-pixel Pr and a green sub-pixel Pg can alternate on a first column 1I, and a blue sub-pixel Pb can be arranged or disposed on a second column 2I adjacent to the first column 1I. In this case, each of the red sub-pixel Pr and the green sub-pixel Pg can have a substantially rectangular shape having a longer side along the x-direction, and the blue sub-pixel Pb can be arranged or disposed to have a substantially rectangular shape having a longer side along the y-direction. The length of the blue sub-pixel Pb in the y-direction can be equal to or greater than the sum of the lengths of the red sub-pixel Pr and the green sub-pixel Pg in the y-direction. Therefore, the size of the blue sub-pixel Pb can be larger than the size of each of the red sub-pixel Pr and the green sub-pixel Pg.

[0240] According to an embodiment, the area occupied by the pixel group PG of the basic unit U can be approximately 1 / 4 of the basic unit U. Figure 13E In this configuration, only one pixel group PG may be included in the basic unit U. However, according to an embodiment, the basic unit U may include two or more pixel groups PG. The area of ​​the auxiliary sub-pixels Pa included in each pixel group PG may vary.

[0241] Reference Figure 13F The basic unit U arranged or set in the component region CA may include two pixel groups PG based on an S-strip structure. The two pixel groups PG may be arranged or set separately from each other, and the transmission region TA is located between the two pixel groups PG.

[0242] According to an embodiment, the area occupied by the two pixel groups PG of the basic unit U can be approximately 1 / 4 of the basic unit U. In other words, Figure 13F The area of ​​the auxiliary sub-pixel Pa can be smaller than Figure 13E The area of ​​the auxiliary sub-pixel Pa.

[0243] Reference Figure 13G The pixel arrangement structure of the component region CA can be a strip structure. In other words, the red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb can be arranged side by side in the x-direction. In this case, each of the red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb can have a longer side along the y-direction.

[0244] Alternatively, the red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb can be arranged side-by-side in the y-direction. In this case, each of the red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb can have a longer side along the x-direction.

[0245] Reference Figures 14A to 14F The auxiliary subpixel Pa can be arranged or configured in a substantially circular shape within the component region CA. For example, the auxiliary subpixel Pa can be arranged or positioned in the circumferential direction of the imaginary circle VC, such that the red subpixel Pr, green subpixel Pg, and blue subpixel Pb can be arranged or positioned sequentially and repeated in the circumferential direction of the imaginary circle VC. The shape, arrangement, and number of auxiliary subpixel Pas included in the pixel group PG can vary.

[0246] For example, such as Figure 14A As shown, the shape of each auxiliary sub-pixel Pa can be a rhombus. Alternatively, as... Figure 14B As shown, each auxiliary subpixel Pa can have a specific or predetermined width and a length extending in the circumferential direction. When the auxiliary subpixels Pa can be arranged or configured in a circular structure as described above, the auxiliary subpixels Pa included in the pixel group PG can be arranged or configured to surround or be adjacent to the transmission region TA. For example... Figure 14C As shown, the basic unit U may include a group of pixels PG, each having a substantially circular shape.

[0247] Reference Figures 14D to 14F The component region CA may include auxiliary sub-pixels Pa arranged or set along the respective circumferences of imaginary circles VC1, VC2, and VC3, which have the same center and different diameters. In the diametrical direction of each of the imaginary circles VC1, VC2, and VC3, the auxiliary sub-pixels Pa arranged or set in the imaginary circles VC1, VC2, and VC3 may be aligned in rows or arranged or set in a zigzag pattern.

[0248] Reference Figure 15 The component region CA may include a first pixel group PG1 and a second pixel group PG2 with different pixel arrangements. Figures 13A to 14FThe pixel arrangement structure shown can be applied to the first pixel group PG1 and the second pixel group PG2. For example, the auxiliary sub-pixels Pa of the first pixel group PG1 can be arranged or set in a pentile structure, and the auxiliary sub-pixels Pa of the second pixel group PG2 can be arranged or set in an S-strip structure.

[0249] Figures 16A to 16H This is a schematic plan view showing the shape of the bottom metal layer BML that can be arranged or set in the component area CA.

[0250] Reference Figures 16A to 16H The bottom metal layer BML can be arranged or configured to correspond to the component area CA, and can include a bottom hole BMLH. The bottom metal layer BML and the bottom hole BMLH can have various shapes and sizes.

[0251] Reference Figure 16A The bottom aperture BMLH can be rectangular, and the bottom aperture BMLH may not face the pixel group PG. In this case, the shape and size of the transmission region TA can be defined by the shape and size of the bottom aperture BMLH. According to the plan view, two bottom apertures BMLH can be included in each basic unit U and can alternate with the pixel group PG.

[0252] Reference Figure 16B The bottom aperture (BMLH) can face the transmission area (TA) and some or a predetermined number of pixel groups (PG). In this case, the shape and size of the bottom aperture (BMLH) can be different from the shape and size of the transmission area (TA).

[0253] Reference Figure 16C The bottom metal layer BML may include a first bottom metal layer BMLa corresponding to pixel group PG and a second bottom metal layer BMLb corresponding to the wiring WL between adjacent pixel groups PG. The width of the second bottom metal layer BMLb may be smaller than the width of the first bottom metal layer BMLa, and the first bottom metal layer BMLa and the second bottom metal layer BMLb may be integral with each other. Therefore, the bottom hole BMLH may have a "+" shape. Since the bottom metal layer BML is arranged or configured to correspond to the wiring WL, light diffraction caused by the slits provided or disposed between the wiring WLs can be prevented.

[0254] Reference Figure 16D and Figure 16EThe bottom aperture BMLH can have a substantially circular shape. When the shape of the transmission region TA is approximately circular, the diffraction properties of light can be improved. Therefore, when the component located below the component region CA is a camera, the transmission region TA can have an approximately circular shape. The bottom aperture BMLH can be a polygon with eight or more sides that is approximately circular, or it can be elliptical. Various modifications can be made to the bottom aperture BMLH. For example, a single bottom aperture BMLH or multiple bottom aperture BMLHs can be included between pixel groups PG.

[0255] Reference Figure 16F The bottom hole BMLH may include a first bottom hole BMLH1 and a second bottom hole BMLH2. For example, the first bottom hole BMLH1 may be rectangular, and the second bottom hole BMLH2 may be circular.

[0256] Reference Figure 16G and Figure 16H The bottom hole BMLH can be arranged or set according to various methods. For example, such as... Figure 16G As shown, the bottom holes BMLH can be arranged side-by-side or positioned in both the x and y directions. Alternatively, as... Figure 16H As shown, the bottom holes BMLH can be arranged or set in a row in the x direction, and can be arranged or set in a zigzag pattern in the y direction.

[0257] By considering this arrangement of the bottom hole BMLH, the shape of the auxiliary sub-pixel Pa in the pixel group PG can be selected for arrangement or setting. For example, the shape of the auxiliary sub-pixel Pa can be arranged or set. Figure 16G In the first pixel group PG1, the blue sub-pixel Pb in the auxiliary sub-pixels Pa can be longer in the y-direction than the red sub-pixels Pr and green sub-pixels Pg arranged or positioned on either side of the blue sub-pixel Pb. Alternatively, for example, they can be arranged or positioned... Figure 16G In the second pixel group PG2, the auxiliary sub-pixels Pa, red sub-pixels Pr and blue sub-pixels Pb can be arranged or set in a basically rhomboid shape, and the green sub-pixel Pg is set in the center.

[0258] Reference Figure 16H The red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb included in the first pixel group PG1 can be arranged or set in a triangular shape, and the green sub-pixel Pg, which is located or set at the center of the auxiliary sub-pixels Pa included in the second pixel group PG2, can be arranged or set to be longer in the y direction than the red sub-pixel Pr and blue sub-pixel Pb arranged or set on both sides of the green sub-pixel Pg.

[0259] Figure 17It is a schematic cross-sectional view of a portion or area (e.g., the main display area MDA and the component area CA) of the display panel 10 according to an embodiment.

[0260] Reference Figure 17 The display panel 10 may include a main display area MDA and a component area CA. A main sub-pixel Pm may be arranged or disposed in the main display area MDA, and an auxiliary sub-pixel Pa and a transmissive area TA may be arranged or disposed in the component area CA. A main pixel circuit PC, including a main thin-film transistor TFT and a main storage capacitor Cst, and a main organic light-emitting diode (OLED) electrically connected to the main pixel circuit PC, may be arranged or disposed in the main display area MDA. An auxiliary pixel circuit PC', including an auxiliary thin-film transistor TFT' and an auxiliary storage capacitor Cst', and an auxiliary organic light-emitting diode (OLED') electrically connected to the auxiliary pixel circuit PC', may be arranged or disposed in the component area CA.

[0261] According to an embodiment, organic light-emitting diodes (OLEDs) can be used as display elements. However, according to an embodiment, inorganic light-emitting diodes (LEDs) or quantum dot LEDs can be used as display elements.

[0262] The structure including the component stack in the display panel 10 will now be described. The display panel 10 may be a stack of substrate 100, buffer layer 111, circuit layer PCL and display element layer EDL.

[0263] As described above, substrate 100 may include insulating materials such as glass, quartz, and polymer resin. Substrate 100 may be a rigid substrate or a flexible substrate, and a flexible substrate may be bendable, foldable, or rollable.

[0264] A buffer layer 111 may be located on the substrate 100 and may reduce or prevent the penetration of foreign matter, moisture, or ambient air from beneath the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may comprise inorganic materials (such as oxides or nitrides), organic materials, or organic-inorganic composites, and may be a single layer or multiple layers of inorganic and organic materials. A barrier layer (not shown) may be located between the substrate 100 and the buffer layer 111 to prevent the penetration of ambient air. According to embodiments, the buffer layer 111 may comprise silicon oxide (SiO2) or silicon nitride (SiN). x The buffer layer 111 may include a first buffer layer 111a and a second buffer layer 111b, with one of the first buffer layer 111a and the second buffer layer 111b stacked on top of the other.

[0265] In the component region CA, the bottom metal layer BML may be located between the first buffer layer 111a and the second buffer layer 111b. According to an embodiment, the bottom metal layer BML may be located between the substrate 100 and the first buffer layer 111a. The bottom metal layer BML may be positioned or disposed below the auxiliary pixel circuit PC' and may prevent the characteristics of the auxiliary thin-film transistor TFT' from being degraded due to light emitted from, for example, the component. The bottom metal layer BML may prevent light emitted from or toward the component from diffracting through narrow gaps between wirings electrically connected to the auxiliary pixel circuit PC'. The bottom metal layer BML may not be present in the transmissive region TA.

[0266] The bottom metal layer (BML) can be electrically connected to the wiring GCL disposed on or on another layer via contact holes. The BML can receive static voltages or signals from the wiring GCL. For example, the BML can receive a drive voltage ELVDD or a scan signal. Because the BML receives static voltages or signals, the probability of electrostatic discharge (ESD) can be significantly reduced. The BML can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). The BML can be a single layer or multiple layers comprising the aforementioned materials.

[0267] The circuit layer PCL may be located on the buffer layer 111 and may include a main pixel circuit PC and an auxiliary pixel circuit PC', a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 115, and a planarization layer 117. The main pixel circuit PC may include a main thin-film transistor TFT and a main storage capacitor Cst, and the auxiliary pixel circuit PC' may include an auxiliary thin-film transistor TFT' and an auxiliary storage capacitor Cst'.

[0268] The main thin-film transistor (TFT) and / or the auxiliary thin-film transistor (TFT') may be located above the buffer layer 111. The main thin-film transistor (TFT) may include a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1, and the auxiliary thin-film transistor (TFT') may include a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The main thin-film transistor (TFT) may be electrically connected to the main organic light-emitting diode (OLED) and may drive the main organic light-emitting diode (OLED). The auxiliary thin-film transistor (TFT') may be electrically connected to the auxiliary organic light-emitting diode (OLED') and may drive the auxiliary organic light-emitting diode (OLED').

[0269] The first semiconductor layer A1 and the second semiconductor layer A2 may be located on the buffer layer 111 and may comprise polycrystalline silicon. According to an embodiment, the first semiconductor layer A1 and the second semiconductor layer A2 may comprise amorphous silicon. According to an embodiment, the first semiconductor layer A1 and the second semiconductor layer A2 may comprise an oxide selected from at least one of the following: indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The first semiconductor layer A1 and the second semiconductor layer A2 may comprise a channel region and impurity-doped source and drain regions.

[0270] The second semiconductor layer A2 can be stacked with the bottom metal layer BML, and the second buffer layer 111b is located between the second semiconductor layer A2 and the bottom metal layer BML. According to an embodiment, the width of the second semiconductor layer A2 can be smaller than the width of the bottom metal layer BML. Therefore, when projection is performed in a direction perpendicular to the substrate 100, the second semiconductor layer A2 can be completely stacked with the bottom metal layer BML.

[0271] The first gate insulating layer 112 may cover the first semiconductor layer A1 and the second semiconductor layer A2, or be stacked with the first semiconductor layer A1 and the second semiconductor layer A2. The first gate insulating layer 112 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x The materials used may be silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The first gate insulating layer 112 may be a single layer or multiple layers comprising the aforementioned inorganic insulating materials.

[0272] The first gate electrode G1 and the second gate electrode G2 can be positioned or disposed above the first gate insulating layer 112, so as to be stacked with the first semiconductor layer A1 and the second semiconductor layer A2, respectively. The first gate electrode G1 and the second gate electrode G2 may include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may both be a single layer or multiple layers. For example, the first gate electrode G1 and the second gate electrode G2 may both be a single layer of Mo.

[0273] The second gate insulating layer 113 may cover the first gate electrode G1 and the second gate electrode G2 or be stacked with the first gate electrode G1 and the second gate electrode G2. The second gate insulating layer 113 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x The inorganic insulating layer 113 may be a single layer or multiple layers comprising the aforementioned inorganic insulating materials, such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO).

[0274] The first upper electrode CE2 of the main storage capacitor Cst and the second upper electrode CE2' of the auxiliary storage capacitor Cst' can be located above the second gate insulating layer 113.

[0275] In the main display area MDA, the first upper electrode CE2 can be stacked with the first gate electrode G1. The first gate electrode G1 and the first upper electrode CE2 are stacked on top of each other, and the second gate insulating layer 113 is located between the first gate electrode G1 and the first upper electrode CE2. The first gate electrode G1 and the first upper electrode CE2 can constitute the main storage capacitor Cst. The first gate electrode G1 can be the first lower electrode CE1 of the main storage capacitor Cst.

[0276] In the component region CA, the second upper electrode CE2' can be stacked with the second gate electrode G2. The second gate electrode G2 and the second upper electrode CE2' are stacked on top of each other, and the second gate insulating layer 113 is located between the second gate electrode G2 and the second upper electrode CE2'. The second gate electrode G2 and the second upper electrode CE2' can constitute an auxiliary storage capacitor Cst'. The second gate electrode G2 can be the second lower electrode CE1' of the auxiliary storage capacitor Cst'.

[0277] The first upper electrode CE2 and the second upper electrode CE2' may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may both be a single layer or multiple layers of the aforementioned materials.

[0278] The interlayer insulating layer 115 may cover the first upper electrode CE2 and the second upper electrode CE2' or be stacked with the first upper electrode CE2 and the second upper electrode CE2'. Within the spirit and scope of the disclosure, the interlayer insulating layer 115 may include silicon oxide (SiO2) or silicon nitride (SiN). x The materials used include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO). The interlayer insulation layer 115 can be a single layer or multiple layers comprising the above-mentioned inorganic insulating materials.

[0279] When the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as the inorganic insulating layer IIL, the inorganic insulating layer IIL may have a first aperture H1 corresponding to the transmission region TA. The first aperture H1 may expose a portion of the upper surface of the buffer layer 111 or the substrate 100. The first aperture H1 may be the result of stacking openings in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 corresponding to the transmission region TA. These openings may be formed individually by separate processes or simultaneously by the same process. When these openings are formed by separate processes, the inner surface of the first aperture H1 may not be smooth and may have a step, such as a substantially stepped shape.

[0280] Alternatively, the inorganic insulating layer IIL may have grooves other than the first hole H1 that exposes the buffer layer 111. Alternatively, the inorganic insulating layer IIL may not have the first hole H1 or groove corresponding to the transmission region TA. Because the inorganic insulating layer IIL can generally comprise an inorganic insulating material with high light transmittance, even if the inorganic insulating layer IIL does not have a hole or groove corresponding to the transmission region TA, the inorganic insulating layer IIL can still have sufficient light transmittance, such that... Figure 2 Component 40 can send / receive a sufficient amount of light.

[0281] The first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 are located on the interlayer insulating layer 115. Each of the first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 may include a conductive material comprising Mo, Al, Cu, and / or Ti, and may be a multilayer or a single layer comprising the aforementioned materials. For example, each of the first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 may be a Ti / Al / Ti multilayer.

[0282] The planarization layer 117 may cover the first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2, or may be stacked with the first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2. The planarization layer 117 may have a flat upper surface, such that the first pixel electrode 121 and the second pixel electrode 121' that can be positioned or disposed thereon can be formed flat.

[0283] The planarization layer 117 may comprise organic or inorganic materials and may have a single-layer or multi-layer structure. Within the spirit and scope of the disclosure, the planarization layer 117 may comprise general-purpose polymers (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, etc.). x The materials used are silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). In the case of forming planarization layer 117, a layer can be formed, and then the upper surface of this layer can be chemically and mechanically polished to provide a flat upper surface.

[0284] The planarization layer 117 may have a second aperture H2 to correspond to the transmission region TA. The second aperture H2 may be stacked with the first aperture H1. Figure 17 A second hole H2, which can be larger than the first hole H1, is shown. According to an embodiment, the planarization layer 117 can cover the edge of the first hole H1 of the inorganic insulating layer IIL or overlap with the edge of the first hole H1 of the inorganic insulating layer IIL, and the second hole H2 can have an area smaller than that of the first hole H1.

[0285] The planarization layer 117 may have vias through which one of the first source electrode S1 and the first drain electrode D1 of the main thin-film transistor TFT is exposed, and the first pixel electrode 121 may contact the first source electrode S1 or the first drain electrode D1 through the vias and be electrically connected to the main thin-film transistor TFT. The planarization layer 117 may include another opening through which one of the second source electrode S2 and the second drain electrode D2 of the auxiliary thin-film transistor TFT' is exposed, and the second pixel electrode 121' may contact the second source electrode S2 or the second drain electrode D2 through the other opening and be electrically connected to the auxiliary thin-film transistor TFT'.

[0286] The first pixel electrode 121 and the second pixel electrode 121' may include conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). Each of the first pixel electrode 121 and the second pixel electrode 121' may include a reflective layer comprising, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a composite of these materials. For example, each of the first pixel electrode 121 and the second pixel electrode 121' may have a structure comprising a film containing ITO, IZO, ZnO, or In2O3 above / below the aforementioned reflective layer. In this case, each of the first pixel electrode 121 and the second pixel electrode 121' may have an ITO / Ag / ITO stacked structure.

[0287] The pixel defining layer 119 may be arranged or disposed on the planarization layer 117 to cover or overlap with the corresponding edges of the first pixel electrode 121 and the second pixel electrode 121', and may include a first opening OP1 and a second opening OP2 that respectively expose the central portions of the first pixel electrode 121 and the second pixel electrode 121'. The first opening OP1 and the second opening OP2 may define the size and shape of the light-emitting regions (i.e., the main sub-pixel Pm and the auxiliary sub-pixel Pa) of the main organic light-emitting diode OLED and the auxiliary organic light-emitting diode OLED'.

[0288] The pixel defining layer 119 can prevent electric arcing or the like from occurring at the edges of the first pixel electrode 121 and the second pixel electrode 121' by increasing the distance between the edges of the first pixel electrode 121 and the second pixel electrode 121' and the portion of the counter electrode 123 located on the first pixel electrode 121 and the second pixel electrode 121'. Within the spirit and scope of the disclosure, the pixel defining layer 119 can be formed from an organic insulating material (such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), or phenolic resin) via spin coating or the like.

[0289] The pixel defining layer 119 may have a third aperture H3 positioned or disposed in the transmissive region TA. The third aperture H3 may be stacked with the first aperture H1 and the second aperture H2. Due to the first aperture H1 to the third aperture H3, the light transmittance in the transmissive region TA can be increased. Although the buffer layer 111 extends continuously to be with Figure 17 The transmission region TA corresponds to the buffer layer 111, but the buffer layer 111 may include holes positioned or disposed in the transmission region TA. A portion of the counter electrode 123, which will be described later, may be arranged or disposed on the inner surfaces of the first hole H1 to the third hole H3.

[0290] The first emitting layer 122b and the second emitting layer 122b' can be arranged or disposed in the first opening OP1 and the second opening OP2 of the pixel limiting layer 119, respectively, to correspond to the first pixel electrode 121 and the second pixel electrode 121'. The first emitting layer 122b and the second emitting layer 122b' can include high molecular weight materials or low molecular weight materials, and can emit red light, green light, blue light or white light.

[0291] The organic functional layer 122e may be located above and / or below the first emission layer 122b and the second emission layer 122b'. The organic functional layer 122e may include the first functional layer 122a and / or the second functional layer 122c. The first functional layer 122a or the second functional layer 122c may be omitted.

[0292] The first functional layer 122a may be located below the first emission layer 122b and the second emission layer 122b'. The first functional layer 122a may be a single layer or multiple layers comprising organic materials. The first functional layer 122a may be a single-layer hole transport layer (HTL). Alternatively, the first functional layer 122a may include a hole injection layer (HIL) and an HTL. The first functional layer 122a may be integrally disposed to correspond to the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') included in the main display area MDA and the component area CA.

[0293] The second functional layer 122c may be located above the first emission layer 122b and the second emission layer 122b'. The second functional layer 122c may be a single layer or multiple layers comprising organic materials. The second functional layer 122c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 122c may be integrally formed to correspond to the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') included in the main display area MDA and the component area CA.

[0294] Counter electrode 123 may be disposed above the second functional layer 122c. Counter electrode 123 may comprise a conductive material having a low work function. For example, counter electrode 123 may comprise a (semi-)transparent layer comprising, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, counter electrode 123 may comprise a layer such as ITO, IZO, ZnO, or In2O3 situated on a (semi-)transparent layer comprising any of the aforementioned materials. Counter electrode 123 may be integrally disposed to correspond to the main organic light-emitting diode (OLED) and auxiliary organic light-emitting diode (OLED') included in the main display area MDA and component area CA.

[0295] A layer arranged or disposed in the main display area MDA, extending from the first pixel electrode 121 to the counter electrode 123, can constitute a main organic light-emitting diode (OLED). A layer arranged or disposed in the component area CA, extending from the second pixel electrode 121' to the counter electrode 123, can constitute an auxiliary organic light-emitting diode (OLED').

[0296] An upper layer 150, comprising organic material, may be located on the counter electrode 123. The upper layer 150 can be configured to protect the counter electrode 123 and also improve light extraction efficiency. The upper layer 150 may comprise an organic material having a refractive index higher than that of the counter electrode 123. Alternatively, the upper layer 150 may be a stack of layers with different refractive indices. For example, the upper layer 150 may be configured by stacking a high-refractive-index layer, a low-refractive-index layer, and another high-refractive-index layer in the order stated herein. In this case, the high-refractive-index layer may have a refractive index of 1.7 or greater, and the low-refractive-index layer may have a refractive index of 1.3 or less.

[0297] The upper layer 150 may additionally include lithium fluoride (LiF). Alternatively, the upper layer 150 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x ).

[0298] The first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 may include a transmission aperture TAH corresponding to the transmission region TA. In other words, the first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 may each include an opening corresponding to the transmission region TA. These openings may have substantially the same area. For example, the area of ​​the opening of the counter electrode 123 may be substantially the same as the area of ​​the transmission aperture TAH.

[0299] The transmission aperture TAH corresponding to the transmission region TA can be understood as a transmission aperture TAH superimposed on the transmission region TA. In this case, the transmission aperture TAH can have an area smaller than the area of ​​the first aperture H1 included in the inorganic insulating layer IIL. Therefore, Figure 17 It is shown that the width Wt of the transmission aperture TAH is smaller than the width of the first aperture H1. The area of ​​the transmission aperture TAH can be defined as the area of ​​the narrowest opening among the openings constituting the transmission aperture TAH. The area of ​​the first aperture H1 can be defined as the area of ​​the narrowest opening among the openings constituting the first aperture H1.

[0300] Because a portion of the counter electrode 123 is not present in the transmission region TA due to the transmission aperture TAH, the transmittance in the transmission region TA can be significantly improved. Various methods can be used to form the counter electrode 123 including the transmission aperture TAH. According to an embodiment, after depositing the material used to form the counter electrode 123 on the entire surface of the substrate 100, the portion of the deposited material corresponding to the transmission region TA is removed by laser lift-off, thus forming the counter electrode 123 with the transmission aperture TAH. According to an embodiment, the counter electrode 123 with the transmission aperture TAH can be formed by metal self-patterning (MSP). According to an embodiment, the counter electrode 123 with the transmission aperture TAH can be formed by a deposition method using a fine metal mask (FMM).

[0301] Figures 18A to 18C This is a schematic cross-sectional view illustrating a method for patterning counter electrodes according to an embodiment. In detail, Figures 18A to 18C Electrode patterning via laser ablation method is shown.

[0302] Reference Figure 18A Before forming the first functional layer 122a, a sacrificial metal layer SML is formed to overlap with the transmission region TA. For example, the sacrificial metal layer SML may be formed within the first hole H1 of the inorganic insulating layer IIL.

[0303] The sacrificial metal layer SML may include metals such as silver (Ag), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), molybdenum (Mo), or titanium (Ti). The sacrificial metal layer SML may include a film formed of ITO, IZO, ZnO, or In2O3 above / below the aforementioned metal. According to an embodiment, the sacrificial metal layer SML may be made of the same or similar material as the first pixel electrode 121 and the second pixel electrode 121' and may be formed simultaneously with the formation of the first pixel electrode 121 and the second pixel electrode 121'.

[0304] Next, as Figure 18BAs shown, a first functional layer 122a, a second functional layer 122c, a counter electrode 123, and an upper layer 150 are sequentially formed on the sacrificial metal layer SML, both extending in the main display region MDA and the component region CA.

[0305] Next, a laser is irradiated from the lower surface of the substrate 100 onto the sacrificial metal layer SML disposed in the transmission region TA. In other words, the laser can travel from the lower surface of the substrate 100 in the +z direction and can irradiate the lower surface of the sacrificial metal layer SML.

[0306] According to an embodiment, the bottom metal layer BML can be arranged or configured to correspond to the entire component region CA, and can include a bottom aperture BMLH corresponding to the transmission region TA. Therefore, the bottom metal layer BML can prevent laser light from reaching areas other than the transmission region TA. In this case, the bottom metal layer BML can have a thickness in the range of about 1000 Å to about 3000 Å. If the bottom metal layer BML has a thickness that may be less than about 1000 Å, voids may be created in the bottom metal layer BML by the laser light.

[0307] The laser can have an IR wavelength. When the laser is IR light, because the transmittance relative to the substrate 100 and the buffer layer 111 is not less than approximately 80% to approximately 90%, the laser can effectively reach the sacrificial metal layer SML. Since the sacrificial metal layer SML may include an opaque metal, it can absorb the laser light. Therefore, thermal expansion occurs in the sacrificial metal layer SML, and the laser-irradiated sacrificial metal layer SML can be peeled off from the substrate 100 or the buffer layer 111.

[0308] Because the sacrificial metal layer SML is stripped, the corresponding portions of the first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 located above the sacrificial metal layer SML can also be stripped together with the sacrificial metal layer SML. Therefore, as Figure 18C As shown, a transmission aperture TAH can be formed, consisting of a first functional layer 122a, a second functional layer 122c, a counter electrode 123, and corresponding openings in the upper layer 150. When forming the transmission aperture TAH using a laser lift-off method, the corresponding side surfaces defining the transmission aperture TAH in the first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 can be located on the same plane. Alternatively, the corresponding openings in the first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 can have the same area.

[0309] Figures 19A to 19C This is a schematic cross-sectional view illustrating a method for patterning counter electrodes according to an embodiment, and a display panel manufactured using this method. In detail, Figures 19A to 19C The metal self-patterning (MSP) technique is shown.

[0310] The deposition material used to form the counter electrode 123 provides different layer formation results depending on the surface on which the deposition material is deposited. For example, magnesium (Mg) in the material used to form the counter electrode 123 is difficult to form a layer on interfaces cleaned with solvents such as MeOH or on the corresponding interfaces of HIL and HTL that may be included in the first functional layer 122a, and Mg is also difficult to form a layer on the material used to form the pixel defining layer 119. This property of Mg can be used in MSP technology for patterning the counter electrode 123.

[0311] Reference Figure 19A Before forming the counter electrode 123, a weak adhesive layer WAL is formed to correspond to the transmission region TA. For example, the weak adhesive layer WAL can be formed on the upper surface of the second functional layer 122c within the first hole H1 of the inorganic insulating layer IIL. The weak adhesive layer WAL can be formed to correspond to the transmission region TA by using a mask MSPM1 having an opening MSPM1_OP corresponding to the transmission region TA.

[0312] The weak adhesion layer WAL may include a material with weak adhesion to the counter electrode 123, so that the counter electrode 123 may not be formed on the upper surface of the weak adhesion layer WAL, or a very thin counter electrode 123 may be formed on the upper surface of the weak adhesion layer WAL.

[0313] For example, within the spirit and scope of the disclosure, the weak adhesive layer WAL can be formed using lithium 8-hydroxyquinoline (Liq), N,N-diphenyl-N,N-bis(9-phenyl-9H-carbazole-3-yl)biphenyl-4,4'-diamine (HT01), N(diphenyl-4-yl)-9,9-dimethyl-N-(4(9-phenyl-9H-carbazole-3-yl)phenyl)-9H-fluorene-2-amine (HT211), 2-(4-(9,10-di(naphthyl-2-yl)anthracene-2-yl)phenyl)-1-phenyl-1H-benzo[D]imidazole (LG201), etc.

[0314] Next, refer to Figure 19B Counter electrodes 123 can be formed in both the main display area MDA and the component area CA by using an opening mask on the weak adhesive layer WAL.

[0315] Because the deposited material used to form the counter electrode 123 has weak adhesion relative to the weakly adhesive layer WAL, therefore... Figure 19B As shown, a counter electrode may not be formed on the upper surface of the weakly adhesive layer WAL, and a transmission hole TAH may be formed. Alternatively, as... Figure 19CAs shown, the counter electrode 123 can be formed very thinly above the weak adhesive layer WAL. In other words, the thickness 123_t2 of the counter electrode 123 above the weak adhesive layer WAL can be very small compared to the thickness 123_t1 of the counter electrode 123 around the weak adhesive layer WAL. In this case, the counter electrode 123 can have a transmission groove TAG corresponding to the transmission region TA.

[0316] According to an embodiment, the display panel 10 may include a weak adhesive layer WAL disposed or provided in the transmission region TA and a counter electrode 123 having a transmission hole TAH or a transmission groove TAG that are both corresponding to the transmission region TA.

[0317] Figure 20A and Figure 20B This is a schematic cross-sectional view illustrating a method for patterning counter electrodes according to an embodiment. Figure 20A and Figure 20B An example of MSP technology is shown.

[0318] Reference Figure 20A Before forming the counter electrode, a second functional layer 122c with a hole 122cH corresponding to the transmission region TA is formed. The second functional layer 122c can be formed by a deposition process using a mask MSPM2 that includes a shielding portion corresponding to the transmission region TA.

[0319] Next, as Figure 20B As shown, the counter electrode 123 can be formed on the entire surface of the substrate 100 via deposition using an open mask. Because the first functional layer 122a may include HIL and / or HTL, the first functional layer 122a may have weak adhesion to the counter electrode 123 formed over the first functional layer 122a. Therefore, as Figure 20B As shown, a counter electrode may not be formed within the hole 122cH of the second functional layer 122c, which exposes the upper surface of the first functional layer 122a, and a transmission hole TAH may be formed instead. Alternatively, a very thin counter electrode may be arranged or provided within the hole 122cH of the second functional layer 122c.

[0320] According to an embodiment, the display panel 10 may include a first functional layer 122a extending continuously in the transmission region TA, a second functional layer 122c disposed above the first functional layer 122a and having a hole 122cH corresponding to the transmission region TA, and a counter electrode 123 having a transmission hole TAH corresponding to the transmission region TA.

[0321] Figure 21A and Figure 21B This is a schematic cross-sectional view illustrating a method for patterning counter electrodes according to an embodiment. In detail, Figure 21A and Figure 21BThe FMM patterning technique is shown.

[0322] Reference Figure 21A and Figure 21B After forming the organic functional layer 122e, an FMM mask FMM_M1, including a shielding portion corresponding to the transmission region TA, can be arranged or disposed relative to the substrate 100, and then a counter electrode 123 can be formed by deposition. Since the counter electrode 123 can be formed using the FMM mask FMM_M1, the counter electrode 123 can include a transmission aperture TAH corresponding to the transmission region TA.

[0323] Next, the FMM mask FMM_M1 can be removed, and an upper layer 150 can be formed to correspond to the entire surface of the substrate 100. Therefore, at least one of the first functional layer 122a, the second functional layer 122c, and the upper layer 150 can be arranged or configured to correspond to the transmission region TA. In other words, at least one of the first functional layer 122a, the second functional layer 122c, and the upper layer 150 can be arranged or disposed within the transmission aperture TAH.

[0324] Figures 22A to 22C This is a plan view illustrating a method for patterning counter electrodes according to an embodiment. In detail, Figures 22A to 22C An example of FMM patterning technology is shown. Figure 22D It is an application Figures 22A to 22C A schematic cross-sectional view of a portion or area of ​​the display panel 10, showing the manufacturing method.

[0325] Reference Figure 22A and Figure 22B The mask M1 used for the electrodes may include mask openings M_OP spaced apart from each other. Figure 22A and Figure 22B In this design, mask openings M_OP can have the same shape. However, mask openings M_OP can include mask openings M_OP with different sizes and / or shapes. Mask openings M_OP can be spaced apart from each other by a specific or predetermined distance in the x and / or y directions.

[0326] The mask M1 used for the electrode can be an open-faced metal mask (FMM). An FMM can be manufactured by forming holes in a metal plate and then extending those holes. Therefore, each mask opening M_OP can be axisymmetric about a first direction passing through the mask opening M_OP or about a second direction passing through the mask opening M_OP.

[0327] Reference Figure 22A Until it forms on substrate 100 Figure 17 After the second functional layer 122c is completed, the mask opening M_OP can be arranged or set to correspond to some or a predetermined number of pixel groups PG.

[0328] Next, the deposition material for forming the counter electrode 123 is discharged from the deposition source (not shown) and initially deposited on the second functional layer 122c to form a portion of the counter electrode 123. At this time, only a portion of the counter electrode 123 can be formed according to the arrangement of the mask openings M_OP of the mask M1.

[0329] Next, as Figure 22B As shown, the mask M1 can be moved and positioned in the x and y directions, and the remainder of the counter electrode 123 is then formed via secondary deposition. The portion of the counter electrode 123 formed during the secondary deposition can overlap and contact the portion of the counter electrode 123 formed during the primary deposition. Figure 22B In this embodiment, after performing the initial deposition for electrode 123, the mask M1 is moved to the right and upward in a 45-degree direction, and then a secondary deposition for electrode 123 is performed. However, the embodiment is not limited to this. For example, after performing the initial deposition for electrode 123, the mask M1 can be moved to the left and downward in a 45-degree direction, and then a secondary deposition for electrode 123 can be performed.

[0330] According to this deposition method, such as Figure 22C As shown, counter electrode 123 can be provided or disposed corresponding to pixel group PG, and counter electrode 123 can be omitted or disposed in the transmissive region TA. Therefore, the transmissive region TA can have high transmittance.

[0331] According to an embodiment, the portions of the counter electrode 123 formed during the initial deposition and the portions of the counter electrode 123 formed during the secondary deposition can be stacked and in contact with each other. Therefore, as... Figure 22D As shown, the thickness of the counter electrode 123 in the stacked region RA1 can be greater than that in the region above the auxiliary organic light-emitting diode OLED'.

[0332] As described above, the counter electrode 123 with a transmission aperture TAH can be formed using the laser lift-off method, the FMM patterning method, and / or the MSP method described above. However, the embodiments are not limited thereto. For example, a combination of the laser lift-off method, the FMM patterning method, and / or the MSP method described above can be used to form the counter electrode 123 with a transmission aperture TAH.

[0333] Figures 23A to 23E A method for patterning the counter electrode using an FMM patterning method and a laser ablation method is shown.

[0334] first, Figure 23A and Figure 23B A first mask MM1 and a second mask MM2 for counter electrodes, suitable for embodiments, are shown. The first mask MM1 may include a shielding layer. Figure 23CThe component region CA has a masked portion MM1_SP, and may include a first mask opening MM1_OP that exposes the main display region MDA. A second mask MM2 may include a second mask opening MM2_OP corresponding to a portion of the component region CA. According to an embodiment, each second mask opening MM2_OP may be rectangular in shape having a longer side corresponding to the length of the component region CA in the y-direction. The second mask openings MM2_OP may be arranged or positioned separately from each other in the x-direction. According to an embodiment, each second mask opening MM2_OP may be rectangular in shape having a longer side corresponding to the length of the component region CA in the x-direction.

[0335] Figure 23C This is a plan view showing the counter electrode 123 obtained by performing an initial deposition using a first mask MM1 and then a secondary deposition using a second mask MM2. Figure 23D yes Figure 23C A magnified planar view of part of the AI.

[0336] Reference Figure 23C and Figure 23D The counter electrode 123 can be obtained via a deposition process to cover or overlap with the main display area MDA, and to cover or overlap with a portion of the component area CA. Depending on the shape of the second mask opening MM2_OP of the second mask MM2, the counter electrode 123 can be formed to cover or overlap with a pixel group PG arranged or disposed in the y-direction.

[0337] Next, as Figure 23E As shown, the transmission aperture TAH can be formed by removing a portion or region of the counter electrode 123 formed in the component region CA using a laser ablation method. Therefore, the transmittance of the transmission region TA can be improved.

[0338] Figure 24 This is a schematic cross-sectional view of a portion or area of ​​the display panel 10 according to an embodiment. Figure 17 and Figure 24 The same reference numerals in the figures represent the same elements, therefore their repeated descriptions are omitted.

[0339] Figure 24 Implementation examples and Figure 17 The difference in the embodiments may be that the auxiliary pixel circuit PC' of the display panel 10 may include thin-film transistors comprising oxide semiconductors and thin-film transistors comprising polycrystalline silicon. Although Figure 24 Only the component region CA is shown, but the above structure of the auxiliary pixel circuit PC' of the component region CA can be equivalently applied to the main pixel circuit PC of the main display region MDA.

[0340] Reference Figure 24 The auxiliary pixel circuit PC' of the display panel 10 may include a first thin film transistor TFT'p and a second thin film transistor TFT'o. The first thin film transistor TFT'p includes a semiconductor layer A2 containing polysilicon, and the second thin film transistor TFT'o includes a semiconductor layer A3 containing oxide semiconductor.

[0341] The first thin-film transistor TFT'p may include a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The first thin-film transistor TFT'p may be related to the above-mentioned... Figure 17 The auxiliary thin-film transistor TFT' described is substantially the same, and the second semiconductor layer A2 of the first thin-film transistor TFT'p may include polycrystalline silicon.

[0342] According to the embodiment, the circuit layer PCL and Figure 17 The difference in the circuit layer PCL may be that the interlayer insulating layer 115 may include a first interlayer insulating layer 115a and a second interlayer insulating layer 115b.

[0343] The second thin-film transistor (TFT) may include a third semiconductor layer A3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3. The third semiconductor layer A3 may be located on the first interlayer insulating layer 115a. In other words, the third semiconductor layer A3 and the second semiconductor layer A2 may be located on different layers. The third semiconductor layer A3 may include a channel region and source and drain regions respectively disposed or disposed on both sides of the channel region. According to an embodiment, the third semiconductor layer A3 may include an oxide semiconductor. For example, the third semiconductor layer A3 may include Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc., which are Zn oxide materials. Alternatively, the third semiconductor layer A3 may include an In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO) semiconductor in which a metal such as In, Ga, or Sn is contained in ZnO.

[0344] The source and drain regions of the third semiconductor layer A3 can be formed by controlling the carrier concentration of the oxide semiconductor to make it conductive. For example, the source and drain regions of the third semiconductor layer A3 can be formed by increasing the carrier concentration of the oxide semiconductor through plasma treatment using hydrogen (H) type gas, fluorine (F) type gas, or a combination thereof.

[0345] The third gate electrode G3 can be stacked with the channel region of the third semiconductor layer A3, and the third gate insulating layer 116 can be located between the third semiconductor layer A3 and the third gate electrode G3. In other words, the third gate electrode G3 can be insulated from the third semiconductor layer A3 through the third gate insulating layer 116. The third gate insulating layer 116 can be patterned according to the shape of the third gate electrode G3.

[0346] The third gate insulating layer 116 may comprise an inorganic material comprising an oxide or a nitride. For example, within the spirit and scope of the disclosure, the third gate insulating layer 116 may comprise silicon oxide (SiO2), silicon nitride (SiN2), or other similar materials. x Materials used include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO). The third gate electrode G3 can be located on the third gate insulating layer 116 and can include molybdenum (Mo), copper (Cu), titanium (Ti), etc., and can be a single layer or multiple layers.

[0347] The second interlayer insulating layer 115b may cover or be stacked with the third gate electrode G3 of the second thin-film transistor TFT'o and may be located on the upper surface of the substrate 100. The third source electrode S3 and the third drain electrode D3 may be located above the second interlayer insulating layer 115b.

[0348] The third source electrode S3 and the third drain electrode D3 can contact the source region and drain region of the third semiconductor layer A3 respectively through contact holes penetrating the second interlayer insulating layer 115b. Each of the third source electrode S3 and the third drain electrode D3 may include a conductive material comprising Mo, Al, Cu, Ti and / or other conductive materials, and may be a multilayer or a single layer comprising the aforementioned materials.

[0349] Because thin-film transistors, which include semiconductor layers containing polycrystalline silicon, have high reliability, high-quality display panels can be achieved by using driving thin-film transistors.

[0350] Because oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not large even when the drive time may be long. In other words, because the color change of the image based on the voltage drop is not large even during low-frequency drive, low-frequency drive is possible. Because oxide semiconductors have low leakage current as described above, they can be used in at least one of the thin-film transistors (TFTs) other than driving TFTs, thereby preventing current leakage and also reducing power consumption.

[0351] Figure 25 This is a schematic cross-sectional view of a portion or area of ​​the display panel 10 according to an embodiment. Figure 17 and Figure 25 The same reference numerals in the figures represent the same elements, therefore their repeated descriptions are omitted.

[0352] Figure 25 Implementation examples and Figure 17 The difference in the embodiments is that the planarization layer 117 may include a first planarization layer 117a and a second planarization layer 117b, the first metal layer BML1 may be arranged or disposed in the main display area MDA, and the transmission area TA may be defined by the bottom hole BMLH of the bottom metal layer BML.

[0353] Reference Figure 25 The circuit layer PCL of the display panel 10 may include a first planarization layer 117a and a second planarization layer 117b. Therefore, conductive patterns such as wiring can be provided or disposed between the first planarization layer 117a and the second planarization layer 117b, which can be beneficial for high integration.

[0354] The first planarization layer 117a may cover or be stacked with the main pixel circuit PC and the auxiliary pixel circuit PC'. The second planarization layer 117b may be located on the first planarization layer 117a and may have a flat upper surface, such that the first pixel electrode 121 and the second pixel electrode 121' can be formed flat. Each of the first planarization layer 117a and the second planarization layer 117b may include organic or inorganic materials and may have a single-layer structure or a multilayer structure. Within the spirit and scope of the disclosure, each of the first planarization layer 117a and the second planarization layer 117b may include general polymers (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), PMMA, or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, etc. Within the spirit and scope of this disclosure, each of the first planarization layer 117a and the second planarization layer 117b may comprise an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x Materials such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO) can be used. After forming the first planarization layer 117a and the second planarization layer 117b, a layer can be formed, and then the upper surface of the layer can be chemically and mechanically polished to provide a flat upper surface.

[0355] The main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') are located on the second planarization layer 117b. The first pixel electrode 121 of the main organic light-emitting diode (OLED) and the second pixel electrode 121' of the auxiliary organic light-emitting diode (OLED') can be electrically connected to the main pixel circuit PC and the auxiliary pixel circuit PC' via connection electrodes CM and CM' arranged or disposed on the planarization layer 117b.

[0356] The connecting electrodes CM and CM' can be disposed between the first planarization layer 117a and the second planarization layer 117b. The connecting electrodes CM and CM' can include conductive materials comprising Mo, Al, Cu, Ti and / or other conductive materials, and can be formed as a multilayer or a single layer comprising the aforementioned materials. For example, each of the connecting electrodes CM and CM' can be a Ti / Al / Ti multilayer.

[0357] The display panel 10 may include a first metal layer BML1 disposed or disposed in the main display area MDA. The first metal layer BML1 may be disposed or disposed between the substrate 100 and the main pixel circuit PC to correspond to the main thin-film transistors (TFTs) of the main display area MDA. According to an embodiment, the first metal layer BML1 may be disposed or disposed to correspond to a portion of the main display area MDA. Alternatively, the first metal layer BML1 may be disposed or disposed to correspond to the entire main display area MDA. Alternatively, the first metal layer BML1 may be integrated with the bottom metal layer BML of the component area CA. Static voltage or signals can be applied to the first metal layer BML1, thus preventing damage to the main pixel circuit PC due to electrostatic discharge.

[0358] The first metal layer BML1 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). The first metal layer BML1 may be a single layer or multiple layers comprising the aforementioned materials.

[0359] The bottom metal layer BML of the component region CA can correspond to the entire component region CA. In this case, the bottom metal layer BML may include a bottom hole BMLH superimposed on the transmission region TA. According to an embodiment, the shape and size of the transmission region TA can be defined by the shape and size of the bottom hole BMLH.

[0360] The display panel 10 may include a first wiring WL1, a second wiring WL2, a third wiring WL3, and a fourth wiring WL4 arranged or disposed on different layers.

[0361] The first wiring WL1 can be located on the first gate insulating layer 112 and can be used as a scan line SL to transmit scan signals to the main pixel circuit PC and the auxiliary pixel circuit PC'. The first wiring WL1 can be located on the same layer on which the first gate electrode G1 and the second gate electrode G2 can be arranged or disposed. Alternatively, the first wiring WL1 can be used as a light emission control line EL.

[0362] The second wiring WL2 may be located on the second gate insulating layer 113 and may be used as a scan line SL and / or a light emission control line EL. The second wiring WL2 is located on the same layer as the first upper electrode CE2 and the second upper electrode CE2' on which the main storage capacitor Cst and the auxiliary storage capacitor Cst' are arranged or disposed.

[0363] The third wiring WL3 can be located on the interlayer insulating layer 115 and can be used as a data line DL to transmit data signals to the main pixel circuit PC and the auxiliary pixel circuit PC'. Alternatively, the third wiring WL3 can be used as a drive voltage line PL to transmit drive voltage to the main pixel circuit PC and the auxiliary pixel circuit PC'.

[0364] The fourth wiring WL4 can be disposed on the first planarization layer 117a and can be used as a driving voltage line PL that can transmit driving voltage to the main pixel circuit PC and the auxiliary pixel circuit PC' or a data line DL that can transmit data signal to the main pixel circuit PC and the auxiliary pixel circuit PC'. The fourth wiring WL4 can be located on the same layer on which the connecting electrodes CM and CM' can be arranged or disposed.

[0365] Each of the first wiring WL1, the second wiring WL2, the third wiring WL3, and the fourth wiring WL4 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may be formed as a multilayer or a single layer comprising the aforementioned materials. Alternatively, each of the first wiring WL1, the second wiring WL2, the third wiring WL3, and the fourth wiring WL4 may include a transparent conductive material. The first wiring WL1, the second wiring WL2, the third wiring WL3, and the fourth wiring WL4 may include the same material or may include different materials.

[0366] Figure 26 This is a schematic cross-sectional view of a portion or area of ​​the display panel 10 according to an embodiment. Figure 25 and Figure 26 The same reference numerals in the figures represent the same elements, therefore their repeated descriptions are omitted. Figure 26 Implementation examples and Figure 25 The difference in the embodiment is that the substrate 100 may have a groove 100GR corresponding to the transmission region TA.

[0367] Reference Figure 26 The substrate 100 of the display panel 10 may include a first substrate layer 101, a first inorganic barrier layer 102, a second substrate layer 103, and a second inorganic barrier layer 104 that can be stacked sequentially. Each of the first substrate layer 101 and the second substrate layer 103 may include a polymer resin as described above. Each of the first inorganic barrier layer 102 and the second inorganic barrier layer 104 can prevent the penetration of external impurities, and therefore may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x Inorganic materials such as silicon oxynitride (SiON) or silicon oxynitride (SiON) can have single-layer or multi-layer structures.

[0368] According to an embodiment, the substrate 100 may have a groove 100GR to correspond to the transmission region TA. The groove 100GR may correspond to a component region CA in which components such as components 40 may be arranged or disposed. The groove 100GR may represent a region or area in which a portion of the substrate 100 has been removed in the downward direction (-z direction) and a portion thereof remains. For example, the first substrate layer 101 and the first inorganic barrier layer 102 may be continuous over the transmission region TA. The second substrate layer 103 and the second inorganic barrier layer 104 may each have openings 103OP and 104OP corresponding to the transmission region TA, respectively. Due to this shape, the substrate 100 may include the groove 100GR. In other words, the groove 100GR of the substrate 100 may include the opening 104OP of the second inorganic barrier layer 104, the opening 103OP of the second substrate layer 103, and the upper surface 102S of the first inorganic barrier layer 102 exposed via the openings 104OP and 103OP.

[0369] The substrate 100 may include grooves 100GR of various shapes. For example, a portion of the upper surface (+z direction) of the first inorganic barrier layer 102 may be removed, while the lower surface (-z direction) of the second substrate layer 103 may be retained. Due to the grooves 100GR of the substrate 100, the thickness of the substrate 100 in the transmission region TA can be reduced, thus significantly improving the light transmittance in the transmission region TA. According to an embodiment, the buffer layer 111 may include buffer holes 111H corresponding to the transmission region TA.

[0370] In the above embodiments, in order to improve the light transmittance of the transmission region TA, the substrate 100 may include a groove 100GR, or the buffer layer 111, the inorganic insulating layer 111, the planarization layer 117, and the pixel defining layer 119 may each include a buffer hole 111H and a first hole H1 to a third hole H3, wherein the buffer hole 111H and the first hole H1 to the third hole H3 all correspond to the transmission region TA. However, the embodiments are not limited to this.

[0371] Because the substrate 100, buffer layer 111, inorganic insulating layer 111, planarization layer 117, and pixel defining layer 119 of the display panel 10 may include materials with high light transmittance, they are arranged or disposed below the component area CA. Figure 2 The type of component 40 may exclude buffer hole 111H and first hole H1 to third hole H3.

[0372] Figures 27A to 27D These are schematic cross-sectional views of corresponding portions of the display panel 10 according to various embodiments. In detail, Figures 27A to 27D A corresponding portion of the component area CA of the display panel 10 according to various embodiments is shown.

[0373] Reference Figure 27A The inorganic insulating layer IIL can extend continuously to correspond to the transmission region TA. Alternatively, at least one of the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 in the inorganic insulating layer IIL can extend continuously to correspond to the transmission region TA. The planarization layer 117 and the pixel defining layer 119 can each include a second aperture H2 and a third aperture H3 that expose the upper surface of the inorganic insulating layer IIL to correspond to the transmission region TA.

[0374] Reference Figure 27B The inorganic insulating layer IIL and the planarization layer 117 can extend continuously to correspond to the transmission region TA, and the pixel defining layer 119 may include a third hole H3 that exposes the upper surface of the inorganic insulating layer IIL to correspond to the transmission region TA. Although Figure 27B It is not shown in the figure, but the pixel defining layer 119 may also extend continuously to correspond to the transmission region TA.

[0375] Reference Figure 27C The counter electrode 123 can extend continuously to correspond to the transmission region TA. Because the counter electrode 123 can include a material with high light transmittance, the transmission region TA can have a specific or predetermined light transmittance even if the counter electrode 123 does not include a transmission hole corresponding to the transmission region TA.

[0376] Reference Figure 27DThe inorganic insulating layer IIL may include a first aperture H1 corresponding to the transmission region TA, and the first planarization layer 117a and the second planarization layer 117b may fill the first aperture H1. According to an embodiment, the first planarization layer 117a and the second planarization layer 117b may include a transparent organic material having a refractive index similar to that of the substrate 100 and the buffer layer 111. For example, the first planarization layer 117a and the second planarization layer 117b may include a siloxane-based organic material with high light transmittance. Examples of siloxane-based organic materials may include hexamethyldisiloxane, octamethyltrisiloxane, decamethyltetrasiloxane, dodecylpentasiloxane, and polydimethylsiloxane.

[0377] Since the planarization layer 117, which can have a refractive index similar to that of the substrate 100 and the buffer layer 111, can be arranged or configured to correspond to the transmission region TA, the loss of light transmittance in the transmission region TA due to the difference between the refractive indices can be minimized.

[0378] Figure 28 It is a schematic cross-sectional view of a portion or area of ​​the display panel according to an embodiment. Figure 24 and Figure 28 The same reference numerals in the figures represent the same elements, therefore their repeated descriptions are omitted.

[0379] Reference Figure 28 The size of the auxiliary sub-pixel Pa can be larger than the size of the main sub-pixel Pm that represents the same color as the auxiliary sub-pixel Pa. In other words, the second opening OP2 of the pixel limiting layer 119 that limits the size of the auxiliary sub-pixel Pa can be larger than the first opening OP1 of the pixel limiting layer 119 that limits the size of the main sub-pixel Pm.

[0380] Because the component region CA can include a transmission region TA, the overall brightness of the component region CA may decrease if the auxiliary sub-pixel Pa has the same size as the main sub-pixel Pm and the same current is applied to the main OLED and auxiliary OLED' that realize the main sub-pixel Pm and the auxiliary sub-pixel Pa. Furthermore, if more current is applied to the auxiliary OLED' arranged or disposed in the component region CA to compensate for the brightness of the component region CA, the auxiliary OLED' may easily degrade.

[0381] According to an embodiment, the auxiliary sub-pixel Pa in the component region CA has a larger size than the main sub-pixel Pm, which represents the same color as the auxiliary sub-pixel Pa, thereby preventing degradation of the auxiliary organic light-emitting diode OLED' and also compensating for the brightness of the component region CA. For this purpose, the component region CA can employ a pixel arrangement structure that may include auxiliary sub-pixels Pa with a large size.

[0382] Figure 29A and Figure 29B This is a schematic layout diagram illustrating the pixel arrangement structure in the component region CA according to an embodiment.

[0383] Reference Figure 29A The auxiliary sub-pixels Pa arranged or disposed in the component region CA may include a first auxiliary sub-pixel Pa1 and a second auxiliary sub-pixel Pa2 implemented by display elements with different transmittances. For example, the pixel electrode of the display element implementing the first auxiliary sub-pixel Pa1 may include a reflective layer, and the pixel electrode of the display element implementing the second auxiliary sub-pixel Pa2 may be included as a transparent electrode. Therefore, the region in which the second pixel group PG2 including the second auxiliary sub-pixel Pa2 may be arranged or disposed may be a semi-transparent region STA that can transmit a portion of light. In other words, the semi-transparent region STA can be defined as a region having a higher transmittance than the region in which the first pixel group PG1 including the first auxiliary sub-pixel Pa1 may be arranged or disposed, and a lower transmittance than the transmissive region TA in which no auxiliary sub-pixels are arranged or disposed. Because the second pixel group PG2 is arranged or disposed, the transmittance of the component region CA can be ensured, and the resolution can also be improved.

[0384] exist Figure 29A In this configuration, the transmissive region TA can be arranged or located within the component region CA. However, in cases where the semi-transmissive region STA can be arranged or located, such as... Figure 29B As shown, the transmissive region TA may be excluded. The shape and pixel arrangement structure of the second auxiliary sub-pixel Pa2, which is arranged or disposed in the semi-transmissive region STA, can vary. For example, the first auxiliary sub-pixel Pa1 can be arranged or disposed in a pentile structure, and the second auxiliary sub-pixel Pa2 can be arranged or disposed in a strip structure.

[0385] Reference Figure 29B The auxiliary sub-pixel Pa arranged or disposed in the component region CA may include a first auxiliary sub-pixel Pa1 and a second auxiliary sub-pixel Pa2, which can be implemented by display elements with different transmittances. For example, the pixel electrode of the display element used to implement the first auxiliary sub-pixel Pa1 may include a reflective layer, and the pixel electrode of the display element used to implement the second auxiliary sub-pixel Pa2 may be included as a transparent electrode. In this case, the size W_Pa1 of the first auxiliary sub-pixel Pa1 may be smaller than the size W_Pa2 of the second auxiliary sub-pixel Pa2, which represents the same color as the first auxiliary sub-pixel Pa1. Under the same conditions, since the brightness of the second auxiliary sub-pixel Pa2 may be less than the brightness of the first auxiliary sub-pixel Pa1, the brightness can be balanced by reducing the size of the first auxiliary sub-pixel Pa1. Figure 29BIt may include a first pixel group PG1, a second pixel group PG2, and a third pixel group PG3.

[0386] Figure 30 This is a schematic cross-sectional view of component region CA according to an embodiment, and along... Figure 29A The schematic cross-sectional view corresponding to line II-II'. Figure 17 and Figure 30 The same reference numerals in the figures represent the same elements, therefore their repeated descriptions are omitted.

[0387] Reference Figure 30 The first auxiliary sub-pixel Pa1 and the second auxiliary sub-pixel Pa2 can be arranged or disposed in the component region CA. The first auxiliary sub-pixel Pa1 can correspond to the light-emitting area of ​​the first organic light-emitting diode OLED1, and the second auxiliary sub-pixel Pa2 can correspond to the light-emitting area of ​​the second organic light-emitting diode OLED2.

[0388] The first organic light-emitting diode (OLED) 1 may include a first pixel electrode 1211, a first functional layer 122a, a first emission layer 1221b', a second functional layer 122c, and a counter electrode 123, which are stacked sequentially. The second organic light-emitting diode (OLED) 2 may include a second pixel electrode 1212, a first functional layer 122a, a second emission layer 1222b', a second functional layer 122c, and a counter electrode 123, which are stacked sequentially.

[0389] The first pixel electrode 1211 of the first organic light-emitting diode OLED1 may include a reflective layer 1211b. Because the first pixel electrode 1211 may include a reflective layer 1211b, light generated by the first emitting layer 1221b' can be reflected by the reflective layer 1211b and emitted in the upward direction (+z direction) of the substrate 100. In other words, the efficiency of light emission in the upward direction of the substrate 100 can be improved. According to an embodiment, the first pixel electrode 1211 may include a first transparent electrode layer 1211a, a reflective layer 1211b, and a second transparent electrode layer 1211c stacked sequentially.

[0390] The first transparent electrode layer 1211a and the second transparent electrode layer 1211c may include transparent conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

[0391] The reflective layer 1211b may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a composite of these materials.

[0392] The second pixel electrode 1212 of the second organic light-emitting diode OLED2 may not include a reflective layer and may include a transparent conductive material. The second pixel electrode 1212 may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

[0393] Because the second pixel electrode 1212 may not include a reflective layer and may include a transparent conductive material, external light can at least partially pass through the second pixel electrode 1212. In other words, light / signals emitted by component 40 or incident on component 40 can pass through the second organic light-emitting diode OLED2. The area where the second organic light-emitting diode OLED2 can be arranged or disposed may be referred to as the semi-transparent region STA. The semi-transparent region STA may be a region including display elements that can transmit light, and may have a transmittance lower than that of the transmissive region TA.

[0394] Because the second pixel electrode 1212 of the second organic light-emitting diode OLED2 may not include a reflective layer, the light generated by the second emitting layer 1222b' can be emitted to both the upper and lower sides of the substrate 100. Therefore, the luminous efficacy of the second organic light-emitting diode OLED2 in the upward direction of the substrate 100 can be less than that of the first organic light-emitting diode OLED1 in the upward direction of the substrate 100. In other words, under the same conditions, the brightness of the second auxiliary sub-pixel Pa2 can be less than the brightness of the first auxiliary sub-pixel Pa1.

[0395] The second pixel electrode 1212 can be formed simultaneously with the formation of the first transparent electrode layer 1211a of the first pixel electrode 1211. Alternatively, when the first transparent electrode layer 1211a of the first pixel electrode 1211 can be formed, a portion of the second pixel electrode 1212 can be formed, and when the second transparent electrode layer 1211c of the first pixel electrode 1211 can be formed, the remaining portion of the second pixel electrode 1212 can be formed. Therefore, the thickness t2 of the second pixel electrode 1212 can be less than the thickness t1 of the first pixel electrode 1211.

[0396] The first emitting layer 1221b' of the first organic light-emitting diode OLED1 can emit light of the same color as the second emitting layer 1222b' of the second organic light-emitting diode OLED2. Alternatively, the first emitting layer 1221b' of the first organic light-emitting diode OLED1 can emit light of a different color than the second emitting layer 1222b' of the second organic light-emitting diode OLED2.

[0397] The first organic light-emitting diode (OLED) OLED1 can be driven by the first pixel circuit PC1, and the second organic light-emitting diode (OLED2) OLED2 can be driven by the second pixel circuit PC2. According to an embodiment, the second pixel circuit PC2 can be arranged or configured to be stacked with the second pixel electrode 1212 at a minimum. The bottom metal layer BML can be arranged or configured to be stacked with the first pixel circuit PC1 and the second pixel circuit PC2. The bottom metal layer BML may include a bottom hole BMLH2 corresponding to the semi-transparent region STA.

[0398] Figure 31 This is a schematic plan view of the component area CA of the display panel 10 according to an embodiment. Figure 17 and Figure 31 The same reference numerals in the figures represent the same elements, therefore their repeated descriptions are omitted.

[0399] Reference Figure 31 An organic light-emitting diode (OLED) arranged or set in the component area CA can have two light-emitting areas, and the two light-emitting areas can correspond to a first auxiliary sub-pixel Pa1 and a second auxiliary sub-pixel Pa2, respectively.

[0400] According to an embodiment, the pixel electrode 121 of an organic light-emitting diode (OLED) may include a first pixel electrode unit 1211P having a reflective layer 1211b and a second pixel electrode unit 1212P comprising a transparent conductive material. The pixel defining layer 119 may include a first opening OP1 exposing the first pixel electrode unit 1211P and a second opening OP2 exposing the second pixel electrode unit 1212P, thereby defining two light-emitting regions.

[0401] The first emitting layer 1221b' may be arranged or disposed within the first opening OP1, and the second emitting layer 1222b' may be arranged or disposed within the second opening OP2. The first emitting layer 1221b' and the second emitting layer 1222b' may emit light of the same color. Alternatively, the first emitting layer 1221b' and the second emitting layer 1222b' may emit light of different colors.

[0402] The first pixel electrode unit 1211P may include a first transparent electrode layer 1211a, a reflective layer 1211b, and a second transparent electrode layer 1211c, which are stacked sequentially. The second pixel electrode unit 1212P may be an extension of the first transparent electrode layer 1211a of the first pixel electrode unit 1211P. The second pixel electrode unit 1212P may include only the first transparent electrode layer 1211a, or it may be a stack of the first transparent electrode layer 1211a and the second transparent electrode layer 1211c.

[0403] Because the second pixel electrode unit 1212P may not include a reflective layer and may include a transparent conductive material, external light can be transmitted to a portion of the organic light-emitting diode (OLED). The second pixel electrode unit 1212P of the OLED can be arranged or disposed in the semi-transparent region STA. The bottom metal layer BML may include a bottom hole BMLH2 corresponding to the semi-transparent region STA.

[0404] Because the second pixel electrode unit 1212P of the organic light-emitting diode (OLED) may not include a reflective layer, the brightness of the second auxiliary sub-pixel Pa2 can be less than the brightness of the first auxiliary sub-pixel Pa1 under the same conditions. The thickness t2 of the second pixel electrode unit 1212P can be less than the thickness t1 of the first pixel electrode unit 1211P. Since the first auxiliary sub-pixel Pa1 and the second auxiliary sub-pixel Pa2 are implemented by a single organic light-emitting diode (OLED), they can be simultaneously driven by a single pixel circuit PC.

[0405] Figure 32 This is a plan view of the display panel 10 and the components arranged or disposed below the display panel 10 according to an embodiment.

[0406] Reference Figure 32 Each component region CA can be included within the display region DA. Each component region CA can be substantially circular and can be arranged or set inside the main display region MDA, thus being surrounded by or adjacent to the main display region MDA.

[0407] The component regions CA can be spaced apart from each other. For example, the component regions CA may include a first component region CA1 arranged or disposed in the center of the upper part of the display panel 10, a second component region CA2 arranged or disposed in the lower left part of the display panel 10, and a third component region CA3 arranged or disposed in the lower right part of the display panel 10. The first component 41, the second component 42, and the third component 43 may be arranged or disposed below the display panel 10 to correspond to the first component region CA1, the second component region CA2, and the third component region CA3, respectively. The first component 41, the second component 42, and the third component 43 may be a camera for capturing images. In this case, since images can be captured from various angles, image compensation can be achieved based on the images captured by the first component 41, the second component 42, and the third component 43.

[0408] In the case of a component region CA, the corresponding pixel arrangement structure and corresponding resolution of the component regions CA can be different from each other. For example, the first component regions CA1 to the third component regions CA3 can adopt the above reference. Figures 13A to 14F , Figure 29A and Figure 29B Different pixel arrangement structures are described in the pixel arrangement structure. Alternatively, the first component region CA1 to the third component region CA3 may be based on the same pixel arrangement structure, but may include different resolutions. For example, the corresponding basic units of the first component region CA1 to the third component region CA3 may include different numbers of auxiliary subpixels arranged or disposed therein.

[0409] Figure 33A and Figure 33B These are schematic plan views illustrating the arrangement of subpixels and wiring in a display panel according to an embodiment. Because these plan views show only a portion of the display panel, more subpixels can be omitted. Because these plan views show wiring for ease of description, more wiring can also be omitted. Each of these plan views shows a component region CA and a main display region MDA, as well as a peripheral region DPA located outside or adjacent to the component region CA.

[0410] Figure 33A and Figure 33B The component region CA can be a notch-shaped component region that can be inserted into the center of the display region DA from one side. However, the embodiment can also be applied to cases where the component region CA can be a strip-shaped component region. In other words, the upper side of the component region CA can contact the peripheral region DPA, and its lower side can contact the main display region MDA. Although in Figure 33A and Figure 33B The primary sub-pixel Pm and the auxiliary sub-pixel Pa can be arranged or set in a pentile structure, but the embodiment can adopt any of the pixel arrangement structures described above.

[0411] Reference Figure 33A The scan lines SL can all extend in the x-direction and transmit the scan signal to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa. The data lines DL can all extend in the y-direction and transmit the data signal to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa.

[0412] The scan line SL may include a first scan line SL1 and a second scan line SL2. The first scan line SL1 may both extend in the x-direction, thus electrically connecting the pixel circuits of the main sub-pixels Pm arranged or disposed on the same row within the main display area MDA, but not necessarily electrically connecting them to the pixel circuits of the auxiliary sub-pixels Pa, and may both extend above the transmissive area TA of the component area CA. The second scan line SL2 may both extend in the x-direction, thus electrically connecting the pixel circuits of the main sub-pixels Pm and the auxiliary sub-pixels Pa arranged or disposed on the same row within the main display area MDA and the component area CA.

[0413] The data lines DL may include a first data line DL1 and a second data line DL2. The first data lines DL1 may both extend in an approximate y-direction, thus electrically connecting the pixel circuits of the main sub-pixels Pm arranged or positioned in the same column within the main display area MDA, and extending above the transmissive area TA of the component area CA to the peripheral area DPA. The end DL1_E of each first data line DL1 may be located or positioned on the upper edge of the component area CA or within the peripheral area DPA.

[0414] The second data lines DL2 can all extend in the y-direction, thus allowing the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa, arranged or disposed in the same column within the main display area MDA and the component area CA, to be electrically connected to each other. The data lines DL can be arranged or disposed on a different layer than the layer on which scan lines SL can be arranged or disposed. According to an embodiment, scan lines SL can be arranged or disposed on which scan lines SL can be arranged or disposed. Figure 25 The first wiring WL1 or the second wiring WL2 is on the same layer, and the data line DL can be arranged or set on it. Figure 25 On the same layer as the third wiring WL3 or the fourth wiring WL4.

[0415] According to an embodiment, the corresponding end DL2_E of the second data line DL2 can be at the same level as the corresponding end DL1_E of the first data line DL1. For example, the corresponding end DL2_E of the second data line DL2 can be located or disposed on the upper edge of the component region CA or in the peripheral region DPA to include an electrical load of each second data line DL2 that is at the same level as the electrical load of each first data line DL1.

[0416] According to an embodiment, at least some or a predetermined number of scan lines SL and data lines DL can all extend over the transmission region TA. According to an embodiment, the scan lines SL and data lines DL can include transparent conductive materials. For example, the scan lines SL and data lines DL can include transparent conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). Because the wiring arranged or disposed in the transmission region TA can include transparent conductive materials, the transmittance of the transmission region TA can be maintained at a high level.

[0417] According to an embodiment, at least some or a predetermined number of scan lines SL and data lines DL may all extend above the transmission region TA, but may include opaque metal. Depending on the type of component to be arranged or configured to correspond to the component region CA, the material included in at least some or a predetermined number of scan lines SL and data lines DL can be appropriately selected by taking transmittance into account.

[0418] exist Figure 33A In this configuration, both the scan line (SL) and the data line (DL) can extend continuously on the main display area (MDA) and the component area (CA). However, as... Figure 33B As shown, the scan line SL and data line DL can be electrically connected via contact holes CNTB1 and CNTB2 in some or a predetermined number of areas to scan bridge wiring SBL and data bridge wiring DBL, which are arranged or set on a different layer from the scan line SL and data line DL.

[0419] Figure 34 This is a schematic cross-sectional view of the display panel 10 according to an embodiment, showing the wiring arranged or disposed in the transmissive area. In detail, Figure 34 The location of transparent wiring arranged or disposed in the transmission region TA is shown when the inorganic insulating layer 1IL, the planarization layer 117 and the pixel defining layer 119 include a first hole H1 to a third hole H3 to correspond to the transmission region TA.

[0420] The substrate 100 of the display panel 10 may include a first substrate layer 101, a first inorganic barrier layer 102, a second substrate layer 103, and a second inorganic barrier layer 104 stacked sequentially.

[0421] The first transparent wiring TTL1 may be located on the lower surface of the substrate 100. The inorganic protective layer PVX may be located on the entire lower surface of the substrate 100 to cover the first transparent wiring TTL1 or to be superimposed on the first transparent wiring TTL1. The second transparent wiring TTL2 may be located between the first inorganic barrier layer 102 and the second substrate layer 103 of the substrate 100. The third transparent wiring TTL3 may be located between the second inorganic barrier layer 104 and the buffer layer 111. The fourth transparent wiring TTL4 may be located on the buffer layer 111.

[0422] The first transparent wiring TTL1 to the fourth transparent wiring TTL4 may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

[0423] At least one of the first transparent wiring TTL1 to the fourth transparent wiring TTL4 can be used as a scan line SL or scan bridge wire SBL capable of transmitting scan signals, and another of the first transparent wiring TTL1 to the fourth transparent wiring TTL4 can be used as a data line DL or data bridge wire DBL capable of transmitting data signals. In this case, the first transparent wiring TTL1 to the fourth transparent wiring TTL4 can be electrically connected to the first wiring WL1 to the fourth wiring WL4 via contact holes.

[0424] According to an embodiment, a fourth transparent wiring TTL4 can be formed simultaneously with the formation of the pixel electrode 121'. The pixel electrode 121' can be a stack of transparent conductive oxide and a reflective layer. For example, the pixel electrode 121' can be a stacked structure of ITO / Ag / ITO.

[0425] Therefore, ITO / Ag / ITO can be formed on the entire surface of the substrate 100 to form pixel electrode 121' and fourth transparent wiring TTL4, and the pixel electrode 121' of ITO / Ag / ITO and the fourth transparent wiring TTL4 of ITO can be formed by a process using a halftone mask or a slit mask.

[0426] Figure 35 This is a schematic cross-sectional view of the display panel according to an embodiment, and shows the view along... Figure 33B A schematic cross-sectional view taken along lines III-III' and IV-IV'. In detail, Figure 35 The diagram shows a structure in which the scan line SL and the data line DL can be electrically connected to a bridge wire that is implemented as transparent wiring.

[0427] Reference Figure 35 The scan line SL can be disposed around the transmission region TA on the first gate insulating layer 112, and the first gate insulating layer 112 can be arranged or disposed thereon. Figure 34 The first wiring WL1 is on the same layer, and the scan bridge line SBL can be disposed on the lower surface of the substrate 100. The scan bridge line SBL can be disposed on the same layer as the first transparent wiring TTL1 to correspond to the transmission region TA. The scan line SL can be electrically connected to the scan bridge line SBL via a contact hole CNTB1 that penetrates the first gate insulating layer 112, the buffer layer 111 and the substrate 100.

[0428] The data cable DL can be disposed on the interlayer insulation layer 115 around the transmission area TA, and the interlayer insulation layer 115 can be arranged or disposed thereon. Figure 34 The third wiring WL3 is on the same layer, and the data bridge wiring DBL can be located on the same layer as the fourth transparent wiring TTL4, corresponding to the transmission area TA. The data line DL can be electrically connected to the data bridge wiring DBL around the transmission area TA via the contact hole CNTB2 penetrating the planarization layer 117. The data bridge wiring DBL can be located on the portion of the buffer layer 111 defined by the first hole H1 of the inorganic insulating layer IIL and the second hole H2 of the planarization layer 117, and the data bridge wiring DBL can be located on the corresponding inner sidewalls of the first hole H1 of the inorganic insulating layer IIL and the second hole H2 of the planarization layer 117.

[0429] although Figure 35 The diagram shows that the scan bridge cable SBL can be disposed on the same layer as the first transparent wiring TTL1, and the data bridge cable DBL can be disposed on the same layer as the fourth transparent wiring TTL4, but the embodiment is not limited thereto. For example, the scan bridge cable SBL can be disposed on the same layer as the first transparent wiring TTL1, and the data bridge cable DBL can be disposed on the same layer as the fourth transparent wiring TTL4, but the embodiment is not limited thereto. Figure 34 The second transparent cabling TTL2 to the fourth transparent cabling TTL4 are on the same layer, and the data bridge wiring DBL can be arranged or set on it. Figure 34 On the same layer as one of the first transparent wiring TTL1 to the third transparent wiring TTL3.

[0430] Figure 36A and Figure 36B This is a schematic plan view illustrating the arrangement relationship between sub-pixels and wiring of a display panel according to an embodiment. Figure 36A and Figure 36B Zhongyu Figure 33A In the accompanying drawings, the same reference numerals indicate the same elements, so their repeated descriptions are omitted.

[0431] Reference Figure 36AThe scan lines SL and data lines DL arranged or disposed in the component region CA may not be located at the center of the transmission region TA, but may be offset to one side of the transmission region TA to improve the light transmittance in the component region CA. For this purpose, the scan lines SL and data lines DL arranged or disposed in the component region CA may be appropriately curved. Therefore, the spacing between scan lines SL passing between spaced pixel groups PG can be smaller than the spacing between scan lines SL passing through sub-pixels included in pixel groups PG. Similarly, the spacing between data lines DL passing between spaced pixel groups PG can be smaller than the spacing between data lines DL passing through sub-pixels included in pixel groups PG.

[0432] According to an embodiment, a first data line DL1 arranged or disposed between spaced-apart pixel groups PG can be offset on the upper left, and a second data line DL2 arranged or disposed between spaced-apart pixel groups PG can be offset on the upper right. According to an embodiment, a first scan line SL1 arranged or disposed between spaced-apart pixel groups PG can be offset on the upper lower side, and a second scan line SL2 arranged or disposed between spaced-apart pixel groups PG can be offset on the upper upper side.

[0433] Based on this wiring arrangement, the transmittance of the transmission region TA and the transmittance of the entire component region CA can be improved. Because light diffraction may occur as the spacing between wirings arranged or placed in the component region CA decreases, the bottom metal layer BML can be... Figure 36B The arrangement shown is superimposed on wiring arranged or disposed in the component region CA. According to an embodiment, the bottom metal layer BML may be arranged or disposed corresponding to the entire component region CA and may include a bottom hole BMLH corresponding to the transmission region TA. Figures 16A to 16H The changes mentioned above.

[0434] Figure 37 This is a schematic plan view illustrating the arrangement relationship between sub-pixels and wiring of a display panel according to an embodiment. Figure 38A and Figure 38B It is along Figure 37 A schematic cross-sectional view taken by line V-V'. Figure 36A and Figure 37 The same reference numerals in the figures represent the same elements, therefore their repeated descriptions are omitted.

[0435] Reference Figure 37Each second data line DL2 can extend continuously from the main display area MDA to the component area CA, but each first data line DL1 can be electrically connected via contact hole CNTB at the edge of the component area CA to each data bridge wire DBL arranged or disposed on a different layer from the layer on which the first data line DL1 can be arranged or disposed. The second data line DL2 can be arranged or disposed on the same layer on which the first data line DL1 can be arranged or disposed.

[0436] Because the data bridge cable DBL can be arranged or set on a different layer than the layer on which the second data line DL2 can be arranged or set, the data bridge cable DBL can be arranged or set adjacent to the second data line DL2, or it can be superimposed on the second data line DL2. For example, Figure 38A As shown, the data bridge cable DBL and the second data line DL2 can be alternated in one direction. Alternatively, as... Figure 38B As shown, the data bridge cable DBL can be stacked at least partially with the second data line DL2.

[0437] Because of this structure, the area occupied by wiring in the component region CA can be reduced, thus allowing the transmission region TA to be relatively enlarged. Therefore, the light transmittance of the component region CA can be improved.

[0438] Figures 39 to 41 These are schematic plan views illustrating the arrangement of subpixels and wiring in a display panel according to an embodiment. Because these plan views show a portion or area of ​​the display panel, additional subpixels may be omitted. Because these plan views show the wiring required for description, additional wiring may also be omitted. These plan views show the component area CA and the main display area MDA located or situated outside the component area CA.

[0439] Figures 39 to 41 The component area CA can be arranged or set inside the display area DA, and surrounded by or adjacent to the main display area MDA. In other words, the upper and lower sides of the component area CA can contact the main display area MDA. Although in Figures 39 to 41 In this embodiment, the auxiliary sub-pixel Pa and the main sub-pixel Pm can be arranged or set in a pentile structure, but the embodiment can adopt any of the pixel arrangement structures described above.

[0440] Reference Figure 39 The scan lines SL can all extend in the x-direction and transmit the scan signal to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa. The data lines DL can all extend in the y-direction and transmit the data signal to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa.

[0441] The scan line SL may include a first scan line SL1 and a second scan line SL2. The first scan line SL1 may both extend in the x-direction, thus electrically connecting the pixel circuits of the main sub-pixels Pm arranged or disposed on the same row within the main display area MDA, but not necessarily electrically connecting them to the pixel circuits of the auxiliary sub-pixels Pa, and both may extend above the transmission area TA. The second scan line SL2 may both extend in the x-direction, thus electrically connecting the pixel circuits of the main sub-pixels Pm and the auxiliary sub-pixels Pa arranged or disposed on the same row within the main display area MDA and the component area CA.

[0442] The data lines DL can include a first data line DL1 and a second data line DL2. The first data lines DL1 can both extend in the approximate y-direction, thus electrically connecting the pixel circuits of the main sub-pixels Pm arranged or disposed in the same column within the portion of the main display area MDA located below the component area CA, and both traverse the transmission area TA of the component area CA, and electrically connecting the pixel circuits of the main sub-pixels Pm arranged or disposed in the same column within the portion of the main display area MDA located above the component area CA. The second data lines DL2 can both extend in the y-direction, thus electrically connecting the pixel circuits of the main sub-pixels Pm and the pixel circuits of the auxiliary sub-pixels Pa arranged or disposed in the same column within the main display area MDA and the component area CA. The data lines DL can be arranged or disposed on a layer different from the layer on which scan lines SL can be arranged or disposed.

[0443] According to an embodiment, at least some or a predetermined number of scan lines SL and data lines DL can all extend over the transmission region TA. According to an embodiment, the scan lines SL and data lines DL can include a transparent conductive material. For example, the scan lines SL and data lines DL can include transparent conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). Because the wiring traversing the transmission region TA includes a transparent conductive material, the transmittance of the transmission region TA can be maintained at a high level.

[0444] According to an embodiment, at least some or a predetermined number of scan lines SL and data lines DL may all extend above the transmission region TA, but may include opaque metal. Depending on the type of component to be arranged or configured to correspond to the component region CA, the material included in at least some or a predetermined number of scan lines SL and data lines DL can be appropriately selected by taking transmittance into account.

[0445] Despite Figure 39The scan lines SL and DL can both extend continuously above the main display area MDA and the component area CA, but the scan lines SL and DL can be electrically connected to bridging lines arranged or set on different layers in some or predetermined areas.

[0446] Reference Figure 40 The scan lines SL and data lines DL arranged or disposed in the component region CA may not be located at the center of the transmission region TA, but may be offset to one side of the transmission region TA to improve the light transmittance in the component region CA. For this purpose, the scan lines SL and data lines DL arranged or disposed in the component region CA may be appropriately curved. Therefore, the spacing between scan lines SL passing between spaced pixel groups PG can be smaller than the spacing between scan lines SL passing through sub-pixels included in pixel groups PG. Similarly, the spacing between data lines DL passing between spaced pixel groups PG can be smaller than the spacing between data lines DL passing through sub-pixels included in pixel groups PG.

[0447] According to an embodiment, a first data line DL1 arranged or disposed between spaced-apart pixel groups PG can be offset on the upper left, and a second data line DL2 arranged or disposed between spaced-apart pixel groups PG can be offset on the upper right. According to an embodiment, a first scan line SL1 arranged or disposed between spaced-apart pixel groups PG can be offset on the upper lower side, and a second scan line SL2 arranged or disposed between spaced-apart pixel groups PG can be offset on the upper upper side.

[0448] According to this wiring arrangement, the light transmittance of the transmission region TA and the light transmittance of the entire component region CA can be improved. Because light diffraction may occur as the spacing between the wiring arranged or set in the component region CA decreases, the bottom metal layer can be arranged or set to overlap with the wiring arranged or set in the component region CA.

[0449] Reference Figure 41 Each second data line DL2 can extend continuously from the main display area MDA to the component area CA, but each first data line DL1 can be electrically connected via contact hole CNTB at the edge of the component area CA to each data bridge wiring DBL that is arranged or disposed on a different layer from the layer on which the first data line DL1 and the second data line DL2 can be arranged or disposed.

[0450] Because the data bridge cable DBL can be arranged or positioned on a different layer than the layer on which the second data line DL2 can be arranged or positioned, the data bridge cable DBL can be arranged or positioned adjacent to or superimposed on the second data line DL2. Due to this structure, the area occupied by wiring in the component region CA can be reduced, and therefore the transmission region TA can be relatively enlarged. Thus, the light transmittance of the component region CA can be improved. Although not shown in the accompanying drawings, at least some or a predetermined number of scan lines SL can be electrically connected to the bridge cable arranged or positioned on a different layer than the layer on which the scan lines SL can be arranged or positioned.

[0451] Figure 42 This is a schematic plan view of the display panel 10 according to an embodiment. Figure 42 and Figure 10 The difference lies in the fact that the main display area MDA and the component area CA are respectively connected to the first display driving unit 32a and the second display driving unit 32b.

[0452] Reference Figure 42 Various components constituting the display panel 10 can be arranged or disposed on the substrate 100. The substrate 100 may include a display area DA and a peripheral area DPA, with the peripheral area DPA surrounding or adjacent to the display area DA. The display area DA may include a main display area MDA on which one or more main images can be displayed, and a component area CA that may contain a transmission area TA and on which one or more auxiliary images can be displayed. The auxiliary images may form a single overall image together with the main image, or they may be images independent of the main image.

[0453] The primary sub-pixel Pm can be arranged or set in the primary display area MDA, and the auxiliary sub-pixel Pa can be arranged or set in the component area CA.

[0454] The pixel circuits driving the main sub-pixel Pm and the auxiliary sub-pixel Pa can be electrically connected to external circuits arranged or disposed in the peripheral area DPA. The first scan drive circuit SDRV1, the second scan drive circuit SDRV2, the first terminal unit PAD1, the second terminal unit PAD2, the first drive voltage supply line 11a, the second drive voltage supply line 11b, the first common voltage supply line 13a, and the second common voltage supply line 13b can be arranged or disposed in the peripheral area DPA.

[0455] The first scan drive circuit SDRV1 and the second scan drive circuit SDRV2 can apply scan signals to the pixel circuits that drive the main sub-pixel Pm and the auxiliary sub-pixel Pa respectively via the scan line SL.

[0456] The first terminal unit PAD1 can be arranged or disposed on one side of the substrate 100. The first terminal unit PAD1 can be exposed without being covered by or superimposed on the insulating layer, and can be electrically connected to the first display circuit board 30a. The first display driving unit 32a can be located on the first display circuit board 30a. According to an embodiment, the first display driving unit 32a can be disposed in the peripheral area DPA of the display panel 10. The first display driving unit 32a can generate data signals, a first driving voltage, a first common voltage, etc., that can be transmitted to the pixel circuits that can drive the main sub-pixels Pm arranged or disposed in the main display area MDA.

[0457] The first display driving unit 32a can generate control signals that are transmitted to the first scan driving circuit SDRV1 and the second scan driving circuit SDRV2. The first display driving unit 32a can supply a first driving voltage to the first driving voltage supply line 11a and a first common voltage to the first common voltage supply line 13a. The first driving voltage can be applied to the pixel circuit of the main sub-pixel Pm via the driving voltage line PL electrically connected to the first driving voltage supply line 11a, and the first common voltage can be electrically connected to the first common voltage supply line 13a and applied to the counter electrode of the display element of the main sub-pixel Pm. The first display driving unit 32a can generate data signals, and the generated data signals can be transmitted to the pixel circuit of the main sub-pixel Pm via the first fan-out wiring FW1 and the data line DL electrically connected to the first fan-out wiring FW1.

[0458] The second terminal unit PAD2 may be arranged or disposed on the other side of the substrate 100. The second terminal unit PAD2 may be exposed without being covered by or superimposed on the insulating layer, and may be electrically connected to the second display circuit board 30b. The second display driving unit 32b may be located on the second display circuit board 30b. According to an embodiment, the second display driving unit 32b may be located in the peripheral region DPA of the display panel 10. The second display driving unit 32b may generate at least one of a data signal, a second driving voltage, and a second common voltage that can be transmitted to the pixel circuit that can drive the auxiliary sub-pixel Pa arranged or disposed in the component region CA.

[0459] The second display driving unit 32b can supply a second driving voltage to the second driving voltage supply line 11b and a second common voltage to the second common voltage supply line 13b. The second driving voltage can be applied to the pixel circuit of the auxiliary sub-pixel Pa via the driving voltage line PL electrically connected to the second driving voltage supply line 11b, and the second common voltage can be electrically connected to the second common voltage supply line 13b and applied to the counter electrode of the display element of the auxiliary sub-pixel Pa. The second display driving unit 32b can generate a data signal, and the generated data signal can be transmitted to the pixel circuit of the auxiliary sub-pixel Pa via the second fan-out wiring FW2 and the data line DL electrically connected to the second fan-out wiring FW2.

[0460] According to an embodiment, the second driving voltage provided by the second display driving unit 32b may be different from the first driving voltage provided by the first display driving unit 32a, and the second common voltage provided by the second display driving unit 32b may be different from the first common voltage provided by the first display driving unit 32a.

[0461] Because the number of auxiliary sub-pixels Pa per unit area of ​​the component region CA can be less than the number of main sub-pixels Pm per unit area of ​​the main display region MDA, the brightness of the component region CA may be lower when the same driving voltage and the same common voltage are applied to the main display region MDA and the component region CA. According to an embodiment, a second display driving unit 32b can be used to drive the component region CA independently, thus allowing control over the brightness of the component region CA.

[0462] According to an embodiment, since a second display driving unit 32b is used in the driving component region CA, the driving component located below the driving component region CA is driven. Figure 2 While the component 40 is in use, the auxiliary sub-pixel Pa of the component region CA can be driven without driving it, thus reducing the noise caused by driving the auxiliary sub-pixel Pa.

[0463] exist Figure 42 The display panel 10 may include a second display circuit board 30b. However, according to an embodiment, the second display circuit board 30b may not be included. In this case, the second terminal unit PAD2 may also be omitted. The second display driving unit 32b may be arranged or disposed in the peripheral area DPA of the display panel 10, or it may be arranged or disposed on the first display circuit board 30a. In this way, various modifications can be made.

[0464] Figure 43 This is a schematic plan view illustrating the arrangement relationship between sub-pixels and wiring of a display panel according to an embodiment. Figure 43This mainly describes the arrangement or placement of the main data line DLm and auxiliary data line DLa in the main display area MDA surrounding the component area CA, when the component area CA can be driven independently.

[0465] Figure 43 The component area CA can be strip-shaped. In other words, the upper side of the component area CA can contact the peripheral area DPA, and its lower side can contact the main display area MDA.

[0466] Reference Figure 43 The main data line DLm can extend in the +y direction throughout the main display area MDA and can be electrically connected to the pixel circuit of the main sub-pixel Pm. Figure 42 The first data signal generated by the first display driving unit 32a is transmitted to the pixel circuit of the main sub-pixel Pm. The main data line DLm can be arranged within the main display area MDA or set as an approximately straight line.

[0467] The auxiliary data line DLa can extend in the -y direction within the component region CA and can be electrically connected to the pixel circuit of the auxiliary sub-pixel Pa. Figure 42 The second data signal generated by the second display driving unit 32b is transmitted to the pixel circuit of the auxiliary sub-pixel Pa. The auxiliary data line DLa can be arranged or configured to be biased on one side when crossing the transmission region TA to improve the transmittance of the transmission region TA. Therefore, the auxiliary data line DLa can be appropriately bent.

[0468] According to the embodiment, because the main sub-pixel Pm and the auxiliary sub-pixel Pa are driven by separate display driving units, the main data line DLm and the auxiliary data line DLa do not need to be connected to each other. In other words, the corresponding end DLm_E of the main data line DLm can face the corresponding end DLa_E of the auxiliary data line DLa and can be spaced apart from it.

[0469] although Figure 43 Although not shown, the drive voltage line that transmits the drive voltage can also be included separately in the component area CA and the main display area MDA, just like the main data line DLm and the auxiliary data line DLa, and can have similar aspects to the main data line DLm and the auxiliary data line DLa.

[0470] Figure 44 This is a schematic plan view illustrating the arrangement relationship between sub-pixels and wiring of a display panel according to an embodiment. Figure 44 This mainly describes the arrangement or setting of data lines in the component area CA and the main display area MDA surrounding the component area CA, in the case where the component area CA can be driven independently. Figure 44The component area CA can be surrounded by or adjacent to the main display area MDA. In other words, both the top and bottom sides of the component area CA can contact the main display area MDA.

[0471] Reference Figure 44 The first main data line DLm1 and the second main data line DLm2 can be arranged or set in the main display area MDA. The first main data line DLm1 and the second main data line DLm2 can be... Figure 42 The first data signal generated by the first display driving unit 32a is transmitted to the pixel circuit of the main sub-pixel Pm.

[0472] The first main data line DLm1 may be discontinuous around the component region CA and may be electrically connected via contact hole CNTB to a data bridge wiring DBL arranged or disposed on a different layer than the first main data line DLm1. The second main data line DLm2 may traverse the transmission region TA of the component region CA and may be electrically connected to the pixel circuitry of the main sub-pixel Pm arranged or disposed above and below the component region CA. The second main data line DLm2 may be disposed on the same layer on which the first main data line DLm1 may be arranged or disposed. For example, the second main data line DLm2 and the first main data line DLm1 may be located on an interlayer insulating layer 115, on which an interlayer insulating layer 115 may be arranged or disposed. Figure 25 The third wiring WL3 is on the same layer. The data bridge wiring DBL can be set on the first flattening layer 117a, which can be arranged or set on it. Figure 25 The fourth wiring WL4 is on the same layer.

[0473] The data bridge cable DBL and the second main data line DLm2 can be appropriately bent and biased on one side of each pixel group PG to ensure the transmittance of the transmission region TA. Because the data bridge cable DBL and the second main data line DLm2 are located on different layers, they can be adjacent to each other or at least partially overlapped while traversing the component region CA. Therefore, the transmittance of the transmission region TA can be improved.

[0474] The auxiliary data line DLa can extend in the -y direction within the component region CA and can be electrically connected to the pixel circuit of the auxiliary sub-pixel Pa. Figure 42 The second data signal generated by the second display driving unit 32b is transmitted to the pixel circuit of the auxiliary sub-pixel Pa. The auxiliary data line DLa can be arranged or configured to be biased on one side when crossing the transmission region TA to improve the transmittance of the transmission region TA. Therefore, the auxiliary data line DLa can be appropriately bent.

[0475] According to an embodiment, the auxiliary data line DLa can be disposed on the same layer as the first main data line DLm1 and the second main data line DLm2. However, the embodiment is not limited to this. For example, the auxiliary data line DLa can be disposed on the same layer as the data bridge cable DBL.

[0476] The auxiliary data line DLa can be arranged or positioned in the main display area MDA or in the portion above the component area CA, but the auxiliary data line DLa may not be electrically connected to the pixel circuit of the main sub-pixel Pm. The corresponding ends of the auxiliary data line DLa can be located within the component area CA. The corresponding ends of the auxiliary data line DLa can face the corresponding ends of the first main data line DLm1 and can be spaced apart from each other.

[0477] Figure 45 This is a schematic plan view of the display panel 10 according to an embodiment. Figure 45 The main description is of the load matching unit LM and / or dummy pixel circuit DPC arranged or set on the display panel 10.

[0478] Reference Figure 45 The display panel 10 may include a display area DA and a peripheral area DPA. The display area DA includes a main display area MDA and a component area CA. The peripheral area DPA is located outside or adjacent to the display area DA. A load matching unit LM and / or a dummy pixel circuit DPC may be arranged near the component area CA or within the peripheral area DPA. Although Figure 45 The component area CA can be notched, but the shape of the component area CA is not limited to this.

[0479] The load matching unit LM and / or the dummy pixel circuit DPC can be arranged near the component area CA or disposed in the peripheral area DPA, and can be electrically connected via a first load connection line LW1 to the pixel circuit of the main sub-pixel Pm arranged or disposed in the main display area MDA. For example, the first load connection line LW1 can be electrically connected via a contact hole CNTL1 to a scan line SL that crosses the main sub-pixel Pm. According to an embodiment, the first load connection line LW1 may include components included in the component area CA. Figure 17 The bottom metal layer BML is made of the same or similar material, and can be arranged or set on it. Figure 17 On the same layer as the bottom metal layer BML. Because the portion of the scan line SL that crosses the component region CA can be electrically connected to the pixel circuit of the auxiliary sub-pixel Pa, the first load connection line LW1 can be a conductive layer arranged or disposed on a different layer from the layer on which the scan line SL can be arranged or disposed.

[0480] Because the number of auxiliary sub-pixels Pa per unit area of ​​the component region CA can be less than the number of main sub-pixels Pm per unit area of ​​the main display region MDA, the load applied to the scan line SL that crosses the component region CA may differ from the load applied to the scan line SL that only crosses the main display region MDA. Therefore, brightness non-uniformity may occur in the display region DA. According to embodiments, employing a load matching unit LM and / or a dummy pixel circuit DPC can make the electrical load uniform across the entire display region DA, thereby ensuring brightness uniformity.

[0481] It may include a load matching unit LM and / or a dummy pixel circuit DPC, and the load matching unit LM and / or the dummy pixel circuit DPC may be electrically connected to each other via a second load connection line LW2. Because the load matching unit LM and / or the dummy pixel circuit DPC are electrically connected to each other, the equipotential zone can be expanded, thereby preventing the display area DA from being damaged by electrostatic discharge.

[0482] exist Figure 45 In this embodiment, the load matching unit LM and / or the dummy pixel circuit DPC can be arranged or disposed in the peripheral area DPA of the display panel 10. However, according to an embodiment, the load matching unit LM and / or the dummy pixel circuit DPC can be provided or disposed on a separate dummy panel and can be electrically connected to the display panel 10. The peripheral area DPA in which the load matching unit LM and / or the dummy pixel circuit DPC are arranged or disposed can be bent.

[0483] Figure 46 This is a schematic plan view of the load matching unit LM of the display panel according to an embodiment. Figure 47 It is along Figure 46 A schematic cross-sectional view taken from line VI-VI'.

[0484] Reference Figure 46 and Figure 47 The load matching unit LM may include a first load conductive layer LCL1, a second load conductive layer LCL2 disposed above the first load conductive layer LCL1, and a third load conductive layer LCL3 disposed above the second load conductive layer LCL2. The first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 may be disposed between the first load conductive layer LCL1 and the third load conductive layer LCL3.

[0485] According to an embodiment, the first load conductive layer LCL1 may include and Figure 17 The semiconductor layer A1 comprises materials that are the same as or similar to those on which it may be arranged or disposed. Figure 17 On the same layer as semiconductor layer A1. The second load conductive layer LCL2 may include the same layer as... Figure 17The gate electrode G1 comprises the same or similar material and can be arranged or disposed thereon. Figure 17 On the same layer as the gate electrode G1. The third load conductive layer LCL3 may include the same layer as the gate electrode G1. Figure 17 The source electrode S1 or the drain electrode D1 may contain materials that are the same or similar to those used in the electrode, and may be arranged or disposed thereon. Figure 17 On the same layer as the source electrode S1 or the drain electrode D1.

[0486] The first load conductive layer LCL1 can be electrically connected to the third load conductive layer LCL3 via contact hole CNTL2. The second load conductive layer LCL2 can be electrically connected to the first load connection line LW1 via contact hole CNTL1. The third load conductive layer LCL3 can be electrically connected to the drive voltage line and receive the static voltage. Due to the arrangement of the first load conductive layer LCL1 to the third load conductive layer LCL3, the load matching unit LM can form an electrical load such as a capacitor.

[0487] According to an embodiment, the first load conductive layer LCL1 to the third load conductive layer LCL3 can all be patterned and extend in the x-direction or the y-direction. In other words, the first load conductive layer LCL1 to the third load conductive layer LCL3 can be conductive lines spaced apart from each other and extending in one direction.

[0488] Reference Figure 46 The first load conductive layer LCL1 can extend in the +y direction, and the second load conductive layer LCL2 can extend in the +x direction. The first load conductive layer LCL1 and the second load conductive layer LCL2 can intersect each other to form a grid shape.

[0489] The third load conductive layer LCL3 can be located on the second load conductive layer LCL2. For example... Figure 47 As shown, the third load conductive layer LCL3 can extend in the +y direction like the first load conductive layer LCL1, and can be stacked with the first load conductive layer LCL1. According to an embodiment, the third load conductive layer LCL3 can be patterned in one direction like the first load conductive layer LCL1. Figure 46 In this embodiment, similar to the first load conductive layer LCL1, the third load conductive layer LCL3 is patterned in the +y direction. However, according to other embodiments, the third load conductive layer LCL3 may be patterned in the +x direction.

[0490] According to an embodiment, the load matching unit LM may not include the first load conductive layer LCL1. According to an embodiment, the third load conductive layer LCL3 of the load matching unit LM may not be patterned and may be integrally provided or disposed over the entire area of ​​the load matching unit LM.

[0491] Figure 48 This is a schematic cross-sectional view of a portion or area of ​​the display panel 10 according to an embodiment. Figure 48 The main description is of the dummy pixel circuit DPC arranged or set in the peripheral area DPA of the display panel 10.

[0492] Reference Figure 48 The main pixel circuit (PC) and the main organic light-emitting diode (OLED) as the display element can be arranged or disposed in the main display area (MDA) of the display panel 10. The dummy pixel circuit (DPC) can be arranged or disposed in the peripheral area (DPA) of the display panel 10. The dummy pixel circuit (DPC) can be similar to... Figure 45 The load matching unit LM is a component that regulates the electrical load and may not be connected to the display element.

[0493] The dummy pixel circuit (DPC) may include a dummy thin-film transistor (TFTd) and a dummy storage capacitor (Cstd). The dummy TFTd may include a dummy semiconductor layer Ad, a dummy gate electrode Gd, a dummy source electrode Sd, and a dummy drain electrode Dd. The dummy storage capacitor Cstd may include a dummy lower electrode Cstd1 and a dummy upper electrode Cstd2.

[0494] The dummy pixel circuit (DPC) may include a thin-film transistor. According to embodiments, the DPC may have the same or similar structure as the main pixel circuit (PC).

[0495] The dummy pixel circuit (DPC) can be electrically connected to scan lines, data lines, and drive voltage lines arranged or disposed in the main display area (MDA). For example, the dummy gate electrode (Gd) of the dummy thin-film transistor (TFTd) can be electrically connected to the scan line arranged or disposed in the main display area (MDA).

[0496] The organic functional layer 122e, counter electrode 123, and upper layer 150 can be arranged or disposed above the dummy pixel circuit (DPC). Since the organic functional layer 122e, counter electrode 123, and upper layer 150 can all extend over the entire display panel 10 using an aperture mask, it is advantageous in terms of manufacturing process to arrange the organic functional layer 122e, counter electrode 123, and upper layer 150 corresponding to the dummy pixel circuit (DPC).

[0497] Figure 49 This is a schematic cross-sectional view of the display panel 10 according to an embodiment. Figure 49 This mainly describes the thin-film encapsulation layer TFEL that can be applied to the arrangement or configuration of the encapsulation component ENCM. Figure 26 The case of the embodiment.

[0498] Reference Figure 49The thin-film encapsulation layer TFEL can be arranged as an encapsulation component ENCM or disposed above the display element layer EDL of the display panel 10. In other words, the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') can be sealed by the thin-film encapsulation layer TFEL. The thin-film encapsulation layer TFEL can be positioned or disposed on the upper layer 150. The thin-film encapsulation layer TFEL can prevent external moisture or foreign matter from penetrating into the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED').

[0499] The thin-film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Regarding this, Figure 49 The thin-film encapsulation layer TFEL is shown to be a stack of a first inorganic encapsulation layer 131, an organic encapsulation layer 132, and a second inorganic encapsulation layer 133. According to embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order of the organic and inorganic encapsulation layers can be modified.

[0500] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may include at least one inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x The organic encapsulation layer 132 may comprise a polymeric material, such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO), and may be formed by chemical vapor deposition (CVD). Examples of polymeric materials include silicone resins, acrylic resins, epoxy resins, polyimides, and polyethylene.

[0501] The first inorganic encapsulation layer 131, the organic encapsulation layer 132, and the second inorganic encapsulation layer 133 can all be integrally configured to cover the main display area MDA and the component area CA, or superimposed on the main display area MDA and the component area CA. Therefore, the first inorganic encapsulation layer 131, the organic encapsulation layer 132, and the second inorganic encapsulation layer 133 can be arranged or disposed within the transmission aperture TAH.

[0502] like Figure 49 As shown, in the case where the substrate 100 may include a groove 100GR to correspond to the transmission region TA, the first inorganic encapsulation layer 131 may be disposed within the groove 100GR of the substrate 100. The first inorganic encapsulation layer 131 may directly contact the upper surface 102S of the first inorganic barrier layer 102 of the substrate 100.

[0503] According to an embodiment, the organic encapsulation layer 132 may be integrally configured to cover the main display area MDA and the component area CA, or superimposed on the main display area MDA and the component area CA, but may not exist in the transmissive area TA. In other words, the organic encapsulation layer 132 may include an opening corresponding to the transmissive area TA. In this case, the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may be in contact with each other within the transmissive aperture TAH.

[0504] Figure 50 It is a schematic cross-sectional view of a portion or area of ​​a display device according to an embodiment. Figure 50 This mainly describes how the encapsulation substrate ENS can be used as an encapsulation component ENCM. Figure 25 The case of the embodiment.

[0505] Reference Figure 50 The encapsulation substrate ENS can be arranged as an encapsulation component ENCM or disposed above the display element layer EDL of the display panel 10. The main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED) can be sealed by the encapsulation substrate ENS. The substrate 100 and the encapsulation substrate ENS can be bonded to each other by glass frit or sealant in the peripheral area.

[0506] Substrate 100 may include a glass material, and the encapsulation substrate ENS may also include a glass material. Each of substrate 100 and encapsulation substrate ENS may include a glass substrate. An internal space INS may be defined between substrate 100 and encapsulation substrate ENS and may include an air layer. Alternatively, the internal space INS may include a transparent material layer. The transparent material layer may include a transparent material having a refractive index similar to that of substrate 100 and encapsulation substrate ENS. Examples of transparent materials may include various liquid transparent materials. Examples of transparent materials may include epoxy resins, polyurethane acrylates, epoxy acrylates, or silicone-based resins (e.g., bisphenol A type epoxy resins, alicyclic epoxy resins, phenyl silicone resins or rubbers, acrylic epoxy resins, aliphatic polyurethane acrylates, or other materials within the spirit and scope of the disclosure). Alternatively, the transparent material may be a material selected from silicone or silicone oil that does not undergo a phase change in a temperature range of about -40°C to about 100°C and has a volume change rate of less than about 5% (e.g., hexamethyldisiloxane, octamethyltrisiloxane, decamethyltetrasiloxane, dodecylpentasiloxane and polydimethylsiloxane).

[0507] Figures 51A to 51C This is a schematic cross-sectional view of a display device according to an embodiment. Figures 51A to 51C The main descriptions are as follows: the application of the touchscreen layer TSL in... Figure 17 The case of the embodiment.

[0508] Reference Figure 51AThe display panel 10 may include a touch screen layer TSL disposed above the display layer DISL. The touch screen layer TSL may be disposed above the encapsulation component ENCM. The encapsulation component ENCM may be as described above. Figure 49 The thin-film encapsulation layer described is TFEL or above (see reference). Figure 50 The encapsulation substrate ENS is described. In the case where the touchscreen layer TSL is disposed on the encapsulation substrate ENS, the touchscreen layer TSL can be provided or disposed on a separate support substrate, and can then be attached to the encapsulation substrate ENS by an adhesive such as OCA.

[0509] The touchscreen layer TSL may have a structure in which a first touch conductive layer TCL1, a first touch insulating layer TINS1, a second touch conductive layer TCL2, and a second touch insulating layer TINS2 are stacked sequentially. The touchscreen layer TSL may include a touch buffer layer TBF.

[0510] According to an embodiment, the second touch conductive layer TCL2 can be used as a touch electrode for sensing contact or non-contact, and the first touch conductive layer TCL1 can be used as a connecting unit that connects the second touch conductive layer TCL2 in a patterned manner in one direction.

[0511] According to an embodiment, both the first touch conductive layer TCL1 and the second touch conductive layer TCL2 can be used as touch electrodes. For example, the first touch insulating layer TINS1 may include vias that expose the upper surface of the first touch conductive layer TCL1, and the first touch conductive layer TCL1 and the second touch conductive layer TCL2 can be electrically connected to each other via the vias. Thus, by using the first touch conductive layer TCL1 and the second touch conductive layer TCL2, the resistance of the touch electrodes can be reduced, thereby improving the response speed of the touchscreen layer TSL.

[0512] According to an embodiment, the touch electrode may have a mesh structure, allowing light emitted from the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') to be transmitted. Therefore, the first touch conductive layer TCL1 and the second touch conductive layer TCL2 may be arranged or configured not to overlap with the light-emitting areas of the main OLED and the auxiliary OLED'.

[0513] Each of the first touch conductive layer TCL1 and the second touch conductive layer TCL2 may be a single layer or multiple layers comprising a highly conductive material. For example, each of the first touch conductive layer TCL1 and the second touch conductive layer TCL2 may include a transparent conductive layer or may be a single layer or multiple layers comprising a conductive material, including aluminum (Al), copper (Cu), molybdenum (Mo), and / or titanium (Ti). The transparent conductive layer may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). Alternatively, within the spirit and scope of the disclosure, the transparent conductive layer may include a conductive polymer (e.g., poly(3,4)-ethylenedioxythiophene (PEDOT)), metal nanowires, graphene, etc. According to an embodiment, the first touch conductive layer TCL1 may include molybdenum (Mo), and the second touch conductive layer TCL2 may have a Ti / Al / Ti stacked structure.

[0514] Each of the first touch insulating layer TINS1 and the second touch insulating layer TINS2 may comprise an inorganic or organic material. The inorganic material may be at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The organic material may be at least one of acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, and perylene resins.

[0515] exist Figure 49 When the thin-film encapsulation layer TFEL is used as the encapsulation component ENCM, the touch buffer layer TBF can be included between the thin-film encapsulation layer TFEL and the touch screen layer TSL. The touch buffer layer TBF can be directly located on the thin-film encapsulation layer TFEL. The touch buffer layer TBF prevents damage to the thin-film encapsulation layer TFEL and blocks interference signals that may be generated during the driving of the touch screen layer TSL. The touch buffer layer TBF can include inorganic insulating materials, such as silicon oxide (SiO2) and silicon nitride (SiN). x It can be silicon oxynitride (SiON) or silicon oxynitride (SiON), and can be a single layer or multiple layers. Figure 51A In this design, the touchscreen layer TSL does not include any openings or recesses corresponding to the transmissive region TA. Because the insulating layer included in the touchscreen layer TSL typically comprises an inorganic insulating material with high light transmittance, the touchscreen layer TSL can still have sufficient transmittance even without openings or recesses corresponding to the transmissive region TA. Figure 2 Component 40 can send / receive a sufficient amount of light.

[0516] According to the embodiments, refer to Figure 51BThe touchscreen layer TSL may include touch openings TSL_OP corresponding to the transmissive region TA of the component region CA. The touch openings TSL_OP may be a stack of openings in the touch buffer layer TBF corresponding to the transmissive region TA, the first touch insulating layer TINS1, and the second touch insulating layer TINS2. When these openings can be formed by separate processes, the inner surface of the touch openings TSL_OP may not be smooth and may have steps, such as a stepped shape. Because the touchscreen layer TSL includes touch openings TSL_OP corresponding to the transmissive region TA, the light transmittance of the transmissive region TA can be further improved. In contrast, the touchscreen layer TSL may have grooves that do not expose the upper surface of the thin-film encapsulation layer TFEL.

[0517] Reference Figure 51C The touchscreen layer TSL can have a structure in which a first touch conductive layer TCL1 and a first touch insulating layer TINS1 are sequentially stacked. The touchscreen layer TSL may include a touch buffer layer TBF. In other words, the touchscreen layer TSL may not include a second touch conductive layer TCL2. In this case, the first touch conductive layer TCL1 can be used as a self-capacitance type touch electrode. The first touch conductive layer TCL1 can be stacked at least with corresponding portions of the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED).

[0518] Figure 52 This is a plan view of the touch screen layer (TSL) of the display panel according to an embodiment.

[0519] exist Figure 52 In the touchscreen layer TSL, the touch electrodes TE and RE include two types of electrodes, such as driving electrodes TE and sensing electrodes RE. The touchscreen layer TSL can be driven using a mutual capacitance method, in which a driving signal is applied to the driving electrode TE, and the voltage charged in the mutual capacitance is sensed through the sensing electrode RE. For ease of explanation, Figure 52 Only the touch electrodes TE and RE, touch wiring TL and RL, first touch pad TP1 and second touch pad TP2, first protective wiring GL1 to fifth protective wiring GL5, and first ground wire GRL1 to third ground wire GRL3 are shown.

[0520] According to an embodiment, both the portion of the touchscreen layer TSL corresponding to the main display area MDA and the portion of the touchscreen layer TSL corresponding to the component area CA can be driven using a mutual capacitance method. Therefore, touch electrodes TE and RE arranged or disposed in the main display area MDA can be electrically connected to touch electrodes TE and RE arranged or disposed in the component area CA.

[0521] Reference Figure 52The touchscreen layer (TSL) may include a touch sensing area (TSA) for sensing user touches and a touch peripheral area (TPA) surrounding the touch sensing area (TSA). The touch sensing area (TSA) may be overlaid with the display area (DA) of the display layer (DISL), and the touch peripheral area (TPA) may be overlaid with the peripheral area (DPA) of the display layer (DISL).

[0522] The touch electrodes TE and RE can include a first touch electrode TE and a second touch electrode RE. Figure 52 In one embodiment, the first touch electrode TE is a driving electrode TE, and the second touch electrode RE is a sensing electrode RE. Although Figure 52 Each of the driving electrode TE and the sensing electrode RE has a rhomboid planar shape, but the embodiments are not limited thereto.

[0523] Sensing electrodes RE can be arranged or positioned in a first direction (x-direction) and can be electrically connected to each other. Driving electrodes TE can be arranged or positioned in a second direction (y-direction) intersecting the first direction (x-direction) and can be electrically connected to each other. Driving electrodes TE and sensing electrodes RE can be spaced apart from each other. Driving electrodes TE can be arranged or positioned side by side in the second direction (y-direction). At the intersection of sensing electrodes RE and driving electrodes TE, two driving electrodes TE adjacent to each other in the second direction (y-direction) can be electrically connected to each other via a first connecting electrode BE1, and two sensing electrodes RE adjacent to each other in the first direction (x-direction) can be electrically connected to each other via a second connecting electrode BE2.

[0524] Touch wiring TL and RL can be arranged or disposed in the touch peripheral area TPA. Touch wiring TL and RL may include sensing wiring RL electrically connected to sensing electrode RE and first driving wiring TL1 and second driving wiring TL2 electrically connected to driving electrode TE.

[0525] The sensing electrode RE, arranged or disposed at the end of the touch sensing area TSA, can be electrically connected to the sensing wiring RL. For example, as Figure 52 As shown, among the sensing electrodes RE that are electrically connected to each other in the first direction (x direction), the sensing electrode RE arranged or disposed at the right end of the touch sensing area TSA can be electrically connected to the sensing wiring RL. The sensing wiring RL can be electrically connected to the second touch pad TP2.

[0526] A drive electrode TE disposed at one end of the touch sensing area TSA can be electrically connected to a first drive wiring TL1, and a drive electrode TE disposed at the other end of the touch sensing area TSA can be electrically connected to a second drive wiring TL2. For example, as Figure 52As shown, among the drive electrodes TE that are electrically connected to each other in the second direction (y-direction), the drive electrode TE disposed or disposed at the lower end of the touch sensing area TSA can be electrically connected to the first drive wiring TL1, and among the drive electrodes TE that are electrically connected to each other in the second direction (y-direction), the drive electrode TE disposed or disposed at the upper end of the touch sensing area TSA can be electrically connected to the second drive wiring TL2. The second drive wiring TL2 can both traverse the left side of the touch sensing area TSA and extend to the upper side of the touch sensing area TSA, and can be electrically connected to the drive electrodes TE. The first drive wiring TL1 and the second drive wiring TL2 can be electrically connected to the first touch pad TP1.

[0527] The first protective wiring GL1 can be arranged or positioned outside the outermost sensing wiring RL within the sensing wiring RL. The first ground wire GRL1 can be located outside the first protective wiring GL1. For example... Figure 52 As shown, the first protective wiring GL1 can be located to the right of the rightmost sensing wiring RL in the sensing wiring RL, and the first ground wire GRL1 can be located to the right of the first protective wiring GL1.

[0528] The second protective wiring GL2 can be located between the innermost sensing wiring RL in the sensing wiring RL and the rightmost first driving wiring TL1 in the first driving wiring TL1. For example... Figure 52 As shown, the innermost sensing wire RL in the sensing wiring RL can be the leftmost sensing wire RL in the sensing wiring RL. The second protection wiring GL2 can be located between the rightmost first driving wiring TL1 and the second ground wire GRL2 in the first driving wiring TL1.

[0529] The third protective wiring GL3 can be located between the innermost sensing wiring RL and the second ground wire GRL2 within the sensing wiring RL. The second ground wire GRL2 can be connected to the rightmost first touch pad TP1 within the first touch pad TP1 and the leftmost second touch pad TP2 within the second touch pad TP2.

[0530] The fourth protective wiring GL4 can be arranged or set outside the outermost second drive wiring TL2 within the second drive wiring TL2. For example... Figure 52 As shown, the fourth protective wiring GL4 can be arranged or set on the left side of the leftmost second drive wiring TL2 in the second drive wiring TL2.

[0531] The third ground wire GRL3 can be located outside the fourth protective wiring GL4. For example... Figure 52As shown, the fourth protective wiring GL4 can be located to the left of the leftmost and topmost second drive wiring TL2, and the third ground wire GRL3 can be located to the left of the fourth protective wiring GL4.

[0532] The fifth protective wiring GL5 can be arranged or set inside the innermost part of the second drive wiring TL2. For example... Figure 52 As shown, the fifth protective wiring GL5 can be disposed between the rightmost second driving wiring TL2 and the sensing electrode RE in the second driving wiring TL2.

[0533] The first ground wire GRL1, the second ground wire GRL2, and the third ground wire GRL3 can have different or the same static voltage levels. The first protective wiring GL1, the second protective wiring GL2, the third protective wiring GL3, the fourth protective wiring GL4, and the fifth protective wiring GL5 can have different or the same static voltage levels.

[0534] Figure 53 An example of a touch sensor driver unit connected to touch electrodes is shown.

[0535] For ease of explanation, Figure 53 Only the drive electrodes TE, arranged or configured as a column and electrically connected to each other in the second direction (y direction), and the sensing electrodes RE, arranged or configured as a row and electrically connected to each other in the first direction (x direction), are shown.

[0536] Reference Figure 53 The touch sensor driving unit TSDR may include a driving signal output unit TSDR1, a first sensor sensing unit TSDR2, and a first analog-to-digital converter (ADC) TSDR3.

[0537] The drive signal output unit TSDR1 can output a touch drive signal TD to the drive electrode TE via drive wiring TL. The touch drive signal TD may include pulses. The drive signal output unit TSDR1 can output the touch drive signal TD to the drive wiring TL in a preset sequence. For example, the drive signal output unit TSDR1 can be arranged or set in... Figure 52 The touch driving signal TD is sequentially output to the driving electrode TE in the left part of the touch sensing area TSA and to the driving electrode TE in the right part of the touch sensing area TSA.

[0538] The first sensor sensing unit TSDR2 senses the voltage charged in the first mutual capacitance Cm1 via sensing wiring RL electrically connected to the sensing electrode RE. For example... Figure 53As shown, the first mutual capacitance Cm1 can be formed between the driving electrode TE and the sensing electrode RE.

[0539] The first sensor sensing unit TSDR2 may include a first operational amplifier OPA1, a first feedback capacitor Cfb1, and a first reset switch RSW1. The first operational amplifier OPA1 may include a first input terminal (-), a second input terminal (+), and an output terminal (out). The first input terminal (-) of the first operational amplifier OPA1 may be electrically connected to the sensing wiring RL, an initialization voltage VREF may be supplied to the second input terminal (+) of the first operational amplifier OPA1, and the output terminal (out) of the first operational amplifier OPA1 may be electrically connected to a first storage capacitor Cs1. The first storage capacitor Cs1 may be electrically connected between the output terminal (out) of the first operational amplifier OPA1 and ground, and stores the output voltage of the first operational amplifier OPA1. The first feedback capacitor Cfb1 and the first reset switch RSW1 may be connected in parallel between the first input terminal (-) and the output terminal (out) of the first operational amplifier OPA1. The first reset switch RSW1 may control the connection between the two ends of the first feedback capacitor Cfb1. When the first reset switch RSW1 is turned on, and therefore the two ends of the first feedback capacitor Cfb1 can be connected to each other, the first feedback capacitor Cfb1 can be reset.

[0540] The output voltage Vout1 of the first operational amplifier OPA1 can be defined as shown in Equation 1.

[0541] Equation 1

[0542] In Equation 1, “Vout1” represents the output voltage of the first operational amplifier OPA1, “Cm1” represents the first mutual capacitance, “Cfb1” represents the capacitance of the first feedback capacitor Cfb1, and “Vt1” represents the voltage charged into the first mutual capacitance Cm1.

[0543] The first ADC TSDR3 can convert the output voltage Vout1 stored in the first storage capacitor Cs1 into first digital data and can output the first digital data. Therefore, the touch screen layer TSL can determine whether a user touch is present by sensing the voltage charged in the first mutual capacitance Cm1.

[0544] Figure 54 This is an enlarged plan view of the touch sensing area of ​​the touch screen layer according to an embodiment.

[0545] For ease of explanation, Figure 54Only two sensing electrodes RE that are adjacent to each other in the first direction (x direction) and two driving electrodes TE that are adjacent to each other in the second direction (y direction) are shown.

[0546] Each of the driving electrode TE and the sensing electrode RE can have a rectangular planar shape, but the embodiments are not limited to this. For example... Figure 54 As shown, when viewed in a plan view, the driving electrode TE, the sensing electrode RE, the first connecting electrode BE1, and the second connecting electrode BE2 can all have a mesh structure.

[0547] It may include a driving electrode TE, a sensing electrode RE, and a second connecting electrode BE2 as having a mesh pattern. Figure 51A The second touch conductive layer TCL2 may include a first connecting electrode BE1 as having a mesh pattern. Figure 51A The first touch conductive layer TCL1. According to an embodiment, it may include a driving electrode TE, a sensing electrode RE, and a second connection electrode BE2 as having a mesh pattern. Figure 51A The first touch conductive layer TCL1 may include a first connection electrode BE1 as having a mesh pattern. Figure 51A The second touch conductive layer, TCL2.

[0548] The first touch conductive layer TCL1 and the second touch conductive layer TCL2 may include an opening T_OP. The opening T_OP may be superimposed on the sub-pixel P of the display panel 10.

[0549] The sensing electrodes RE can be electrically connected to each other via the second connecting electrode BE2, which can be disposed or disposed on the same layer as the sensing electrodes RE. For example, the sensing electrodes RE can include the same or similar material as the material included in the second connecting electrode BE2, and can be integral with the second connecting electrode BE2.

[0550] The driving electrodes TE can be electrically connected to each other via the first connecting electrode BE1, which is provided or disposed on a layer different from the layer on which the driving electrodes TE can be provided or disposed. The driving electrodes TE can be electrically connected to the first connecting electrode BE1 via contact holes provided or disposed in the first touch insulating layer TINS1.

[0551] Figure 55 This is a plan view of the touch screen layer (TSL) of the display panel according to an embodiment.

[0552] exist Figure 55 In the touchscreen layer TSL, the touch electrode SE includes one type of electrode. The touchscreen layer TSL uses a self-capacitance method, which applies a driving signal to the touch electrode SE and then senses the voltage charged in the self-capacitance of the touch electrode SE, to drive it. For ease of explanation, Figure 55 Only the touch electrode SE, touch wiring SEL, touch pad TP, first ground line GRL1, and second ground line GRL2 are shown.

[0553] According to an embodiment, both the portion of the touchscreen layer TSL corresponding to the main display area MDA and the portion of the touchscreen layer TSL corresponding to the component area CA can be driven using a self-capacitance method.

[0554] Reference Figure 55 The touch electrodes SE can be electrically isolated from each other. The touch electrodes SE can be spaced apart from each other. The touch electrodes SE can be individually electrically connected to the touch wiring SEL. Although in Figure 55 Each touch electrode SE includes a mesh pattern, but a touch electrode SE may not include a mesh pattern.

[0555] Touch wiring SELs can be arranged or disposed in the touch sensing area TSA and the touch peripheral area TPA. Touch wiring SELs can be arranged or disposed in a portion of the touch peripheral area TPA that may be located on one side of the touch sensing area TSA. Touch wiring SELs can be electrically connected to touch electrodes SE. Each touch wiring SEL can be arranged or disposed on one side of the touch electrode SE.

[0556] Ground voltage can be applied to the first ground wire GRL1 and the second ground wire GRL2. The first ground wire GRL1 can be arranged or located in the portion of the touch peripheral area TPA that is located on the upper right side of the touch sensing area TSA. The second ground wire GRL2 can be arranged or located in the portion of the touch peripheral area TPA that is located on the upper left side of the touch sensing area TSA and the portion of the touch peripheral area TPA that is located on the upper side of the touch sensing area TSA. Protective wiring can be arranged or located in the touch peripheral area TPA.

[0557] Figure 56 It is connected to Figure 55 The circuit diagram of the touch sensor driving unit for each touch electrode SE. For ease of illustration, Figure 56 The touch sensor driver unit TSDR connected to the touch electrode SE is shown.

[0558] Reference Figure 56 The touch sensor driving unit TSDR may include a driving signal output unit TSDR1, a first sensor sensing unit TSDR2, and a first ADC TSDR3.

[0559] The drive signal output unit TSDR1 can output the touch drive signal TD to the touch electrode SE via the touch wiring SEL. The touch drive signal TD may include pulses. The drive signal output unit TSDR1 can output the touch drive signal TD to the touch wiring SEL in a preset sequence.

[0560] The first sensor sensing unit TSDR2 senses the voltage charged into the self-capacitor Cs via touch wiring SEL, which is electrically connected to the touch electrode SE. For example... Figure 56 As shown, the self-capacitance Cs can be formed between the touch electrode SE and another electrode superimposed on the touch electrode SE.

[0561] The first sensor sensing unit TSDR2 may include a first operational amplifier OPA1, a first feedback capacitor Cfb1, and a first reset switch RSW1. The first operational amplifier OPA1, the first feedback capacitor Cfb1, and the first reset switch RSW1 of the first sensor sensing unit TSDR2 are as described above. Figure 53 The first operational amplifier OPA1, the first feedback capacitor Cfb1, and the first reset switch RSW1 described are essentially the same. The first storage capacitor Cs1 can be electrically connected between the output terminal (out) of the first operational amplifier OPA1 and ground, and can store the output voltage of the first operational amplifier OPA1.

[0562] The first ADC TSDR3 can convert the output voltage Vout1 stored in the first storage capacitor Cs1 into first digital data and can output the first digital data. Thus, in the self-capacitance method, the self-capacitance Cs of the touch electrode SE is charged according to the touch drive signal TD, and then the voltage charged in the self-capacitance Cs is sensed. Therefore, it is possible to determine whether a user touch is present.

[0563] Figure 57 This is a plan view of the touch screen layer (TSL) of the display panel according to an embodiment.

[0564] Figure 57 This illustrates the cases where a portion or region of the touchscreen layer TSL is driven using the mutual capacitance method and the self-capacitance method. For ease of explanation, Figure 57 Only some or a predetermined number of touch electrodes SE, RE and TE, some or a predetermined number of wiring SEL, TL and RL, and touch pad TP are shown.

[0565] According to an embodiment, the portion of the touchscreen layer TSL corresponding to the main display area MDA can be driven using a mutual capacitance method, and the portion of the touchscreen layer TSL corresponding to the component area CA can be driven using a self-capacitance method.

[0566] The portion of the touchscreen layer TSL corresponding to the main display area MDA may include driving electrodes TE and sensing electrodes RE. The sensing electrodes RE may be arranged or positioned in a first direction (x-direction) and may be electrically connected to each other. The driving electrodes TE may be arranged or positioned in a second direction (y-direction) intersecting the first direction (x-direction) and may be electrically connected to each other. The driving electrodes TE and sensing electrodes RE may be spaced apart from each other. The driving electrodes TE may be arranged or positioned side-by-side in the second direction (y-direction). At the intersection of the sensing electrodes RE and the driving electrodes TE, two adjacent driving electrodes TE in the second direction (y-direction) may be electrically connected to each other via a first connecting electrode BE1, and two adjacent sensing electrodes RE in the first direction (x-direction) may be electrically connected to each other via a second connecting electrode BE2.

[0567] The driving electrode TE and the sensing electrode RE can be electrically connected to the driving wiring TL and sensing wiring RL, respectively, arranged or disposed in the touch peripheral area TPA. The driving wiring TL and sensing wiring RL can be electrically connected to the touch pad TP, and can send signals to or receive signals from the sensor driving unit electrically connected to the touch pad TP. In this case, the presence of a user touch can be determined based on the capacitance change between the driving electrode TE and the sensing electrode RE arranged or disposed in the main display area MDA.

[0568] The component area CA may include touch electrodes SE spaced apart from each other. Each touch electrode SE may be electrically connected to touch wiring SEL. The touch wiring SEL may be electrically connected to touch pad TP and may send signals to or receive signals from sensor driving units connected to touch pad TP. In this case, the presence of a user touch can be determined by sensing the voltage charged in the self-capacitance Cs of the touch electrodes SE arranged or disposed in the component area CA.

[0569] By arranging both driving and sensing electrodes within the component region CA, the presence or absence of a user's touch can be sensed using mutual capacitance. However, because the component region CA may include a transmission region TA, it can be difficult to sense capacitance changes between the driving and sensing electrodes if they are arranged or set at a large distance from each other to ensure the transmittance of the transmission region TA.

[0570] According to the embodiment, because the component region CA employs a structure for sensing the presence or absence of a user's touch based on a self-capacitance method, a minimum number of touch electrodes can be arranged or provided in the transmission region TA. Therefore, the transmittance of the transmission region TA can be improved.

[0571] Figure 58 and Figure 59 This is an enlarged plan view of a corresponding portion of the touchscreen layer TSL according to an embodiment. In detail, Figure 58 and Figure 59 It is a magnified plan view of the component area CA and the main display area MDA surrounding the component area CA. Figure 58 and Figure 59 Only some or a predetermined number of drive electrodes TE and some or a predetermined number of sensing electrodes RE are shown, and more touch electrodes may be omitted.

[0572] Reference Figure 58 and Figure 59 The sensing electrodes RE can be arranged or disposed in the x-direction within the main display area MDA, and the driving electrodes TE can be arranged or disposed in the y-direction within the main display area MDA. The sensing electrodes RE arranged or disposed on the left and right sides of the component area CA can be electrically connected to each other via a second connecting electrode BE2. The second connecting electrode BE2 can extend across the component area CA in the x-direction. The second connecting electrode BE2 can be arranged or disposed on the same layer on which the sensing electrodes RE can be arranged or disposed, and can be integrated with the sensing electrodes RE.

[0573] The drive electrodes TE arranged or disposed on the upper and lower sides of the component region CA can be electrically connected to each other via a first connecting electrode BE1. The first connecting electrode BE1 can extend across the component region CA in the y direction. The first connecting electrode BE1 can be disposed on a different layer than the layer on which the drive electrodes TE can be arranged or disposed, and can be electrically connected to the drive electrodes TE via contact holes CNT.

[0574] The first connecting electrode BE1 and the second connecting electrode BE2 may not be arranged or may be arranged at the center of the transmission region TA to ensure the transmittance of the transmission region TA, and may be biased toward the pixel group PG in the component region CA. According to an embodiment, the first connecting electrode BE1 and the second connecting electrode BE2 may be arranged or arranged to overlap with the wiring (e.g., scan lines and data lines) of the pixel circuit of the component region CA. Alternatively, the first connecting electrode BE1 and the second connecting electrode BE2 may be arranged or arranged to overlap with the bottom metal layer.

[0575] like Figure 58 As shown, the touch electrodes SE corresponding to pixel groups PG can be arranged or disposed in the component area CA. Alternatively, as... Figure 59 As shown, a single touch electrode SE can be arranged or configured to correspond to a pixel group PG.

[0576] Touch electrodes SE can be electrically connected to touch wiring SEL. Touch wiring SEL can be located on a different layer than the layer on which touch electrodes SE can be disposed or arranged. Therefore, touch wiring SEL can be electrically connected to touch electrodes SE via contact holes CNT. Touch wiring SEL can be omitted or located at the center of the transmissive region TA to ensure the transmittance of the transmissive region TA, and can be biased towards pixel group PG in component region CA. According to an embodiment, touch wiring SEL can be arranged or configured to overlap with wiring (e.g., scan lines and data lines) of pixel circuits electrically connected to component region CA. Alternatively, touch wiring SEL can be arranged or configured to overlap with bottom metal layer BML.

[0577] like Figure 59 As shown, when a single touch electrode SE can be arranged or configured to correspond to a pixel group PG, the corresponding areas of the single touch electrode SE corresponding to the pixel group PG can be electrically connected to each other via a third connecting electrode BE3 and a fourth connecting electrode BE4. In other words, a single touch electrode SE may include an opening corresponding to a transmission region TA. The third connecting electrode BE3 can be arranged or disposed on the same layer on which the touch electrode SE can be arranged or disposed, and the fourth connecting electrode BE4 can be arranged or disposed on a different layer than the layer on which the touch electrode SE can be arranged or disposed, and can be electrically connected to the touch electrode SE via a contact hole CNT.

[0578] According to an embodiment, it may include a driving electrode TE, a sensing electrode RE, a touch electrode SE, a second connection electrode BE2, and a third connection electrode BE3 as... Figure 51A The second touch conductive layer TCL2 may include a first connection electrode BE1, a fourth connection electrode BE4, and touch wiring SEL, all extending in the y-direction. Figure 51A The first touch conductive layer TCL1. The driving electrode TE, sensing electrode RE, and touch electrode SE may all have a mesh structure. Alternatively, at least some or a predetermined number of the driving electrode TE, sensing electrode RE, and touch electrode SE may not have a mesh structure and may have a substantially rectangular shape in a plan view. In this case, the driving electrode TE, sensing electrode RE, and touch electrode SE may comprise a transparent conductive material.

[0579] Figures 60 to 62 This is a schematic cross-sectional view of a corresponding portion of the display panel 10 according to an embodiment. Figures 60 to 62 The main description includes a mirror area MA in the main display area MDA of the display panel 10. Figures 60 to 62 In and Figure 17 In the accompanying drawings, the same reference numerals indicate the same elements, so their repeated descriptions are omitted.

[0580] Reference Figure 60 The display panel 10 may include a mirror member MRM, and the main display area MDA of the display panel 10 may include a mirror area MA. The mirror area MA can reflect light incident from the outside of the display panel 10. The display panel 10 can perform a mirror function by including the ...

Claims

1. A display panel, comprising: a substrate including a main display area and a component area, the component area including a transmission area: main display elements in the main display area and disposed on the substrate, the main display elements arranged in a pentile matrix structure; main pixel circuits electrically connected to the main display elements; auxiliary display elements in the component area and disposed on the substrate, the auxiliary display elements arranged in an S-bar structure; and auxiliary pixel circuits electrically connected to the auxiliary display elements; a thin film encapsulation layer disposed over the main display elements and the auxiliary display elements, and including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer; a touch buffer layer disposed directly on the thin film encapsulation layer; and a touch electrode having a mesh structure disposed on the touch buffer layer, wherein the auxiliary pixel circuits are disposed in the component area; and wherein, in a plan view, at least one of light emitting areas of the auxiliary display elements overlaps at least one of the auxiliary pixel circuits. The touch electrode has an aperture in the component area, and wherein the aperture of the touch electrode in the component area does not include any mesh structure of the touch electrode.

2. The display panel of claim 1, wherein, a bottom metal layer in the component area and on the substrate.

3. The display panel of claim 1, further comprising: The bottom metal layer has a bottom aperture.

4. The display panel of claim 3, wherein, The bottom aperture has a circular shape.

5. The display panel of claim 4, wherein, The bottom aperture has a rectangular shape.

6. The display panel of claim 4, wherein, 7.The display panel of claim 1, further comprising: a first main data line electrically connected to the main pixel circuits; and a first auxiliary data line electrically connected to the auxiliary pixel circuits, wherein the first main data line and the first auxiliary data line are disposed in a same column, and ends of the first main data line and the first auxiliary data line are spaced apart from each other with the transmission area disposed between the ends of the first main data line and the first auxiliary data line. 8.The display panel of claim 1, further comprising: a second data line extending from the main display area to the component area; and a data bridge line disposed in the component area, wherein the data bridge line and the second data line are disposed in different layers, and wherein the second data line and the data bridge line are alternated with each other in one direction. The data bridge line overlaps at least part of the second data line in a plan view. 10.The display panel of claim 1, further comprising: an upper layer disposed on a counter electrode disposed in the main display elements and the auxiliary display elements, 9. The display panel of claim 8, wherein, wherein the counter electrode includes a first opening in the transmission area, the upper layer includes a second opening in the transmission area, and inner side surfaces of the first opening and the second opening are coplanar. 11.The display panel of claim 1, further comprising: a weak adhesion layer disposed in the transmission area; and a ​ ​ ​ a counter electrode provided in the main display element and the auxiliary display element, wherein the counter electrode includes a transmission hole or a transmission groove corresponding to the weak adhesion layer.

12. The display panel according to claim 1, further comprising: a weak adhesion layer provided in the transmission region; a functional layer provided in the main display element and the auxiliary display element and including an organic material, the functional layer being continuously provided in the transmission region; and a counter electrode provided in the main display element and the auxiliary display element and including a transmission hole or a transmission groove corresponding to the weak adhesion layer.

13. The display panel according to claim 1, further comprising: a counter electrode provided in the main display element and the auxiliary display element, the counter electrode including: a first thickness at a portion of the counter electrode superimposed with a pixel electrode of the auxiliary display element; and a second thickness at a portion of the counter electrode between the auxiliary display elements, wherein the second thickness is greater than the first thickness.

14. The display panel according to claim 1, wherein: the auxiliary display element includes an auxiliary sub-pixel including an auxiliary sub-pixel emitting a first color, the main display element includes a main sub-pixel including a main sub-pixel emitting the first color, and a size of the auxiliary sub-pixel emitting the first color is greater than a size of the main sub-pixel emitting the first color. at least one of the main pixel circuit and the auxiliary pixel circuit includes:

15. The display panel of claim 1, wherein, a first thin film transistor including an oxide semiconductor layer; and a second thin film transistor including a polycrystalline silicon semiconductor layer.

16. The display panel according to claim 1, further comprising: a wiring provided in the transmission region and including a transparent conductive material.

17. The display panel according to claim 1, further comprising: a first display driving unit driving the main pixel circuit; and a second display driving unit driving the auxiliary pixel circuit, wherein at least one of a driving voltage and a common voltage applied to the main pixel circuit is different from at least one of a driving voltage and a common voltage applied to the auxiliary pixel circuit.

18. The display panel according to claim 1, further comprising: a touch screen layer including the touch electrode, wherein the touch screen layer includes a first touch region superimposed with the main display region and a second touch region superimposed with the component region, the first touch region includes: a sensing electrode provided in a first direction; a driving electrode provided in a second direction intersecting the first direction; a first connection electrode electrically connecting the sensing electrodes to each other; and a second connection electrode electrically connecting the driving electrodes to each other, and the second touch region includes: a second touch electrode provided in the first direction and the second direction and spaced apart from each other.

19. A display panel, comprising: a main display region and a component region, the component region including a transmission region; ​ ​ a substrate including a recess provided in the transmissive region in a depth direction of the substrate, the recess being provided within a layer of the substrate based on removal of a portion of the layer from the substrate in a thickness direction of the substrate corresponding to the depth direction; a main display element in the main display region and provided over the substrate; a main pixel circuit electrically connected to the main display element; a sub-display element provided in the assembly region and over the substrate; and a sub-pixel circuit electrically connected to the sub-display element, wherein the substrate includes a first base layer, a first inorganic barrier layer, a second base layer, and a second inorganic barrier layer stacked in order, wherein the main display element includes a main sub-pixel provided in the main display region, the main sub-pixel having a first pixel arrangement structure, the sub-display element includes a sub-sub-pixel provided in the assembly region, the sub-sub-pixel having a second pixel arrangement structure, and the first pixel arrangement structure is different from the second pixel arrangement structure.

20. The display panel of claim 19, wherein, the second inorganic barrier layer includes a first opening in the transmissive region.

21. The display panel of claim 20, wherein, the second base layer includes a second opening superposed with the first opening, and wherein the recess includes the first opening, the second opening, and an upper surface of the first inorganic barrier layer.

22. The display panel of claim 19, wherein the assembly region includes a first assembly region and a second assembly region, the sub-sub-pixel provided in the first assembly region has a third pixel arrangement structure, and the sub-sub-pixel provided in the second assembly region has a fourth pixel arrangement structure different from the third pixel arrangement structure.

23. The display panel of claim 19, wherein a plurality of pixel groups corresponding to groups of the sub-display element are provided in the assembly region, a plurality of transmissive regions are provided in the assembly region, and the plurality of pixel groups and the plurality of transmissive regions are alternated with each other.

24. The display panel of claim 19, further comprising: an upper layer provided on a counter electrode provided in the main display element and the sub-display element, wherein the counter electrode includes a first opening in the transmissive region, the upper layer includes a second opening in the transmissive region, and an inner side surface of the first opening and an inner side surface of the second opening are coplanar.

25. A display panel, comprising: a main display region and an assembly region, the assembly region including a transmissive region; a substrate; an inorganic layer provided on the substrate and including a recess provided in the transmissive region in a depth direction of the substrate; a main display element provided in the main display region and over the substrate; a main pixel circuit electrically connected to the main display element; a sub-display element provided in the assembly region and over the substrate; a sub-pixel circuit electrically connected to the sub-display element; and a bottom metal layer provided between the substrate and the sub-pixel circuit, wherein the bottom metal layer includes a bottom hole in the transmissive region, and the bottom hole has a polygonal shape with eight or more sides or a circular shape.

26. The display panel of claim 25, further comprising: an upper layer disposed on a counter electrode disposed in the main display element and the auxiliary display element, wherein the counter electrode includes a first opening in the transmissive region, the upper layer includes a second opening in the transmissive region, and inner side surfaces of the first opening and the second opening are coplanar.

27. The display panel of claim 25, wherein the assembly region includes a first assembly region and a second assembly region, an auxiliary sub-pixel disposed in the first assembly region has a third pixel arrangement structure, and an auxiliary sub-pixel disposed in the second assembly region has a fourth pixel arrangement structure different from the third pixel arrangement structure.

28. The display panel of claim 25, wherein a plurality of pixel groups corresponding to groups of the auxiliary display elements are disposed in the assembly region, a plurality of transmissive regions are disposed in the assembly region, and the plurality of pixel groups and the plurality of transmissive regions are alternated with each other.

29. The display panel of claim 25, wherein, the substrate includes a first base layer, a first inorganic barrier layer, a second base layer, and a second inorganic barrier layer sequentially stacked.

30. The display panel of claim 25, further comprising: a counter electrode disposed in the main display element and the auxiliary display element, the counter electrode including: a first thickness at a portion of the counter electrode superimposed with a pixel electrode of the auxiliary display element; and a second thickness at a portion of the counter electrode between the auxiliary display elements, wherein the second thickness is greater than the first thickness.

31. The display panel of claim 25, wherein the auxiliary display element includes an auxiliary sub-pixel, the auxiliary sub-pixel including an auxiliary sub-pixel emitting a first color, the main display element includes a main sub-pixel, the main sub-pixel including a main sub-pixel emitting the first color, and a size of the auxiliary sub-pixel emitting the first color is greater than a size of the main sub-pixel emitting the first color.

32. The display panel of claim 25, wherein, at least one of the main pixel circuit and the auxiliary pixel circuit includes: a first thin film transistor including an oxide semiconductor layer; and a second thin film transistor including a polysilicon semiconductor layer.

33. The display panel of claim 25, further comprising: a wiring disposed in the transmissive region and including a transparent conductive material.

34. The display panel of claim 25, further comprising: a first display driving unit driving the main pixel circuit; and a second display driving unit driving the auxiliary pixel circuit, wherein at least one of a driving voltage and a common voltage applied to the main pixel circuit is different from at least one of a driving voltage and a common voltage applied to the auxiliary pixel circuit.

35. An electronic device, the electronic device comprising: a lower cover having a first assembly region; ​ a display panel disposed on the lower cover, the display panel including a main display area and a second component area, the second component area including a transmission area; a second component in the second component area and disposed between the display panel and the lower cover; a bracket between the display panel and the lower cover; a main circuit board including a main processor; a battery below the bracket; a first component in the first component area and disposed in the lower cover; a main display element disposed in the main display area, the main display element arranged in a first pixel structure; a main pixel circuit electrically connected to the main display element; an auxiliary display element disposed in the second component area, the auxiliary display element arranged in a second pixel structure; an auxiliary pixel circuit electrically connected to the auxiliary display element; a thin film encapsulation layer disposed over the main display element and the auxiliary display element, and including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer; a touch buffer layer directly disposed on the thin film encapsulation layer; a touch electrode having a mesh structure disposed on the touch buffer layer; and a bottom metal layer disposed between the substrate and the auxiliary pixel circuit, wherein the bottom metal layer includes a bottom hole in the transmission area, and the bottom hole is in a polygonal shape having eight or more sides or in a circular shape.

36. The electronic device of claim 35, further comprising: an upper layer disposed on a counter electrode disposed in the main display element and the auxiliary display element, wherein the counter electrode includes a first opening in the transmission area, the upper layer includes a second opening in the transmission area, and an inner side surface of the first opening and an inner side surface of the second opening are coplanar. the first pixel structure is different from the second pixel structure.

37. The electronic device of claim 35, wherein, the first pixel structure is a Pentile matrix structure, and wherein the second pixel structure is an S-bar structure.

38. The electronic device of claim 37, wherein, 39. The electronic device of claim 35, further comprising: a counter electrode disposed in the main display element and the auxiliary display element, the counter electrode including: a first thickness at a portion of the counter electrode that overlaps with a pixel electrode of the auxiliary display element; and a second thickness at a portion of the counter electrode between the auxiliary display elements, wherein the second thickness is greater than the first thickness.

40. The electronic device of claim 35, wherein the auxiliary display element includes auxiliary sub-pixels, the auxiliary sub-pixels including an auxiliary sub-pixel that emits a first color, the main display element includes main sub-pixels, the main sub-pixels including a main sub-pixel that emits the first color, and a size of the auxiliary sub-pixel that emits the first color is greater than a size of the main sub-pixel that emits the first color. at least one of the main pixel circuit and the auxiliary pixel circuit includes: 41.The electronic device of claim 35, wherein, a first thin film transistor including an oxide semiconductor layer; and a second thin film transistor including a polysilicon semiconductor layer. ​ 42. The electronic device of claim 35, further comprising: a wiring disposed in the transmissive region and comprising a transparent conductive material.

43. The electronic device of claim 35, further comprising: a first display driving unit driving the main pixel circuit; and a second display driving unit driving the auxiliary pixel circuit, wherein at least one of a driving voltage and a common voltage applied to the main pixel circuit is different from at least one of a driving voltage and a common voltage applied to the auxiliary pixel circuit.

44. The electronic device of claim 35, further comprising: a weak adhesion layer disposed in the transmissive region; and a counter electrode disposed in the main display element and the auxiliary display element, wherein the counter electrode comprises a transmissive hole or a transmissive groove corresponding to the weak adhesion layer.

45. The electronic device of claim 35, further comprising: a weak adhesion layer disposed in the transmissive region; a functional layer disposed in the main display element and the auxiliary display element and comprising an organic material, the functional layer being continuously disposed in the transmissive region; and a counter electrode disposed in the main display element and the auxiliary display element and comprising a transmissive hole or a transmissive groove corresponding to the weak adhesion layer.

46. The electronic device of claim 35, wherein, the electronic device further comprising: a second data line extending from the main display region to the element region; and a data bridge line disposed in the assembly region, wherein the data bridge line is disposed in a different layer from the second data line, wherein the second data line and the data bridge line are alternated with each other in one direction.

47. The electronic device of claim 46, wherein, the data bridge line overlaps at least a portion of the second data line in a plan view. 48.The electronic device of claim 35, wherein, the touch electrode has a hole in the assembly region, and wherein the hole of the touch electrode in the assembly region does not include any mesh structure of the touch electrode.

49. The electronic device of claim 35, further comprising: a color filter and a black matrix on the touch electrode.

50. The electronic device of claim 35, further comprising: a color filter, a black matrix, and a microlens on the touch electrode. 51.The electronic device of claim 35, wherein, the first assembly is a sensor that senses visible light, and wherein the second assembly is a sensor that senses infrared light.

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