Mechanism to enhance PCIe generation handover

Abstract

Various embodiments include methods and devices for enabling peripheral component interconnect express (PCIe) link configuration by a computing device. Various embodiments may include selecting, by a PCIe device, a predetermined PCIe link speed based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system; and selecting, by the PCIe device, a PCIe link width for one channel for configuring the PCIe link. Various embodiments may include selecting a PCIe link speed level that is lower than a current PCIe link speed in response to a reliability indicator exceeding a reliability threshold of a first PCIe link configuration mode. Various embodiments may include selecting a maximum PCIe link speed for the PCIe link for a second PCIe link configuration mode. Various embodiments may include increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

Description

Related Applications

[0001] This application claims the benefit of priority to U.S. Nonprovisional Application No. 18 / 339,904, filed June 22, 2023; the entirety of which is incorporated by reference herein. BACKGROUND

[0002] The Peripheral Component Interconnect Express (PCIe) standard provides mechanisms to manage bandwidth provided by a PCIe link based on host or endpoint data rate requirements. Bandwidth management of a PCIe link is variably implemented by software at the host or endpoint by changing the PCIe gen / version speed or PCIe link width of the currently operating PCIe link. Software designers are responsible for optimizing PCIe link configuration, including bandwidth management, resulting in PCIe link performance that is specific to each software implementation. Design choices for PCIe link configuration for each software implementation can result in PCIe link reliability issues and / or excess power consumption. SUMMARY

[0003] Various aspects provide methods, including methods for a Peripheral Component Interconnect Express (PCIe) device of a computing device to select a PCIe link configuration, and apparatuses for implementing such methods. Various aspects can include selecting, based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system, a predetermined PCIe link speed as a PCIe link speed for configuring a PCIe link, where the plurality of PCIe link configuration modes includes at least a first PCIe link configuration mode and a second PCIe link configuration mode; and selecting a PCIe link width of one lane for configuring the PCIe link.

[0004] In some aspects, the PCIe link configuration mode is the first PCIe link configuration mode, and various aspects can further include comparing a reliability indicator of a lane of the PCIe link to a reliability threshold, where selecting the predetermined PCIe link speed includes selecting a PCIe link speed level that is lower than a current PCIe link speed of the PCIe link in response to the reliability indicator of the lane of the PCIe link exceeding the reliability threshold.

[0005] In some aspects, the PCIe link configuration mode is the first PCIe link configuration mode, and various aspects can further include comparing a requested bandwidth to a configured bandwidth of the PCIe link; and increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

[0006] Some aspects can also include comparing the PCIe link width to a PCIe link width threshold, wherein increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link can include increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link and the PCIe link width not reaching the PCIe link width threshold.

[0007] In some aspects, the PCIe link configuration mode is a second PCIe link configuration mode, and selecting the predetermined PCIe link speed can include selecting a maximum PCIe link speed of the PCIe link.

[0008] In some aspects, the PCIe link configuration mode is a second PCIe link configuration mode, and the aspects can also include comparing the requested bandwidth to a configured bandwidth of the PCIe link, and increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

[0009] In some aspects, the PCIe link configuration mode is a second PCIe link configuration mode, and the aspects can also include comparing the requested bandwidth to a configured bandwidth of the PCIe link, and decreasing the PCIe link speed in response to the configured bandwidth of the PCIe link exceeding the requested bandwidth.

[0010] Some aspects can also include interpreting a PCIe link configuration mode, modifying a current PCIe link configuration having a current PCIe link width and a current PCIe link speed by increasing the PCIe link width relative to the current PCIe link width in response to a requested bandwidth exceeding a current bandwidth and decreasing the predetermined PCIe link speed relative to the current PCIe link speed in response to the current bandwidth exceeding the requested bandwidth in response to interpreting the PCIe link configuration mode as a first PCIe link configuration mode, and modifying the current PCIe link configuration by increasing the predetermined PCIe link speed relative to the current PCIe link speed in response to the requested bandwidth exceeding the current bandwidth and decreasing the PCIe link width relative to the current PCIe link width in response to the current bandwidth exceeding the requested bandwidth in response to interpreting the PCIe link configuration mode as a second PCIe link configuration mode.

[0011] Further aspects include a computing device including a memory and a Peripheral Component Interconnect Express (PCIe) controller configured to perform operations of any of the methods summarized above. Further aspects include a non-transitory processor-readable storage medium having stored thereon processor-executable software instructions configured to cause a processor to perform operations of any of the methods summarized above. Further aspects include a computing device having means for implementing functionality of any of the methods summarized above. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate example implementations of various implementations and, together with the general description given above and the detailed description given below, serve to explain the features of the claims.

[0013] Figure 1 is a component block diagram illustrating an example computing device suitable for implementing various implementations.

[0014] Figure 2 is a component block diagram illustrating an example peripheral device system suitable for implementing various implementations.

[0015] Figure 3 is a component block diagram illustrating an example Peripheral Component Interconnect Express (PCIe) system suitable for implementing various implementations.

[0016] Figure 4 is a graphical flow diagram illustrating example link training states and state machines in accordance with an implementation.

[0017] Figures 5A to 5C is a process flow diagram illustrating an example method for triggering a PCIe link configuration at a PCIe device in accordance with an implementation.

[0018] Figure 6 is a process flow diagram illustrating an example method for implementing a PCIe link configuration at a PCIe device in accordance with an implementation.

[0019] Figure 7 is a process flow diagram illustrating an example method for implementing a PCIe link configuration for a PCIe link reliability mode at a PCIe device in accordance with an implementation.

[0020] Figure 8 is a process flow diagram illustrating an example method for implementing a PCIe link configuration for a PCIe link power mode at a PCIe device in accordance with an implementation.

[0021] Figure 9is a component block diagram illustrating an example mobile computing device suitable for implementing various embodiments.

[0022] Figure 10 is a component block diagram illustrating an example mobile computing device suitable for implementing various embodiments.

[0023] Figure 11 is a component block diagram illustrating an example server suitable for implementing various embodiments.

[0024] Figures 12A to 12C is a component block diagram illustrating an example embedded vehicle computing system suitable for implementing various embodiments. DETAILED DESCRIPTION

[0025] Various embodiments will be described in detail with reference to the drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes, and are not intended to limit the scope of the claims.

[0026] Various embodiments include methods of implementing Peripheral Component Interconnect Express (PCIe) link configurations and computing devices for implementing such methods. Embodiments can include selecting, by a PCIe device, a predetermined PCIe link speed and selecting, by the PCIe device, a PCIe link width of one lane for configuring a PCIe link. Embodiments can include selecting a predetermined PCIe link speed from a plurality of PCIe link configuration modes of a PCIe system based on a PCIe link configuration mode of the PCIe system. For example, a PCIe link reliability mode can have a PCIe link speed that is one level lower than a current PCIe link speed. As another example, a PCIe link power mode can have a PCIe link speed that is a maximum PCIe link speed of the PCIe link. Embodiments can include adjusting a PCIe link width based on comparing a requested bandwidth to a configured bandwidth of the PCIe link. Embodiments can include adjusting a PCIe link speed based on comparing a requested bandwidth to a configured bandwidth of the PCIe link.

[0027] The term "computing device" is used herein to refer to a stationary computing device, including personal computers, desktop computers, all-in-one computers, workstations, supercomputers, mainframe computers, embedded computers such as those embedded in vehicles and other larger systems, computer systems within or configured for use in vehicles, servers, multimedia computers, and game consoles. The terms "computing device" and "mobile computing device" are used interchangeably herein to refer to any or all of cellular telephones, smartphones, personal or mobile multimedia players, personal data assistants (PDAs), laptop computers, tablet computers, convertible laptop / tablet computers (2-in-l computers), smartbooks, ultrabooks, netbooks, palm-top computers, wireless electronic mail receivers, multimedia Internet enabled cellular telephones, mobile gaming consoles, wireless gaming controllers, and similar personal electronic devices that include a memory and a programmable processor.

[0028] For ease of explanation and clarity, while various embodiments are described in terms of code (e.g., processor-executable instructions), similar applies to any data, e.g., code, program data, or other information stored in memory. The terms "code," "data," and "information" are used interchangeably herein and are not intended to limit the scope of the claims and the specification to the type of code, data, or information used as examples in describing various embodiments.

[0029] The PCIe standard provides mechanisms to manage the bandwidth provided by a PCIe link based on host or endpoint data rate requirements. Bandwidth management of a PCIe link is variably achieved by software at the host or endpoint by changing the PCIe gen / revision speed or PCIe link width of the currently operating PCIe link. Software designers are responsible for optimizing the PCIe link configuration, including bandwidth management, resulting in PCIe link performance specific to each software implementation. Design choices for PCIe link configuration for each software implementation can result in PCIe link reliability issues and / or excess power consumption.

[0030] Design choices for PCIe link configuration for each software implementation typically configure the PCIe link for the desired software implementation. However, design choices for PCIe link configuration can be limited based on lack of information availability or lack of consideration for external factors that affect PCIe link performance under varying environments. Designing a PCIe link configuration for external factors variable implementations adds complexity that is difficult to consider at the design and manufacturing stages.

[0031] For example, the temperature of the environment in which a PCIe link is implemented and the generation speed of the PCIe link can affect the reliability of the PCIe link, where increased temperature and generation speed are associated with decreased reliability. Example applications of PCIe links in which the temperature of the environment and the generation speed of the PCIe link can be factors include automotive applications due to engine heat and cell site modems in hot climates.

[0032] As another example, the operating frequency of a PCIe link can affect the reliability of the PCIe link, where increased operating frequency is associated with decreased reliability. Some examples of decreased reliability include increased bit error rate, electromagnetic interference, loss of the PCIe link, and other channel losses. Computing systems used in or embedded in vehicles (e.g., automobiles) are example applications of PCIe links in which link reliability is important, but link reliability issues have been observed, such as increased bit error rate as operating frequency is increased.

[0033] As another example, in applications in which power availability is limited, the generation speed of a PCIe link and the width of the PCIe link (related to the number of lanes used for the PCIe link) can affect the power consumption of the PCIe link, where increased generation speed and / or link width is associated with increased power consumption. Some examples of applications of PCIe links in which power availability is limited can include computing devices with limited power reserves (such as batteries) or inconsistent power sources (such as renewable energy sources).

[0034] Various embodiments address and overcome the aforementioned issues related to PCIe link configuration by providing real-time, flexible PCIe link configuration via a PCIe device configured to adjust the PCIe link generation speed and / or the PCIe link width based on a PCIe link configuration mode configured for the reliability of the PCIe link and / or the power consumption of the PCIe link. The PCIe link configuration mode can be preset and / or set in real-time at the PCIe device. Based on the PCIe link configuration mode, the PCIe device can adjust the PCIe link generation speed and / or the PCIe link width in response to various factors, thereby preserving or improving PCIe link bandwidth and / or PCIe link reliability.

[0035] The PCIe link configuration mode can be set to prioritize reliability of the PCIe link and / or power consumption of the PCIe link. For example, for a PCIe link application that exposes the PCIe link system to an environment that is not conducive to PCIe link reliability, some embodiments can prioritize reliability and set the PCIe link configuration to a reliability PCIe link configuration mode. PCIe devices informed by the reliability PCIe link configuration mode can be prompted to configure the PCIe link configuration to achieve a higher PCIe link reliability than the current PCIe link configuration. The prompt can be based on a measure of PCIe link reliability compared to a PCIe link reliability threshold, indicating that the reliability of the PCIe link is lower than the PCIe link reliability threshold. The PCIe device can select a predetermined PCIe link speed and / or a predetermined PCIe link width. For example, the PCIe device can select a PCIe link speed that is lower (i.e., slower) than the current PCIe link speed of the current PCIe link configuration. At temperatures that are not conducive to PCIe link reliability, the PCIe link speed can be a contributing factor to the reduction in PCIe link reliability. Reducing the PCIe link speed can mitigate at least some degree of the reduction in PCIe link reliability. The PCIe device can select a PCIe link width of one lane.

[0036] The PCIe device can further adjust the PCIe link width based on a comparison of the PCIe link configuration bandwidth to a requested bandwidth from a host and / or endpoint of the PCIe system. Selecting the PCIe link speed and / or the PCIe link width can result in the PCIe link configuration bandwidth being insufficient to achieve the requested bandwidth. In response to the requested bandwidth exceeding the PCIe link configuration bandwidth, the PCIe device can increase the PCIe link width by increasing the number of lanes used in order to use a lower speed PCIe link speed to achieve the requested bandwidth.

[0037] As another example, for PCIe link applications with limited availability of power, the PCIe link configuration mode can be set to a power PCIe link configuration mode. PCIe devices notified by the power PCIe link configuration mode can be prompted to configure the PCIe link configuration to achieve lower PCIe link power consumption than the current PCIe link configuration. The PCIe devices can select a predetermined PCIe link speed and / or a predetermined PCIe link width. For example, the PCIe devices can select a maximum PCIe link speed and / or the PCIe devices can select a PCIe link width of one lane. The combination of the PCIe link speed and the PCIe link width can be a contributing factor to the reduction of PCIe link power consumption in power-limited applications. The combination of a larger PCIe link speed and a lower PCIe link width can consume less power while enabling the PCIe link to provide the same bandwidth compared to the combination of a lower PCIe link speed and a larger PCIe link width.

[0038] The PCIe devices can further adjust the PCIe link width and / or the PCIe link speed based on a comparison of the PCIe link configuration bandwidth to the requested bandwidth from the host and / or endpoints of the PCIe system. The selected PCIe link speed and / or the PCIe link width can result in the PCIe link configuration bandwidth not achieving the requested bandwidth. To achieve the requested bandwidth using the selected PCIe link speed, the PCIe devices can increase the PCIe link width by increasing the number of lanes used in response to the requested bandwidth exceeding the PCIe link configuration bandwidth. As another example, to achieve the requested bandwidth using the selected PCIe link width, the PCIe devices can decrease the PCIe link speed in response to the PCIe link configuration bandwidth exceeding the requested bandwidth.

[0039] Various embodiments improve the operation and reliability of computing systems using PCIe links by configuring the links with effective link width and link speed combinations to accommodate changes in operating frequency and temperature. Various embodiments can be particularly useful in computing systems embedded in vehicles, such as automobiles, due to the high temperatures and harsh environmental conditions often experienced by vehicle systems.

[0040] Figure 1 A system including a computing device 10 suitable for use with various embodiments is illustrated. Reference is made to Figure 1, the computing device 10 can include a system on a chip (SoC) 12 having a processor 14, a memory 16, a communication interface 18, a storage memory interface 20, a memory interface 34, a power manager 28, a clock controller 30, a peripheral interface 38, and an interconnect 32. The computing device 10 can also include a communication component 22 such as a wired or wireless modem, a storage memory 24, an antenna 26 for establishing wireless communication links, a memory 36, and a peripheral 40. The processor 14 can include any of a variety of processing devices, e.g., multiple processor cores.

[0041] The term “system on a chip” (SoC) is used herein to refer to a collection of interconnected electronic circuits, typically but not exclusively including a processing device, a memory, and a communication interface. The processing device can include a wide variety of different types of processors 14 and processor cores, such as general-purpose processors, central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), security processing units (SPUs), subsystem processors for particular components of the computing device such as image processors for cameras subsystems or display processors for displays, auxiliary processors, single-core processors, multi-core processors, controllers, and microcontrollers. The processing device can also embody other hardware and combinations of hardware, such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), other programmable logic devices, discrete gate logic components, transistor logic components, performance monitoring hardware, watchdog hardware, and time references. The integrated circuit can be configured such that the components of the integrated circuit reside on a single piece of semiconductor material, such as silicon.

[0042] The SoC 12 can include one or more processors 14. The computing device 10 can include more than one SoC 12, thereby increasing the number of processors 14 and processor cores. The computing device 10 can also include processors 14 that are not associated with a SoC 12. The processors 14 can each be configured for a particular purpose that can be the same as or different from other processors 14 of the computing device 10. One or more of the processors 14 and processor cores of the same or different configuration can be grouped together. A group of processors 14 or processor cores can be referred to as a multi-processor cluster.

[0043] The memory 16, 36 of the SoC 12 can be volatile or non-volatile memory configured to store data and processor-executable code for access by the processor 14. The computing device 10 and / or the SoC 12 can include one or more memories 16, 36 configured for various purposes. The one or more memories 16, 36 can include volatile memory, such as random access memory (RAM) or main memory, including static RAM (SRAM) and / or dynamic RAM (DRAM) or cache memory. These memories 16, 36 can be configured to temporarily hold a limited amount of data received from data sensors or subsystems, data and / or processor-executable code instructions requested from the non-volatile memory 16, 24 to be loaded from the non-volatile memory 16, 24 to the memory 16 at a future access expected based on a variety of factors, and / or intermediate processing data and / or processor-executable code instructions generated by the processor 14 and temporarily stored for future fast access without storage in the non-volatile memory 16, 24. The memory interface 34 and the memory 36 can work in unison to allow the computing device 10 to load and retrieve data and processor-executable code on the memory 36.

[0044] The storage memory interface 20 and the storage memory 24 can work in unison to allow the computing device 10 to store data and processor-executable code on non-volatile storage media. The storage memory 24 can be configured very similarly to embodiments of the memory 16, where the storage memory 24 can store data or processor-executable code for access by one or more of the processors in the processor 14. The non-volatile storage memory 24 can retain information after the computing device 10 has been powered off. When re-powered and the computing device 10 is restarted, the information stored on the storage memory 24 can be available to the computing device 10. The storage memory interface 20 can control access to the storage memory 24 and allow the processor 14 to read data from and write data to the storage memory 24.

[0045] The power manager 28 can be configured to control the power state of one or more power rails (not shown) for power delivery to components of the SoC 12. In some embodiments, the power manager 28 can be configured to control the amount of power provided to components of the SoC 12. For example, the power manager 28 can be configured to control connections between components of the SoC 12 and power rails. As another example, the power manager 28 can be configured to control the amount of power on power rails connected to components of the SoC 12. The power manager 28 can be configured as a power management integrated circuit (power management IC or PMIC).

[0046] Clock controller 30 can be configured to control clock signals sent to components of SoC 12. For example, clock controller 30 can gate components of SoC 12 by disconnecting the components of SoC 12 from clock signals, and can ungate components of SoC 12 by connecting the components of SoC 12 to clock signals.

[0047] Peripheral interface 38 can enable components of SoC 12, such as processor 14 and / or memory 16, to communicate with peripheral devices 40. Peripheral interface 38 can provide and manage physical and logical connections between components of SoC 12 and peripheral devices 40. Peripheral interface 38 can also manage communication between components of SoC 12 and peripheral devices 40, such as by directing and / or allowing communication between transmitters and receiver pairs of components of SoC 12 and peripheral devices 40. Communication can include the transmission of memory access commands, addresses, data, interrupt signals, status signals, etc. Peripheral devices 40 can be any components of computing device 10 that are separate from SoC 12, such as processors, memories, subsystems, etc. In some embodiments, peripheral interface 38 can include a PCIe root complex, and can enable PCIe protocol communication between components of SoC 12 and peripheral devices 40.

[0048] Interconnect 32 can be a communication structure, such as a communication bus, configured to communicatively connect components of SoC 12. Interconnect 32 can transmit signals between components of SoC 12. In some embodiments, interconnect 32 can be configured to control signals between components of SoC 12 by controlling timing and / or transmission paths of the signals.

[0049] Some or all of components of computing device 10 and / or SoC 12 can be arranged differently and / or can be combined, while still providing the functionality of various embodiments. Computing device 10 can not be limited to one of each component, and multiple instances of each component can be included in various configurations of computing devices.

[0050] Figure 2 An example peripheral device system 200 suitable for implementing various embodiments is illustrated. Referring to Figure 1 and Figure 2 Peripheral device system 200 can include any number and combination of peripheral devices 202, 204, 206, 208, 210, 212, 214 (e.g., peripheral devices 40) communicatively connected to one or more peripheral interfaces 38 of SoC 12.

[0051] The peripheral device interface 38 can communicatively connect one or more peripheral devices 202, 204, 206, 208, 210, 212, 214 with one or more components of the SoC 12 as described, including processors (e.g., the processor 14) and / or memory (e.g., the memory 16). The processors can include any number and combination of CPUs, GPUs, DSPs, APUs, SPUs, etc. The memory can include any number and combination of system cache, random access memory (RAM), registers, flash memory, EPROM, etc. Communicatively connecting the peripheral devices 202, 204, 206, 208, 210, 212, 214 with the components of the SoC 12 via the peripheral device interface 38 can enable the transmission of communications between the peripheral devices 202, 204, 206, 208, 210, 212, 214 and the components of the SoC 12. Such communications can include memory access commands, addresses, data, interrupt signals, status signals, etc. In some examples, the peripheral device interface 38 can be a PCIe root complex of a PCIe system and enable PCIe protocol communications between the components of the SoC 12 and the one or more peripheral devices 202, 204, 206, 208, 210, 212, 214.

[0052] In some embodiments, the peripheral device can include one or more processors 210 (e.g., processors 14), such as processors or processor clusters separate from the SoC 12. For example, the processors 210 can include any number and combination of CPUs, GPUs, DSPs, APUs, SPUs, etc. In some embodiments, the peripheral device can include various peripheral subsystems (e.g., communication components 22, storage memory 24, memory 36, peripherals 40) having one or more processors (e.g., processors 14) and memories (e.g., memories 16, 24, 36), such as camera subsystem 202, video subsystem 204, display subsystem 206, audio subsystem 208, memory subsystem 212, and wireless communication subsystem 214. The processors can include any number and combination of CPUs, GPUs, DSPs, APUs, SPUs, etc. The memories can include any number and combination of caches, RAM, registers, flash, EPROM, etc. In some embodiments, the peripherals 202, 204, 206, 208, 210, 212, 214 can include any number and combination of sensors, receivers, transmitters, controllers, and dedicated memories, such as caches and memory registers configured for controlling and enabling the functionality of the peripherals 202, 204, 206, 208, 210, 212, 214. In some examples, the peripherals 202, 204, 206, 208, 210, 212, 214 can include and / or be connected to a PCIe system endpoint (not shown) configured to enable PCIe protocol communication between the peripherals 202, 204, 206, 208, 210, 212, 214 and one or more components of the SoC 12.

[0053] To Figure 2 The illustrated descriptions of the peripherals 202, 204, 206, 208, 210, 212, 214 are intended to be examples only and are in no way limiting. Several of the components of the illustrated example peripherals 202, 204, 206, 208, 210, 212, 214 can be variably configured, combined, and separated. Several of the peripherals 202, 204, 206, 208, 210, 212, 214 can be included in greater or fewer numbers, and can be positioned and connected differently than illustrated.

[0054] Figure 3 An example PCIe system 300 suitable for implementing various embodiments is illustrated. Reference is made to Figures 1 to 3The PCIe system 300 may include at least one pair of PCIe-enabled devices 302, 330 of a computing device (e.g., computing device 10) configured to communicate with each other via the PCIe protocol. The pair of PCIe-enabled devices 302, 330 may include, for example, a PCIe peripheral device 302 (e.g., peripheral devices 40, 202, 204, 206, 208, 210, 212, 214) and a SoC 330 (e.g., SoC 12). The PCIe peripheral device 302 may be any peripheral device of the computing device configured to communicate with another component of the computing device via the PCIe protocol.

[0055] The pair of PCIe-enabled devices 302, 330 may include any combination of hardware, software, firmware, etc., configured to enable communication between the pair of PCIe-enabled devices 302, 330 via the PCIe protocol. For example, each pair of PCIe-enabled devices 302, 330 may include PCIe controllers 304a, 304b configured to communicate via the PCIe protocol (e.g., Figure 1 and Figure 2 The PCIe controller 304a may be a peripheral component interconnect device (PCIe endpoint) and / or part of such a PCIe interconnect device, and the PCIe controller 304 may be a PCIe device as a PCIe root complex and / or part of such a PCIe device. In some embodiments, each PCIe-enabled device 302, 330 may include processors 318, 332 (e.g., processors 14, 210) and memories 320, 334 (e.g., memories 16, 24, 36 and / or memory subsystem 212). In some embodiments, the PCIe controllers 304a, 304b may be communicatively connected to the processors 318, 332 and / or memories 320, 334 of the associated PCIe-enabled devices 302, 330.

[0056] PCIe controllers 304a, 304b can include control modules 306a, 306b, input / output (I / O) control modules 316a, 316b, and PCIe configuration registers 314a, 314b. In some embodiments, PCIe controllers 304a, 304b can also include power modules 310a, 310b and / or clock modules 312a, 312b. Control modules 306a, 306b can be configured to control various functions of PCIe controllers 304a, 304b. Such functions can include enumeration of PCIe-enabled devices 302, 330 in PCIe system 300, PCIe link 340 configuration between PCIe-enabled devices 302, 330, communication functions for communicating between PCIe controllers 304a, 304b and PCIe-enabled devices 302, 330 associated therewith and between PCIe-enabled devices 302, 330 and processors 318, 332 and / or memories 320, 334 of PCIe-enabled devices 302, 330, etc.

[0057] PCIe configuration registers 314a, 314b can be configured to store data related to configuration of PCIe link 340. For example, PCIe configuration registers 314a, 314b can store data detailing configuration of PCIe link 340, including PCIe link configuration mode data. In some examples, PCIe link configuration mode data can indicate that PCIe controllers 304a, 304b implement a PCIe link reliability mode, a PCIe link power mode, a PCIe link default mode, or no PCIe link mode, etc.

[0058] The PCIe controllers 304a, 304b implementing the PCIe link reliability mode can implement a PCIe link configuration process configured to configure the PCIe link 340 with increased reliability as compared to a current PCIe link configuration that can include a default PCIe link configuration. The PCIe controllers 304a, 304b implementing the PCIe link power mode can implement a PCIe link configuration process configured to configure the PCIe 304 with low power consumption as compared to a current PCIe link configuration that can include a default PCIe link configuration. The PCIe controllers 304a, 304b implementing the PCIe link default mode or no PCIe link mode can implement a PCIe link configuration process configured to configure the PCIe link 340 according to default PCIe link configuration parameters and / or PCIe link configuration parameters provided by software executing at the PCIe-enabled devices 302, 330. The PCIe controllers 304a, 304b can retrieve the PCIe link configuration mode data from the PCIe configuration registers 314a, 314b and implement the PCIe link configuration process according to the corresponding PCIe link configuration mode implemented by the PCIe controllers 304a, 304b in the configuration state ("Config") of the link training state and state machine (LTSSM) 400 (referenced in Figures 1 to 4 , Figure 4

[0059] The PCIe link configuration mode data can be loaded into the PCIe configuration registers 314a, 314b at startup and / or runtime. The PCIe link configuration mode data can be loaded into the PCIe configuration registers 314a, 314b at startup by a developer / manufacturer that selected the PCIe link configuration mode data based on the PCIe system 300 application. For example, the developer / manufacturer can set the PCIe link configuration mode data to indicate the PCIe link reliability mode for a PCIe system application exposed to an environment that is adverse to PCIe link reliability due to temperature. As another example, the developer / manufacturer can set the PCIe link configuration mode data to indicate the PCIe link power mode for a PCIe system application with limited and / or inconsistent power sources. The PCIe link configuration mode data can be loaded into the PCIe configuration registers 314a, 314b at runtime by software executing at the PCIe-enabled devices 302, 330.

[0060] ​The I / O control modules 316a, 316b can be configured to generate, transmit, and / or receive PCIe communications and signals via the PCIe link 340 established between the pair of PCIe-enabled devices 302, 330. The communications and signals can include memory access commands, addresses, data, interrupt signals, status signals, and the like generated, transmitted, and / or received by the I / O control modules 316a, 316b. For example, the I / O control modules 316a, 316b can generate, transmit, and / or receive instructions via the communications and / or signals to set the PCIe link configuration mode data at the PCIe configuration registers 314a, 314b. For example, the instructions can be for the PCIe controllers 304a, 304b to set the PCIe link configuration mode data at the PCIe configuration registers 314a, 314b to indicate a PCIe link reliability mode, a PCIe link power mode, a PCIe link default mode, or no PCIe link mode, among others.

[0061] The clock modules 312a, 312b can provide clock signals to the PCIe controllers 304a, 304b to control the timing of the execution of the functions of the PCIe controllers 304a, 304b. In some embodiments, the clock modules 312a, 312b can provide clock signals to the control modules 306a, 306b and / or the I / O control modules 316a, 316b. In some embodiments, the clock modules 312a, 312b can be integral with the PCIe controllers 304a, 304b. In some embodiments, the clock modules 312a, 312b can be separate from the PCIe controllers 304a, 304b, such as integral with the PCIe-enabled devices 302, 330 with which the PCIe controllers 304a, 304b are associated.

[0062] The power modules 310a, 310b can be configured to provide power to and / or regulate the power for the PCIe controllers 304a, 304b to control the ability to execute the functions of the PCIe controllers 304a, 304b. In some embodiments, the power modules 310a, 310b can provide power to and / or regulate the power for the control modules 306a, 306b, the I / O control modules 316a, 316b, and / or the PCIe configuration registers 314a, 314b. In some embodiments, the power modules 310a, 310b can be integral with the PCIe controllers 304a, 304b. In some embodiments, the power modules 310a, 310b can be separate from the PCIe controllers 304a, 304b, such as integral with the PCIe-enabled devices 302, 330 with which the PCIe controllers 304a, 304b are associated.

[0063] Figure 4 An example LTSSM 400 is illustrated in accordance with an embodiment. Reference is made toFigures 1 to 4 The LTSSM 400 illustrates the operational states of a PCIe controller (e.g., Figure 1 and Figure 2 the peripheral interface 38 in Figure 3 the PCIe controllers 304a, 304b in Figure 4 The example state machine in the LTSSM illustrated in

[0064] The LTSSM 400 can be implemented by a PCIe controller in a regular manner except for the configuration state 402 (“Configuration”). In other words, the PCIe controller can implement any of the detection state 404 (“Detection”), the polarization state 406 (“Polarization”), the normal operation state 408 (“LO”), the standby state 410 (“LOs”), the low power states 412, 414 (“LI”, “L2”), the recovery state 416 (“Recovery”), the loopback state 418 (“Loopback”), the hot reset state 420 (“Hot Reset”), and the disable state 422 (“Disable”) that perform known operations. The PCIe controller can also transition between any of the states of the LTSSM 400 under known transition conditions.

[0065] In the configuration state 402, the PCIe controller can retrieve PCIe link configuration mode data from a PCIe configuration (e.g., Figure 3 the PCIe configuration registers 314a, 314b in

[0066] Figures 5A to 5C Example methods 500, 510, 520 for triggering PCIe link configuration of a PCIe device are illustrated in accordance with various embodiments. Reference is made to Figures 1 to 5CMethods 500, 510, 520 can be implemented in a computing device (e.g., computing device 10, SoC 12, PCIe-enabled device 330), in hardware (e.g., peripheral device interface 38, PCIe controller 304b, control module 306b, I / O control module 316b, LTSSM 400), in software (e.g., control module 306b, I / O control module 316b, LTSSM 400) executed by a processor (e.g., processor 14, 210, PCIe controller 304b), or in a combination of software-configured processor and dedicated hardware, such as a PCIe system (e.g., PCIe system 300) that includes other separate components, such as various memories / caches (e.g., memories 16, 24, 36, memory sub-system 212, PCIe configuration registers 314b, memory 334) and various memory / cache controllers. To cover alternative configurations implemented in various embodiments, the hardware that implements methods 500, 510, 520 is referred to herein as a “PCIe control device.”

[0067] Referring to Figure 5A At block 502, the PCIe control device can load a PCIe configuration mode of a PCIe system (e.g., PCIe system 300) at boot-up of a SoC (e.g., SoC 12, PCIe-enabled device 330) having a PCIe device (e.g., peripheral device interface 38, PCIe controller 304b). At boot-up, part of the boot-up process can include instructions to load PCIe link configuration mode data from a memory (e.g., memories 16, 24, 36, 334) to PCIe configuration registers (e.g., PCIe configuration registers 314b). The PCIe link configuration mode data can be configured to indicate that the PCIe control device implements a PCIe link reliability mode, a PCIe link power mode, a PCIe link default mode, or no PCIe link mode, etc. In some embodiments, the PCIe control device that loads the PCIe configuration mode of the PCIe system at boot-up of the SoC having the PCIe device at block 502 can include a peripheral device interface (e.g., peripheral device interface 38), a PCIe controller (PCIe controller 304b), a control module (control module 306b), and / or an I / O control module (I / O control module 316b).

[0068] In block 504, the PCIe control device can interpret a PCIe configuration mode of the PCIe system. During a link training process, such as implemented by the LTSSM (LTSSM 400) in a configuration state, the PCIe control device can be configured to retrieve PCIe link configuration mode data from PCIe configuration registers. Based on one or more values of the PCIe link configuration mode data, the PCIe control device can be configured to interpret whether to implement one of a PCIe link reliability mode, a PCIe link power mode, a PCIe link default mode, or a no PCIe link mode, among others. In some embodiments, the PCIe control device that interprets the PCIe configuration mode of the PCIe system in block 504 can include a peripheral interface, a PCIe controller, and / or a control module.

[0069] In block 506, the PCIe control device can configure the PCIe link (e.g., PCIe link 340) based on the PCIe configuration mode of the PCIe system. The PCIe control device that implements the PCIe link reliability mode can implement a PCIe link configuration process configured to configure the PCIe link with increased reliability as compared to a current PCIe link configuration that can include a default PCIe link configuration. The PCIe control device that implements the PCIe link power mode can implement a PCIe link configuration process configured to configure the PCIe link with low power consumption as compared to a current PCIe link configuration that can include a default PCIe link configuration. In some embodiments, the PCIe control device that configures the PCIe link based on the PCIe configuration mode of the PCIe system in block 506 can include a peripheral interface, a PCIe controller, and / or a control module. The PCIe control device that implements the PCIe link default mode or the no PCIe link mode can implement a PCIe link configuration process configured to configure the PCIe link according to default PCIe link configuration parameters and / or PCIe link configuration parameters provided by software executing at a processing device (e.g., SoC 12, peripheral 40, 202, 204, 206, 208, 210, 212, 214, PCIe-enabled device 302, 330).

[0070] Referring to Figure 6 Configuring the PCIe link based on the PCIe link reliability mode and / or the PCIe link power mode is further described with respect to method 600. Referring to Figure 7Configuring the PCIe link based on the PCIe link reliability mode is further described with respect to method 700. Configuring the PCIe link configuration based on the PCIe link reliability mode can include modifying a current PCIe link configuration having a current PCIe link width and a current PCIe link speed. The current PCIe link configuration can be modified by increasing the PCIe link width relative to the current PCIe link width in response to the requested bandwidth exceeding the current bandwidth. The current PCIe link configuration can be modified by decreasing the predetermined PCIe link speed relative to the current PCIe link speed in response to the current bandwidth exceeding the requested bandwidth.

[0071] Referring to Figure 8 Configuring the PCIe link based on the PCIe link power mode is further described with respect to method 800. Configuring the PCIe link configuration based on the PCIe link power mode can include modifying a current PCIe link configuration having a current PCIe link width and a current PCIe link speed. The current PCIe link configuration can be modified by increasing the predetermined PCIe link speed relative to the current PCIe link speed in response to the requested bandwidth exceeding the current bandwidth. The current PCIe link configuration can be modified by decreasing the PCIe link width relative to the current PCIe link width in response to the current bandwidth exceeding the requested bandwidth.

[0072] Referring to Figure 5B In block 512, the PCIe control device can receive a bandwidth request from software executing at a processing device (e.g., SoC 12, peripheral device 40, 202, 204, 206, 208, 210, 212, 214, PCIe-enabled device 302, 330). The requested bandwidth from the software can be the bandwidth required to send information between a PCIe endpoint and a PCIe host (e.g., SoC 12, peripheral device 40, 202, 204, 206, 208, 210, 212, 214, PCIe-enabled device 302, 330) in a PCIe system (e.g., PCIe system 300) for the software to perform a function within given parameters. In some embodiments, the PCIe control device receiving the bandwidth request from software executing at a processing device in block 512 can include a peripheral device interface (e.g., peripheral device interface 38), a PCIe controller (PCIe controller 304b), a control module (control module 306b), and / or an I / O control module (I / O control module 316b).

[0073] In block 504, the PCIe control device can interpret a PCIe configuration mode of the PCIe system. Block 504 can be performed by a PCIe control device (e.g., PCIe control device 306a, 306b) and / or a control module (e.g., control module 306a, 306b). Block 504 can be performed in response to a request for a PCIe configuration mode of the PCIe system (e.g., PCIe system 300). The PCIe configuration mode can be a PCIe link reliability mode and / or a PCIe link power mode. Figure 5AThe same as described for the similarly numbered block is implemented in a similar manner. In some embodiments, the PCIe control device that interprets the PCIe configuration mode of the PCIe system in block 504 can include a peripheral device interface, a PCIe controller, and / or a control module.

[0074] In block 506, the PCIe control device can configure the PCIe link (e.g., PCIe link 340) based on the PCIe configuration mode of the PCIe system. Block 506 can be implemented in a similar manner as described with reference to Figure 5A The same as described for the similarly numbered block is implemented in a similar manner. In some embodiments, the PCIe control device that configures the PCIe link based on the PCIe configuration mode of the PCIe system in block 506 can include a peripheral device interface, a PCIe controller, and / or a control module.

[0075] Referring to Figure 5C In block 522, the PCIe control device can set the PCIe link configuration mode for the PCIe system (e.g., PCIe system 300) according to instructions received from software executing at a processing device (e.g., SoC 12, peripheral device 40, 202, 204, 206, 208, 210, 212, 214, PCIe-enabled device 302, 330). The instructions can include an indication of the PCIe link configuration mode, such as PCIe link configuration mode data. The PCIe control device can store the PCIe link configuration mode data to a PCIe configuration register (e.g., PCIe configuration register 314b). The PCIe link configuration mode data can be configured to indicate that the PCIe control device implement a PCIe link reliability mode, a PCIe link power mode, a PCIe link default mode, or no PCIe link mode, among others. In some embodiments, the PCIe control device that sets the PCIe link configuration mode for the PCIe system according to instructions received from software executing at a processing device in block 522 can include a peripheral device interface (e.g., peripheral device interface 38), a PCIe controller (PCIe controller 304b), a control module (control module 306b), and / or an I / O control module (I / O control module 316b).

[0076] In block 504, the PCIe control device can interpret the PCIe configuration mode of the PCIe system. Block 504 can be implemented in a similar manner as described with reference to Figure 5A The same as described for the similarly numbered block is implemented in a similar manner. In some embodiments, the PCIe control device that interprets the PCIe configuration mode of the PCIe system in block 504 can include a peripheral device interface, a PCIe controller, and / or a control module.

[0077] In block 506, the PCIe control device can configure the PCIe link (e.g., PCIe link 340) based on a PCIe configuration mode of the PCIe system. The operations in block 506 can be implemented in a manner similar to those described with respect to Figure 5A Those described with respect to like numbered blocks are implemented in a similar manner. In some embodiments, the PCIe control device that configures the PCIe link based on a PCIe configuration mode of the PCIe system in block 506 can include a peripheral interface, a PCIe controller, and / or a control module.

[0078] Figure 6 An example method 600 for implementing PCIe link configuration at a PCIe device is illustrated in accordance with an embodiment. With reference to Figures 1 to 6 The method 600 can be implemented in a computing device (e.g., computing device 10, SoC 12, PCIe-enabled device 330), in hardware (e.g., peripheral interface 38, PCIe controller 304b, control module 306b, I / O control module 316b, LTSSM 400), in software (e.g., control module 306b, I / O control module 316b, LTSSM 400) executed by a processor (e.g., processor 14, 210, PCIe controller 304b), or in a combination of software-configured processor and special-purpose hardware, such as a PCIe system (e.g., PCIe system 300) that includes other separate components, such as various memories / caches (e.g., memories 16, 24, 36, memory sub-system 212, PCIe configuration registers 314b, memory 334) and various memory / cache controllers. To cover alternative configurations implemented in various embodiments, the hardware that implements the method 600 is referred to herein as a “PCIe control device.”

[0079] In block 602, the PCIe control device can select a predetermined PCIe link speed. The predetermined PCIe link speed can be used by the PCIe control device to configure a PCIe link (e.g., PCIe link 340) between a PCIe host (e.g., SoC 12, 330) and a PCIe endpoint (e.g., peripheral 40, 202, 204, 206, 208, 210, 212, 214, 302) of a PCIe system (e.g., PCIe system 300). In some embodiments, with reference to Figure 7 The selection of a predetermined PCIe link speed for a PCIe link reliability mode is further described with respect to the operations of block 706 of the method 700. In some embodiments, with reference to Figure 8The operation of block 802 of method 800 is further described selecting a predetermined PCIe link speed for a PCIe link power mode. In some embodiments, the PCIe control device that selects the predetermined PCIe link speed in block 602 can include a peripheral interface (e.g., peripheral interface 38), a PCIe controller (PCIe controller 304b), and / or a control module (control module 306b).

[0080] In block 604, the PCIe control device can select a one-lane PCIe link width for the PCIe link. The one-lane PCIe link width can be used by the PCIe control device to configure the PCIe link between a PCIe host and a PCIe endpoint of the PCIe system. The one-lane PCIe link width can control the number of lanes for the PCIe link. In some embodiments, selecting a one-lane PCIe link width for a PCIe link power mode can refer to Figure 7 The operation of block 708 of method 700 is implemented. In some embodiments, selecting a one-lane PCIe link width for a PCIe link power mode can refer to Figure 8 The operation of block 804 of method 800 is implemented. In some embodiments, the PCIe control device that selects a one-lane PCIe link width in block 604 can include a peripheral interface, a PCIe controller, and / or a control module.

[0081] Figure 7 An example method 700 for PCIe link configuration to implement a PCIe link reliability mode at a PCIe device is illustrated in accordance with an embodiment. Referring to Figures 1 to 7 Method 700 can be implemented in a computing device (e.g., computing device 10, SoC 12, PCIe-enabled device 330), in hardware (e.g., peripheral interface 38, PCIe controller 304b, control module 306b, I / O control module 316b, LTSSM 400), in software (e.g., control module 306b, I / O control module 316b, LTSSM 400) executed by a processor (e.g., processor 14, 210, PCIe controller 304b), or in a combination of software-configured processor and special-purpose hardware, such as a PCIe system (e.g., PCIe system 300) that includes other separate components, such as various memories / caches (e.g., memories 16, 24, 36, memory sub-system 212, PCIe configuration registers 314b, memory 334) and various memory / cache controllers. To cover alternative configurations implemented in various embodiments, the hardware that implements method 700 is referred to herein as a “PCIe control device.”

[0082] In block 702, the PCIe control device can compare the reliability of a lane of a PCIe link (e.g., PCIe link 340) to a reliability threshold. The reliability of the lane of the PCIe link and the reliability threshold can include various indicators and / or metrics of reliability. For example, the reliability can be represented by a bit error rate, an amount of electromagnetic interference, and / or other channel impairments. In some embodiments, the indicators and / or metrics of reliability can be provided to the PCIe controller, such as by software executing at a processing device (e.g., SoC 12, peripheral device 40, 202, 204, 206, 208, 210, 212, 214, PCIe-enabled device 302, 330). In some embodiments, the indicators and / or metrics of reliability can be generated by the PCIe controller. The PCIe controller can be preconfigured with the reliability threshold. For example, the reliability threshold can be stored to and retrieved from a PCIe configuration register (e.g., PCIe configuration register 314b). In some embodiments, the PCIe control device that compares the reliability of the lane of the PCIe link to the reliability threshold in block 702 can include the peripheral device interface (e.g., peripheral device interface 38), the PCIe controller (PCIe controller 304b), and / or the control module (control module 306b).

[0083] In determination block 704, the PCIe control device can determine whether the reliability of the lane of the PCIe link exceeds the reliability threshold. The PCIe device can use the result of the comparison of the reliability of the lane of the PCIe link to the reliability threshold to determine whether the reliability of the lane of the PCIe link exceeds the reliability threshold. In some embodiments, the PCIe control device that determines whether the reliability of the lane of the PCIe link exceeds the reliability threshold in determination block 704 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0084] In response to determining that the reliability of the lane of the PCIe link does not exceed the reliability threshold (i.e., block 704 = "No"), the PCIe control device can compare the reliability of the lane of the PCIe link to the reliability threshold in block 702. In some embodiments, the PCIe control device that compares the reliability of the lane of the PCIe link to the reliability threshold in block 702 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0085] In response to determining that the reliability of the lanes of the PCIe link exceeds the reliability threshold (i.e., block 704 =“Yes”), the PCIe control device can select a PCIe link speed that is lower than the current PCIe link speed in block 706. The PCIe link can be configured using various PCIe generation / version link speeds. Although the PCIe link speed used for the current PCIe link configuration is not the lowest PCIe link speed, the PCIe control device can select a PCIe link speed that is lower than the current PCIe link speed. For example, the PCIe control device can select a PCIe link speed that is one level lower than the current PCIe link speed. The selected PCIe link speed can be used by the PCIe control device to configure the PCIe link between a PCIe host (e.g., SoC 12, 330) and a PCIe endpoint (e.g., peripheral 40, 202, 204, 206, 208, 210, 212, 214, 302) of the PCIe system (e.g., PCIe system 300). In some embodiments, the PCIe control device that selects the PCIe link speed that is lower than the current PCIe link speed in block 706 can include the peripheral interface, the PCIe controller, and / or the control module.

[0086] In block 708, the PCIe control device can select a PCIe link width of one lane. The PCIe link width can be used by the PCIe control device to configure the PCIe link between the PCIe host and the PCIe endpoint of the PCIe system. The PCIe link width can control the number of lanes used for the PCIe link. In some embodiments, the PCIe control device that selects the PCIe link width of one lane in block 708 can include the peripheral interface, the PCIe controller, and / or the control module.

[0087] In block 710, the PCIe control device can compare the requested bandwidth to a configuration bandwidth. The PCIe control device can receive a bandwidth request from software executing at a processing device (e.g., SoC 12, peripheral device 40, 202, 204, 206, 208, 210, 212, 214, PCIe-enabled device 302, 330). The requested bandwidth from the software can be the bandwidth required to send information between a PCIe endpoint and a PCIe host in the PCIe system for the software to perform a function within given parameters. The configuration bandwidth can be the bandwidth implemented by the PCIe link configuration based on the PCIe link speed and the PCIe link width. The PCIe control device can determine the configuration bandwidth based on a PCIe link configuration such as from a lookup table associated with the PCIe link speed and the PCIe link width. The PCIe controller can be preconfigured with configuration bandwidths associated with different combinations of PCIe link speeds and PCIe link widths. In some embodiments, the PCIe control device that compares the requested bandwidth to the configuration bandwidth in block 710 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0088] In determination block 712, the PCIe control device can determine whether the requested bandwidth exceeds the configuration bandwidth. The PCIe device can use the results of the comparison of the requested bandwidth to the configuration bandwidth to determine whether the requested bandwidth exceeds the configuration bandwidth. In some embodiments, the PCIe control device that determines whether the requested bandwidth exceeds the configuration bandwidth in determination block 712 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0089] In response to determining that the requested bandwidth does not exceed the configuration bandwidth (i.e., block 712 = "No"), the PCIe control device can compare the requested bandwidth to the configuration bandwidth in block 710. In some embodiments, the PCIe control device that compares the requested bandwidth to the configuration bandwidth in block 710 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0090] In response to determining that the requested bandwidth exceeds the configured bandwidth (i.e., block 712 =“Yes”), the PCIe control device can compare the PCIe link width to a PCIe link width threshold in optional block 714. PCIe links can be configured using various PCIe link widths of different numbers of lanes. There can be a limit on the number of lanes that can be used for a PCIe link, which can be represented as a PCIe link width threshold. The PCIe configuration device can be preconfigured with the PCIe link width threshold. The PCIe control device can compare the PCIe link width (which can be represented as a number of lanes) to the PCIe link width threshold (which can be represented as a maximum number of lanes). In some embodiments, the PCIe control device that compares the PCIe link width to the PCIe link width threshold in optional block 714 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0091] In optional determination block 716, the PCIe control device can determine whether the PCIe link width does not meet the PCIe link width threshold. The PCIe device can use the result of the comparison of the PCIe link width to the PCIe link width threshold to determine whether the PCIe link width does not meet the PCIe link width threshold. In some embodiments, the PCIe control device that determines whether the PCIe link width does not meet the PCIe link width threshold in optional determination block 716 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0092] In response to determining that the PCIe link width meets the PCIe link width threshold (i.e., optional block 716 =“No”), the PCIe control device can compare the reliability of the lanes of the PCIe link to a reliability threshold in block 702. In some embodiments, the PCIe control device that compares the reliability of the lanes of the PCIe link to the reliability threshold in block 702 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0093] In response to determining that the requested bandwidth exceeds the configured bandwidth (i.e., block 712 =“Yes”); or in response to determining that the PCIe link width does not meet the PCIe link width threshold (i.e., optional block 716 =“Yes”), the PCIe control device can increase the PCIe link width in block 718. The PCIe control device can increase the PCIe link width by increasing the number of lanes used for the PCIe link. For example, the PCIe control device can increase the number of lanes used for the PCIe link by one lane. The PCIe link width can be used by the PCIe control device to configure the PCIe link between the PCIe host and the PCIe endpoint of the PCIe system. In some embodiments, the PCIe control device that increases the PCIe link width in block 718 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0094] After increasing the PCIe link width in block 718, the PCIe control device can compare the requested bandwidth to the configured bandwidth in block 710. In some embodiments, the PCIe control device comparing the requested bandwidth to the configured bandwidth in block 710 can include the peripheral interface, the PCIe controller, and / or the control module.

[0095] Figure 8 An example method 800 for implementing a PCIe link configuration for a PCIe link power mode at a PCIe device is illustrated in accordance with an embodiment. Referring to Figures 1 to 8 , the method 800 can be implemented in a computing device (e.g., computing device 10, SoC 12, PCIe-enabled device 330), in hardware (e.g., peripheral interface 38, PCIe controller 304b, control module 306b, I / O control module 316b, LTSSM 400), in software (e.g., control module 306b, I / O control module 316b, LTSSM 400) executed by a processor (e.g., processor 14, 210, PCIe controller 304b), or in a combination of software-configured processors and special-purpose hardware, such as a PCIe system (e.g., PCIe system 300) that includes other separate components, such as various memories / caches (e.g., memories 16, 24, 36, memory sub-system 212, PCIe configuration registers 314b, memory 334) and various memory / cache controllers. To cover alternative configurations implemented in various embodiments, the hardware that implements the method 800 is referred to herein as a “PCIe control device.”

[0096] In block 802, a PCIe control device can select a maximum PCIe link speed for a PCIe link (PCIe link 304). PCIe links can be configured using various PCIe generation / version link speeds. There can be limitations on how fast a PCIe link speed can be set based on which PCIe generation / version link speeds are enabled. The PCIe control device can preconfigure the PCIe link with the maximum PCIe link speed and can select the maximum PCIe link speed for the PCIe link. The selected PCIe link speed can be used by the PCIe control device to configure the PCIe link between a PCIe host (e.g., SoC 12, 330) and a PCIe endpoint (e.g., peripheral 40, 202, 204, 206, 208, 210, 212, 214, 302) of a PCIe system (e.g., PCIe system 300). In some embodiments, the PCIe control device that selects the maximum PCIe link speed for the PCIe link in block 802 can include a peripheral interface (e.g., peripheral interface 38), a PCIe controller (PCIe controller 304b), and / or a control module (control module 306b).

[0097] In block 804, the PCIe control device can select a one-lane PCIe link width. The PCIe link width can be used by the PCIe control device to configure the PCIe link between the PCIe host and the PCIe endpoint of the PCIe system. The PCIe link width can control the number of lanes used for the PCIe link. In some embodiments, the PCIe control device that selects the one-lane PCIe link width in block 804 can include the peripheral interface, the PCIe controller, and / or the control module.

[0098] In block 806, the PCIe control device can compare the requested bandwidth to the configured bandwidth. The PCIe control device can receive a bandwidth request from software executing at a processing device (e.g., SoC 12, peripheral device 40, 202, 204, 206, 208, 210, 212, 214, PCIe-enabled device 302, 330). The requested bandwidth from the software can be the bandwidth required to send information between a PCIe endpoint and a PCIe host in the PCIe system for the software to perform a function within given parameters. The configured bandwidth can be the bandwidth implemented by the PCIe link configuration based on the PCIe link speed and the PCIe link width. The PCIe control device can determine the configured bandwidth based on a PCIe link configuration such as from a lookup table associated with the PCIe link speed and the PCIe link width. The PCIe controller can be preconfigured with configured bandwidths associated with different combinations of PCIe link speeds and PCIe link widths. In some embodiments, the PCIe control device that compares the requested bandwidth to the configured bandwidth in block 806 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0099] In determination block 808, the PCIe control device can determine whether the requested bandwidth exceeds the configured bandwidth. The PCIe device can use the results of the comparison of the requested bandwidth to the configured bandwidth to determine whether the requested bandwidth exceeds the configured bandwidth. In some embodiments, the PCIe control device that determines whether the requested bandwidth exceeds the configured bandwidth in determination block 808 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0100] In response to determining that the requested bandwidth does not exceed the configured bandwidth (i.e., block 808 = "No"), the PCIe control device can determine in determination block whether the configured bandwidth exceeds the requested bandwidth. The PCIe device can use the results of the comparison of the requested bandwidth to the configured bandwidth to determine whether the configured bandwidth exceeds the requested bandwidth. In some embodiments, the PCIe control device that determines whether the configured bandwidth exceeds the requested bandwidth in determination block 810 can include the peripheral device interface, the PCIe controller, and / or the control module.

[0101] In response to determining that the configured bandwidth exceeds the requested bandwidth (i.e., block 810 = "Yes"), the PCIe control device can reduce the PCIe link speed in block 812. Although the PCIe link speed configured for the PCIe link is not the lowest PCIe link speed, the PCIe control device can reduce the PCIe link speed to a lower PCIe link speed. For example, the PCIe control device can reduce the PCIe link speed to one level lower than the PCIe link speed. The PCIe link speed can be used by the PCIe control device to configure the PCIe link between the PCIe host and the PCIe endpoint. In some embodiments, the PCIe control device that reduces the PCIe link speed in block 812 can include the peripheral interface, the PCIe controller, and / or the control module.

[0102] After reducing the PCIe link speed in block 812, the PCIe control device can compare the requested bandwidth to the configured bandwidth in block 806. In some embodiments, the PCIe control device that compares the requested bandwidth to the configured bandwidth in block 806 can include the peripheral interface, the PCIe controller, and / or the control module.

[0103] In response to determining that the requested bandwidth exceeds the configured bandwidth (i.e., block 808 = "Yes"), the PCIe control device can increase the PCIe link width in block 814. The PCIe control device can increase the PCIe link width by increasing the number of lanes used for the PCIe link. For example, the PCIe control device can increase the number of lanes used for the PCIe link by one lane. The PCIe link width can be used by the PCIe control device to configure the PCIe link between the PCIe host and the PCIe endpoint of the PCIe system. In some embodiments, the PCIe control device that increases the PCIe link width in block 814 can include the peripheral interface, the PCIe controller, and / or the control module.

[0104] After increasing the PCIe link width in block 814, the PCIe control device can compare the requested bandwidth to the configured bandwidth in block 806. In some embodiments, the PCIe control device that compares the requested bandwidth to the configured bandwidth in block 806 can include the peripheral interface, the PCIe controller, and / or the control module.

[0105] Systems in accordance with various embodiments, including but not limited to the embodiments described above with reference to Figures 1 to 8 Systems in accordance with various embodiments, including but not limited to the embodiments described above with reference to Figure 9The mobile computing device 900 can include a processor 902 coupled to a touch screen controller 904 and internal memory 906. The processor 902 can be one or more multi-core integrated circuits designated for general or specific processing tasks. The internal memory 906 can be volatile or non-volatile memory and can also be secure and / or encrypted memory, or unsecure and / or unencrypted memory, or any combination thereof. Examples of memory types that can be utilized include, but are not limited to, DDR, low power DDR (LPDDR), graphics DDR (GDDR), WIDEIO, RAM, static RAM (SRAM), dynamic RAM (DRAM), parameter RAM (P-RAM), resistive RAM (R-RAM), magnetoresistive RAM (M-RAM), spin-torque MRAM (STT-RAM), and embedded DRAM. The touch screen controller 904 and the processor 902 can also be coupled to a touch screen panel 912, such as a resistive-sensing touch screen, a capacitive-sensing touch screen, an infrared-sensing touch screen, etc. Additionally, the display of the mobile computing device 900 need not have touch screen capabilities.

[0106] The mobile computing device 900 can have one or more wireless radio transceivers 908 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio) and antennas 910 for transmitting and receiving communications coupled to each other and / or to the processor 902. The transceivers 908 and antennas 910 can be used with the circuitry mentioned above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 900 can include a cellular network wireless modem chip 916 that enables communication via a cellular network and is coupled to the processor.

[0107] The mobile computing device 900 can include a peripheral device connection interface 918 coupled to the processor 902. The peripheral device connection interface 918 can be configured to accept one type of connection individually, or can be configured to accept various types of physical and communication connections that are common or proprietary, such as universal serial bus (USB), Firewire, Thunderbolt, or PCIe. The peripheral device connection interface 918 can also be coupled to a similarly configured peripheral device connection port (not shown).

[0108] The mobile computing device 900 can also include a speaker 914 for providing audio outputs. The mobile computing device 900 can also include a housing 920 that houses all or some of the components described herein, constructed of a plastic, metal, or a combination of materials. The mobile computing device 900 can include a power supply 922, such as a disposable or rechargeable battery, coupled to the processor 902. The rechargeable battery can also be coupled to the peripheral device connection port to receive a charging current from an external source of the mobile computing device 900. The mobile computing device 900 can also include physical buttons 924 for receiving user inputs. The mobile computing device 900 can also include a power button 926 for turning the mobile computing device 900 on and off.

[0109] Systems in accordance with various embodiments, including but not limited to the embodiments described above, reference Figures 1 to 8 The systems described in accordance with various embodiments can be implemented in a wide variety of computing systems including laptop computers 1000, examples of which are illustrated in Figure 10 Many laptop computers include a touchpad touch surface 1017 that functions as a pointing device for the computer and thus can receive gestures similar to drag, scroll, and tap gestures implemented on computing devices equipped with touch screen displays and as described above. The laptop computer 1000 will typically include a processor 1002 coupled to volatile memory 1012 and a large capacity nonvolatile memory, such as a disk drive 1013 of Flash memory. Additionally, the computer 1000 can have one or more antenna 1008 for the transmission and reception of electromagnetic radiation that can be connected to a wireless data link and / or to a cellular telephone transceiver 1016 coupled to the processor 1002. The computer 1000 can also include a floppy disk drive 1014 and a compact disk (CD) drive 1015 coupled to the processor 1002. In a notebook configuration, the computer housing includes a touchpad 1017, a keyboard 1018 and a display 1019 all coupled to the processor 1002. Other configurations of the computing device can include a computer mouse or track ball as is known to those skilled in the art coupled to the processor (e.g., via a USB input), which can also be used in conjunction with various embodiments.

[0110] Systems in accordance with various embodiments, including but not limited to the embodiments described above, reference Figures 1 to 8 Systems in accordance with various embodiments can also be implemented in stationary computing systems, such as any of a variety of commercially available servers. Figure 11 An example server 1100 is illustrated. Such a server 1100 typically includes one or more multi-core processor assemblies 1101 coupled to volatile memory 1102 and large capacity nonvolatile memory, such as a disk drive 1104. As is well known in the art, the server 1100 typically includes an operating system 1105 which can be any one of a variety of commercially available operating systems. The server 1100 also includes a Figure 11As illustrated, multi-core processor assemblies 1101 can be added to the server 1100 by plugging them into the assembly's rack. The server 1100 can also include a floppy disk drive, compact disk (CD) or digital versatile disk (DVD) disk drive 1106 coupled to the processor 1101. The server 1100 can also include a network access port 1103 coupled to the multi-core processor assembly 1101 for establishing network interface connections with a network 1105, such as a local area network coupled to other broadcast system computers and servers, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, 5G, or any other type of cellular data network).

[0111] Methods in accordance with various embodiments, including but not limited to the embodiments described above with reference to Figures 1 to 8 The methods and apparatuses for implementing such methods in accordance with various embodiments, including but not limited to the embodiments described above with reference to Figures 12A to 12C The methods and apparatuses for implementing such methods in accordance with various embodiments, including but not limited to the embodiments described above with reference to

[0112] The plurality of sensors 1242-1270 disposed in or on the vehicle can be used for various purposes, such as navigation, collision avoidance, etc., as well as to provide sensor data about objects and people in or on the vehicle. The sensors 1242-1270 can include one or more of a variety of sensors capable of detecting a variety of information useful for navigation and collision avoidance. Each of the sensors 1242-1270 can be in wired or wireless communication with the control unit 1240, as well as with each other. In particular, the sensors can include one or more cameras 1258, 1260 or other optical or photoelectric sensors. The sensors can also include other types of object detection and ranging sensors, such as exterior sensors 1268, 1270, IR sensors, and ultrasonic sensors. The sensors can also include tire pressure sensors 1254, 1256, humidity sensors, temperature sensors, satellite geolocation sensors 1242, control input sensors 1245, accelerometers 1244, vibration sensors, gyroscopes, gravitometers, impact sensors 1266, force gauges, stress gauges, strain sensors, fluid sensors, chemical sensors, gas content analyzers, pH sensors, radiation sensors, Geiger counters, neutron detectors, biological material sensors, microphones 1262, 1264, occupancy sensors 1246, 1248, 1250, 1252, proximity sensors, and other sensors.

[0113] The vehicle control unit 1240 can include one or more processors configured with processor-executable instructions to perform navigation and collision avoidance operations using information received from the various sensors, particularly the cameras 1258, 1260. In some embodiments, the control unit 1240 can supplement processing of camera images with distances and relative positioning (e.g., relative bearing angles) that can be obtained from the exterior sensors 1268, 1270. The control unit 1240 can be further configured to use information about other vehicles determined using various embodiments to control steering, braking, and speed of the vehicle. The vehicle control unit 1240 can include one or more processors configured with processor-executable instructions to receive information from the sensors 1242-1270 and perform operations using such information, as further described herein. In various embodiments, the vehicle control unit 1240 can comprise, be a component of, or be in communication with V2X on-board equipment of the vehicle.

[0114] Figure 12Cis a component block diagram of an embedded vehicle computing system 1200 including components and support systems suitable for implementing various embodiments. The embedded vehicle computing system 1200 can include a control unit 1240, which can include various circuits and devices for controlling operation of the vehicle. The control unit 1240 can include a processor 1240a (such as a CPU, AI processor, etc.), a memory 1240b, an input module 1240c, an output module 1240d, and a radio module 1240e. The control unit 1240 can be coupled to and configured to control driving control components 1272a, navigation components 1272b, and one or more sensors 1272c of the embedded vehicle computing system 1200. The control unit 1240 can be in communication with V2X on-board equipment 1240f. The processor 1240a can be configured with processor-executable instructions to control maneuvering, navigation, and / or other operations of the vehicle, including operations of various embodiments, including gathering and analyzing real-world vehicle operation data gathered from the sensors 1272c. The processor 1240a can be coupled to the memory 1240b. The V2X on-board equipment 1240f can include one or more processors 1240g configured with processor-executable instructions to perform various operations of various embodiments, including communicating real-world vehicle operation data gathered from the sensors 1272c between the embedded vehicle computing system 1240 and computing devices on wireless communication devices 1212 and / or communication networks (e.g., core network 1232) via the radio module 1240e.

[0115] The radio module 1240e can be configured for wireless communication. The radio module 1240e can exchange signals (e.g., command signals for controlling maneuvering, signals from navigation facilities, data signals, etc.) with network transceivers (e.g., base stations 1210) via the communication links 1222 and can provide these signals to the processors 1240a, 1240g and / or the navigation unit 1272b. In some embodiments, the radio module 1240e can enable the embedded vehicle computing system 1200 to communicate with the wireless communication devices 1212 over the wireless communication links 1224. The wireless communication links 1224 can be bi-directional or unidirectional communication links and can use one or more communication protocols.

[0116] The input module 1240c can receive sensor data from one or more vehicle sensors 1272c as well as electronic signals from other components, including the drive control components 1272a and the navigation components 1272b. The output module 1240d can communicate with or activate various components of the embedded vehicle computing system 1200, including the drive control components 1272a, the navigation components 1272b, and the sensors 1272c.

[0117] The control unit 1240 can be coupled to the drive control components 1272a to control the physical elements of the vehicle related to the vehicle's locomotion and navigation, such as the engine, motor, throttle, steering elements, flight control elements, braking or deceleration elements, and the like. The drive control components 1272a can also include components that control other devices of the vehicle, including interior environmental controls (e.g., air conditioning and heating), exterior and / or interior lighting, interior and / or exterior information displays (which can include a display screen or other device for displaying information), safety devices (e.g., haptic devices, audible alarms, etc.), and other similar devices.

[0118] The control unit 1240 can be coupled to the navigation components 1272b and can receive data from the navigation components 1272b and be configured to use such data to determine the current location and orientation of the vehicle, as well as an appropriate route toward a destination. The navigation components 1272b can include or be coupled to a global navigation satellite system (GNSS) receiver system (e.g., one or more global positioning system (GPS) receivers) that enables the embedded vehicle computing system 1200 to determine its current positioning using GNSS signals. Alternatively or additionally, the navigation components 1272b can include radio navigation receivers for receiving navigation beacons or other signals from radio nodes such as Wi-Fi access points, cellular network sites, radio stations, remote computing devices, other vehicles, etc. Through control of the drive control elements 1272a, the processor 1240a can control the vehicle to navigate and locomote. The processors 1240a, 1240g, and / or the navigation components 1272b can be configured to communicate with network elements, such as servers in a communications network (e.g., a core network 1232), via wireless communication links 1222, 1226 to receive commands to control locomotion, to receive data useful in navigation, to provide real-time positioning reports, etc.

[0119] The control unit 1240 can be coupled to one or more sensors 1272c. The sensors 1272c can include the sensors 1242-1270 as described and can be configured to provide a variety of data to the processors 1240a, 1240g.

[0120] Although the control unit 1240 is described as including separate components, in some embodiments, some or all of the components (e.g., the processor 1240a, the memory 1240b, the input module 1240c, the output module 1240d, and the radio module 1240e) can be integrated in a single device or module, such as a SoC processing device. Such a SoC processing device can be configured for use in a vehicle and configured, such as with processor-executable instructions executed in the processor 1240a, to perform operations of navigation and collision avoidance.

[0121] Specific implementation examples are described in the following paragraphs. While some of the following specific implementation examples are described in terms of example systems, devices, or methods, additional example implementations can include: example systems or devices discussed in the following paragraphs implemented as methods that perform operations of the example systems or devices, example systems, devices, or methods discussed in the following paragraphs implemented by a computing device that includes a processing device configured with processing device-executable instructions and / or a PCIe controller to perform operations of the example systems, devices, or methods; a PCIe controller configured to perform operations of the example systems, devices, or methods; a computing device configured to perform operations of the example systems, devices, or methods; example systems, devices, or methods discussed in the following paragraphs implemented by a computing device that includes means for performing the functions of the example systems, devices, or methods; and example systems, devices, or methods discussed in the following paragraphs implemented as non-transitory processor-readable storage media having stored thereon processor-executable instructions configured to cause a processor of a computing device to perform operations of the example systems, devices, or methods.

[0122] Example 1. A method performed by a Peripheral Component Interconnect Express (PCIe) device of a computing device for selecting a link configuration, the method comprising: selecting, as a PCIe link speed for configuring a PCIe link, a predetermined PCIe link speed based on a PCIe link configuration mode of the PCIe system of a plurality of PCIe link configuration modes of a PCIe system, wherein the plurality of PCIe link configuration modes includes at least a first PCIe link configuration mode and a second PCIe link configuration mode; and selecting a PCIe link width of one lane for configuring the PCIe link.

[0123] Embodiment 2. The method of embodiment 1, wherein the PCIe link configuration mode is the first PCIe link configuration mode, the method further comprising: comparing a reliability indicator of a lane of the PCIe link to a reliability threshold, wherein selecting the predetermined PCIe link speed comprises: selecting a PCIe link speed level lower than a current PCIe link speed of the PCIe link in response to the reliability indicator of the lane of the PCIe link exceeding the reliability threshold.

[0124] Embodiment 3. The method of any of embodiments 1 or 2, wherein the PCIe link configuration mode is the first PCIe link configuration mode, the method further comprising: comparing a requested bandwidth to a configured bandwidth of the PCIe link; and increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

[0125] Embodiment 4. The method of embodiment 3, the method further comprising: comparing the PCIe link width to a PCIe link width threshold, wherein increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link comprises: increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link and the PCIe link width not reaching the PCIe link width threshold.

[0126] Embodiment 5. The method of any of embodiments 1 to 4, wherein the PCIe link configuration mode is the second PCIe link configuration mode, and wherein selecting the predetermined PCIe link speed comprises selecting a maximum PCIe link speed of the PCIe link.

[0127] Embodiment 6. The method of any of embodiments 1 to 5, wherein the PCIe link configuration mode is the second PCIe link configuration mode, the method further comprising: comparing a requested bandwidth to a configured bandwidth of the PCIe link; and increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

[0128] Embodiment 7. The method of any of embodiments 1 to 6, wherein the PCIe link configuration mode is the second PCIe link configuration mode, the method further comprising: comparing a requested bandwidth to a configured bandwidth of the PCIe link; and decreasing the PCIe link speed in response to the configured bandwidth of the PCIe link exceeding the requested bandwidth.

[0129] Example 8. The method of any of Examples 1-8, further comprising: interpreting the PCIe link configuration mode; in response to interpreting the PCIe link configuration mode as the first PCIe link configuration mode, modifying a current PCIe link configuration having the current PCIe link width and the current PCIe link speed by: increasing the PCIe link width relative to a current PCIe link width in response to a requested bandwidth exceeding a current bandwidth and decreasing the predetermined PCIe link speed relative to a current PCIe link speed in response to the current bandwidth exceeding the requested bandwidth; and in response to interpreting the PCIe link configuration mode as the second PCIe link configuration mode, modifying the current PCIe link configuration by: increasing the predetermined PCIe link speed relative to the current PCIe link speed in response to the requested bandwidth exceeding the current bandwidth and decreasing the PCIe link width relative to the current PCIe link width in response to the current bandwidth exceeding the requested bandwidth.

[0130] Computer program code or "program code" for execution on a programmable processor for performing operations of various embodiments can be written in a high level of programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, a structured query language (e.g., Transact-SQL), Perl, or in various other programming languages. Program code stored on a computer readable storage medium as used in this application can refer to machine language that is understood by a processor, such as object code.

[0131] The foregoing method descriptions and the process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As will be appreciated by one of skill in the art the order of operations in the foregoing embodiments can be performed in any order. Words such as "thereafter," "then," "next," etc. are not intended to limit the order of the operations; these words are simply used to guide the reader through the description of the methods. Furthermore, any reference to claim elements in the singular, for example, using the articles "one," "the," or "said," is not

[0132] The various illustrative logical blocks, modules, circuits, and algorithm operations described in connection with the various embodiments can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0133] The hardware used to implement various illustrative logics, logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field

[0134] In one or more embodiments, the functions described can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operations of a method or algorithm disclosed herein can be implemented in a processor-executable software module which can reside on a non-transitory computer- readable or processor-readable storage medium. Non-transitory computer-readable or processor-readable storage media can be any storage media that can be accessed by a computer or a processor. By way of example but not limitation, such non-transitory computer-readable or processor-readable media can include RAM, ROM, EEPROM, FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, includes compact discs (CD), laser discs, optical discs, digital versatile discs (DVD), floppy disks and Blu-ray discs where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of non-transitory computer- readable and processor-readable media. Additionally, the operations of methods or algorithms can reside in one or any combination of the above memory or storage devices, which can be located in a computing device or a processor. The processor-executable software module can reside in RAM memory, on a non-transitory computer-readable memory or storage medium, or in a processor or controller until executed. Above and below, the wide term "non-transitory computer- readable medium" is expressly defined herein to exclude only the following: modulated data signals superimposed to a carrier and a media layer, such as any semiconductor memory, whether volatile or non-volatile, or any storage media implemented with magnetic, optical, or other retrieving means.

[0135] The above description of disclosed embodiments is provided to enable any person skilled in the art to practice or use the claims. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein but is to be accorded the widest scope consistent with the claims and the principles and novel features disclosed herein.

Claims

1. A method performed by a Peripheral Component Interconnect Express (PCIe) device of a computing device to select a PCIe link configuration, the method comprising: selecting a predetermined PCIe link speed as a PCIe link speed for configuring a PCIe link based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system, wherein the plurality of PCIe link configuration modes includes at least a first PCIe link configuration mode and a second PCIe link configuration mode; and selecting a PCIe link width of one lane for configuring the PCIe link.

2. The method of claim 1, wherein the PCIe link configuration mode is the first PCIe link configuration mode, the method further comprising: comparing a reliability metric of a lane of the PCIe link to a reliability threshold, wherein selecting the predetermined PCIe link speed comprises selecting a PCIe link speed level that is lower than a current PCIe link speed of the PCIe link in response to the reliability metric of the lane of the PCIe link exceeding the reliability threshold.

3. The method of claim 1, wherein the PCIe link configuration mode is the first PCIe link configuration mode, the method further comprising: comparing a requested bandwidth to a configured bandwidth of the PCIe link; and increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

4. The method of claim 3, further comprising: comparing the PCIe link width to a PCIe link width threshold, wherein increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link comprises increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link and the PCIe link width not reaching the PCIe link width threshold.

5. The method of claim 1, wherein the PCIe link configuration mode is the second PCIe link configuration mode, and wherein selecting the predetermined PCIe link speed comprises selecting a maximum PCIe link speed of the PCIe link.

6. The method of claim 1, wherein the PCIe link configuration mode is the second PCIe link configuration mode, the method further comprising: comparing a requested bandwidth to a configured bandwidth of the PCIe link; and increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

7. The method of claim 1, wherein the PCIe link configuration mode is the second PCIe link configuration mode, the method further comprising: comparing a requested bandwidth to a configured bandwidth of the PCIe link; and decreasing the PCIe link speed in response to the configured bandwidth of the PCIe link exceeding the requested bandwidth.

8. The method of claim 1, the method further comprising: interpreting the PCIe link configuration mode; in response to interpreting the PCIe link configuration mode as the first PCIe link configuration mode, modifying a current PCIe link configuration having the current PCIe link width and the current PCIe link speed by increasing the PCIe link width relative to a current PCIe link width and decreasing the predetermined PCIe link speed relative to a current PCIe link speed in response to a requested bandwidth exceeding a current bandwidth; and in response to interpreting the PCIe link configuration mode as the second PCIe link configuration mode, modifying the current PCIe link configuration by increasing the predetermined PCIe link speed relative to the current PCIe link speed and decreasing the PCIe link width relative to the current PCIe link width in response to the requested bandwidth exceeding the current bandwidth.

9. A computing device, the computing device comprising: a Peripheral Component Interconnect Express (PCIe) device configured to: select a predetermined PCIe link speed as a PCIe link speed for configuring a PCIe link based on a PCIe link configuration mode of the PCIe system of a plurality of PCIe link configuration modes of the PCIe system, wherein the plurality of PCIe link configuration modes includes at least a first PCIe link configuration mode and a second PCIe link configuration mode; and select a PCIe link width of one lane for configuring the PCIe link.

10. The computing device of claim 9, wherein the PCIe link configuration mode is the first PCIe link configuration mode, the PCIe device is further configured to: compare a reliability indicator of a lane of the PCIe link to a reliability threshold; and in response to the reliability indicator of the lane of the PCIe link exceeding the reliability threshold, select the predetermined PCIe link speed having a PCIe link speed level lower than a current PCIe link speed of the PCIe link.

11. The computing device of claim 9, wherein the PCIe link configuration mode is the first PCIe link configuration mode, the PCIe device is further configured to: compare a requested bandwidth to a configured bandwidth of the PCIe link; and in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link, increase the PCIe link width.

12. The computing device of claim 11, wherein the PCIe device is further configured to: compare the PCIe link width to a PCIe link width threshold; and increasing the PCIe link width in response to a requested bandwidth exceeding a configured bandwidth of the PCIe link and the PCIe link width not reaching the PCIe link width threshold.

13. The computing device of claim 9, wherein the PCIe link configuration mode is the second PCIe link configuration mode, the PCIe device being further configured to select the predetermined PCIe link speed as a maximum PCIe link speed for the PCIe link.

14. The computing device of claim 9, wherein the PCIe link configuration mode is the second PCIe link configuration mode, the PCIe device being further configured to: compare a requested bandwidth to a configured bandwidth of the PCIe link; and increase the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

15. The computing device of claim 9, wherein the PCIe link configuration mode is the second PCIe link configuration mode, the PCIe device being further configured to: compare a requested bandwidth to a configured bandwidth of the PCIe link; and decrease the PCIe link speed in response to the configured bandwidth of the PCIe link exceeding the requested bandwidth.

16. The computing device of claim 9, wherein the PCIe device is further configured to: interpret the PCIe link configuration mode; in response to interpreting the PCIe link configuration mode as the first PCIe link configuration mode, modify a current PCIe link configuration having a current PCIe link width and a current PCIe link speed by increasing the PCIe link width relative to the current PCIe link width in response to a requested bandwidth exceeding a current bandwidth and decreasing the predetermined PCIe link speed relative to the current PCIe link speed in response to the current bandwidth exceeding the requested bandwidth; and in response to interpreting the PCIe link configuration mode as the second PCIe link configuration mode, modify the current PCIe link configuration by increasing the predetermined PCIe link speed relative to the current PCIe link speed in response to the requested bandwidth exceeding the current bandwidth and decreasing the PCIe link width relative to the current PCIe link width in response to the current bandwidth exceeding the requested bandwidth.

17. A computing device, the computing device comprising: means for selecting a predetermined Peripheral Component Interconnect Express (PCIe) link speed as a PCIe link speed for configuring a PCIe link based on a PCIe link configuration mode of the PCIe system of a plurality of PCIe link configuration modes of a PCIe system, wherein the plurality of PCIe link configuration modes comprises at least a first PCIe link configuration mode and a second PCIe link configuration mode; and A component for selecting a PCIe link width of one lane for configuring the PCIe link.

18. The computing device of claim 17, wherein the PCIe link configuration mode is the first PCIe link configuration mode, the computing device further comprising: A component for comparing a reliability indicator of a lane of the PCIe link to a reliability threshold, wherein the component for selecting the predetermined PCIe link speed comprises a component for selecting a PCIe link speed level lower than a current PCIe link speed of the PCIe link in response to the reliability indicator of the lane of the PCIe link exceeding the reliability threshold.

19. The computing device of claim 17, wherein the PCIe link configuration mode is the first PCIe link configuration mode, the computing device further comprising: A component for comparing a requested bandwidth to a configured bandwidth of the PCIe link; and A component for increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

20. The computing device of claim 19, further comprising: The component for comparing the PCIe link width to a PCIe link width threshold, wherein the component for increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link comprises a component for increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link and the PCIe link width not reaching the PCIe link width threshold.

21. The computing device of claim 17, wherein the PCIe link configuration mode is the second PCIe link configuration mode, and wherein the component for selecting the predetermined PCIe link speed comprises a component for selecting a maximum PCIe link speed of the PCIe link.

22. The computing device of claim 17, wherein the PCIe link configuration mode is the second PCIe link configuration mode, the computing device further comprising: A component for comparing a requested bandwidth to a configured bandwidth of the PCIe link; and A component for increasing the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

23. The computing device of claim 17, wherein the PCIe link configuration mode is the second PCIe link configuration mode, the computing device further comprising: A component for comparing a requested bandwidth to a configured bandwidth of the PCIe link; and A component for decreasing the PCIe link speed in response to the configured bandwidth of the PCIe link exceeding the requested bandwidth.

24. The computing device of claim 17, the computing device further comprising: A component for interpreting the PCIe link configuration mode; in response to interpreting the PCIe link configuration mode as the first PCIe link configuration mode, means for modifying a current PCIe link configuration having the current PCIe link width and the current PCIe link speed by, in response to a requested bandwidth exceeding a current bandwidth, increasing the PCIe link width relative to a current PCIe link width and, in response to the current bandwidth exceeding the requested bandwidth, decreasing the predetermined PCIe link speed relative to a current PCIe link speed; and in response to interpreting the PCIe link configuration mode as the second PCIe link configuration mode, means for modifying the current PCIe link configuration by, in response to the requested bandwidth exceeding the current bandwidth, increasing the predetermined PCIe link speed relative to the current PCIe link speed and, in response to the current bandwidth exceeding the requested bandwidth, decreasing the PCIe link width relative to the current PCIe link width.

25. A Peripheral Component Interconnect Express (PCIe) device configured to: select a predetermined PCIe link speed as a PCIe link speed for configuring a PCIe link based on a PCIe link configuration mode of the PCIe system of a plurality of PCIe link configuration modes of the PCIe system, wherein the plurality of PCIe link configuration modes includes at least a first PCIe link configuration mode and a second PCIe link configuration mode; and select a PCIe link width of one lane for configuring the PCIe link.

26. The PCIe device of claim 25, wherein the PCIe link configuration mode is the first PCIe link configuration mode, the PCIe device is further configured to: compare a reliability metric of a lane of the PCIe link to a reliability threshold; select the predetermined PCIe link speed having a PCIe link speed level lower than a current PCIe link speed of the PCIe link in response to the reliability metric of the lane of the PCIe link exceeding the reliability threshold; compare a requested bandwidth to a configured bandwidth of the PCIe link; and increase the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link.

27. The PCIe device of claim 26, wherein the PCIe device is further configured to: compare the PCIe link width to a PCIe link width threshold; and increase the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link and the PCIe link width not meeting the PCIe link width threshold.

28. The PCIe device of claim 25, wherein the PCIe link configuration mode is the second PCIe link configuration mode, the PCIe device being further configured to select the predetermined PCIe link speed as a maximum PCIe link speed of the PCIe link.

29. The PCIe device of claim 25, wherein: the PCIe link configuration mode is the second PCIe link configuration mode; and the PCIe device is further configured to: compare a requested bandwidth to a configured bandwidth of the PCIe link; increase the PCIe link width in response to the requested bandwidth exceeding the configured bandwidth of the PCIe link; and decrease the PCIe link speed in response to the configured bandwidth of the PCIe link exceeding the requested bandwidth.

30. The PCIe device of claim 25, wherein the PCIe device is further configured to: interpret the PCIe link configuration mode; in response to interpreting the PCIe link configuration mode as the first PCIe link configuration mode, modify a current PCIe link configuration having a current PCIe link width and a current PCIe link speed by increasing the PCIe link width relative to the current PCIe link width in response to a requested bandwidth exceeding a current bandwidth and decreasing the predetermined PCIe link speed relative to the current PCIe link speed in response to the current bandwidth exceeding the requested bandwidth; and in response to interpreting the PCIe link configuration mode as the second PCIe link configuration mode, modify the current PCIe link configuration by increasing the predetermined PCIe link speed relative to the current PCIe link speed in response to the requested bandwidth exceeding the current bandwidth and decreasing the PCIe link width relative to the current PCIe link width in response to the current bandwidth exceeding the requested bandwidth. ​

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