An encoder signal fault detection circuit

Abstract

The application discloses an encoder signal fault detection circuit, comprising: a bias circuit for generating a first bias voltage and a second bias voltage according to a power supply VCC; a first comparison circuit, a same-phase input end of the first comparison circuit receiving a first mixed voltage formed by mixing a signal voltage transmitted by a positive end of a differential signal and the first bias voltage, and an opposite-phase input end of the first comparison circuit receiving a second mixed voltage formed by mixing a signal voltage transmitted by a negative end of the differential signal and the second bias voltage; a second comparison circuit, a same-phase input end of the second comparison circuit receiving a third mixed voltage formed by mixing the signal voltage transmitted by the negative end of the differential signal and the first bias voltage, and an opposite-phase input end of the second comparison circuit receiving a fourth mixed voltage formed by mixing the signal voltage transmitted by the positive end of the differential signal and the second bias voltage; wherein the output ends of the first comparison circuit and the second comparison circuit are connected in parallel, and are configured to output corresponding fault indication signals when a wire break occurs in the differential signal pair or the absolute value of a voltage difference of the differential signal pair is lower than a preset voltage amplitude threshold.

Description

Technical Field

[0001] This invention relates to the field of encoder signal processing technology, and in particular to an encoder signal fault detection circuit with open circuit and amplitude detection functions. Background Technology

[0002] Differential encoders are widely used in motor control, servo drives, and automation systems to provide position or speed signals. Current technology typically employs bidirectional optocouplers as open-circuit detection devices to promptly detect disconnections between the differential encoder acquisition card and the differential encoder. If the connection is broken, the voltage or current at the optocoupler's input will change significantly (e.g., a negative shift), triggering a fault indication. This prevents the servo system or controller from failing to acquire position / speed data due to interrupted encoder feedback signals caused by disconnections, thus affecting equipment operating accuracy. However, using bidirectional optocouplers as open-circuit detection receivers requires a large drive current, placing high demands on the encoder's output drive capability. Furthermore, it cannot detect other potential encoder signal faults, resulting in a relatively limited functionality. Summary of the Invention

[0003] This invention provides an encoder signal fault detection circuit to solve the technical problem that existing differential encoders, which use bidirectional optocouplers for wire breakage detection, have high requirements for encoder output drive capability and relatively simple functions.

[0004] To solve the above-mentioned technical problems, the present invention provides an encoder signal fault detection circuit, comprising:

[0005] The bias circuit is used to generate a first bias voltage and a second bias voltage based on the power supply VCC.

[0006] The first comparator circuit has a non-inverting input terminal receiving a first composite voltage formed by mixing the signal voltage transmitted from the positive terminal of the differential signal with the first bias voltage, and an inverting input terminal receiving a second composite voltage formed by mixing the signal voltage transmitted from the negative terminal of the differential signal with the second bias voltage.

[0007] The second comparator circuit has a non-inverting input terminal that receives a third composite voltage formed by mixing the signal voltage transmitted from the negative terminal of the differential signal with the first bias voltage, and an inverting input terminal that receives a fourth composite voltage formed by mixing the signal voltage transmitted from the positive terminal of the differential signal with the second bias voltage.

[0008] The outputs of the first comparison circuit and the second comparison circuit are connected in parallel and configured to output a corresponding fault indication signal when the differential signal pair is disconnected or the absolute value of its voltage difference is lower than a preset voltage amplitude threshold.

[0009] A further technical solution is as follows: the bias circuit includes a voltage divider network composed of multiple resistors, connected to the power supply VCC, for dividing the power supply VCC to generate the first bias voltage and the second bias voltage.

[0010] Its further technical solution is as follows: the voltage divider network includes a first voltage divider branch and a second voltage divider branch, wherein,

[0011] The first voltage divider branch includes a first resistor, a second resistor, a third resistor, and a fourth resistor connected in series between the power supply VCC and ground. The connection point of the first resistor and the second resistor, and the connection point of the third resistor and the fourth resistor, serve as the two output terminals of the first voltage divider branch, respectively outputting the first bias voltage and the second bias voltage, and respectively transmitting them to the non-inverting input terminal of the first comparator circuit and the inverting input terminal of the second comparator circuit.

[0012] The second voltage divider branch includes a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor connected in series between the power supply VCC and ground. The connection point of the fifth resistor and the sixth resistor, and the connection point of the seventh resistor and the eighth resistor, serve as the two output terminals of the second voltage divider branch, respectively outputting the first bias voltage and the second bias voltage, which are transmitted to the non-inverting input terminal of the second comparator circuit and the inverting input terminal of the first comparator circuit.

[0013] The further technical solution is as follows: the non-inverting input terminal of the first comparator circuit and the inverting input terminal of the second comparator circuit are respectively connected to the positive terminal of the differential signal through the second resistor and the third resistor; the inverting input terminal of the first comparator circuit and the non-inverting input terminal of the second comparator circuit are respectively connected to the negative terminal of the differential signal through the seventh resistor and the sixth resistor.

[0014] The further technical solution is as follows: the resistance values ​​of the first resistor, the fourth resistor, the fifth resistor and the eighth resistor are the same, and the resistance values ​​of the second resistor, the third resistor, the sixth resistor and the seventh resistor are the same.

[0015] The further technical solution is as follows: the resistance values ​​of the first resistor, the fourth resistor, the fifth resistor and the eighth resistor are 10KΩ.

[0016] The further technical solution is as follows: the resistance values ​​of the second resistor, the third resistor, the sixth resistor and the seventh resistor are 5.1KΩ.

[0017] The further technical solution is that the first comparison circuit and the second comparison circuit are implemented by voltage comparators.

[0018] The further technical solution is as follows: the output terminals of the first comparison circuit and the second comparison circuit are both connected to the power supply VDD through a pull-up resistor.

[0019] The further technical solution is as follows: the preset voltage amplitude threshold is determined by the power supply VCC and the resistance value of the bias circuit.

[0020] The encoder signal fault detection circuit described above includes a bias circuit, a first comparator circuit, and a second comparator circuit. The bias circuit generates a first bias voltage and a second bias voltage. The non-inverting input of the first comparator circuit receives a first composite voltage formed by mixing the signal voltage transmitted from the positive terminal of the differential signal with the first bias voltage. The non-inverting input of the second comparator circuit receives a third composite voltage formed by mixing the signal voltage transmitted from the negative terminal of the differential signal with the first bias voltage. The inverting input of the first comparator circuit receives a second composite voltage formed by mixing the signal voltage transmitted from the negative terminal of the differential signal with the second bias voltage. The inverting input of the second comparator circuit receives a fourth composite voltage formed by mixing the signal voltage transmitted from the positive terminal of the differential signal with the second bias voltage. The outputs of the first and second comparator circuits are connected in parallel and configured to output a fault signal when the differential signal pair (composed of the positive and negative terminals of the differential signal) is disconnected or its absolute voltage difference is lower than a preset voltage amplitude threshold. The invention employs a comparator circuit instead of a traditional bidirectional optocoupler as the detection core, significantly reducing the driving capability requirements of the differential encoder output signal, improving compatibility with various encoders, and offering a faster response speed. Furthermore, the inputs of the first and second comparator circuits are cross-connected to the differential signal pair, and their outputs are connected in parallel. This ensures that when any signal line is broken, the two comparator circuits will collaboratively output a consistent fault indication signal, forming a redundant detection mechanism that greatly improves the reliability of line breakage detection. Simultaneously, when the absolute value of the voltage difference between the differential signal pair is lower than a preset voltage amplitude threshold, a corresponding fault indication signal can be output, enabling timely detection of insufficient signal amplitude due to line attenuation, interface oxidation, etc., and rapid monitoring of low differential signal voltage amplitude. This invention integrates line breakage detection and voltage amplitude monitoring functions, improving the comprehensiveness of fault detection. Moreover, the circuit topology is simple, the driving capability requirements for the encoder output signal are low, and the circuit design cost is also low. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic block diagram of the encoder signal fault detection circuit in one embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the specific circuit structure of the encoder signal fault detection circuit in one embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] The encoder signal fault detection circuit provided in this invention can be applied to frequency conversion drive systems and automation control systems. The frequency conversion drive system mainly includes electrical devices using power electronics technology, such as frequency converters, servo drives, inverters, and motor speed controllers. In the frequency conversion drive system and automation control system, the encoder signal fault detection circuit of this invention can be used as a data acquisition and feedback module to acquire the output signals of various types of differential encoders, perform encoder disconnection detection and voltage amplitude detection, and transmit the corresponding detection results to the control device therein for corresponding control operations.

[0026] Reference Figure 1 , Figure 1 This is a schematic block diagram of an encoder signal fault detection circuit according to an embodiment of the present invention. In the embodiment shown in the figure, the encoder signal fault detection circuit includes a bias circuit 10, a first comparison circuit 20, and a second comparison circuit 30. The bias circuit 10 generates a first bias voltage and a second bias voltage based on the power supply VCC. The input terminals of the first comparison circuit 20 and the second comparison circuit 30 are alternately connected to the positive and negative terminals of a differential signal pair. The output terminals of the first comparison circuit 20 and the second comparison circuit 30 are connected in parallel. Specifically, as shown... Figure 1 and Figure 2As shown, in this embodiment, the non-inverting input of the first comparator circuit 20 receives a first composite voltage V1 formed by mixing the signal voltage transmitted from the positive terminal A+ of the differential signal with the first bias voltage, and its inverting input receives a second composite voltage V2 formed by mixing the signal voltage transmitted from the negative terminal A- of the differential signal with the second bias voltage; the non-inverting input of the second comparator circuit 30 receives a third composite voltage V3 formed by mixing the signal voltage transmitted from the negative terminal A- of the differential signal with the first bias voltage, and its inverting input receives a fourth composite voltage V4 formed by mixing the signal voltage transmitted from the positive terminal A+ of the differential signal with the second bias voltage; wherein, the output terminals of the first comparator circuit 20 and the second comparator circuit 30 are connected in parallel and configured to output a corresponding fault indication signal when the differential signal pair is disconnected, i.e., the positive terminal A+ / negative terminal of the differential signal is disconnected or the absolute value of the voltage difference between the positive terminal A+ and the negative terminal of the differential signal is lower than a preset voltage amplitude threshold.

[0027] Based on the above design, this invention uses a bias circuit 10, a first comparator circuit 20, and a second comparator circuit 30 to achieve encoder disconnection detection and differential signal voltage amplitude detection. The circuit topology is simple and avoids the drawbacks of using a bidirectional optocoupler as the disconnection detection receiver, which requires a large driving current and has a single detection function. By using a comparator circuit instead of the traditional bidirectional optocoupler as the detection core, the driving capability requirement for the differential encoder output signal is significantly reduced, improving compatibility with various encoders and providing a faster response speed. Furthermore, the input terminals of the first comparator circuit 20 and the second comparator circuit 30 are cross-connected to the differential signal pair; that is, the non-inverting input terminal of the first comparator circuit 20 and the second comparator circuit 30... The inverting input terminal is simultaneously connected to the positive terminal A+ of the differential signal, and the inverting input terminal of the first comparator circuit 20 and the non-inverting input terminal of the second comparator circuit 30 are simultaneously connected to the negative terminal A- of the differential signal. This cross-symmetrical structure ensures that the two comparator circuits can fully cover the positive and negative polarity changes of the differential signal, so that when any signal line is broken, the two comparator circuits will work together to output a fault indication signal, forming a redundant detection mechanism, which greatly improves the reliability of the break detection. At the same time, when the absolute value of the voltage difference between the differential signal pairs is lower than the preset voltage amplitude threshold, a corresponding fault indication signal can also be output, which can promptly detect the insufficient signal amplitude caused by line attenuation, interface oxidation, etc., and quickly detect the problem of low differential signal voltage amplitude.

[0028] In some embodiments, the bias circuit 10 may include a voltage divider network composed of multiple resistors connected to the power supply VCC to divide the power supply VCC to generate the first bias voltage and the second bias voltage.

[0029] Specifically, in this embodiment, as Figure 2As shown, the voltage divider network includes a first voltage divider branch 11 and a second voltage divider branch 12. The first voltage divider branch 11 includes a first resistor R79, a second resistor R78, a third resistor R82, and a fourth resistor R81 connected in series between the power supply VCC and ground. The connection point of the first resistor R79 and the second resistor R78, and the connection point of the third resistor R82 and the fourth resistor R81, serve as the two output terminals of the first voltage divider branch 11, respectively outputting the first bias voltage and the second bias voltage, which are then transmitted to the non-inverting input terminal of the first comparator circuit 20. The second voltage divider branch 12 includes a fifth resistor R86, a sixth resistor R84, a seventh resistor R76, and an eighth resistor R74 connected in series between the power supply VCC and ground. The connection point of the fifth resistor R86 and the sixth resistor R84, and the connection point of the seventh resistor R76 and the eighth resistor R74 serve as the two output terminals of the second voltage divider branch 12, respectively outputting the first bias voltage and the second bias voltage, which are transmitted to the non-inverting input terminal of the second comparator circuit 30 and the inverting input terminal of the first comparator circuit 20.

[0030] In this invention, the preset voltage amplitude threshold can be determined by the power supply VCC and the resistance values ​​in the voltage divider network. Preferably, the first resistor R79, the fourth resistor R81, the fifth resistor R86, and the eighth resistor R74 have the same resistance value, and the second resistor R78, the third resistor R82, the sixth resistor R84, and the seventh resistor R76 have the same resistance value. In this embodiment, VCC can be a 5V voltage source, the first resistor R79, the fourth resistor R81, the fifth resistor R86, and the eighth resistor R74 can be 10KΩ, and the second resistor R78, the third resistor R82, the sixth resistor R84, and the seventh resistor R76 have a resistance value of 5.1KΩ. In this embodiment, the minimum limit value for differential signal voltage amplitude monitoring, i.e., the preset voltage amplitude threshold, is set according to the power supply VCC, the first voltage divider branch 11, and the second voltage divider branch 12. Understandably, in some other embodiments, the power supply VCC and the resistance values ​​can be adjusted according to the actual required preset voltage amplitude threshold value.

[0031] Furthermore, the non-inverting input terminal of the first comparator circuit 20 and the inverting input terminal of the second comparator circuit 30 are respectively connected to the positive terminal A+ of the differential signal through the second resistor R78 and the third resistor R82. The inverting input terminal of the first comparator circuit 20 and the non-inverting input terminal of the second comparator circuit 30 are also respectively connected to the negative terminal A- of the differential signal through the seventh resistor R76 and the sixth resistor R84. In this embodiment, the first synthesized voltage V1 is the voltage obtained by superimposing the signal transmitted from the positive terminal A+ of the differential signal with the first bias voltage after passing through the second resistor R78; the second synthesized voltage V2 is the voltage obtained by superimposing the signal transmitted from the negative terminal A- of the differential signal with the second bias voltage after passing through the seventh resistor R76; the third synthesized voltage V3 is the voltage obtained by superimposing the signal transmitted from the negative terminal A- of the differential signal with the first bias voltage after passing through the sixth resistor R84; and the fourth synthesized voltage V4 is the voltage obtained by superimposing the signal transmitted from the positive terminal A+ of the differential signal with the second bias voltage after passing through the third resistor R82. In this embodiment, the synthesized voltage is formed by the combined action of the voltage at the positive terminal A+ and the voltage at the negative terminal A- of the differential signal, as well as the power supply VCC.

[0032] Continue to refer to Figure 2 In some implementations, the first comparison circuit 20 includes a first voltage comparator U13A, and the second comparison circuit 30 includes a second voltage comparator U13B; that is, the first comparison circuit 20 and the second comparison circuit 30 are implemented by voltage comparators. Specifically, in this embodiment, a dual-channel differential comparator integrated circuit of model LM393DR can be used, which includes two independent voltage comparators to realize the functions of the first comparison circuit 20 and the second comparison circuit 30. In some other embodiments, the first comparison circuit 20 and the second comparison circuit 30 can also be selected from separate voltage comparators.

[0033] Preferably, the output terminals of the first comparator circuit 20 and the second comparator circuit 30 are both connected to the power supply VDD through a pull-up resistor R75. VDD can be 3.3V. By connecting the output terminals of the voltage comparators in parallel and pulling them up to +3.3V, when applied to frequency conversion drive systems or automatic control systems, the output signal can be directly read by commonly used microcontrollers without the need for additional level conversion circuits, thus simplifying system design.

[0034] The following is combined with Figure 1 and Figure 2 The working principle of the encoder signal fault detection circuit in this embodiment will be explained in detail:

[0035] In this embodiment, when there is no open circuit in the differential signal pair and the voltage amplitude of the differential signal is not lower than a preset voltage amplitude threshold, the output terminals of the first comparison circuit 20 and the second comparison circuit 30 are connected in parallel and ANDed to output a low level. Otherwise, a high-level fault indication signal is output. Specifically, during operation, the first voltage divider branch 11, composed of R79, R78, R82, and R81, and the second voltage divider branch 12, composed of R86, R84, R76, and R74, divide the 5V power supply VCC, respectively, with R79=R74=R81=R86, R78=R76=R84=R82, and the voltage U applied to the signals transmitted by A+ and A- is... A+ U A- The maximum voltage amplitude does not exceed the maximum bias voltage, VCC, and the minimum voltage amplitude is 0V, i.e., 0≤U A+ ≤VCC、0≤U A- ≤VCC.

[0036] When the differential signal pair outputs normally, the voltage received at the non-inverting input of the first comparator circuit 20 is determined by the current U. A+ The signal voltage generated by the individual action of VCC and the first bias voltage generated by the individual action of VCC in the voltage divider network are superimposed, U A+ When acting alone, VCC is considered grounded, while when VCC acts alone, U A+ If we consider it as grounded, then the voltage at the non-inverting input of the first comparator circuit 20 is V1 = U. A+ *R79 / (R78+R79)+VCC*R78 / (R78+R79), while the voltage at the inverting input terminal is determined by the current U A- The signal voltage generated by VCC acting alone is superimposed with the second bias voltage generated by VCC acting alone, therefore V2 = U A- *R74 / (R76+R74)+0*R76 / (R76+R74), Similarly, the voltage received at the non-inverting input of the second comparator circuit 30 is determined by the current U A- The signal voltage generated by the individual action of VCC is superimposed with the first bias voltage generated by the individual action of VCC, therefore V3 = U. A- *R86 / (R84+R86)+VCC*R84 / (R84+R86), while the voltage at the inverting input terminal is V4=U A+ *R81 / (R81+R82)+0*R82 / (R81+R82).

[0037] When setting the minimum limit for differential signal voltage amplitude monitoring, i.e., the preset voltage amplitude threshold, since the outputs of the first comparator circuit 20 and the second comparator circuit 30 are ANDed, the output POSA_FBK will be low if either of the outputs of the first comparator circuit 20 or the second comparator circuit 30 is low. Therefore, the output signal POSA_FBK will be low when either the voltage at the non-inverting input of the first comparator circuit 20 is less than the voltage at the inverting input, or the voltage at the non-inverting input of the second comparator circuit 30 is less than the voltage at the inverting input, i.e., V1 < V2 or V3 < V4. Given that R79 = R74 = R81 = R86, R78 = R76 = R84 = R82, substituting these values ​​into the above formula and simplifying, we can obtain the differential signal voltage amplitude |U_FBK| during normal operation. A+ -U A- |>VCC*R76 / R74, i.e., differential signal voltage U A+ and U A- When the absolute value of the voltage difference is higher than VCC*R76 / R74, POSA_FBK is at a low level. In this embodiment, VCC=5V, R76=5.1KΩ, R74=10KΩ, so the preset voltage amplitude threshold is 2.55V, |U A+ -U A- When the voltage is greater than 2.55V, at least one of the first voltage comparator U13A and the second voltage comparator U13B outputs a low level, and POSA_FBK is low. When the absolute value of the differential signal voltage is less than 2.55V, the output is a continuously high fault indication signal. Understandably, the first bias voltage and the second bias voltage can be changed by altering the resistance value and VCC voltage in the bias circuit 10, thereby changing the preset voltage amplitude threshold. In some other embodiments, the resistance value and VCC voltage can be adjusted according to actual needs.

[0038] When a disconnection occurs, if the A+ signal is disconnected, the non-inverting input of the first voltage comparator U13A is equivalent to only the bias circuit 10 being active. At this time, the first composite voltage V1 received at the non-inverting input is VCC*(R78+R82+R81) / (R79+R78+R82+R81)=5V*(10K+5.1K+5.1K) / (10K+5.1K+5.1K+10K)≈3.3444V. That is, the received first composite voltage V1 is only the voltage divided by the resistors of the first voltage divider branch 11 at this time. Meanwhile, the second composite voltage V2 received at the inverting input of the first voltage comparator U13A is determined by U... A- The result is obtained by the combined action of V and 5V, then V2 = U. A- *R74 / (R76+R74) +0*R76 / (R76+R74)=U A- *10K / (10K+5.1K)≈U A- *0.6623, if U A-If the maximum voltage is no more than 5V, then V2 < 3.3113V, which is less than V1 at the non-inverting input. Therefore, U13A outputs a high-level fault indication signal. The inverting input of the second voltage comparator U13B is also equivalent to only the bias circuit 10 being active. The received fourth composite voltage V4 = VCC * R81 / (R78 + R79 + R81 + ... R82) = 5V*10K / (10K+5.1K+5.1K+10K)≈1.6556V. The third composite voltage V3 received at its non-inverting input terminal is obtained by the combined action of UA- and 5V. Therefore, the received third composite voltage V3 = UA-*R86 / (R86+R84)+VCC*R84 / (R86+R84) = UA-*10K / (10K+5.1K)+5V*5.1K / (10K+5.1K)>1.6887V, which is greater than V4 at the inverting input terminal. Therefore, U13B outputs a high-level fault indication signal, and U13A and U13B, connected in parallel, also output a high-level fault indication signal. Understandably, when A- is disconnected, the principle and calculation process are similar to the above. The first voltage comparator U13A and the second voltage comparator U13B, connected in parallel, also output a high-level fault indication signal.

[0039] In summary, the encoder signal fault detection circuit of this invention integrates open-circuit detection and voltage amplitude monitoring functions, improving the comprehensiveness of fault detection. It consists of only a conventional comparator and a few resistive components, resulting in a simple circuit topology. Furthermore, by using a comparator circuit instead of the traditional bidirectional optocoupler as the detection core, the driving capability requirements of the differential encoder output signal are significantly reduced, improving compatibility with various encoders and providing a faster response speed. This makes the circuit suitable for high-speed encoder systems, enabling rapid fault response and meeting the requirements of high-performance servo drives and other application scenarios. Moreover, the inputs of the first and second comparator circuits are cross-connected to the differential signal pair, and their outputs are connected in parallel. This ensures that when any signal line is broken, the two comparator circuits will collaboratively output a consistent fault indication signal, forming a redundant detection mechanism that greatly improves the reliability of open-circuit detection. Simultaneously, when the absolute value of the voltage difference between the differential signal pair is lower than a preset voltage amplitude threshold, a corresponding fault indication signal can be output, enabling timely detection of insufficient signal amplitude caused by line attenuation, interface oxidation, etc., and quickly identifying problems with low differential signal voltage amplitude.

[0040] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An encoder signal fault detection circuit, characterized in that, The encoder signal fault detection circuit includes: A bias circuit for generating a first bias voltage and a second bias voltage based on the power supply VCC, comprising a voltage divider network consisting of multiple resistors; The first comparator circuit has a non-inverting input terminal receiving a first composite voltage formed by mixing the signal voltage transmitted from the positive terminal of the differential signal with the first bias voltage, and an inverting input terminal receiving a second composite voltage formed by mixing the signal voltage transmitted from the negative terminal of the differential signal with the second bias voltage. The second comparator circuit has a non-inverting input terminal that receives a third composite voltage formed by mixing the signal voltage transmitted from the negative terminal of the differential signal with the first bias voltage, and an inverting input terminal that receives a fourth composite voltage formed by mixing the signal voltage transmitted from the positive terminal of the differential signal with the second bias voltage. The voltage divider network includes a first voltage divider branch and a second voltage divider branch. The first voltage divider branch includes a first resistor, a second resistor, a third resistor, and a fourth resistor connected in series between the power supply VCC and ground. The connection point of the first resistor and the second resistor, and the connection point of the third resistor and the fourth resistor, serve as the two output terminals of the first voltage divider branch, respectively outputting the first bias voltage and the second bias voltage, and respectively transmitting them to the non-inverting input terminal of the first comparator circuit and the inverting input terminal of the second comparator circuit. The second voltage divider branch includes a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor connected in series between the power supply VCC and ground. The connection point of the fifth resistor and the sixth resistor, and the connection point of the seventh resistor and the eighth resistor, serve as the two output terminals of the second voltage divider branch, respectively outputting the first bias voltage and the second bias voltage, and respectively transmitting them to the non-inverting input terminal of the second comparator circuit and the inverting input terminal of the first comparator circuit. The outputs of the first comparison circuit and the second comparison circuit are connected in parallel and configured to output a corresponding fault indication signal when the differential signal pair is disconnected or the absolute value of its voltage difference is lower than a preset voltage amplitude threshold.

2. The encoder signal fault detection circuit as described in claim 1, characterized in that, The non-inverting input of the first comparator circuit and the inverting input of the second comparator circuit are respectively connected to the positive terminal of the differential signal through the second resistor and the third resistor. The inverting input of the first comparator circuit and the non-inverting input of the second comparator circuit are respectively connected to the negative terminal of the differential signal through the seventh resistor and the sixth resistor.

3. The encoder signal fault detection circuit as described in claim 1 or 2, characterized in that, The first, fourth, fifth, and eighth resistors have the same resistance value, and the second, third, sixth, and seventh resistors have the same resistance value.

4. The encoder signal fault detection circuit as described in claim 3, characterized in that, The resistance values ​​of the first resistor, the fourth resistor, the fifth resistor, and the eighth resistor are 10KΩ.

5. The encoder signal fault detection circuit as described in claim 3, characterized in that, The resistance values ​​of the second, third, sixth, and seventh resistors are 5.1 kΩ.

6. The encoder signal fault detection circuit as described in claim 1, characterized in that, The first comparison circuit and the second comparison circuit are implemented by voltage comparators.

7. The encoder signal fault detection circuit as described in claim 1, characterized in that, The outputs of both the first and second comparator circuits are connected to the power supply VDD via a pull-up resistor.

8. The encoder signal fault detection circuit as described in claim 1, characterized in that, The preset voltage amplitude threshold is determined by the power supply VCC and the resistance value of the bias circuit.

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