A method for polling read and write data based on fine management of EEPROM memory

Abstract

This invention belongs to the field of embedded system data storage technology, and particularly relates to a method for polling and reading / writing data based on fine-grained management of EEPROM memory. It includes finely dividing the EEPROM storage area into a data access area and a data storage backup area; creating a unique access interface, configuring the data access area as the smallest erase / write unit, and isolating the user from the data storage backup area; further dividing the data storage backup area into multiple block-shaped memory, with each block serving as the actual EEPROM memory; monitoring the block-shaped memory, recording its actual usage, and categorizing it into high-frequency usage areas, low-frequency usage areas, and damaged areas; and polling for data reading and storage, prioritizing the use of low-frequency block-shaped memory areas during data writing. This invention can significantly extend the erase / write cycles and lifespan of the EEPROM while ensuring data security and reliability.

Description

Technical Field

[0001] This invention belongs to the field of embedded system data storage technology, and in particular relates to a method for polling and reading / writing data based on fine-grained management of EEPROM memory. Background Technology

[0002] EEPROMs, due to their electrically erasable nature, data retention even when power is off, and flexible byte-level read / write capabilities, are widely used in embedded systems for storing critical information such as device configuration parameters, sensor calibration data, operation logs, and fault thresholds. However, existing EEPROM methods suffer from several core defects that limit their reliability and lifespan. For example, uneven wear and short lifespan: In traditional EEPROM usage, users typically operate directly on the storage area, and data updates are often concentrated in fixed address regions (such as the frequently updated operation log area). This causes these areas to become "hot spots," rapidly approaching the EEPROM's rated erase / write cycles, while other areas may remain idle for extended periods. The overall lifespan is limited by these hot spots, preventing the full utilization of the EEPROM's rated erase / write potential. Crude partitioning management and lack of frequency partitioning: Some existing solutions only perform simple functional partitioning of the EEPROM (such as parameter configuration area and operation log area), but do not monitor and classify the usage frequency of the memory storage units. Even if a certain area of ​​memory has a high number of erase / write cycles and severe wear, it cannot be dynamically adjusted according to actual usage, thus failing to improve the lifespan of the EEPROM. Direct user interaction with the storage area leads to low data security: In existing solutions, users typically directly access the physical storage address of the EEPROM, lacking unified interface management, which easily leads to data corruption due to erroneous operations; at the same time, there is a lack of data verification mechanisms, making it impossible to identify whether the data is distorted. Lack of effective block memory status management: Existing solutions do not perform fine-grained status monitoring of the EEPROM storage units, and cannot statistically analyze key information such as the number of erase / write cycles and update frequency of each unit in real time, nor can they detect bad blocks in a timely manner. This not only easily causes data write failures but also poses the possibility of contaminating other data. The polling strategy is simple and does not consider priority: Among the existing solutions, a few support polling writing, but they only support sequential writing and do not consider prioritizing based on usage. This still cannot avoid situations where some cells are erased and written more frequently due to usage scenarios, making it difficult to achieve the best wear leveling effect.

[0003] To address the above issues, there is an urgent need for a technical solution that can achieve fine-grained management of EEPROM, dynamic monitoring of storage unit usage status, and optimization of erase / write allocation strategies, so as to maximize the lifespan of EEPROM while ensuring data security and reliability. Summary of the Invention

[0004] This invention optimizes and improves upon the many shortcomings of existing EEPROM solutions, proposing a method for polling and reading / writing data based on fine-grained management of EEPROM memory.

[0005] To achieve the above objectives, the technical solution adopted by the present invention includes the following steps:

[0006] S1. First, perform fine-grained EEPROM memory partitioning, manually dividing the EEPROM memory into a data access area and a data storage backup area, wherein the data access area is configured as the smallest data erase / write unit of the EEPROM.

[0007] S2. Create a unique data access interface to isolate users from the actual data storage backup area. Users can only perform data read and write operations through the unique interface to achieve data isolation.

[0008] S3. Configure erase and write block memory, divide the data storage backup area into multiple independent block memory, the size of each block memory should not be less than the size of the smallest erase and write unit memory of EEPROM, and each block memory serves as the actual data storage carrier of EEPROM.

[0009] S4, Block Memory Monitoring, performs real-time monitoring of all block memory, records the actual usage of each block memory, and classifies it into high-frequency use area, low-frequency use area and damaged area according to the number of times it is used;

[0010] S5. A data polling read / write strategy is adopted, and operations are performed through a unique data access interface. When writing data, the block memory is located by polling, and the block memory in the low-frequency use area is selected first to perform the data writing operation. When reading data, the same unique data access interface is called, and the reading operation is completed after passing the corresponding verification.

[0011] The data write operation includes:

[0012] S51. Users write data to the data access area through the unique data access interface.

[0013] S52. The unique data access interface performs integrity verification on the cached data in the data access area.

[0014] S53. After the verification is passed, the unique data access interface polls and retrieves the block memory in a round-robin fashion, and determines the target memory according to the priority.

[0015] S54. Erase the existing data in the target block memory;

[0016] S55. Write the cached data of the data access area into the target memory;

[0017] S56. Update the usage record of this block memory, and synchronously adjust the division results of the high-frequency usage area, low-frequency usage area and damaged area.

[0018] Preferably, the memory size of the data access area in step S1 is consistent with the memory size of the smallest erase / write unit of the EEPROM, used to temporarily cache the actual data of user interaction, and to serve as a transfer medium between the user and the data storage backup area.

[0019] Preferably, the unique data access interface in step S2 inherits the data integrity verification function. When writing data, the data that the user wants to operate on is verified, and when reading data, the validity of the data read from the data storage backup area is verified. The integrity verification and validity verification are implemented by one or more combinations of CRC verification, parity verification, and SHA verification.

[0020] Preferably, in step S3, the size of each block of memory in the data storage backup area is exactly the same, and the size of each block of memory is not less than the size of the memory in the data access area.

[0021] Preferably, the actual usage of the block memory in step S4 includes the actual number of erase / write operations for each block memory, the data update frequency, the data storage duration, and the data erase / write error situation. Based on the actual usage, the erase / write frequency threshold and the continuous erase / write error threshold are manually set. If the value is higher than the erase / write frequency threshold, it is classified as a high-frequency usage area; if it is lower than the erase / write frequency threshold, it is classified as a low-frequency usage area; and if it is higher than the continuous erase / write error threshold, it is classified as a damaged area and is no longer used.

[0022] Preferably, the erase / write frequency threshold is dynamically adjusted based on the total capacity of the EEPROM, the minimum erase / write unit, and the expected lifespan.

[0023] Preferably, in step S5, the block memory in the low-frequency usage area is selected first to perform the data writing operation, including: polling and searching all the block memory in the low-frequency usage area, and prioritizing the block memory with the fewest write operations; if there is no free block memory in the low-frequency usage area, the block memory in the high-frequency usage area is polled and searched, and the target block memory is selected in order of increasing actual erase and write counts.

[0024] Preferably, the system also includes block memory status management operations, including: configuring a status identifier for each block memory, the identifier including an idle state, a valid data state, and a bad block state; counting the number of erase and write operations for each block memory through the status identifier, detecting and marking bad blocks in real time, and automatically skipping block memory in the bad block state during writing.

[0025] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0026] 1. Wear leveling and significantly extended lifespan: By dividing the data storage backup area into multiple block memory blocks and combining usage frequency monitoring and priority polling writing, the block memory blocks in the low-frequency usage area are used first, avoiding excessive erasure and writing of a single area. This makes the number of erasure and writing cycles of all block memory blocks tend to be uniform, extending the overall lifespan of the EEPROM to N times that of traditional solutions (N is the number of block memory blocks), and fully utilizing the total erasure and writing potential of the EEPROM.

[0027] 2. Strong data security and protection: The unique data access interface isolates users from the data storage backup area, preventing data corruption due to user error. Furthermore, the interface features data verification to effectively prevent data transmission errors and distortion caused by aging storage units. Simultaneously, bad block detection and skipping functions prevent bad blocks from contaminating valid data, further enhancing data security and reliability.

[0028] 3. Refined management and strong adaptability: It supports real-time monitoring of the usage of each block memory and divides it according to the frequency threshold parameter. The frequency threshold can be dynamically adjusted according to the actual use scenario, which can adapt to different EEPROM models and different application scenarios. At the same time, the block memory status management function allows developers to better grasp the health status of EEPROM in real time, which is convenient for maintenance.

[0029] 4. Simple operation and good compatibility: The single data access interface hides the complex logic of the underlying storage management. Users do not need to worry about memory partitioning, address mapping, polling retrieval strategies, etc. Users only need to operate on data through the access interface, reducing development difficulty. In addition, this solution is implemented in software, so there is no need to care about the hardware structure of EEPROM, further enhancing compatibility. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a flowchart illustrating a method for polling and reading / writing data based on fine-grained management of EEPROM memory.

[0032] Figure 2 This is a schematic diagram of the EEPROM distributed structure;

[0033] Figure 3 This is a schematic diagram of the interaction between the unique data access interface;

[0034] Figure 4 This is a schematic diagram of block memory monitoring and partitioning logic;

[0035] Figure 5 Write the data into the flowchart;

[0036] Figure 6 This is a flowchart of the data reading process. Detailed Implementation

[0037] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0038] Numerous specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways than those described herein, and therefore the invention is not limited to the specific embodiments disclosed in the following specification.

[0039] Example 1: To achieve a technical solution for fine-grained management of EEPROM, dynamic monitoring of memory cell usage status, and optimization of erase / write allocation strategies, and to maximize the lifespan of EEPROM while ensuring data security and reliability, a method for polling and reading / writing data based on fine-grained management of EEPROM memory is proposed. The specific implementation process is as follows: Figure 1 As shown.

[0040] First, perform fine-grained partitioning of the EEPROM storage area, such as... Figure 2 As shown, the physical storage area of ​​the EEPROM is logically divided into two main functional areas: a data access area and a data storage backup area, with no address overlap between the partitions. The data access area is configured as the smallest erase / write unit of the EEPROM, with a uniform memory size, serving as a relay medium between the user and the data storage backup area. This temporarily caches user operation data, preventing direct user manipulation of the data storage backup area. The data storage backup area occupies the main memory of the EEPROM and is further divided into N independent block-shaped memory units. The size of each block-shaped memory unit should be greater than or equal to the size of the smallest erase / write unit. All these block-shaped memory units serve as the actual data carriers, supporting the function of long-term data storage.

[0041] A unique data access interface is then created, serving as the sole interaction channel between the user and the EEPROM, achieving physical isolation between the user and the data storage backup area. Users can only perform read and write operations through this interface, but cannot directly access the data, thus achieving data isolation. Simultaneously, this unique data access interface inherits data integrity verification functionality. During data writing, the user's intended data is verified; during data reading, the validity of data retrieved from the data storage backup area is verified. The integrity and validity verification are implemented using one or more combinations of CRC checksum, parity checksum, and SHA checksum, and are performed during user read and write operations. An address mapping function automatically maps the user's logical operations in the data access area to physical read and write operations in the data storage backup area, hiding the actual underlying storage address. A status feedback function returns the user's read and write operations and the current usage status of the EEPROM. Its interaction is as follows: Figure 3 As shown, specifically, firstly, the user initiates a read / write request, which is passed to the unique access interface. This interface integrates data verification, address mapping, and status feedback functions. During a write operation: the interface first forwards the user data and completes verification, then writes the data to the data access area cache. The data access area then transfers the cached data to the data storage backup area, where the backup area finally stores the data. During a read operation: the interface triggers the data access area to retrieve the target data from the storage backup area. After the access area caches the data, the interface reads the cached data. At the end of the process, the unique access interface returns the read / write status or the target data result to the user. Through the layered collaboration of each module, both secure data transfer and storage reliability are achieved.

[0042] Configure the erase and write block memory. Configure the memory of the data storage backup area into N block memory. Each block memory is exactly the same size. Its memory size should not be less than the memory size of the smallest erase and write unit of EEPROM. Each block memory serves as the actual data storage carrier of EEPROM.

[0043] Next, block memory monitoring is performed, such as... Figure 4 As shown, all block-shaped memory in the data storage backup area is monitored in real time, recording the actual usage of each block-shaped memory and classifying them into high-frequency usage areas, low-frequency usage areas, and damaged areas based on usage frequency. Specific operations include monitoring the actual usage of block-shaped memory, including the actual number of erase / write operations, data update frequency, data storage duration, and data erase / write errors. Based on the actual usage, erase / write frequency thresholds and consecutive erase / write error thresholds are manually set. Memory exceeding the erase / write frequency threshold is classified as a high-frequency usage area, below the erase / write frequency threshold as a low-frequency usage area, and above the consecutive erase / write error threshold as a damaged area, which is no longer used. The frequency thresholds support dynamic adjustment, which can be dynamically adjusted according to the total capacity of the EEPROM, the minimum erase / write unit, and the expected lifespan.

[0044] Finally, a data polling read / write strategy is adopted, operating through a unique data access interface. During data writing, the block memory is located by polling, prioritizing low-frequency usage areas for write operations. Similarly, during data reading, the same unique data access interface is called, and the read operation is completed after appropriate verification. The implementation flow of write and read operations is as follows: Figure 5 and Figure 6 As shown. During writing, after the user initiates a data write request, the data is first submitted through the unique data access interface. The interface performs data integrity verification on the data. If the verification passes, the data is temporarily stored in the data access area cache. Subsequently, the interface starts a round-robin search, skipping bad blocks of memory, prioritizing the selection of blocks of memory in low-frequency usage areas, and selecting the block with the fewest erase / write cycles as the target memory. Then, the original data in the target memory is erased, the cached data is written to the block of memory, and its erase / write cycles, usage frequency, and other status information are updated synchronously. Its round-robin strategy prioritizes low-frequency memory, which can balance the wear of each block of memory and significantly extend the overall lifespan of the EEPROM. The pre-verification and intermediate caching of the unique interface not only avoid illegal data writing but also simplify the user's operation logic. During data reading, a data read request is first initiated through the unique access interface, followed by the traversal of the block of memory. If the data is not found by the end of the traversal, the read failure status is returned directly, and the process ends here. If the data is found, the data validity verification is performed on the current block of memory. If the verification fails, the traversal cycle continues. If the verification passes, the block of memory is locked as the target memory. The system then attempts to read data from the target memory. If the read fails, it returns a read failure status; if the read succeeds, it returns a read success status, and the process ends. Its pre-processing block memory traversal and validity checks accurately filter out usable and valid storage blocks, avoiding invalid access to damaged or invalid memory and improving read accuracy. The step-by-step judgment logic (traversal status, data verification, data reading) makes the process more rigorous, effectively reducing the probability of read failures. Furthermore, the single access interface serves as a unified entry point, freeing users from concern themselves with the underlying traversal and verification details, simplifying the operation process and ensuring the stability and reliability of the read process.

[0045] In addition, it includes block memory status management operations, including: configuring status identifiers for each block memory, the identifiers including idle state, valid data state, and bad block state; counting the number of erase / write operations for each block memory through status identifiers, detecting and marking bad blocks in real time, and automatically skipping blocks memory in the bad block state during write operations. Specifically, each block memory is configured with status identifiers containing three categories: idle, valid data, and bad block: the idle state corresponds to available memory without stored data, the valid data state marks memory currently containing valid information, and the bad block state is used to mark memory that is damaged and cannot be read or written normally. The system will synchronously count the cumulative number of erase / write operations for each block memory based on these status identifiers and monitor its read / write stability in real time; when a block memory experiences consecutive read / write errors and reaches a set threshold, it will be automatically marked as a bad block, and its damage information will be recorded, completing the dynamic update of the status.

[0046] Example 2: Specific implementation based on 24C64 EEPROM. An external EEPROM chip 24C64 with an I2C interface is selected. Its capacity is 64KB, address range is 0x0000 ~ 0xFFFF, minimum erase / write unit is 16 bytes, and rated erase / write lifetime is 1 million cycles / byte. The embedded main control chip is S32K144, and communication with the EEPROM is achieved through the I2C bus.

[0047] Based on the hardware parameters of the 24C64, the configuration is performed. First, the memory is finely partitioned into a data access area and a data storage backup area. The data access area is 16 bytes in size, with an address range of 0x0000~0x000F. The data storage backup area is 64KB – 16B ≈ 64KB, divided into 8 independent blocks of memory. Each block is approximately 8KB in size, with the following address ranges: Block 0 (0x0010~0x1FFF), Block 1 (0x2000~0x3FFF), Block 2 (0x4000~0x5FFF), Block 3 (0x6000~0x7FFF), Block 4 (0x8000~0x9FFF), Block 5 (0xA000~0xBFFF), Block 6 (0xC000~0xDFFF), and Block 7 (0xEFFF~0xFFFF).

[0048] Secondly, a unique data access interface was created based on the S32K144's I2C driver. The interface functions are: `uint8_t EEPROM_Write(uint8_t *data, uint16_t len)`, which is the user's write interface and returns the write result (0 for success, 1 for failure); `uint8_t EEPROM_Read(uint8_t *data_buf, uint16_t len)`, which is the user's data read interface, returning 0 for success and 1 for failure; and `uint8_t EEPROM_GetStatus(uint8_t *free_blocks, uint8_t *bad_blocks)`, which is the status query interface, returning the number of remaining available block memory and the number of bad blocks. Simultaneously, the interface integrates a CRC16 checksum function. A checksum is calculated during data writing, stored together with the data, and verified during data reading to ensure data validity.

[0049] Next, the block memory is monitored in real time and divided into high-frequency, low-frequency, and bad block areas. Frequency thresholds are set. In this embodiment, the EEPROM has a rated erase / write lifespan of 1 million cycles, and the number of block memory units N=8. The initial frequency threshold is set to 1 million cycles / 8 = 125,000 cycles. When the number of write cycles for a block memory exceeds this frequency threshold, it is marked as a high-frequency area; otherwise, it is marked as a low-frequency area. Simultaneously, after each data write and read operation by the user, statistics are performed. If the written and read data differ, a count is added. If a block memory experiences three or more consecutive errors, it is marked as a bad block, and subsequent user operations will automatically skip this block memory.

[0050] Finally, a priority-based round-robin write-read process is implemented. When a user performs a write operation, the `EEPROM_Write(data, len)` interface function is called to write data to the access area. After passing the corresponding verification, the data is then written to the data storage backup area. During the write operation, each block of memory is polled and searched, skipping bad blocks and prioritizing low-frequency areas. When there is no free block of memory in the low-frequency area, the high-frequency area is searched. The priority is sorted according to the actual number of writes to the block of memory, and the write operation is performed from low to high. When a user reads data, the corresponding read data interface is called, and the read operation is completed after passing the corresponding verification.

[0051] Furthermore, a lifespan comparison test was conducted based on the configurations of the above embodiments. The traditional solution terminated the overall lifespan of the EEPROM after 1 million write cycles, while the solution of the present invention achieved 8 million write cycles, thus extending the lifespan.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments for application in other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for polling and reading / writing data based on fine-grained management of EEPROM memory, characterized in that, Includes the following steps: S1. First, perform fine-grained EEPROM memory partitioning, manually dividing the EEPROM memory into a data access area and a data storage backup area, wherein the data access area is configured as the smallest data erase / write unit of the EEPROM. S2. Create a unique data access interface to isolate users from the actual data storage backup area. Users can only perform data read and write operations through the unique interface to achieve data isolation. S3. Configure erase and write block memory, divide the data storage backup area into multiple independent block memory, the size of each block memory should not be less than the size of the smallest erase and write unit memory of EEPROM, and each block memory serves as the actual data storage carrier of EEPROM. S4, Block Memory Monitoring, performs real-time monitoring of all block memory, records the actual usage of each block memory, and classifies it into high-frequency use area, low-frequency use area and damaged area according to the number of times it is used; S5. A data polling read / write strategy is adopted, and operations are performed through a unique data access interface. When writing data, the block memory is located by polling, and the block memory in the low-frequency use area is selected first to perform the data writing operation. When reading data, the same unique data access interface is called, and the reading operation is completed after passing the corresponding verification. The system includes a unique data access interface, which serves as the sole interaction channel between the user and the EEPROM, achieving physical isolation between the user and the data storage backup area. Users can only perform read and write operations through this interface and cannot directly access the EEPROM, thus achieving data isolation. This unique data access interface also inherits data integrity verification functionality, verifying the data the user intends to manipulate during data writing and verifying the validity of data read from the data storage backup area during data reading. The integrity and validity verification are implemented using one or more combinations of CRC checksum, parity checksum, and SHA checksum, and are performed during user read and write operations. An address mapping function automatically maps the user's logical operations in the data access area to physical read and write operations in the data storage backup area, hiding the actual underlying storage address. A status feedback function returns information about the user's read and write operations and the current usage status of the EEPROM. In step S5, the block memory in the low-frequency usage area is selected first to perform data writing operations, including: polling and searching all the block memory in the low-frequency usage area, and prioritizing the block memory with the fewest write operations; If no low-frequency usage area has free block memory, continue polling and searching for block memory in the high-frequency usage area, selecting target block memory in order of increasing actual erase / write count.

2. The method for polling and reading / writing data based on fine-grained management of EEPROM memory according to claim 1, characterized in that, In step S1, the memory size of the data access area is the same as the memory size of the smallest erase / write unit of the EEPROM. It is used to temporarily cache the actual data of user interaction and to serve as a transfer medium between the user and the data storage backup area.

3. The method for polling and reading / writing data based on fine-grained management of EEPROM memory according to claim 1, characterized in that, In step S2, the unique data access interface inherits the data integrity verification function. When writing data, the data that the user wants to operate on is verified, and when reading data, the validity of the data read from the data storage backup area is verified. The integrity verification and validity verification are implemented using one or more combinations of CRC verification, parity verification, and SHA verification.

4. The method for polling and reading / writing data based on fine-grained management of EEPROM memory according to claim 1, characterized in that, In step S3, the size of each block of memory in the data storage backup area is exactly the same, and the size of each block of memory is not less than the size of the memory in the data access area.

5. The method for polling and reading / writing data based on fine-grained management of EEPROM memory according to claim 1, characterized in that, In step S4, the actual usage of the block memory includes the actual number of erase / write operations, data update frequency, data storage duration, and data erase / write error situation of each block memory. Based on the actual usage, the erase / write frequency threshold and the continuous erase / write error threshold are manually set. If the value is higher than the erase / write frequency threshold, it is classified as a high-frequency usage area; if it is lower than the erase / write frequency threshold, it is classified as a low-frequency usage area; and if it is higher than the continuous erase / write error threshold, it is classified as a damaged area and is no longer used.

6. The method for polling and reading / writing data based on fine-grained management of EEPROM memory according to claim 5, characterized in that, The erase / write frequency threshold is dynamically adjusted based on the total capacity of the EEPROM, the minimum erase / write unit, and the expected lifespan.

7. The method for polling and reading / writing data based on fine-grained management of EEPROM memory according to claim 1, characterized in that, It also includes block memory status management operations, including: configuring a status identifier for each block memory, the identifier including idle status, valid data status and bad block status; counting the number of erase and write operations for each block memory through the status identifier, detecting bad blocks in real time and marking them, and automatically skipping block memory in the bad block status when writing.

8. The method for polling and reading / writing data based on fine-grained management of EEPROM memory according to claim 1, characterized in that, The data writing operation in step S5 includes: S51. Users write data to the data access area through the unique data access interface. S52. The unique data access interface performs integrity verification on the cached data in the data access area. S53. After the verification is passed, the unique data access interface polls and retrieves the block memory in a round-robin fashion, and determines the target memory according to the priority. S54. Erase the existing data in the target block memory; S55. Write the cached data of the data access area into the target memory; S56. Update the usage record of this block memory, and synchronously adjust the division results of the high-frequency usage area, low-frequency usage area and damaged area.

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