Method for realizing full adder based on Flash

Abstract

The invention relates to a method for realizing a full adder based on Flash, and belongs to the technical field of Flash storage and calculation fusion. The invention designs a full adder implementation method based on the association of inherent characteristics (multi-word line sensing (MWS), RowCopy operation and NOT logic) of Flash and multi-input majority voting (MAJ3 / MAJ5) operation, is suitable for machine learning multiply-accumulate (MAC), edge AI reasoning and other data intensive internal memory calculation scenes, and does not need to perform structural modification on Flash hardware.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of Flash storage and computing fusion, and particularly relates to a method for implementing a full adder based on Flash. BACKGROUND

[0002] Under the background that in-memory computing (PIM) becomes a key direction to break through the "memory wall", commercial Flash has significant advantages in future in-memory computing due to its inherent characteristics: first, Flash has a storage density far exceeding DRAM, and the single-chip capacity can reach hundreds of GB, which can support the localized storage and computing of large-scale data and avoid frequent data migration caused by the separation of storage and computing; second, the non-volatility of Flash can reduce the energy consumption in the computing process (no need to refresh continuously), which is suitable for low-power in-memory computing scenarios such as edge devices and Internet of Things terminals; third, commercial Flash has realized large-scale production, has strong hardware compatibility and controllable cost, and can deploy in-memory computing capabilities without customized chips, providing a feasible path for the popularization of PIM technology; fourth, Flash supports multi-word line sensing (MWS) and simultaneous multi-row and column activation (SiMRA) operations, which can naturally adapt to the parallel logical operations required by in-memory computing and provide a hardware basis for efficient implementation of full adder and other basic units.

[0003] The full adder is a core unit of arithmetic operation, which is responsible for the summation (S) of two input bits (A, B) and carry input (C_in) and the calculation of carry output (C_out), and its core logic relationship is: C_out=(A∧B)∨(A∧C_in)∨(B∧C_in), S=A XOR B XOR C_in, which is the basis for building complex operations such as multiplication and matrix operation, and these complex operations are the core support for data-intensive tasks such as machine learning multiply-accumulate (MAC) and edge AI inference.

[0004] Therefore, it is urgent to design a Flash-based full adder implementation method to improve the efficiency and reliability of full add operation in Flash. SUMMARY

[0005] (I) Technical problem to be solved

[0006] The technical problem to be solved by the application is to overcome the defects of multiple operation steps and error accumulation of the existing Flash full adder, and to provide a Flash-based full adder implementation method, which directly matches the MSB logic to calculate C_out using MAJ3 operation, matches the LSB logic to calculate S using MAJ5 operation, and realizes efficient and low-error full add operation by combining the RowCopy and NOT operations of Flash without additional hardware modification.

[0007] (II) Technical scheme

[0008] To solve the above technical problems, the application provides a method for implementing a full adder based on Flash, comprising the following steps:

[0009] Step S1: input data loading and subarray arrangement

[0010] A subarray of the Flash is selected, and the input bits A, B and the carry-in C_in of the full adder are respectively migrated to three independent word lines WL_A, WL_B and WL_Cin of the subarray through the RowCopy operation of the Flash;

[0011] The data randomization function of the Flash is enabled during data writing, so that the original bit states of A, B and C_in are stable, and the three independent word lines are located in adjacent regions of the same subarray;

[0012] Step S2: calculation of the carry-out C_out based on the MAJ3 operation

[0013] SiMRA activation and MAJ3 implementation: the SiMRA function of the Flash is called, and an activation command ACT is applied to WL_A, WL_B and WL_Cin, so that the charges of the three independent word lines are redistributed on the shared bit line; if the number of "1"s in A, B and C_in is greater than or equal to 2, that is, (A∧B)∨(A∧C_in)∨(B∧C_in) is satisfied, and the total charge of the bit line is greater than or equal to 1.5 times the full charge of a single word line, then the sensor in the Flash outputs "1"; if the number of "1"s is less than or equal to 1, then the sensor in the Flash outputs "0"; the output result of the sensor is the SiMRA sensing result;

[0014] C_out output and storage: the SiMRA sensing result is the output of the MAJ3 operation, and completely matches the logical definition of MSB(A, B, C), so that it is taken as the carry-out C_out and temporarily stored in a cache latch L_Cout of the Flash;

[0015] Step S3: calculation of the sum result S based on the MAJ5 operation

[0016] Reference row generation: the NOT logical operation of the Flash is called to read C_out in the cache latch L_Cout and generate the inverse value of C_out C_out, and C_out is written into two reference word lines WL_REF1 and WL_REF2 of the same subarray through RowCopy;

[0017] ​SiMRA activation and MAJ5 implementation: perform SiMRA operation while activating WL_A, WL_B, WL_Cin, WL_REF1, WL_REF2 five word lines, and use charge sharing to implement MAJ5 operation; the total charge of the bit line is jointly determined by the charges of "A, B, C_in + 2 reference rows of C_out", and the sensor outputs the sum result S according to the parity of 1: if the sum result S is "1", it indicates that the number of "1" in A, B, C_in is 1 or 3; if the sum result S is "0", it indicates that the number of "1" is 0 or 2; C_out reference row of C_out", and the sensor outputs the sum result S according to the parity of 1: if the sum result S is "1", it indicates that the number of "1" in A, B, C_in is 1 or 3; if the sum result S is "0", it indicates that the number of "1" is 0 or 2;

[0018] S output and storage: the operation result of MAJ5 is the sum result S, which is temporarily stored in another cache latch L_S of Flash;

[0019] Step S4: result verification and output

[0020] Inverse operation verification: based on the inverse logic of the full adder, the S stored in L_S is verified; if the input is A, B, C_in, the input bits are backtracked through A' = S XOR B XOR C_in or B' = S XOR A XOR C_in, if the backtracked result A', B' is consistent with the original input, it is considered that the inverse operation verification is successful, that is, it is determined that the operation result S is valid; if the inverse operation verification fails, steps S2-S3 are re-executed;

[0021] Result output: through the read command RD of Flash, the S stored in L_S and the C_out stored in L_Cout are written from the corresponding cache latch to the target storage address of Flash.

[0022] The application also provides a full adder designed based on the method.

[0023] The application also provides a working method of the full adder.

[0024] The application also provides a use method of the full adder.

[0025] (Three) beneficial effects

[0026] Based on the inherent characteristics of Flash (multi-word line sensing MWS, RowCopy operation, NOT logic) and the correlation of multi-input majority voting (MAJ3 / MAJ5) operation, the application designs a full adder implementation method, which is suitable for machine learning multiply-accumulate (MAC), edge AI inference and other data-intensive in-memory computing scenarios, without structural modification of Flash hardware. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 Loading diagram for subarray input data;

[0028] Figure 2 Diagram for calculating carry-out C_out based on MAJ3 operation;

[0029] Figure 3 Diagram for placing carry-out C_out negation to designated two rows;

[0030] Figure 4 Diagram for calculating sum result S based on MAJ5 operation. DETAILED DESCRIPTION

[0031] In order to make the objects, contents and advantages of the present application clearer, the specific embodiments of the present application are further described in detail below in combination with the drawings and examples.

[0032] In order to solve the problems of many operation steps and error accumulation in the full adder operation in the existing Flash, the present application provides a Flash-based full adder implementation method, which uses MAJ3 operation to directly match MSB logic to calculate C_out, uses MAJ5 operation to match LSB logic to calculate S, and combines RowCopy and NOT operation of Flash to realize efficient and low-error full add operation without additional hardware modification.

[0033] The method is a Flash and MAJ3 / MAJ5 operation-based full adder implementation method, which simplifies operation steps and reduces errors through MAJx, and at the same time matches the specified MSB / LSB logic expression to improve the efficiency and reliability of the full add operation in the Flash.

[0034] The present application is based on the principle of "full adder = MAJ3 algorithm carry (C_out) + MAJ5 algorithm sum (S) + Flash inherent operation support", and uses the following characteristics of Flash and the association of MAJx operation to realize:

[0035] Association of MAJ3 and C_out: the logic of C_out = (A and B) or (A and C_in) or (B and C_in) is completely consistent with the MSB (A, B, C) = (A and B) or (B and C) or (C and A), and the commercial Flash can activate three word lines of A, B and C_in through block MWS, realize MAJ3 operation by using charge sharing, and output C_out in a single sensing;

[0036] Association of MAJ5 and S: the result of S = A XOR B XOR C_in is equivalent to the parity of the number of "1" in the input bit, and The logic precisely reflects the parity of the number of "1"s (LSB = 1 when there are 1 or 3 "1"s, LSB = 0 when there are 0 or 2 "1"s). Commercial Flash memory can perform operations via MAJ5 (combined with...). The C_out reference line implements LSB output, i.e., S;

[0037] Flash support operations: RowCopy is used to migrate A, B, and C_in to the same subarray (ensuring charge sharing in MAJx), and the NOT operation is used to generate the necessary data for MAJ5. The C_out reference line requires no additional hardware.

[0038] Based on the above principles, this method includes the following steps:

[0039] Step S1: Input data loading and subarray arrangement

[0040] Select a subarray of commercial 3D NAND Flash (containing ≥5 available word lines, supporting SiMRA), and use the Flash's standard RowCopy operation to migrate the input bits A, B and carry input C_in of the full adder to the three independent word lines of the subarray (denoted as WL_A, WL_B, and WL_Cin, respectively).

[0041] When writing data, the Flash data randomization function is enabled (to suppress program interference caused by consecutive identical bits), ensuring that the original bit states of A, B, and C_in are stable ("0" corresponds to no charge, and "1" corresponds to full charge), and the three independent word lines are located in adjacent areas of the same subarray, satisfying the charge sharing conditions of commercial Flash multi-row and column activation (SiMRA).

[0042] Step S2: Calculate the carry output (C_out) based on MAJ3 operation.

[0043] SiMRA Activation and MAJ3 Implementation: The SiMRA function of commercial Flash memory is invoked, and activation commands (ACT) are applied to WL_A, WL_B, and WL_Cin simultaneously. This violates the traditional single-row / column activation timing of DRAM / Flash, causing the charge of the three independent word lines to redistribute on the shared bit line. If the number of "1"s in A, B, and C_in is ≥2 (i.e., satisfying (A∧B)∨(A∧C_in)∨(B∧C_in)), and the total charge of the bit line is ≥1.5 times the full charge of a single word line, then the sensor amplifier in the Flash memory outputs "1"; if the number of "1"s is ≤1, then the sensor amplifier in the Flash memory outputs "0". The output result of the sensor amplifier is the SiMRA sensing result.

[0044] C_out output and storage: the SiMRA sensing result is the MAJ3 operation output, and completely matches the logic definition of MSB(A, B, C), and is taken as the carry output C_out and temporarily stored in a cache latch (L_Cout) of the Flash;

[0045] This step only needs 1 MAJ3 operation, replaces 5 AND / OR continuous operations in the traditional method, and reduces the delay from 5 μs to 1.5-2 μs, and reduces the error link by 80%.

[0046] Step S3: calculating the sum result (S) based on the MAJ5 operation

[0047] Reference row generation: calling the NOT logic operation of the Flash, reading C_out in the cache latch L_Cout, generating the inverse value thereof C_out, and writing C_out into the other two reference word lines WL_REF1 and WL_REF2 of the same subarray through RowCopy, to ensure that the two reference word lines are adjacent to WL_A, WL_B and WL_Cin;

[0048] SiMRA activation and MAJ5 implementation: performing the SiMRA operation, simultaneously activating the five word lines WL_A, WL_B, WL_Cin, WL_REF1 and WL_REF2, and implementing the MAJ5 operation by using charge sharing-the total charge of the bit line is jointly determined by the charges of A, B and C_in and the charges of the two C_out reference rows, and the sensing amplifier outputs the sum result S according to the parity of 1: if the sum result S is “1”, it indicates that the number of “1” in A, B and C_in is 1 or 3 (satisfying the logic definition of LSB(A, B, C), that is, S=1); if the sum result S is “0”, it indicates that the number of “1” is 0 or 2 (that is, S=0);

[0049] S output and storage: the MAJ5 operation result is the sum result S, which is temporarily stored in another cache latch (L_S) of the Flash, and completely matches the logic of S=A XOR B XOR C_in (because the parity judgment of LSB is consistent with the XOR result);

[0050] This step only needs 1 MAJ5 operation, replaces 2 XOR continuous operations in the traditional method, and reduces the delay from 3 μs to 2-2.5 μs.

[0051] Step S4: result verification and output

[0052] ​​Inverse operation verification: based on the inverse logic of full adder, the verification is performed on S stored in L_S and C_out stored in L_Cout--if the input is A, B, C_in, the input bit can be deduced through A'=S XOR B XOR C_in or B'=S XOR A XOR C_in, if the deduced result A', B' is consistent with the original input (i.e. the input bit A, B in step S1), it is considered that the inverse operation verification is successful, that is, it is determined that the operation result S is valid; if the inverse operation verification fails, steps S2-S3 are re-executed to ensure the reliability of the operation result S;

[0053] Result output: through the conventional read command (RD) of the Flash, S stored in L_S and C_out stored in L_Cout are written from the corresponding cache latches to the target storage address of the Flash, for subsequent complex operation (such as MAC, matrix multiplication) calling.

[0054] The above only describes the preferred embodiments of the present application, and it should be noted that for those skilled in the art, without departing from the technical principles of the present application, a number of improvements and modifications can be made, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. A method for implementing a full adder based on Flash memory, characterized in that, Includes the following steps: Step S1: Input data loading and subarray arrangement Select a subarray of Flash, and use the Flash RowCopy operation to migrate the input bits A, B and carry input C_in of the full adder to the three independent word lines of the subarray, denoted as WL_A, WL_B and WL_Cin respectively. When writing data, the Flash data randomization function is enabled to ensure that the original bit states of A, B, and C_in are stable and that the three independent word lines are located in adjacent areas of the same subarray. Step S2: Calculate the carry output C_out based on MAJ3 operation SiMRA Activation and MAJ3 Implementation: The SiMRA function of Flash is invoked, and the activation command ACT is applied to WL_A, WL_B, and WL_Cin simultaneously, causing the charge of the three independent word lines to redistribute on the shared bit line. If the number of "1"s in A, B, and C_in is ≥2, i.e., satisfying (A∧B)∨(A∧C_in)∨(B∧C_in), and the total charge of the bit line is ≥1.5 times the full charge of a single word line, then the sensor in Flash outputs "1". If the number of "1"s is ≤1, then the sensor in Flash outputs "0". The sensor output is the SiMRA sensing result. C_out output and storage: The SiMRA sensing result is the MAJ3 operation output, which perfectly matches the logic definition of MSB(A,B,C). It is used as the carry output C_out and temporarily stored in a Flash cache latch L_Cout. Step S3: Calculate the summation result S based on the MAJ5 operation. Reference line generation: Call the Flash NOT logic operation, read C_out from the buffer latch L_Cout, and generate its inverse value. and through RowCopy Write to the other two reference word lines WL_REF1 and WL_REF2 of the same subarray; SiMRA Activation and MAJ5 Implementation: Perform SiMRA operations to simultaneously activate five word lines: WL_A, WL_B, WL_Cin, WL_REF1, and WL_REF2. MAJ5 operations are implemented using charge sharing. The total bit line charge consists of the charges of "A, B, C_in" plus the charges of the two word lines. The charge of the reference row determines the summation result S of the sensor based on whether the summation result S is "1" or "3" in A, B, and C_in; if the summation result S is "0", it means that the summation result S is "0" or "2". S Output and Storage: The result of MAJ5's operation is the summation result S, which is temporarily stored in another cache latch L_S in Flash; Step S4: Result Verification and Output Inverse operation verification: Based on the inverse logic of the full adder, the S stored in L_S is verified; if the input is A, B, C_in, the input bits are reversed by A' = S XOR B XOR C_in or B' = S XOR A XOR C_in. If the reversed results A' and B' are consistent with the original input, the inverse operation verification is considered successful, that is, the operation result S is determined to be valid; if the inverse operation verification fails, steps S2 to S3 are re-executed. Output: Using the Flash read command RD, S stored in L_S and C_out stored in L_Cout are written from the corresponding cache latches to the target memory address of Flash.

2. The method as described in claim 4, characterized in that, This Flash is a 3D NAND Flash.

3. The method as described in claim 4, characterized in that, Step S4 also involves verifying C_out stored in L_Cout.

4. A full adder designed based on the method described in claim 1, 2 or 3.

5. The full adder as described in claim 4, characterized in that, This full adder is used in in-memory computation.

6. The full adder as described in claim 4, characterized in that, This full adder is used in Flash storage.

7. The full adder as described in claim 4, characterized in that, This full adder is used in computational fusion.

8. The full adder as described in claim 4, characterized in that, This full adder is used in edge AI inference.

9. A method of operating the full adder as described in claim 4.

10. A method of using the full adder as described in claim 4.

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