An instruction verification method, apparatus, device, and storage medium

Abstract

This application provides an instruction verification method, apparatus, device, and storage medium, relating to the field of chip design verification technology. The method includes: dividing the instruction to be verified according to a preset multi-layer instruction structure to obtain at least one instruction block corresponding to the multi-layer instruction structure; the instruction to be verified is a composite instruction including multiple basic instructions; the multi-layer instruction structure is used to characterize the basis for dividing the instruction blocks from the perspective of instruction function, and each instruction block has its own function; randomly generating a first verification instruction block based on a first instruction block, and generating a second verification instruction block based on the first verification instruction block and a second instruction block; wherein the first instruction block is an instruction block without constraints on other instruction blocks, and the second instruction block is constrained by the first instruction block; obtaining verification instructions based on each verification instruction block corresponding to at least one instruction block; and verifying the instruction to be verified using the verification instructions. This improves the random efficiency and fairness of instruction verification.

Description

Technical Field

[0001] This invention relates to the field of chip design verification technology, and in particular to an instruction verification method, apparatus, device and storage medium. Background Technology

[0002] In chip design or GPU technologies, instructions need to be verified for correctness after design. During instruction verification, a verification instruction is randomly generated from a large pool of instruction types, formats, or addresses. This verification instruction is then used to determine whether the instruction behaves correctly.

[0003] However, due to the large number of instructions, the complex format, and the mutual constraints between different types of instructions, the efficiency of randomly generating a verification instruction is low. Furthermore, due to the constraints, some instructions cannot be randomly generated, affecting the fairness of instruction randomization. Summary of the Invention

[0004] This application provides an instruction verification method, apparatus, device, and storage medium to improve the efficiency of instruction verification.

[0005] In a first aspect, embodiments of this application provide an instruction verification method, including:

[0006] According to the preset multi-level instruction structure, the instruction to be verified is divided to obtain at least one instruction block corresponding to the multi-level instruction structure; the instruction to be verified is a composite instruction including multiple basic instructions; the multi-level instruction structure is used to characterize the basis for dividing the instruction block from the perspective of instruction function, and each instruction block has its own function.

[0007] A first verification instruction block is randomly generated based on a first instruction block, and a second verification instruction block is generated based on the first verification instruction block and a second instruction block; wherein, the first instruction block is an instruction block that has no constraint relationship with other instruction blocks, and the second instruction block is constrained by the first instruction block;

[0008] Based on each verification instruction block corresponding to the at least one instruction block, a verification instruction is obtained;

[0009] The verification instruction is used to verify the instruction to be verified.

[0010] In this embodiment, by dividing the instruction to be verified according to a preset instruction structure, instruction blocks corresponding to each layer of instruction structure are obtained. This allows for a clear understanding of the function of each part of the instruction. When the instruction is randomized, all the divided instruction blocks can be randomized, thus avoiding the inability to randomize certain instruction blocks and improving the fairness of instruction randomization. The random order between instruction blocks is determined according to the constraint relationship between each instruction block, so that constrained instruction blocks are randomized later and unconstrained instruction blocks are randomized first. This avoids errors in the generated random instructions due to constraint issues and improves the efficiency of instruction randomization.

[0011] Optionally, the multi-layer instruction structure includes an infrastructure layer, a formatting layer, and a resource management layer;

[0012] The infrastructure layer represents instruction blocks composed of basic instructions that are independent of the execution behavior of instructions;

[0013] The formatting layer represents a block of instructions composed of basic instructions related to the execution behavior of the instructions;

[0014] The resource management layer represents the instruction block composed of basic instructions related to the resources required by the instructions.

[0015] In this embodiment, the instruction structure is divided into an infrastructure layer, a formatting layer, and a resource management layer. From the multi-layered instruction structure, it can be determined which instruction blocks are unconstrained and which instruction blocks are constrained by other instruction blocks, which facilitates the subsequent determination of the random order of instructions.

[0016] Optionally, the formatting layer includes a parameter metadata layer and a hardware execution information layer; the parameter metadata layer represents the metadata of the instruction execution object; and the hardware execution information layer represents the basic information of the hardware where the instruction execution takes place.

[0017] In this embodiment, the instruction structure of the formatting layer is further divided into layers to obtain instruction blocks corresponding to each layer. This ensures that even in a complex instruction structure, instruction blocks can be randomly generated, further guaranteeing the fairness of instruction randomization.

[0018] Optionally, for each first instruction block that has no constraint relationship, a corresponding first verification instruction block is generated in parallel randomization.

[0019] In this embodiment of the application, by randomly randomizing instruction blocks that do not have any constraints in parallel, the speed of instruction randomization can be improved without waiting for other instruction blocks to finish randomizing.

[0020] Optionally, after obtaining at least one instruction block corresponding to the multi-layer instruction structure and before generating the corresponding first verification instruction blocks in parallel randomization, the method further includes:

[0021] The at least one instruction block and the randomization method are summarized into a verification instruction code set;

[0022] Randomizing the generation of a verification instruction block corresponding to each instruction block in the at least one instruction block includes:

[0023] The verification instruction code set is used to randomly generate a verification instruction block corresponding to each instruction block in the at least one instruction block.

[0024] In this embodiment of the application, by summarizing each instruction block and the randomization generation method into a verification instruction code set, and using the verification instruction code set to generate verification instruction blocks, the individual instruction blocks of the instruction to be verified can be clearly identified, thereby quickly generating verification instruction blocks.

[0025] Optionally, the infrastructure layer includes one or more of instruction types, instruction codes, and synchronization methods; the formatting layer includes one or more of data types, data sizes, and operands; and the resource management layer includes one or more of registers and memory access addresses.

[0026] Secondly, embodiments of this application provide an instruction verification device, comprising:

[0027] The partitioning module is used to partition the instruction to be verified according to a preset multi-level instruction structure to obtain at least one instruction block corresponding to the multi-level instruction structure; the instruction to be verified is a composite instruction including multiple basic instructions; the multi-level instruction structure is used to characterize the basis for partitioning the instruction block from the perspective of instruction function, and each instruction block has its own function.

[0028] The generation module is used to randomly generate a first verification instruction block based on a first instruction block, and to generate a second verification instruction block based on the first verification instruction block and a second instruction block; wherein, the first instruction block is an instruction block that has no constraint relationship with other instruction blocks, and the second instruction block is constrained by the first instruction block;

[0029] The verification module is used to obtain verification instructions based on each verification instruction block corresponding to the at least one instruction block;

[0030] The verification module is also used to verify the instruction to be verified through the verification instruction.

[0031] Optionally, the multi-layer instruction structure includes an infrastructure layer, a formatting layer, and a resource management layer;

[0032] The infrastructure layer represents instruction blocks composed of basic instructions that are independent of the execution behavior of instructions;

[0033] The formatting layer represents a block of instructions composed of basic instructions related to the execution behavior of the instructions;

[0034] The resource management layer represents the instruction block composed of basic instructions related to the resources required by the instructions.

[0035] Optionally, the formatting layer includes a parameter metadata layer and a hardware execution information layer;

[0036] The parameter metadata layer represents the metadata of the instruction execution object;

[0037] The hardware execution information layer represents the basic information of the hardware in which the instruction is executed.

[0038] Optionally, the generation module is specifically used for:

[0039] For each first instruction block that has no constraints, a corresponding first verification instruction block is generated in parallel randomization.

[0040] Optionally, the generation module is further configured to:

[0041] The at least one instruction block and the randomization method are summarized into a verification instruction code set;

[0042] Optionally, the generation module is specifically used for:

[0043] The verification instruction code set is used to randomly generate a verification instruction block corresponding to each instruction block in the at least one instruction block.

[0044] Optionally, the infrastructure layer includes one or more of the following: instruction type, instruction code, and synchronization method;

[0045] The formatting layer includes one or more of the following: data type, data size, and operands;

[0046] The resource management layer includes one or more of registers and memory access addresses.

[0047] Thirdly, embodiments of this application provide a computer device, including a memory, an artificial intelligence chip, and a computer program stored in the memory and executable on the artificial intelligence chip, wherein the artificial intelligence chip executes the computer program to implement the steps of the above-described instruction verification method.

[0048] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the above-described instruction verification method.

[0049] Fifthly, embodiments of this application provide a computer program product, the computer program product including a computer program stored on a computer-readable storage medium, the computer program including program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the above-described instruction verification method.

[0050] In this embodiment, by dividing the instruction to be verified according to a preset instruction structure, instruction blocks corresponding to each layer of instruction structure are obtained. This allows for a clear understanding of the function of each part of the instruction. When the instruction is randomized, all the divided instruction blocks can be randomized, thus avoiding the inability to randomize certain instruction blocks and improving the fairness of instruction randomization. The random order between instruction blocks is determined according to the constraint relationship between each instruction block, so that constrained instruction blocks are randomized later and unconstrained instruction blocks are randomized first. This avoids errors in the generated random instructions due to constraint issues and improves the efficiency of instruction randomization. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A structural diagram of an artificial intelligence chip provided in an embodiment of this application;

[0053] Figure 2 A flowchart illustrating an instruction verification method provided in an embodiment of this application;

[0054] Figure 3 A flowchart illustrating a method for randomly generating verification instruction blocks provided in an embodiment of this application;

[0055] Figure 4 This is a schematic diagram of the structure of an instruction verification device provided in an embodiment of this application;

[0056] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0057] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0058] refer to Figure 1This is a structural diagram of an artificial intelligence chip applicable to embodiments of this application. The artificial intelligence chip 100 includes at least: multiple computing cores 101, on-chip cache 102, and video memory 103. The computing cores 101 include registers 1011.

[0059] Artificial intelligence chips 100 can be: Central Processing Unit (CPU), Graphics Processing Unit (GPU), General-purpose computing on graphics processing units (GPGPU), Domain-Specific Architecture (DSA), etc.

[0060] The computing core 101 fetches instructions from register 1011, on-chip cache 102, or video memory 103.

[0061] If the instructions cached in register 1011 can meet the computational needs of computing core 101, then instructions are provided to computing core 101 through register 1011.

[0062] If the instructions cached in register 1011 cannot meet the computational needs of computing core 101, then instructions are provided to computing core 101 through on-chip cache 102.

[0063] If the instructions cached in the on-chip cache 102 cannot meet the computational needs of the computing core 101, then the instructions are provided to the computing core 101 through the video memory 103.

[0064] In instruction verification, the randomly generated instructions are not created randomly, but rather generated according to constraints. When generating random instructions, the hardware and syntax rules of the instructions must first be clearly defined. Then, random generation starts from the smallest field of the instruction, and finally, the instructions are concatenated and verified to ensure that the instructions can be used for verification and possess both randomness and validity.

[0065] An instruction is the smallest unit of operation that a computing core can recognize and execute; it serves as the interface bridge between software and hardware. Essentially, it is binary code containing "operation type," "operand address / value," and "execution control information." The core components of an instruction are the opcode, operands, and control fields.

[0066] The opcode specifies the type of operation performed by the instruction (such as addition, multiplication, memory read / write, branch jump). Operands specify the objects of the operation, which can be categorized as: register operands (such as CPU general-purpose registers X0-X31, GPU SIMD registers R0-R255); immediate values ​​(constants directly embedded in the instruction, such as #10 in ADD W0, W0, #10); memory addresses (calculated through the addressing mode, such as LDR W0, [X1, #8] indicating loading data from memory address X1+8). Control fields include conditional execution bits, privilege level flags, and exception suppression bits.

[0067] When generating random instructions, the generation constraints and basic rules need to be clearly defined in the early stages, such as:

[0068] Extracting Hardware and Instruction Information: First, obtain the key configurations of the computing core under test, such as supported instruction types (e.g., FMA, ADD, atomic instructions, etc.), register model (number of GPRs, access permissions, register sets corresponding to data types), and the value range of immediate values ​​(e.g., -2^31 to 2^31 -1 for INT32 immediate values). Simultaneously, clarify core rules, such as FP64 instructions only adapting to 64-bit registers, and the memory addresses of atomic instructions needing to be aligned.

[0069] Define multi-level constraints: Divide constraints according to the instruction level. The field level limits the value of each field (e.g., the opcode field only supports 0x0D corresponding to FMA.F32); the instruction level specifies the instruction format (e.g., the order of opcode + source register 1 + source register 2 + destination register); if subsequent combination of instruction blocks is required, the association constraints between instructions also need to be defined (e.g., whether resource dependencies are allowed, whether abnormal scenarios need to be simulated).

[0070] Random instruction generation in steps: random construction from fields to complete instruction. An instruction is essentially composed of fields such as opcode, register address, and immediate value concatenated in a fixed format. Generation can be performed in the order of "random field generation → compliant field concatenation," with the specific steps as follows:

[0071] Randomly generate instruction fields: For each field of the instruction, call the corresponding generation function to randomly select a value within the constraints. For example, when generating the opcode, a valid opcode is randomly selected according to the encoding rules, such as randomly selecting 0x0A corresponding to the ADD.I32 instruction; when generating register fields, an address is randomly selected from the register set supported by the computing core, such as selecting R10 from R0-R255 as the source register 1; when generating immediate values, values ​​are randomly generated according to the data type, such as randomly generating the immediate value 123 for the ADD.I32 instruction. If it is necessary to simulate abnormal scenarios, some out-of-bounds fields (such as register addresses that are out of range) can also be deliberately generated.

[0072] Compliant concatenation into a complete instruction: Following the format rules corresponding to the instruction type, the randomly generated fields are concatenated. For example, the format of the ADD.I32 instruction is "opcode + source register 1 + source register 2 + destination register". If the generated fields are 0x0A, R10, 123, and R20 respectively, then the concatenated result is the instruction "ADD.I32 R20, R10,123". This is then converted into binary instruction code recognizable by the Core to complete the construction of a single instruction.

[0073] Randomly concatenated instructions may contain hidden violations (such as fields that are compliant individually but conflict when combined), requiring additional validation and filtering to prevent invalid instructions from entering the verification process.

[0074] Perform compliance checks. Iterate through and check instructions using predefined constraint rules, such as determining if the operand types match the registers (e.g., whether an FP32 instruction misuses an integer register) and if immediate values ​​exceed the supported range of the current instruction. If a violation is found, discard the instruction and regenerate it.

[0075] Simple function pre-validation. Instructions can be input into a simple instruction simulator to quickly determine if there are obvious logical errors (such as null pointer access or invalid results caused by arithmetic overflow). For example, if the generated subtraction instruction contains "SUB R5, R5,R5", although it is compliant, the logic is redundant. You can choose to keep it or regenerate it based on the verification requirements.

[0076] The constraints of instructions are essentially limitations imposed by hardware design, operating range, resource consumption, and coordination rules. These constraints determine what instructions can and cannot do, and what conditions must be met for them to execute correctly. Therefore, the constraints of instructions directly affect software compilation and hardware resource utilization.

[0077] Instructions generally need to conform to the following specifications:

[0078] In terms of syntax and format, the directive constraints conform to the following specifications:

[0079] Opcode.

[0080] An opcode corresponds to only one fixed operation and cannot be customized (e.g., ADD can only perform addition, not memory access; TMA_LOAD can only trigger batch loading, not computation). The operand type of the opcode is usually explicitly specified. For example, FMA.F32 (32-bit floating-point multiply-add) only supports register operands (R0-R255) and cannot directly use memory addresses; the target register for LD.U8 (8-bit unsigned load) must be a register whose lower 8 bits are independently accessible (some GPU registers support byte-level operations, while others only support 32 / 64-bit aligned operations).

[0081] The number and range of operands.

[0082] Number constraints: The number of operands for most instructions is fixed (e.g., the "3-operand instructions" ADDR1, R2, R3 in RISC architecture, which cannot transmit more or fewer operands).

[0083] Range constraints: Register operands can only be from the specified register sets (e.g., the number of general-purpose registers (GPRs) in a GPU is 65536 per SM; threads within a warp share this resource, and a single thread can use a maximum of 255 GPRs). Immediate values ​​have bit limitations (e.g., immediate values ​​for GPU instructions are typically 16-bit or 32-bit; values ​​exceeding this must be read from memory via a "load instruction" and cannot be directly embedded). Memory addresses: must be "aligned addresses" (e.g., 64-bit data loaded at LD.E.64 addresses must be aligned to 8 bytes; otherwise, hardware anomalies or performance degradation will be triggered—unaligned addresses will be split into multiple memory transactions by the hardware).

[0084] The instruction has a fixed length.

[0085] Under the same relevant regulations, the length of instructions is uniform (e.g., some instructions are 32 bits long, and some are 64 bits long) and cannot be dynamically adjusted. Short instructions cannot carry complex parameters (e.g., the parameters of TMA instructions need to be stored in memory / registers through "descriptors," and the instruction only carries the address of the descriptor, rather than directly containing all parameters).

[0086] In terms of hardware, instruction constraints conform to the following specifications:

[0087] Instruction execution relies on the chip's physical hardware units (ALU, registers, TMA engine, etc.), and the number and performance of these units directly limit the execution efficiency and parallelism of instructions.

[0088] Constraints on the number and type of functional units.

[0089] Instructions must be executed by the corresponding hardware unit, and the number of units is limited, for example:

[0090] (1) Computation instructions (ADD / FMA) depend on CUDA Cores (ALU / FPU). The number of CUDA Cores in each SM is fixed (e.g., each SM has 128 FP32 Cores, 64 FP64 Cores, etc.). Warp needs to queue up and occupy Cores when executing computation instructions.

[0091] (2) Memory access instructions (LD / ST) depend on LD / ST units (about 32 per SM), and TMA instructions depend on the TMA engine (usually 1-2 per SM). If multiple warps initiate TMA requests at the same time, the arbitration of the TMA engine will be triggered, and some warps will have to wait.

[0092] Bandwidth and capacity constraints of register file (RF).

[0093] Capacity constraint: The total number of registers in each SM is fixed. The total register usage of all threads in a Warp cannot exceed this limit (e.g., if an SM has 65536 32-bit GPRs, and a 32-thread Warp uses 2048 GPRs per thread, the total will be 65536, which is exactly full, and no other Warp can be started at this time).

[0094] Bandwidth constraint: Register read and write bandwidth is limited. If instructions in a thread within Warp read and write a large number of registers simultaneously (such as in a "multi-instruction pipeline" where the previous instruction writes to a register and the next instruction reads the same register), it may trigger a "register port conflict" and cause instruction blocking.

[0095] Bandwidth / latency constraints for caching and memory.

[0096] Cache constraints: The instruction cache (ICache) has a limited capacity (e.g., 32KB ICache per SM). If the instruction sequence is too long (e.g., complex loops), it will lead to a decrease in ICache hit rate and an increase in instruction fetch latency.

[0097] Memory bandwidth constraint: The transmission speed of memory access instructions (LD / ST) and TMA instructions is limited by the video memory bandwidth. If multiple warp requests initiate high bandwidth requests at the same time (such as batch loading of GB-level data), it will lead to bandwidth saturation and increased instruction execution latency.

[0098] Latency constraints: The inherent latency of memory access (such as the latency of global video memory access of about 100-200ns), instructions must wait for data to be returned before they can continue to execute (unless the latency is hidden by "instruction reordering" or "TMA and computational parallelism").

[0099] The following verification methods are commonly used in command verification:

[0100] 1. Software Simulation: This method uses an instruction-level simulator to simulate the instruction execution process without requiring real hardware. It decodes, executes, and calculates the results of instructions according to relevant specifications, while simultaneously simulating the state changes of hardware resources (registers, shared memory, TMA engine) and outputting instruction execution logs (such as register values, memory data, and module interaction timing). This method can quickly locate instruction logic errors but cannot simulate hardware timing and performance.

[0101] 2. Formal Verification: This method uses mathematical logic to prove that the execution behavior of instructions conforms to the specifications, covering all possible inputs (such as all valid operands, addresses, and constraint parameters). It ensures comprehensive verification without blind spots. This method can detect errors in extreme scenarios that are difficult to cover through simulation, but it is complex and time-consuming. It is suitable for critical logic verification of core instructions (such as TMA and FMA).

[0102] 3. Hardware Real-World Testing and Verification. Instruction sequences are executed on real GPU hardware, and data is collected using hardware counters and debugging tools to verify the functionality and performance of the instructions. Verification in real-world scenarios does not affect the normal operation of the GPU and cannot achieve large-scale batch verification.

[0103] 4. Random Testing. Generate a large number of random instruction sequences (such as random register values, random TMA descriptors, and random branch conditions). However, in scenarios with a large variety or number of instructions and complex formats and constraints, the efficiency of randomly generating a single instruction is also low. Furthermore, randomly generated instructions tend to be repeatedly randomized in a certain local position, while some positions will never be randomized, resulting in some functions being repeatedly verified or some functions never being verified, meaning that the fairness of instruction verification cannot be guaranteed.

[0104] To address the aforementioned issues, this application proposes an instruction verification method. Before verifying the instruction, it first divides the instruction to be verified into a multi-layered instruction structure based on its function. Each layer corresponds to an instruction block, and different instruction blocks have their own functions. Then, a verification instruction block is randomly generated for each instruction block. Specifically, when randomly generating the verification instruction block, if there are no constraints between the instruction blocks, a verification instruction block is randomly generated for each instruction block simultaneously. If there are instruction blocks with constraints, the verification instruction blocks for the unconstrained instruction blocks are generated first, followed by the verification instruction blocks for the constrained instruction blocks. Finally, after randomly generating the verification instruction block for each instruction block, the verification instruction blocks are concatenated to obtain the verification instruction, which is then used to verify the instruction to be verified.

[0105] like Figure 2The illustration shows an instruction verification method provided in an embodiment of this application, which specifically includes the following steps:

[0106] Step 201: According to the preset multi-level instruction structure, divide the instruction to be verified into at least one instruction block corresponding to the multi-level instruction structure; the instruction to be verified is a composite instruction including multiple basic instructions; the multi-level instruction structure is used to characterize the basis for dividing the instruction block from the perspective of instruction function, and each instruction block has its own function.

[0107] In one optional implementation, the instruction to be verified is a compound instruction. A compound instruction is a high-level instruction capable of performing multiple low-level operations. It encapsulates a set of related basic instructions (such as load, compute, and store) into a single instruction, which can reduce code size and improve execution efficiency. A compound instruction is composed of multiple basic instructions combined in a specific order, completes a complex sequence of operations within a single instruction cycle, typically corresponds to an operation in a high-level language (such as matrix access), and can directly manipulate complex data structures (such as matrices) without requiring manual handling of low-level details.

[0108] This application's embodiments target composite instructions, dividing them into multi-layered instruction structures, with each layer corresponding to an instruction block. The multi-layered instruction structure is based on instruction function; therefore, each layer's instruction block has its own specific function.

[0109] In some embodiments, the multi-layer instruction structure includes an infrastructure layer, a formatting layer, and a resource management layer; the infrastructure layer represents an instruction block composed of basic instructions that are independent of the execution behavior of the instruction; the formatting layer represents an instruction block composed of basic instructions that are related to the execution behavior of the instruction; and the resource management layer represents an instruction block composed of basic instructions that are related to the resources required by the instruction.

[0110] In one optional implementation, the multi-layer instruction structure includes an infrastructure layer, a formatting layer, and a resource management layer. The infrastructure layer consists of basic instructions unrelated to instruction execution behavior, generally consisting of parameters common to instructions. The formatting layer consists of basic instructions related to instruction execution behavior, and its structure is more complex. The resource management layer typically contains resources required by the instructions, such as registers accessed by the instructions, memory addresses, or coordinates.

[0111] In some embodiments, the infrastructure layer includes one or more of instruction type, instruction code, and synchronization mode; the formatting layer includes one or more of data type, data size, and operand; and the resource management layer includes one or more of registers and memory access addresses.

[0112] The infrastructure layer can consist of common, general parameters such as instruction type, instruction code, and synchronization method. Instruction types can include arithmetic instructions, memory access instructions, and process instructions. The infrastructure layer typically guides the generation of the instruction formatting layer and does not affect the actual execution behavior of the instructions.

[0113] The formatting layer has different parameters depending on the instruction type, and these parameters need to be handled by different classes. The formatting layer typically contains parameters that are strongly related to the instruction. For example, for an arithmetic addition instruction, there will be source operand 1, source operand 2, destination operand, data type, data size, etc.; and for a memory access instruction, there will be data line, data size, storage type, L1 cache access mode, L2 cache access mode, etc.

[0114] For example, registers, memory access addresses or coordinates, address alignment, etc., are also large-bit-width information. Based on the results of the instruction formatting layer, they can be calculated or constrained, thereby reducing coupling with the information of the instruction formatting layer.

[0115] It should be understood that the above division of the multi-layer instruction structure into infrastructure layer, formatting layer and resource management layer is an optional implementation method provided by the embodiments of this application and is not intended to limit this application.

[0116] In some embodiments, the formatting layer includes a parameter metadata layer and a hardware execution information layer; the parameter metadata layer represents the metadata of the instruction execution object; and the hardware execution information layer represents the basic information of the hardware on which the instruction execution takes place.

[0117] An alternative implementation approach is to further abstract complex instructions, such as the formatting layer, into a two-layer structure: a parameter metadata layer and a hardware execution information layer. For example, matrix memory access instructions have a complex instruction format and involve mathematical calculations and large bit widths, requiring further abstraction into a two-layer structure.

[0118] The first layer is the hardware execution information layer. Because this is usually a large bit-width information, if it is coupled with other information, it will not be friendly to the simulator's deconstraint removal.

[0119] The second layer is the parameter metadata layer, such as matrix data type and size. The length and width information of the matrix and the information of the tiles are subjected to mathematical operations, and the results of these operations are subject to constraints.

[0120] The two-layer structure simplifies the problems of simulator constraint resolution efficiency and unfairness caused by the simultaneous occurrence of mathematical calculations and large bit widths.

[0121] It should be understood that the above-described subdivision of the formatting layer into a parameter metadata layer and a hardware execution information layer is an optional implementation method provided by the embodiments of this application and is not intended to limit this application.

[0122] Step 202: Randomly generate a first verification instruction block based on the first instruction block, and generate a second verification instruction block based on the first verification instruction block and the second instruction block; wherein, the first instruction block is an instruction block that has no constraint relationship with other instruction blocks, and the second instruction block is constrained by the first instruction block.

[0123] In one optional implementation, after dividing the instructions into a multi-layered instruction structure, multiple instruction blocks are obtained. Among these multiple instruction blocks, some instruction blocks are not bound by other instruction blocks, while others are bound by other instruction blocks. The instruction blocks that are not bound by other instruction blocks are designated as the first instruction block, and the instruction blocks that are bound by other instruction blocks are designated as the second instruction block.

[0124] For the first instruction block, a first verification instruction block is randomly generated. After obtaining the first verification instruction block, a second verification instruction block is generated based on the first verification instruction block and the second instruction block.

[0125] Taking a multi-layered instruction structure consisting of an infrastructure layer, a formatting layer, and a resource management layer as an example, the infrastructure layer comprises basic instructions unrelated to the execution behavior of other instructions. Therefore, the infrastructure layer is the first instruction block, unconstrained by other instruction blocks, and is the first to be randomly generated. The formatting layer constrains the resource management layer; therefore, the formatting layer and the resource management layer are the second instruction blocks. The resource management layer is also constrained by the formatting layer. Thus, after randomly generating the verification instruction block for the formatting layer, the verification instruction block for the resource management layer is then randomly generated.

[0126] Step 203: Obtain verification instructions based on each verification instruction block corresponding to at least one instruction block.

[0127] Step 204: Verify the instruction to be verified using the verification instruction.

[0128] In one optional implementation, multiple verification instruction blocks are concatenated to obtain a verification instruction, which is then used to verify the instruction to be verified. When using the verification instruction to verify the instruction to be verified, a random testing method can be employed.

[0129] Optionally, if there are no constraints between the instructions: First, the instructions to be verified are divided into multi-layered instruction structures as described above, obtaining instruction blocks corresponding to each layer. Then, each instruction block is randomly generated in parallel to obtain the verification instruction block corresponding to each instruction block. Optionally, if there are constraints between the instructions: First, the instructions to be verified are divided into multi-layered instruction structures as described above, obtaining instruction blocks corresponding to each layer. Then, instruction blocks without constraints are randomly generated first, and for instruction blocks with constraints, the unconstrained instruction blocks are randomly generated first, followed by the constrained instruction blocks, thus obtaining the verification instruction blocks corresponding to each instruction block.

[0130] Finally, the various verification instruction blocks are concatenated to obtain the verification instruction. This instruction is then run on the corresponding hardware device according to the format requirements of the instruction to be verified, and the validity of the instruction is determined based on the execution result. For example, in an addition instruction "c=a+b", "int a=3, int b=5" is randomly generated. If the execution result is "8", then the instruction "c=a+b" is valid; if the execution result reports an error, then the instruction "c=a+b" is invalid.

[0131] In some embodiments, randomizing the generation of a verification instruction block corresponding to each instruction block in at least one instruction block includes: for each first instruction block that has no constraint relationship, generating its corresponding first verification instruction block in parallel randomizing the generation of each first verification instruction block.

[0132] In one alternative implementation, since the first instruction block is not constrained by other instruction blocks, it can generate its corresponding verification instruction blocks in parallel using randomization. For example, the infrastructure layer and the formatting layer can simultaneously generate their respective verification instruction blocks randomly.

[0133] In some embodiments, after obtaining at least one instruction block corresponding to the multi-layer instruction structure, before parallel randomization to generate the corresponding first verification instruction block, such as Figure 3 As shown, it also includes:

[0134] Step 301: Summarize at least one instruction block and randomization generation method into a verification instruction code set.

[0135] In one optional implementation, after dividing the instruction to be verified into a multi-layered instruction structure, multiple instruction blocks are obtained. Furthermore, based on a randomized generation method applied to each instruction block, these blocks are aggregated to obtain a verification instruction code set. For example, after dividing the instruction to be verified into an infrastructure layer, a formatting layer, and a resource management layer, instruction blocks corresponding to the respective instruction structures are obtained.

[0136] Step 302: By verifying the instruction code set, at least one verification instruction block is randomly generated for each instruction block in the instruction block.

[0137] In one optional implementation, a verification instruction block is randomly generated for each instruction block within a set of verification instruction codes. For example, in the verification instruction code set, a corresponding verification instruction block is generated based on the infrastructure layer code block, the formatting layer code block, and the resource management layer code block, with the resource management layer verification code block generated after the formatting layer verification code block.

[0138] To facilitate understanding of this solution, the specific operation steps of the embodiments of this application are explained below using a specific application scenario. Since the matrix memory access instruction format is relatively complex and involves key factors such as mathematical calculations and large bit width, the instruction to be verified is a matrix memory access instruction as an example for illustration. The following is the verification instruction code set for the matrix memory access instruction:

[0139] Class BasicInfo

[0140] Rand bit[2:0] op_type;

[0141] Rand bit[2:0] opcode;

[0142] Rand bit[2:0] sync_mode;

[0143] …. Some constraint

[0144] Endclass

[0145] Class TileInfo;

[0146] Rand int w;

[0147] Rand int c;

[0148] Rand int stride_w;

[0149] … some constraint

[0150] Endclass

[0151] Class MatrixOpFmt;

[0152] Rand bit[2:0] data_type;

[0153] Rand bit[2:0] row;

[0154] Rand bit[2:0] col;

[0155] Rand bit[2:0] ns;

[0156] Rand bit[2:0] data_size;

[0157] TileInfo u_tileinfo;

[0158] …. Some constraint;

[0159] Endclass

[0160] Class MatrixaddrInfo;

[0161] Rand bit[2:0] alignment;

[0162] Rand bit[2:0] coord_x;

[0163] Rand bit[2:0] coord_y;

[0164] TileInfo u_tileinfo;

[0165] MatrixOpFmt u_matrix_op;

[0166] … some constraint

[0167] endclass

[0168] Class Opfmt;

[0169] BasicInfo u_basicinfo

[0170] TileInfo u_tileinfo;

[0171] MatrixOpFmt u_matrixop;

[0172] MatrixaddrInfo u_matrix_addr;

[0173] Function void pre_randomize();

[0174] U_basicinfo.randomize();

[0175] U_tileinfo.randomize();

[0176] U_matrixop.u_tileinfo = u_tileinfo

[0177] U_matrixop.randomize();

[0178] U_matrix_addr.u_tileinfo = u_tileinfo;

[0179] U_matrix_addr.u_matrix_op = u_matrixop;

[0180] U_matrix_addr.randomize();

[0181] endfunction

[0182] endclass

[0183] The above code is the verification instruction code set in the embodiments of this application. The instruction to be verified is divided into multiple classes. Among them, Class BasicInfo is the infrastructure layer of the matrix memory access instruction, which is class A, including instruction type (op_type), opcode, and synchronization mode (sync_mode). Class TileInfo is the hardware execution information layer in the formatting layer of the matrix memory access instruction, which is class B. Class MatrixOpFmt is the parameter meta-information layer in the formatting layer, which is class C, including the data type of the matrix (data_type), the number of rows of the matrix (row), the number of columns of the matrix (col), etc. In matrix operations, Tile decomposes the large matrix into fixed-size sub-matrices. The information of Tile is the core parameter set used in the matrix memory access instruction to describe "how to split, locate, load / store the sub-matrix". Therefore, Tile is divided into a separate class. Class MatrixaddrInfo is the resource management layer of the matrix memory access instruction, which is class D, such as address alignment (alignment) and address coordinates (coord_x / coord_y). Class Opfmt is the instruction class E, in which the above classes are instantiated. In class E, randomization is performed on A->B->C->D in the order of randomization. Since randomization of class C depends on the result of randomization of class B, the randomization result of class B needs to be obtained before randomization of class C; similarly, class D needs the randomization results of classes B and C. The information from classes A / B / C / D is packaged into a complete instruction and placed in class E.

[0184] The function `void pre_randomize()` generates randomized versions of the aforementioned instruction blocks. For example, `U_basicinfo.randomize()` randomizes the infrastructure layer; `U_tileinfo.randomize()` randomizes the hardware execution information layer of the formatting layer; `U_matrixop.u_tileinfo = u_tileinfo` and `U_matrixop.randomize()` randomize the parameter metadata layer of the formatting layer; and `U_matrix_addr.u_tileinfo = u_tileinfo`, `U_matrix_addr.u_matrix_op = u_matrixop`, and `U_matrix_addr.randomize()` randomizes the resource management layer.

[0185] In this embodiment, by dividing the instruction to be verified according to a preset instruction structure, instruction blocks corresponding to each layer of instruction structure are obtained. This allows for a clear understanding of the function of each part of the instruction. When the instruction is randomized, all the divided instruction blocks can be randomized, thus avoiding the inability to randomize certain instruction blocks and improving the fairness of instruction randomization. The random order between instruction blocks is determined according to the constraint relationship between each instruction block, so that constrained instruction blocks are randomized later and unconstrained instruction blocks are randomized first. This avoids errors in the generated random instructions due to constraint issues and improves the efficiency of instruction randomization.

[0186] Based on the same technical concept, embodiments of this application provide an instruction verification device 400, such as... Figure 4 As shown, it includes:

[0187] The partitioning module 401 is used to partition the instruction to be verified according to a preset multi-level instruction structure to obtain at least one instruction block corresponding to the multi-level instruction structure; the instruction to be verified is a composite instruction including multiple basic instructions; the multi-level instruction structure is used to characterize the basis for partitioning the instruction block from the perspective of instruction function, and each instruction block has its own function.

[0188] The generation module 402 is used to randomly generate a first verification instruction block based on a first instruction block, and to generate a second verification instruction block based on the first verification instruction block and a second instruction block; wherein, the first instruction block is an instruction block that has no constraint relationship with other instruction blocks, and the second instruction block is constrained by the first instruction block;

[0189] The verification module 403 is used to obtain a verification instruction based on each verification instruction block corresponding to the at least one instruction block; the verification instruction is used to verify the instruction to be verified.

[0190] Optionally, the multi-layer instruction structure includes an infrastructure layer, a formatting layer, and a resource management layer;

[0191] The infrastructure layer represents instruction blocks composed of basic instructions that are independent of the execution behavior of instructions;

[0192] The formatting layer represents a block of instructions composed of basic instructions related to the execution behavior of the instructions;

[0193] The resource management layer represents the instruction block composed of basic instructions related to the resources required by the instructions.

[0194] Optionally, the formatting layer includes a parameter metadata layer and a hardware execution information layer;

[0195] The parameter metadata layer represents the metadata of the instruction execution object;

[0196] The hardware execution information layer represents the basic information of the hardware in which the instruction is executed.

[0197] Optionally, the generation module 402 is specifically used for:

[0198] For each first instruction block that has no constraints, a corresponding first verification instruction block is generated in parallel randomization.

[0199] Optionally, the generation module is further configured to:

[0200] The at least one instruction block and the randomization method are summarized into a verification instruction code set;

[0201] Optionally, the generation module 402 is specifically used for:

[0202] The verification instruction code set is used to randomly generate a verification instruction block corresponding to each instruction block in the at least one instruction block.

[0203] Optionally, the infrastructure layer includes one or more of the following: instruction type, instruction code, and synchronization method;

[0204] The formatting layer includes one or more of the following: data type, data size, and operands;

[0205] The resource management layer includes one or more of registers and memory access addresses.

[0206] Based on the same technical concept, embodiments of this application provide a computer device, such as... Figure 5 As shown, it includes at least one artificial intelligence chip 100 and a memory 104 connected to at least one artificial intelligence chip 100. In this embodiment, the specific connection medium between the artificial intelligence chip 100 and the memory 104 is not limited. Figure 5Taking the connection between the AI ​​chip 100 and the memory 104 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0207] In this embodiment, the memory 104 stores instructions that can be executed by at least one artificial intelligence chip 100. By executing the instructions stored in the memory 104, at least one artificial intelligence chip 100 can perform the steps of the above-mentioned instruction verification execution method.

[0208] The artificial intelligence chip 100 serves as the control center of the computer device. It connects to various parts of the computer device via various interfaces and lines, and executes instructions stored in the memory 104 and retrieves data stored in the memory 104 to perform instruction verification. Optionally, the artificial intelligence chip 100 may include one or more processing units. The artificial intelligence chip 100 may integrate an application processor and a modem processor. The application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into the artificial intelligence chip 100. In some embodiments, the artificial intelligence chip 100 and the memory 104 may be implemented on the same chip; in other embodiments, they may be implemented on separate chips.

[0209] The artificial intelligence chip 100 can be a general-purpose processor, such as a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0210] Memory 104, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 104 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 104 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer device, but is not limited thereto. In the embodiments of this application, memory 104 may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0211] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to execute the steps of the above-described instruction verification method.

[0212] Based on the same inventive concept, this application provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, which, when executed by a computer device, cause the computer device to perform the above-mentioned instruction verification steps.

[0213] Those skilled in the art will understand that embodiments of the present invention can be provided as methods or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0214] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer apparatus or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0215] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer device or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0216] These computer program instructions may also be loaded onto a computer device or other programmable data processing equipment to cause a series of operational steps to be performed on the computer device or other programmable equipment to produce a process implemented by the computer device, thereby providing instructions that execute on the computer device or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0217] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0218] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An instruction verification method, characterized by, The method comprises the following steps: According to a preset multi-layer instruction structure, the to-be-verified instruction is divided to obtain at least one instruction block corresponding to the multi-layer instruction structure; The to-be-verified instruction is a composite instruction comprising a plurality of basic instructions; the multi-layer instruction structure is used to represent the basis for dividing the instruction block from the perspective of instruction function, each instruction block has its own function; the multi-layer instruction structure comprises an infrastructure layer, a formatting layer and a resource management layer; the infrastructure layer represents an instruction block composed of basic instructions irrelevant to the execution behavior of the instruction, is used to guide the generation of the instruction formatting layer and does not affect the actual execution behavior of the instruction; the formatting layer represents an instruction block composed of basic instructions related to the execution behavior of the instruction, contains parameters strongly related to the instruction, has different parameters according to different instruction types and needs to be carried by different classes; the resource management layer represents an instruction block composed of basic instructions related to the resources required by the instruction; A first verification instruction block is randomly generated based on a first instruction block, and a second verification instruction block is generated based on the first verification instruction block and a second instruction block; wherein the first instruction block is an instruction block having no constraint relationship with other instruction blocks, and the first verification instruction block corresponding to each first instruction block is randomly generated in parallel; the second instruction block is constrained by the first instruction block; Verification instructions are obtained based on the respective verification instruction blocks corresponding to the at least one instruction block; The to-be-verified instruction is verified through the verification instructions.

2. The method of claim 1, wherein, The method comprises the following steps: The formatting layer comprises a parameter meta-information layer and a hardware execution information layer; The parameter meta-information layer represents the meta-information of the instruction execution object; The hardware execution information layer represents the basic information of the hardware where the instruction is executed.

3. The method of claim 1, wherein, After obtaining the at least one instruction block corresponding to the multi-layer instruction structure, and before randomly generating the respective first verification instruction block in parallel, the method further comprises the following steps: The at least one instruction block and the random generation mode are summarized into a verification instruction code set; Randomly generating the verification instruction block corresponding to each instruction block in the at least one instruction block comprises the following steps: The verification instruction code set is used to randomly generate the verification instruction block corresponding to each instruction block in the at least one instruction block.

4. The method according to any one of claims 1 to 2, wherein The infrastructure layer comprises one or more of instruction type, instruction code and synchronization mode; The formatting layer comprises one or more of data type, data size and operand; The resource management layer comprises one or more of register and memory access address.

5. An instruction verification apparatus characterized by comprising: The method comprises the following steps: A division module is configured to divide the to-be-verified instruction according to a preset multi-layer instruction structure to obtain at least one instruction block corresponding to the multi-layer instruction structure; The to-be-verified instruction is a composite instruction including a plurality of basic instructions; the multi-layer instruction structure is used to represent a basis for dividing instruction blocks from the perspective of instruction functions, each instruction block having a respective function; the multi-layer instruction structure includes an infrastructure layer, a formatting layer, and a resource management layer; the infrastructure layer represents an instruction block composed of basic instructions irrelevant to execution behavior of the instruction, used to guide generation of the instruction formatting layer, and does not affect actual execution behavior of the instruction; the formatting layer represents an instruction block composed of basic instructions related to execution behavior of the instruction, including parameters strongly related to the instruction, different parameters according to different instruction types, and different classes needed to carry the parameters; and the resource management layer represents an instruction block composed of basic instructions related to resources required by the instruction. The generating module is configured to generate a first verification instruction block based on a first instruction block, and generate a second verification instruction block based on the first verification instruction block and a second instruction block; the first instruction block is an instruction block having no constraint relationship with other instruction blocks, and the first instruction block is randomly generated in parallel to generate a first verification instruction block corresponding to the first instruction block; the second instruction block is constrained by the first instruction block. The verification module is configured to obtain a verification instruction based on each verification instruction block corresponding to the at least one instruction block. The verification module is further configured to verify the to-be-verified instruction based on the verification instruction. 6.A computer device, comprising a memory, an artificial intelligence chip, and a computer program stored on the memory and running on the artificial intelligence chip, wherein, The artificial intelligence chip executes the computer program to implement the steps of the method of any one of claims 1-4.

7. A computer readable storage medium characterized in that, The computer program product includes a computer program stored on a computer readable storage medium, and the computer program includes program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the method of any one of claims 1-4.

8. A computer program product, characterised in that, The computer program product includes a computer program stored on a computer readable storage medium, and the computer program includes program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the method of any one of claims 1-4.

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