Memory device

Abstract

A memory device includes a first bit line group, a first column selection circuit, a first data line, and a second data line. The first bit line group includes a first bit line and a second bit line. The first column selection circuit is coupled to the first bit line and the second bit line. The first data line includes a first line segment coupled to the first column selection circuit. The second data line includes a second line segment coupled to the first column selection circuit. Wherein the first column selection circuit is used for electrically connecting a first bit line to a first line segment to transmit a first bit of normal data to the first line segment, and electrically connecting a second bit line to a second line segment to transmit a first bit of error correction / detection code data to the second line segment.

Description

TECHNICAL FIELD

[0001] The present invention relates to a memory device, and more particularly, to a memory device capable of increasing input / output bandwidth by providing extra bits. BACKGROUND

[0002] Dynamic random access memory (DRAM) is widely used as the main memory of a computer due to its cost effectiveness. A DRAM device includes a plurality of memory cells, each of which can store one bit of data, typically implemented using a capacitor and a transistor. The capacitor can be charged or discharged to represent the value of the data bit stored in the memory cell. For example, an empty capacitor can represent a logic value of 0, while a fully charged capacitor can represent a logic value of 1. As technology nodes shrink, the memory cells become smaller, and the capacitor will store a very limited amount of charge. To provide data that can be correctly interpreted, a DRAM device utilizes a sense amplifier to produce an output in the form of a recognizable logic level. SUMMARY

[0003] The present invention is directed to a memory device capable of increasing input / output bandwidth by providing extra bits.

[0004] According to an embodiment of the present invention, a memory device includes a first bit line group, a first column selection circuit, a first data line, and a second data line. The first bit line group includes a first bit line and a second bit line. The first column selection circuit is coupled to the first bit line and the second bit line. The first data line includes a first line segment coupled to the first column selection circuit. The second data line includes a second line segment coupled to the first column selection circuit. Wherein the first column selection circuit is to electrically connect the first bit line to the first line segment to transfer a first bit of normal data to the first line segment, and to electrically connect the second bit line to the second line segment to transfer a first bit of error correction / detection code data to the second line segment.

[0005] Another memory device includes a plurality of memory cell arrays and a plurality of data sensing circuit regions. Each data sensing circuit region is arranged between two adjacent memory cell arrays, each data sensing circuit region includes a main space and an extension space. The main space has a plurality of input / output pads to output normal stored data during a normal data read operation. The extension space is arranged adjacent to the main space and has a plurality of extended input / output pads to output error correction / detection code data during an error correction / detection code data read operation. Wherein at least a first bit of the normal stored data is generated from the extension space during the normal data read operation.

[0006] In summary, the memory device of the present embodiment provides a segmented data line structure and can transmit extra bits through at least one extra line segment of the data line. In the present embodiment, the extra bits can be provided as error correction / detection codes to improve the data reliability of the memory device. Attached Figure Description

[0007] Figure 1 A schematic diagram showing a partial physical design of a memory device according to some embodiments is provided.

[0008] Figure 2 A schematic diagram showing a portion of a memory device according to an embodiment of the present invention is shown.

[0009] Figure 3A and Figure 3B A schematic diagram showing a portion of a memory device according to another embodiment of the present invention.

[0010] Figure 4 A schematic diagram showing a portion of a memory device according to an embodiment of the present invention is shown.

[0011] Figure 5 A schematic diagram showing a portion of a memory device according to an embodiment of the present invention is shown.

[0012] Figure 6 A schematic diagram showing a portion of a memory device according to an embodiment of the present invention is shown.

[0013] Figure 7 A schematic diagram of a semiconductor device according to an embodiment of this application is shown.

[0014] Figure 8 A block diagram of a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0015] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0016] Reference will now be made to details of presently preferred embodiments of the invention, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0017] The accompanying drawings provide a detailed description of embodiments of the present invention. It should be understood that the present invention is not intended to be limited to the specifically disclosed structural embodiments and methods, but rather that other features, components, methods, and embodiments may be used to implement the present invention. Preferred embodiments are provided to illustrate the present invention and not to limit its scope, which is defined by the claims. Those skilled in the art will recognize various equivalent variations described below.

[0018] As used in this article, the term "coupling" refers to operational coupling. In this sense, coupled projects are not necessarily directly connected, and there may be intervening projects between coupled projects.

[0019] Referring to Figure 1 , Figure 1 A schematic diagram illustrating a portion of a physical design of a memory device according to some embodiments is shown. In Figure 1 , the memory device 100 can be implemented as a dynamic random access memory (DRAM) bank including a plurality of tiles 102 arranged in an array. Each tile 102, also referred to as a memory array tile (MAT), can include a cell array (CA) 110, a row decoder (RDEC) 120, and a sense amplifier (SA) block 130. The cell array 110 includes a plurality of storage cells arranged in rows and columns. The storage cells in a given row share a common word line (not shown) that extends in the row direction; the storage cells in a given column are coupled to the same bit line (not shown) that extends in the column direction. The row decoder 120 is configured to activate the word lines. A plurality of sense amplifiers are disposed in the sense amplifier block 130. The sense amplifier block 130 is configured to sense and amplify data signals of the bit lines and provide sense signals to corresponding data lines.

[0020] The memory device 100 can be implemented using, but not limited to, an open bit line architecture. For example, in a given row of the cell array 110, a portion of the storage cells disposed in the row are coupled to a sense amplifier block at the top of the cell array 110 through a portion of the bit lines, while another portion of the storage cells are coupled to another sense amplifier block at the bottom of the cell array 110 through another portion of the bit lines.

[0021] The memory device 100 can further include a column selection circuit 140 configured to select a sense amplifier from the sense amplifier block and couple the selected sense amplifier to a data line group. For example, each bit line disposed in the cell array 110 is coupled to an associated sense amplifier of the sense amplifier block 130. The column selection circuit 140 can be used to activate a column select line from a group of column select lines {CSL} to select a group of bit lines arranged in the cell array 110, and then couple the selected group of bit lines to a group of data lines {LDL}. Each data line in the group of data lines {LDL} can be shared among a plurality of columns of storage cells in the cell array 110. It should be noted that the memory device 100 can be implemented to have a hierarchical structure, in which the group of data lines {LDL} can be referred to as a local data line group that is coupled to a global data line group (not shown) arranged in the column direction.

[0022] Referring to Figure 2 , Figure 2 A schematic diagram illustrating a portion of a memory device according to embodiments of the present disclosure is shown. Figure 2 In Figure 1The memory device 200 includes a plurality of bit line groups BLSe, BLS1 to BLS8, a data line group LDLS, a column selection circuit 210, and an additional column selection circuit 220. In this embodiment, the bit line group BLSe includes bit lines B0e and B1e, and the bit line groups BLS1 to BLS8 respectively include bit lines B01, B11 to B08, B18. Compared to the corresponding part of the prior art memory device, the bit line group BLSe is an additional bit line group. More specifically, at least two technical effects can be achieved from the bit line group BLSe, one is to solve the problem caused by the data line group {LDL} segmentation, and the other is to provide the memory device 200 with error correction / detection code (ECC) data. The detailed description of the bit line group BLSe will be described in the following paragraphs.

[0023] The bit line group BLSe corresponds to a plurality of sense amplifiers SA0e and SA1e, and the bit line groups BLS1 to BLS8 respectively correspond to a plurality of sense amplifiers SA01, SA11 to SA08, SA18. The sense amplifiers SA0e and SA1e are further coupled to complementary bit lines B0eB and B1eB respectively, and the sense amplifiers SA01, SA11 to SA08, SA18 are further coupled to complementary bit lines B01B, B11B to B08B, B18B respectively. For the sake of brevity, the bit lines B0eB, B1eB, B01B, B11B to B08B, B18B and the bit lines in another embodiment can also be regarded as data bits of the memory device, because these bit lines are electrically connected to the storage units of the memory device. In this embodiment, the signals on the bit lines B0e, B1e and B01 to B18 can be respectively inverted to the signals on the complementary bit lines B0eB, B1eB and B01B to B18B. In this embodiment, the structure of each sense amplifier SA0e, SA1e, SA01, SA11 to SA08 to SA18 can be the same and can be implemented by any sense amplification circuit known to those skilled in the art.

[0024] The column selection circuit 210 includes a plurality of switches formed by transistors. Each switch corresponds to each bit line B01 to B18 and is used to couple the corresponding bit line to the data line. Two adjacent switches of the column selection circuit 210 form a switch pair. The control terminals of the switch pair are respectively coupled to the column selection lines CSL0-1 to CSL3-2.

[0025] For example, in column selection circuit 210, transistors T01 and T11 form two switches, transistor T01 is coupled between bit line B01 and a segment SEG11 of data line LDL-1. Transistor T11 is coupled between bit line B11 and a segment SEG21 of data line LDL-2. The control terminals of transistors T10 and T11 are coupled to the same column selection line CSL0-1 and have the same open or off state according to a column selection signal on column selection line CSL0-1. In detail, when the switch formed by transistor T01 is open, bit line B01 is coupled to segment SEG11 of data line LDL-1, and when the switch formed by transistor T11 is open, bit line B11 is coupled to segment SEG21 of data line LDL-2.

[0026] In this embodiment, bit line groups BLS1 to BLS4 can form a first bit line group, and bit line groups BLS5 to BLS8 can form a second bit line group. Column selection lines CSL0-1 to CSL3-1 can correspond to the first bit line group, and column selection lines CSL0-2 to CSL3-2 can correspond to the second bit line group. During operation, in the first bit line group, one of column selection lines CSL0-1 to CSL3-1 can be activated to open the corresponding switch, and the others of column selection lines CSL0-1 to CSL3-1 are deactivated. Likewise, in the second bit line group, one of column selection lines CSL0-2 to CSL3-2 can be activated to open the corresponding switch at the same time, and the others of column selection lines CSL0-2 to CSL3-2 are deactivated. In this embodiment, column selection line CSL0-1 corresponding to the first bit line group and column selection line CSL0-2 corresponding to the second bit line group are activated by the same column selection signal CSL0, wherein column selection signal CSL0 can include CSL0-1 and CSL0-2. Column selection line CSL1-1 corresponding to the first bit line group and column selection line CSL1-2 corresponding to the second bit line group are activated by the same column selection signal CSL1, wherein column selection signal CSL1 can include CSL1-1 and CSL1-2. Column selection line CSL2-1 corresponding to the first bit line group and column selection line CSL2-2 corresponding to the second bit line group are activated by the same column selection signal CSL2, wherein column selection signal CSL2 can include CSL2-1 and CSL2-2. Column selection line CSL3-1 corresponds to the first bit line group and the second bit line group, and column selection line CSL3-2 corresponds to the second bit line group and a third bit line group (not shown in the figure). Column selection lines CSL3-1 and CSL3-2 can be activated by the same column selection signal CSL3, wherein column selection signal CSL3 can include CSL3-1, CSL3-e, and CSL3-2.

[0027] In this embodiment, the data line LDL-1 can be divided into a plurality of line segments SEG11-SEG13 compared to the corresponding part of the prior art memory device. The data line LDL-2 can be divided into a plurality of line segments SEG21-SEG22 and one extra line segment SEG2e. Each line segment SEG11-SEG13 can be used to transmit first data, and each line segment SEG21-SEG22 can be used to transmit second data. In addition, the extra line segment SEG2e can be used to transmit extra bits in addition to the first data and the second data. In this embodiment, in the data line LDL-1, the adjacent line segments SEG11 and SEG12 are isolated by a gap X, and the adjacent line segments SEG12 and SEG13 are isolated by another gap X. Similarly, in the data line LDL-2, the adjacent line segments SEG2e and SEG21 are isolated by a gap X, and the adjacent line segments SEG21 and SEG22 are also isolated by another gap. In some embodiments, the width GW of the line segment is within 1 μm. This size is suitable for implementation in a local data line (LDL) design, and a higher density of LDL line segments can be achieved. In some embodiments, because the pitch 230 between two adjacent vias on the LDL line segment is about 1.1 μm, and the gap X with a width GW within 1 μm can be introduced in the mask design of the LDL, the size of the gap X and the density of the LDL line segment can be well controlled. In some embodiments, the implementation of the gap X in the data line does not cause space waste in the sensing amplifier block, and does not require the placement of dummy patterns in the sensing amplifier block or the cell array.

[0028] The extra column selection circuit 220 includes switches formed by transistors Te0 and Te1, respectively. The transistor Te0 is coupled between the bit line B0e and the extra line segment SEG2e of the data line LDL-2. The transistor Te1 is coupled between the bit line B1e and the line segment SEG11 of the data line LDL-1. The transistors Te0 and Te1 are commonly controlled by a column selection signal CSL3 on the column selection line CSL3-e. When the column selection signal CSL3 on the column selection line CSL3-e is activated, the switches formed by the transistors Te0 and Te1 are turned on, and the bit line B0e can be coupled to the extra line segment SEG2e of the data line LDL-2, and the bit line B1e can be coupled to the line segment SEG11 of the data line LDL-1. It can be seen that the extra line segment SEG2e of the data line LDL-2 can be used to provide or receive the extra bits generated by the sensing amplifier SA0e.

[0029] In this embodiment, in detail, the line segment to receive four bits corresponding to column selection signals CSL0-1 to CSL3-1 or column selection signals CSL0-2 to CSL3-2 is a full bit segment. For example, line segment SEG11 includes four addressable bits, which read bit line B01 selected by column selection signal CLS0-1; bit line B12 selected by column selection signal CSL1-1; bit line B03 selected by column selection signal CSL2-1; and bit line Be selected by column selection signal CSL3-e, respectively. Likewise, line segment SEG21 includes four addressable bits, which read bit line Bl 1 selected by column selection signal CLS0-1; bit line B02 selected by column selection signal CSL1-1; bit line B13 selected by column selection signal CSL2-1; and bit line B04 selected by column selection signal CSL3-1, respectively. In the same manner, line segment SEG12 and line segment SEG22 are also full bit segments.

[0030] In this embodiment, in detail, additional line segment SEG2e is an incomplete bit segment. For brevity, line segment SEG13 can also be considered as an incomplete bit segment. During operation, when one of column selection signals CSL0, CSL1, CSL2 is activated, corresponding data is output on line segments SEG11 and SEG21, and no bit is present on additional line segment SEG2e. When column selection signal CSL3 is activated, not only corresponding data is output on line segments SEG11 (i.e., bits read from bit line Be) and SEG21 (i.e., bits read from bit line B04), additional line segment SEG2e also includes one addressable bit read from bit line Boe selected by column selection signal CSL3-e. On the other hand, when one of column selection signals CSL0, CSL1, CSL2 is activated, corresponding data is output on line segments SEG12 and SEG22, and no bit is present on line segment SEG13. When column selection signal CSL3 is activated, not only corresponding data is output on line segments SEG12 (i.e., bits read from bit line B14) and SEG22 (i.e., bits read from bit line B08), line segment SEG13 also includes one addressable bit read from bit line B18 selected by column selection signal CSL3-2. Thus, during read operation of memory device 200, the addressable bits on additional line segment SEG2e and line segment SEG13 can be considered as additional bits.

[0031] Thus, in this embodiment, the bits on the line segments SEG11, SEG12, SEG21 and SEG22 are the main bits that represent the data stored in the memory device 200. The bits on the line segments SEG2e and SEG13 are extra bits in addition to the data normally stored. According to the present application, the extra bits can be provided as ECC, such as the ECC or any other error correction / detection information. The number of extra bits to be corrected by the ECC can be adjusted by adding extra line segments, extra column select lines and extra sense amplifiers. More extra bits can perform higher level of error correction / detection.

[0032] Reference is made to Figure 3A , Figure 3A a schematic diagram showing a portion of a memory device according to another embodiment of the present application. Figure 3A The portion of the memory device 300 in Figure 1 may also correspond to the sense amplifier block 130 in Figure 2 In this embodiment, unlike the embodiment of Figure 2 , the number of extra bits can be expanded by setting more extra bit line groups. For brevity, the detailed description of the extra bits on the line segment SEG13 in

[0033] In Figure 3A , the memory device 300 includes extra bit line groups BLse0 to BLse7. Each of the extra bit line groups BLse0 to BLse7 includes two bit lines. For example, the extra bit line group BLse0 includes bit lines B1e0 and B0e0, the extra bit line group BLse1 includes bit lines B1e1 and B0e1, and so on. The extra bit line groups BLse0 to BLse7 correspond to the sense amplifiers SA10e, SA00e to SA17e and SA07e, respectively. The sense amplifiers SA10e, SA00e to SA17e and SA07e are further coupled to complementary bit lines B1e0B, B0e0B to B1e7B and B0e7B, respectively. The extra column select circuits 321 and 322 include a plurality of switches formed by transistors Te10, Te00 to Te17 and Te07, respectively. In this embodiment, the data line LDL-1 further includes extra line segments SEG1e1 and SEG1e2, and the data line LDL-2 further includes extra line segments SEG2e1 and SEG2e2, wherein the length of the extra line segment SEG2e1 of the second data line LDL-2 is extended to be a full line segment compared to the embodiment shown in Figure 2 . The extra line segments SEG1e1 and SEG1e2 are separated by a gap X, and the extra line segments SEG2e1 and SEG2e2 are also separated by a gap X. The width GW of each gap X between two adjacent line segments can be within 1 μm. However, this is not a limitation of the present application. The width GW can be adjusted according to the spacing between two adjacent vias on the line segment.

[0034] In this embodiment, the bit line group BLS1 includes bit lines B01 and B11. Transistors T01 and T11 are arranged in the column selection circuit 320, with transistor T01 coupled between bit line B01 and line segment SEG11, and transistor T11 coupled between bit line B11 and line segment SEG21. Transistor T01 is to electrically connect bit line B01 to line segment SEG11 to transfer bits of normal data from bit line B01 to line segment SEG11. Transistor T11 is to electrically connect bit line B11 to line segment SEG21 to transfer bits of normal data from bit line B11 to line segment SEG21. In some embodiments, line segment SEG21 and line segment SEG2e1 are separated by a gap X, where the gap X between line segment SEG11 and line segment SEG1e1 and the gap X between line segment SEG21 and line segment SEG2e1 can form a straight line, and this straight line is perpendicular to data line LDL-1 and data line LDL-2.

[0035] In detail, in the column selection circuit 321, a switch formed by transistor Te10 is coupled between sensing amplifier SA10e and line segment SEG11 of data line LDL-1; a switch formed by transistor Te00 is coupled between sensing amplifier SA00e and additional line segment SEG2e1 of data line LDL-2; a switch formed by transistor Te11 is coupled between sensing amplifier SA11e and additional line segment SEG2e1 of data line LDL-2; and a switch formed by transistor Te01 is coupled between sensing amplifier SA01e and additional line segment SEG1e1 of data line LDL-1. In addition, a switch formed by transistor Te12 is coupled between sensing amplifier SA12e and additional line segment SEG1e1 of data line LDL-1; a switch formed by transistor Te02 is coupled between sensing amplifier SA02e and additional line segment SEG2e1 of data line LDL-2; a switch formed by transistor Te13 is coupled between sensing amplifier SA13e and additional line segment SEG2e1 of data line LDL-2; and a switch formed by transistor Te03 is coupled between sensing amplifier SA03e and additional line segment SEG1e1 of data line LDL-1.

[0036] Further, in the column selection circuit 322, a switch formed by the transistor Te14 is coupled between the sense amplifier SA14e and the extra segment SEG1e1 of the data line LDL-1; a switch formed by the transistor Te04 is coupled between the sense amplifier SA04e and the extra segment SEG2e2 of the data line LDL-2; a switch formed by the transistor Te15 is coupled between the sense amplifier SA15e and the extra segment SEG2e2 of the data line LDL-2; and a switch formed by the transistor Te05 is coupled between the sense amplifier SA05e and the extra segment SEG1e2 of the data line LDL-1. Further, a switch formed by the transistor Te16 is coupled between the sense amplifier SA16e and the extra segment SEG1e2 of the data line LDL-1; a switch formed by the transistor Te06 is coupled between the sense amplifier SA06e and the extra segment SEG2e2 of the data line LDL-2; a switch formed by the transistor Te17 is coupled between the sense amplifier SA17e and the extra segment SEG2e2 of the data line LDL-2; and a switch formed by the transistor Te07 is coupled between the sense amplifier SA07e and the extra segment SEG1e2 of the data line LDL-1.

[0037] According to the present application, in addition to normal data storage, the extra segments SEG1e1, SEG1e2, SEG2e1 and SEG2e2 are used to transmit extra bits, and the extra bits can be ECC.

[0038] In the present embodiment, by arranging 8 extra bit line groups BLSe0 to BLSe7, the extra segments SEG1e1 and SEG1e2 can provide seven extra bits, and the extra segments SEG2e1 and SEG2e2 can provide eight extra bits, 15 extra bits can be provided in the memory device 300. In other embodiments, if 4 extra bit line groups are arranged, 7 extra bits can be provided in the memory device.

[0039] It should be noted herein that in other embodiments, the number of data lines and extra bit line groups can be adjusted according to user requirements. For example, the number of data lines can be adjusted to 4, the number of extra bit line groups can be adjusted to 4, and the bit line groups of the memory device can provide 14 extra bits. By providing single error correction double error detection (SECDED) 14 extra bits, a codeword containing 213 bits can be checked and corrected. In some embodiments, the memory device includes n data lines and m groups of extra bit line groups. The number of extra bits can be simplified as (n*m)-(n / 2). However, this is not a limitation. The number of extra bits can be adjusted by increasing or decreasing the number of data line segments or extra bit line groups.

[0040] Referring to Figure 3B , Figure 3B A schematic diagram showing a portion of a memory device according to another embodiment of the present application is shown.Figure 3B The portion of the memory device 300' is similar to that of the memory device 300. Figure 3A Unlike the memory device 300, in the memory device 300', the gaps X on the data line LDL-1 are aligned with the corresponding gaps X on the data line LDL-2 on the same straight line perpendicular to the data lines LDL-1 and LDL-2, respectively. In this way, the line segments SEG1e2 and SEG1e1 are aligned with the corresponding line segments SEG2e2 and SEG2e, respectively. Thus, the layout complexity of the memory device 300' is lower than that of the memory device 300. In the present embodiment, the width GW of each gap X can be within 1 μm. However, this is not a limitation of the present application. The width GW can be adjusted according to the pitch between two adjacent vias on the line segment.

[0041] Referring to Figure 4 , Figure 4 A schematic diagram showing a portion of a memory device according to an embodiment of the present application is shown. In the present embodiment, the memory device 400 can include four data lines LDL0 to LDL3, and a plurality of bit line groups. Each bit line group is controlled by signals on a plurality of column select lines CSL0-1 ~ CSL7-1 to CSL0-5 ~ CSL7-5. The memory device 400 further includes an extra bit line group controlled by control signals on extra column select lines CSL0-e to CSL7-e.

[0042] In the present embodiment, each of the data lines LDL0 to LDL3 is divided into a plurality of line segments by a plurality of physical gaps GP. In detail, the data line LDL0 is divided into line segments LDL0<0> to LDL0<5>; the data line LDL1 is divided into line segments LDL1<0> to LDL1<5>; the data line LDL2 is divided into line segments LDL2<0> to LDL2<5>; and the data line LDL3 is divided into line segments LDL3<0> to LDL3<5>.

[0043] The column select circuit of the memory device 400 is configured to perform a selection operation between the bit line groups in the memory device 400 according to the column select lines CSL0-1 ~ CSL7-1 to CSL0-5 ~ CSL7-5, and couple each bit line in each selected bit line group to a corresponding line segment of one of the data lines LDL0 ~ LDL3. The extra column select circuit of the memory device 400 is configured to select one of the extra bit line groups according to the extra column select lines CSL0-e to CSL7-e, and couple each bit line in the selected extra bit line group to a corresponding extra line segment of one of the data lines LDL0 ~ LDL3.

[0044] It should be noted herein that the number of data lines and the number of bit line groups can be adjusted by the designer according to the actual requirement of the memory device. Figure 4The illustration is only an example and does not limit the scope of the present application.

[0045] In some embodiments, the gaps of the additional line segments can be aligned on the same line. In some embodiments, the gaps aligned on the same line can simplify the design. In some embodiments, the gaps aligned on the same line have the same width.

[0046] Reference is made to Figure 5 , Figure 5 A schematic diagram illustrating a portion of a memory device according to an embodiment of the present application is shown. The memory device has a main space MSPC and an extended space ECSL. The main space MSPC is the normal data input / output (I / O) space of the memory device, while the extended space ECSL is an additional storage I / O space other than the main space MSPC. In the present embodiment, the main space MSPC is configured to have a plurality of I / O pads D0x8~D3x8 to output normal storage data during a normal data read operation. The extended space ECSL is arranged adjacent to the main space and is configured to have a plurality of extended I / O pads to output ECC data during an ECC read operation, wherein at least one bit of the normal storage data is generated from the extended space during the normal data read operation. More specifically, the main space MSPC is evenly divided into 8 groups of memory spaces, each group being controlled by 16 column select lines, i.e. CSL<15:0>. When one column select line is activated, each group can have four I / O pads to output four data bits, i.e. D0, D1, D2, D3, on four data lines respectively. In other words, in each group, the four I / O pads are electrically connected to the four data lines respectively. Thus, when one column select line is activated, the 8 groups of memory spaces can output 32 bits of data (i.e. 4 bits * 8 groups) from the main space MSPC through 32 I / O pads (i.e. D3*8+D2*8+D0*8+D1*8) respectively. As such, the main space MSPC can have a memory capacity of 512 bits (i.e. 4 bits * 8 groups * 16 CSL).

[0047] On the other hand, the extended space ECSL is provided to have four (or more) additional columns of memory spaces, i.e. a total memory capacity of 16 bits can be output. The four columns are controlled by 4 column select lines, i.e. CSL<3:0> respectively. Likewise, when one column select line is activated, each column can output four data bits, i.e. D0, D1, D2, D3, on four data lines respectively through four I / O pads. According to the present application, the data bits D1 and D3 (i.e. the two data bits marked with "X" in the middle) controlled by the column select line CSL 0 are allocated to the normal storage space. The reason has been described above with reference to Figure 5 Figures 2-4 ​As described in the related section, for brevity, the detailed description is omitted here. Thus, the 14 extra bits in the extension space ECSL can be output and used by the memory controller to perform ECC operation on the data output from the main space MSPC. For example, 10 bits of ECC can be needed to perform SECDED ECC operation on the data with 512 bits output from the main space MSPC. In this embodiment, the 14 extra bits output from the extension space ECSL are sufficient to perform SECDED ECC operation on the data from the main space MSPC.

[0048] In addition, in Figure 5 In the extension space ECSL, the data D3 controlled by the extra column select lines CSL1-CSL3, the data D2 controlled by the extra column select lines CSL0-CSL3, the data D1 controlled by the extra column select lines CSL1-CSL3, and the data D0 controlled by the extra column select lines CSL0-CSL3 can be output to the controller through 4 different input / output (I / O) pads or vias electrically connected to the four data lines of the extension space ECSL, respectively.

[0049] Please refer to Figure 6 , Figure 6 A schematic diagram showing the arrangement of the memory device 600 according to an embodiment of the present application is shown. For brevity, the capacity of the memory device 600 is similar to that shown in Figure 5The illustrated memory device. The main space MSPC and the extension space ECSL are controlled by column select circuit 601. The main space MSPC is controlled by 16 column select lines CSL<15:0>, and the extension space ECSL is controlled by 4 column select lines CSL<3:0>. When one of the column select lines CSL<15:0> is activated, 32 bits of data (i.e., DQ<31:0>) are output from the main space MSPC. In addition, when one of the column select lines CSL<3:0> is activated, 4 bits of data (i.e., DQ<35:32>) are output from the extension space ECSL. Note that when column select line CSL0 is activated, only 2 bits of data (i.e., D2 and D0) are output from the extension space ECSL because the other 2 bits of data (i.e., D3 and Dl) are allocated to the main space MSPC, and detailed description is omitted for brevity. As can be seen, the size or circuit area A62 of the extension space ECSL for storing ECC data is smaller than the circuit area of the existing corresponding portion of the ECC data storage memory (i.e., A61+A62). More specifically, for performing ECC operations on the accessed data, in the case of the existing ECC data storage memory, the memory data length can extend to 36 bits (DQ<35:0>) to correspond to all of the column select lines CSL<15:0>, i.e., when one of the column select lines CSL<15:0> is activated, 36 bits of data (i.e., DQ<35:0>) can be output from the memory space. In other words, the circuit areas A61 and A62 are necessary for the existing memory device. In contrast, in the present application, only some of the column select lines CSL<15:0> (e.g., 4 column select lines CSL<3:0>) are connected to the extension space ECSL to output the extension data DQ<35:32>. Therefore, only the circuit area A62 is needed, and the circuit area A61 can be saved. As a result, the circuit size of the memory device 600 can be reduced. Note that, according to the present application, the size of the extension space ECSL or the circuit area A62 is smaller than the size of the main space MSPC.

[0050] In addition, the memory controller can perform the ECC operation after the data in the main space MSPC is read out. In other words, the controller is configured to read the ECC data in the extension space ECSL after the data in the main space MSPC has been read. The memory controller can then use the ECC data in the extension space ECSL to perform the ECC operation on the data in the main space MSPC. For example, the memory controller can control column select line CSL0 to read the corresponding ECC data in the extension space ECSL after the main data bit in the main space MSPC corresponding to column select line CSL0 has been read out.

[0051] In some embodiments, the memory capacity of the main space MSPC can be expanded to 1024 bits by copying the original main space having 512 bits. The original main space shares the same area with the copied main space MSPC, which is also referred to as the open bit line architecture. The original main space and the copied main space constitute the main space MSPC. Similarly, the expansion space ECSL can also be expanded to 28 bits by copying the original expansion space having 14 bits. The original expansion space and the copied expansion space constitute the expansion space ECSL. The 28 bits of data in the expansion space ECSL can be used to perform a SECDED ECC operation on the 1024 bits of data in the main space MSPC. Note that the SECDED ECC operation is just one example, and one of ordinary skill in the art can modify the expansion space ECSL to have appropriate memory capacity according to different types of ECC operations.

[0052] Reference is made to Figure 7 , Figure 7 A schematic diagram of a semiconductor device according to an embodiment of the present application is shown. The semiconductor device 500 can be formed by two chips 510 and 520, where the chips 510 and 520 are electrically stacked with each other. The semiconductor device 500 can be implemented using a wafer-on-wafer (WoW) bonding technique. For example, one of the wafer-on-wafer bonding techniques is a hybrid bonding technique. For brevity, the bonding between the two chips 510 and 520 is shown as a dashed line as shown in Figure 7

[0053] ​Chip 510 includes a plurality of memory cell arrays MC that form memory device 511. Note that local data lines (LDLs) can be implemented in chip 510 with respective memory cell arrays MC. Chip 520 includes a controller that includes a plurality of logic circuits 521. Logic circuits 521 can be integrated with memory cell arrays MC in chip 510 via a bonding process or other integration methods well known to those of ordinary skill in the art. Each logic circuit 521 is configured to perform ECC operations for a respective memory cell array MC. Each logic circuit 521 can perform ECC encoding operations or ECC decoding operations. During a data write operation, each logic circuit 521 can perform an ECC encoding operation on write data to generate error correction codes. Each logic circuit 521 further writes the write data and respective error correction codes to a respective memory cell array MC. During a data read operation, stored data and respective ECC data can be read out, and each logic circuit 521 can perform an ECC decoding operation on the read out stored data and respective ECC data to generate syndrome values. The syndrome values are checked by logic circuits 521 to determine whether the read out stored data is correct, and further to correct erroneous bits of the read out stored data via the ECC operation. In some embodiments, the control logic can include a memory controller, an embedded memory controller, a processor, a central processing unit (CPU), or a graphics processing unit (GPU).

[0054] In this embodiment, ECC data can be transferred via the LDL structure mentioned in the above embodiments by the extra bits. More specifically, ECC data can be transferred from memory cell arrays MC in chip 510 to logic circuits 521 via a bond between the two chips 510 and 520. Logic circuits 521 can first read out stored data from respective memory cell arrays MC, second read out respective ECC data from respective memory cells, and then perform ECC operations. In some embodiments, each logic circuit 521 and each memory cell array MC can be placed laterally instead of being stacked vertically with each other on a packaging substrate such as a package board or an interposer.

[0055] Note that each memory cell array MC can have its own extra bits that are configured to be received as ECC data for detection or correction of the particular memory cell array MC. In some embodiments, the extra bits of a particular memory cell array MC are configured to be received as ECC data for detection or correction of another memory cell array MC. In some embodiments, the extra bits from a plurality of memory cell arrays MC are configured to be grouped and received as ECC data for detection or correction of a majority of the plurality of memory cell arrays MC.

[0056] In some embodiments, the memory device implemented by the semiconductor device 500 can include a memory controller. The memory controller can be disposed in the chip 520. The memory controller can be electrically coupled to the memory device 620 through the I / O pads 701 and the extended I / O pads 702. The memory controller can receive the normal storage data and the ECC data through the I / O pads 701 and the extended I / O pads 702, respectively. In addition, in some embodiments, the memory controller can be further configured to perform an ECC operation on the received normal storage data. Figure 6 The memory controller can receive the normal storage data and the ECC data through the I / O pads 701 and the extended I / O pads 702, respectively. In addition, in some embodiments, the memory controller can be further configured to perform an ECC operation on the received normal storage data.

[0057] It is noted herein that, in some embodiments, the ECC decoder and the ECC encoder can be disposed together with the memory cell array MC in the first chip 510. However, it is not limited thereto. In some embodiments, the ECC decoder and the ECC encoder can be disposed in the logic circuit 521 of the second chip 520 corresponding to the memory cell array MC in the first chip 510.

[0058] It is noted herein that, in some embodiments, the ECC decoder and the ECC encoder can be disposed together with the memory cell array MC in the first chip 510. However, it is not limited thereto. In some embodiments, the ECC decoder and the ECC encoder can be disposed in the logic circuit 521 of the second chip 520 corresponding to the memory cell array MC in the first chip 510. Figure 8 , Figure 8 A block diagram of a semiconductor device according to an embodiment of the present application is shown. The semiconductor device 800 includes a controller 610 and a memory device 620. The controller 610 is electrically coupled to the memory device 620. The controller 610 includes an ECC circuit 611 which can be implemented by a digital circuit. The ECC circuit 611 is configured to perform an ECC operation based on extra bits transmitted from the memory device 620. The memory device 620 includes a memory cell array 621, a word line (WL) decoder 622, a sense amplifier 623, and a column decoder 624. In this embodiment, a first portion of the memory cell array 621 can be configured to store main bits, and another portion of the memory cell array 621 can be configured to store extra bits. The extra bits can be error correction / detection information, such as ECC data. In some embodiments, the memory device 620 can be disposed in a first chip 510, and the controller 610 can be disposed in a second chip 520. In this embodiment, the memory cell array 621 can be a DRAM array.

[0059] The controller 610 is coupled to the WL decoder 622 and the column decoder 624, and transmits address information ADD to the WL decoder 622 and the column decoder 624. The WL decoder 622 and the column decoder 624 decode the address information ADD to access the memory cell array 621, and during a data read operation, the memory cell array 621 can transmit read data to the controller 610 through the sense amplifier 623, where the read data can be either the main bits MBIT (or normal storage data) or the extra bits EBIT as described in the foregoing.

[0060] The ECC circuit 611 can include a plurality of ECC decoders and ECC encoders. The memory cell array 621 can be divided into a plurality of portions, and the ECC decoders and the ECC encoders can correspond to the portions of the memory cell array 621, respectively.

[0061] In the present disclosure, a large number of I / Os can be achieved by Figure 1 The segmentation of the local data lines {LDL} and the additional bit line groups is shown to achieve a large number of I / Os. In some embodiments, the number of I / Os can exceed 10,000. In some embodiments, the number of I / Os can exceed 500,000. Thus, high bandwidth operation on a memory device can be achieved by a large number of I / Os.

[0062] Various modifications and changes can be made to the disclosed embodiments without departing from the scope or spirit of the application. Accordingly, it is intended that the present application cover all such modifications and changes as fall within the scope of the following claims and their equivalents.

[0063] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit it; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory device, comprising: The first line group includes the first line and the second line; The first column selection circuit is coupled to the first bit line and the second bit line; The first data line includes a first segment coupled to the first column select circuit; as well as The second data line includes a second segment coupled to the first column select circuit; The first column selection circuit is used to electrically connect the first bit line to the first line segment to transmit the first bit of normal data to the first line segment, and to electrically connect the second bit line to the second line segment to transmit the first bit of error correction / detection code data to the second line segment.

2. The memory device according to claim 1, further comprising: The first through hole is configured to be electrically coupled to the first line segment; The second through hole is configured to be electrically coupled to the second line segment; A memory controller is configured to be electrically coupled to the first via and the second via to receive the first bit of the normal data and the first bit of the error correction / detection code data, respectively, during a normal data read operation and an error correction / detection code data read operation.

3. The memory device of claim 2, wherein the memory controller performs the error correction / detection code data read operation after the normal data read operation.

4. The memory device of claim 2, wherein the first data line further comprises a third segment, and the memory device further comprises: The second line group includes the third and fourth lines; as well as The second column selection circuit is coupled to the third bit line and the fourth bit line; The second column selection circuit is used to electrically connect the third bit line to the third line segment to transmit the second bit of the error correction / detection code data to the third line segment, and to electrically connect the fourth bit line to the second line segment to transmit the third bit of the error correction / detection code data to the second line segment.

5. The memory device according to claim 4, further comprising: The third through hole is configured to be electrically coupled to the third line segment; The memory controller is further configured to receive the second bit of the error correction / detection code data through the third through-hole during the error correction / detection code data read operation, and to receive the third bit of the error correction / detection code data through the second through-hole.

6. The memory device of claim 4, wherein the first line segment and the third line segment are separated by a first gap.

7. The memory device of claim 6, wherein the second data line further comprises a fourth segment, and the memory device further comprises: The third line group includes the fifth and sixth lines; as well as The third column selection circuit is coupled to the fifth bit line and the sixth bit line; The third column selection circuit is used to electrically connect the fifth bit line to the first line segment to transmit the second bit of the normal data to the first line segment, and to electrically connect the sixth bit line to the fourth line segment to transmit the third bit of the normal data to the fourth line segment. The second line segment and the fourth line segment are separated by a second gap, and the first gap and the second gap form a first straight line, which is perpendicular to the first data line and the second data line.

8. The memory device of claim 7, wherein the first data line further includes a fifth segment, and the second data line further includes a sixth segment, and the memory device further includes: The fourth line group includes the seventh and eighth lines; as well as The fourth column selection circuit is coupled to the seventh bit line and the eighth bit line; The fourth column selection circuit is used to electrically connect the seventh line to the fifth line segment to transmit a fourth bit of the error correction / detection code data to the fifth line segment, and to electrically connect the eighth line to the sixth line segment to transmit a fifth bit of the error correction / detection code data to the sixth line segment. The third line segment and the fifth line segment are separated by a third gap, and the second line segment and the sixth line segment are separated by a fourth gap. The third gap and the fourth gap form a second straight line, which is perpendicular to the first data line and the second data line.

9. The memory device according to claim 8, further comprising: The fifth line group includes the ninth and tenth lines; as well as The fifth column selection circuit is coupled to the ninth bit line and the tenth bit line; The fifth column selection circuit is used to electrically connect the ninth line to the third line segment to transmit the sixth bit of the error correction / detection code data to the third line segment, and to electrically connect the tenth line to the sixth line segment to transmit the seventh bit of the error correction / detection code data to the sixth line segment.

10. The memory device according to claim 9, further comprising: The fourth through hole is configured to be electrically coupled to the third line segment; as well as The fifth through hole is configured to be electrically coupled to the sixth line segment; The memory controller is further configured to be electrically coupled to the fourth and fifth vias to receive the sixth and seventh bits of the error correction / detection code data during the error correction / detection code data read operation.

11. A memory device, comprising: Multiple memory cell arrays; as well as Multiple data sensing circuit regions, each of which is arranged between two adjacent data sensing circuit regions in the memory cell array, each of which includes: The main space has multiple input / output pads to output normally stored data during normal data read operations; and An extended space, arranged adjacent to the main space, has multiple extended input / output pads to output error correction / detection code data during an error correction / detection code data read operation; During the normal data read operation, at least the first bit of the normally stored data is generated from the expanded space.

12. The memory device of claim 11, wherein the size of the expansion space is smaller than the size of the main space.

13. The memory device of claim 11, further comprising: The memory controller is electrically coupled to the main space and the expansion space via the input / output pads and the extended input / output pads to receive the normally stored data and the error correction / detection code data; The memory controller is further configured to perform the error correction / detection code read operation on the normally stored data.

14. The memory device of claim 13, wherein the main space and the extended space are formed in a first chip of a first semiconductor wafer, the memory controller is formed in a second chip of a second semiconductor wafer, and the memory controller is bonded to the main space and the extended space via the input / output pads and the extended input / output pads.

15. The memory device of claim 11, wherein each of the data sensing circuit regions further comprises: A column selection circuit is configured to control the output of the normally stored data in the main space and the extended space during the normal data read operation, and to control the output of the error correction / detection code data in the extended space during the error correction / detection code data read operation after the normal data read operation.

16. The memory device of claim 11, wherein the main space includes a first line segment, and the expansion space includes: The first line group includes the first line and the second line; The first column selection circuit is coupled to the first bit line and the second bit line; as well as The second segment is coupled to the first column selection circuit; The first column selection circuit is used to electrically connect the first bit line to the first line segment to transmit the first bit of the normal data to the first line segment, and to electrically connect the second bit line to the second line segment to transmit the first bit of the error correction / detection code data to the second line segment.

17. The memory device of claim 16, wherein the main space further includes a first through-hole disposed for electrically coupled to the first line segment, the expanded space further includes a second through-hole disposed for electrically coupled to the second line segment, and the memory device further includes: A memory controller is configured to be electrically coupled to the first via and the second via to receive the first bit of the normal data and the first bit of the error correction / detection code data during the normal data read operation and the error correction / detection code data read operation, respectively.

18. The memory device of claim 16, wherein the expansion space further comprises: The third line segment; The second line group includes the third and fourth lines; as well as The second column selection circuit is coupled to the third bit line and the fourth bit line; The second column selection circuit is used to electrically connect the third bit line to the third line segment to transmit the second bit of the error correction / detection code data to the third line segment, and to electrically connect the fourth bit line to the second line segment to transmit the third bit of the error correction / detection code data to the second line segment.

19. The memory device of claim 18, wherein the first line segment and the third line segment are separated by a first gap.

20. The memory device of claim 19, wherein the main space further comprises: Fourth line segment; The third line group includes the fifth and sixth lines; as well as The third column selection circuit is coupled to the fifth bit line and the sixth bit line; The third column selection circuit is used to electrically connect the fifth bit line to the first line segment to transmit the second bit of the normal data to the first line segment, and to electrically connect the sixth bit line to the fourth line segment to transmit the third bit of the normal data to the fourth line segment. The second line segment and the fourth line segment are separated by a second gap, and the first gap and the second gap form a first straight line, and the first straight line is perpendicular to the first data line and the second data line.

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