Amplifier noise cancellation

Abstract

The invention relates to amplifier noise cancellation. The wireless circuitry may include amplifier circuitry. The amplifier circuit may include: a first input transistor having a gate terminal coupled to an input terminal; a second input transistor having a gate terminal coupled to the input terminal; a first inductor coupled to a source terminal of the first input transistor; and a capacitor having a first terminal coupled to the source terminal of the first input transistor and having a second terminal coupled to the source terminal of the second input transistor. The amplifier circuit may also include a second inductor coupled between the source terminal of the second input transistor and a power line. The capacitor may be configured to resonate with the first inductor and the second inductor to provide noise cancellation at a target operating frequency.

Description

[0001] This application claims priority to U.S. Patent Application No. 18 / 778,687, filed July 19, 2024, and U.S. Patent Application No. 18 / 778,709, filed July 19, 2024, which are hereby incorporated by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates generally to electronic devices, and more particularly to electronic devices having wireless communication circuitry. BACKGROUND

[0003] Electronic devices can have wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless communication circuitry with one or more antennas. Wireless transceiver circuitry in the wireless communication circuitry uses the antennas to transmit and receive radio frequency signals.

[0004] Radio frequency signals transmitted by an antenna can be fed through a power amplifier configured to amplify a low power analog signal into a high power signal more suitable for long distance transmission through air. Radio frequency signals received at an antenna can be fed through a low noise amplifier configured to amplify a low power analog signal into a high power signal for processing at a receiver. Designing satisfactory amplifiers for electronic devices can be challenging. SUMMARY

[0005] One aspect of the present disclosure provides a circuit, comprising: a first input transistor having a gate terminal coupled to an input terminal; a second input transistor having a gate terminal coupled to the input terminal; a first inductor coupled to a source terminal of the first input transistor; and a capacitor having a first terminal coupled to the source terminal of the first input transistor and having a second terminal coupled to a source terminal of the second input transistor. The circuit can further comprise a second inductor coupled between the source terminal of the second input transistor and a power supply line and an input matching network coupled to the input terminal. The circuit can further comprise a first transformer having a first primary coil coupled to the first input transistor and a second transformer having a second primary coil coupled to the second input transistor. The capacitor can be configured to resonate with the first inductor and the second inductor. The first input transistor and the second input transistor can have a differential mode source impedance based on an inductance of the first inductor or the second inductor and a capacitance of the capacitor and a common mode source impedance based on the inductance of the first inductor or the second inductor and not based on the capacitance of the capacitor.

[0006] One aspect of the disclosure provides a circuit, comprising: a first amplifier having a first source degeneration inductor; a second amplifier having a second source degeneration inductor; and a noise cancellation circuit coupled between the first source degeneration inductor and the second source degeneration inductor. The first amplifier can include a first input transistor coupled in series with the first source degeneration inductor; the first input transistor can have a gate terminal coupled to an input terminal; the second amplifier can include a second input transistor coupled in series with the second source degeneration inductor; and the second input transistor can have a gate terminal coupled with the input terminal. The noise cancellation circuit can include a capacitor coupled across a source terminal of the first input transistor and a source terminal of the second input transistor.

[0007] One aspect of the disclosure provides an amplifier circuit, comprising: a first input transistor having a gate terminal coupled to an input terminal; a second input transistor having a gate terminal coupled to the input terminal; a first inductor coupled to a source terminal of the first input transistor; and a second inductor coupled to a source terminal of the second input transistor. The second inductor can be magnetically coupled to the first inductor according to a magnetic coupling coefficient, and the first input transistor and the second input transistor can exhibit a source impedance based on the magnetic coupling coefficient. The magnetic coupling coefficient can be based on an amount of overlap between the first inductor and the second inductor. The first inductor can have a first footprint, and the second inductor can have a second footprint that coincides with the first footprint. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a diagram of an exemplary electronic device having wireless circuitry in accordance with some embodiments.

[0009] Figure 2 is a diagram of an exemplary radio circuit having a radio frequency amplifier in accordance with some embodiments.

[0010] Figure 3 is a diagram of an exemplary amplifier having improved noise cancellation capability in accordance with some embodiments.

[0011] Figure 4 is a diagram of an exemplary amplifier having magnetically coupled source inductors in accordance with some embodiments.

[0012] Figure 5 is a side view showing partially overlapping source inductors in accordance with some embodiments.

[0013] Figure 6is a side view showing an overlapping source inductor according to some embodiments.

[0014] Figure 7 is a plot of noise figure as a function of frequency according to some embodiments. DETAILED DESCRIPTION

[0015] An electronic device, such as Figure 1 Device 10 of FIG. 1 can be equipped with wireless circuitry. The wireless circuitry can include amplifier circuitry, such as low noise amplifier (LNA) circuitry configured to amplify signals received via one or more antennas. The amplifier circuitry can include a first amplifier coupled to a quadrature (Q) mixer and having a first input transistor coupled in series with a first source inductor, a second amplifier coupled to an in-phase (I) mixer and having a second input transistor coupled in series with a second source inductor, and a differential capacitor coupled between the first source inductor and the second source inductor.

[0016] The differential capacitor can be configured to resonate with the source inductors. The first input transistor and the second input transistor can exhibit uncorrelated common mode noise and differential (differential mode) noise. By configuring the differential capacitor to resonate with the source inductors, the differential capacitor provides high impedance and can be technologically advantageous and beneficial by eliminating the differential noise. Alternatively, the first source inductor and the second source inductor can be magnetically coupled to each other to provide the desired differential noise cancellation.

[0017] Figure 1 Electronic device 10 of FIG. 1 can be a computing device, such as a laptop computer, a desktop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other hand-held or portable electronic device; a smaller device, such as a wrist-watch device, a pendant device, a headphone or earpiece device, a device embedded in eyeglasses, or other wearable equipment; or other wearable or miniature equipment, a television, a computer monitor, a gaming device, a navigation device, an embedded system such as a system in which electronic equipment having a display is installed in a kiosk or automobile, a voice- controlled speaker connected to wireless Internet, a home-entertainment system, a remote control, a game controller, a peripheral user input device, a wireless base station or access point, equipment implementing the functionality of two or more of these devices; or other electronic equipment.

[0018] As Figure 1As shown in the functional block diagram in FIG. 1, device 10 can include components that are located on or within an electronic device housing, such as housing 12. Housing 12 (which can sometimes be referred to as a case) can be formed from plastic, glass, ceramic, fiber composite, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations of these materials. In some embodiments, portions or all of housing 12 can be formed from a dielectric or other low electrical conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, housing 12 or at least some of the structures that make up housing 12 can be formed from metal elements.

[0019] Device 10 can include control circuitry 14. Control circuitry 14 can include storage, such as storage circuitry 16. Storage circuitry 16 can include hard disk drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid state drive), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage circuitry 16 can include storage that is integrated within device 10 and / or removable storage media.

[0020] Control circuitry 14 can include processing circuitry, such as processing circuitry 18. Processing circuitry 18 can be used to control the operation of device 10. Processing circuitry 18 can include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processors integrated circuits, application-specific integrated circuits, central processing units (CPUs), etc. Control circuitry 14 can be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 can be stored on storage circuitry 16 (e.g., storage circuitry 16 can include non-transitory (tangible) computer-readable storage media that stores software code). This software code can sometimes be referred to as program instructions, software, data, instructions, or code. Software code stored on storage circuitry 16 can be executed by processing circuitry 18.

[0021] Control circuitry 14 can be used to run software on device 10, such as satellite navigation application programs, Internet browsing application programs, Voice-over-Internet Protocol (VOIP) telephone call application programs, electronic mail application programs, media playback application programs, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include: Internet Protocols, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocols - sometimes referred to as Wi-Fi®), Bluetooth® protocols for other short-range wireless communication links, etc. ​The communication protocol can be a Bluetooth® protocol or other wireless personal area network (WPAN) protocol, an IEEE 802. ad protocol (e.g., an ultra-wideband protocol), a cellular telephone protocol (e.g., a 3G protocol, a 4G (LTE) protocol, a 5G protocol, etc.), an antenna diversity protocol, a satellite navigation system protocol (e.g., a global positioning system (GPS) protocol, a global navigation satellite system (GLONASS) protocol, etc.), an antenna-based spatial ranging protocol (e.g., a radio detection and ranging (RADAR) protocol or other desired distance detection protocol for signals transmitted at millimeter and centimeter wave frequencies), or any other desired communication protocol. Each communication protocol can be associated with a corresponding radio access technology (RAT) that specifies a physical connection method for implementing the protocol.

[0022] Device 10 can include input-output circuitry 20. Input-output circuitry 20 can include input-output devices 22. Input-output devices 22 can be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 can include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 can include touch sensors, displays (e.g., touch-sensitive displays and / or force-sensitive displays), light-emitting components such as displays without touch sensor capabilities, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jack and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses that detect motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to displays to detect pressure applied to the displays), etc. In some configurations, keyboards, headphones, displays, pointing devices such as trackpads, mice, and joysticks, and other input-output devices can be coupled to device 10 using wired or wireless connections (e.g., some of input-output devices 22 can be peripheral devices that are coupled to a main processing unit or other portion of device 10 via wired or wireless links).

[0023] Input-output circuitry 20 can include wireless circuitry 24 to support wireless communication. Wireless circuitry 24 (sometimes referred to herein as wireless communication circuitry 24) can include one or more antennas. Wireless circuitry 24 can also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, radio frequency transmit lines, and / or any other circuitry for transmitting and / or receiving radio frequency signals with antennas.

[0024] The wireless circuitry 24 can transmit and / or receive radio frequency signals within a corresponding frequency band of a radio frequency band (sometimes referred to herein as a communication band or simply a "band"). The frequency bands handled by the wireless circuitry 24 can include a wireless local area network (WLAN) band (e.g., a band of the IEEE 802.11 family of standards (IEEE 802.11) or other WLAN communication band) such as a 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), a 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), a 6E band (e.g., 5925 MHz to 7125 MHz), and / or other bands (e.g., 1875 MHz to 5160 MHz); a wireless personal area network (WPAN) band such as a 2.4 GHz band or other WPAN communication band; a cellular telephone band (e.g., a band of frequencies from about 600 MHz to about 5 GHz, a 3G band, a 4G LTE band, a 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, a 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); other centimeter or millimeter wave bands between 10 GHz and 300 GHz; a near field communication band (e.g., 13.56 MHz); a satellite navigation band (e.g., a GPS band of 1565 MHz to 1610 MHz, a GLONASS band, a BeiDou Navigation Satellite System (BDS) band, etc.); an ultra-wideband (UWB) band operating under the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; a communication band under the 3GPP family of wireless communication standards; a communication band under the IEEE 802.XX family of standards, and / or any other desired band of interest.

[0025] Figure 2 is a diagram illustrating exemplary components within the wireless circuitry 24. As shown in Figure 2 the wireless circuitry 24 can include processing circuitry (such as the processing circuitry 26), radio frequency (RF) transceiver circuitry (such as the radio frequency transceiver 28), radio frequency front end circuitry (such as the radio frequency front end module (FEM) 40), and an antenna 42. The processing circuitry 26 can include one or more baseband processors, application processors, general-purpose processors, microprocessors, microcontrollers, digital signal processors, host processors, specialized signal processing hardware, or other types of processors. The processing circuitry 26 can be coupled to the transceiver 28 by way of a path 34. The transceiver 28 can be coupled to the antenna 42 via a radio frequency transmission line path 36. The radio frequency front end module 40 can be disposed on the radio frequency transmission line path 36 between the transceiver 28 and the antenna 42.

[0026] In​Figure 2 In the example of FIG. 1, for clarity, the wireless circuit 24 is illustrated as including only one instance of the processing circuit 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. In general, the wireless circuit 24 can include any desired number of processing circuits 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. The processing circuit 26 can be coupled to one or more transceivers 28 by respective paths 34. Each transceiver 28 can include a transmitter circuit 30 configured to output uplink signals to the antenna 42, can include a receiver circuit 32 configured to receive downlink signals from the antenna 42, and can be coupled to one or more antennas 42 by a respective radio frequency transmission line path 36. Each radio frequency transmission line path 36 can have a respective front-end module 40 disposed thereon. If desired, two or more front-end modules 40 can be disposed on the same radio frequency transmission line path 36. If desired, one or more of the radio frequency transmission line paths in the wireless circuit 24 can be implemented without any front-end modules disposed thereon.

[0027] The radio frequency transmission line path 36 can be coupled to an antenna feed on the antenna 42. The antenna feed can include, for example, a positive antenna feed terminal and a ground antenna feed terminal. The radio frequency transmission line path 36 can have a positive transmission line signal path that is coupled to the positive antenna feed terminal on the antenna 42. The radio frequency transmission line path 36 can have a ground transmission line signal path that is coupled to the ground antenna feed terminal on the antenna 42. This example is merely illustrative, and in general the antenna 42 can be fed using any desired antenna feed scheme. If desired, the antenna 42 can have multiple antenna feeds that are coupled to one or more radio frequency transmission line paths 36.

[0028] The radio frequency transmission line path 36 can include a transmission line for routing radio frequency antenna signals within the device 10 Figure 1 The transmission lines in the device 10 can include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed from combinations of these types of transmission lines, etc. The transmission lines in the device 10, such as the transmission lines in the radio frequency transmission line path 36, can be integrated into rigid and / or flexible printed circuit boards.

[0029] In performing wireless transmission, the processor 26 can provide transmit signals (e.g., digital or baseband signals) to the transceiver 28 through the path 34. The transceiver 28 can also include circuitry for converting transmit (baseband) signals received from the processor 26 to corresponding radio frequency signals. For example, the transceiver circuitry 28 can include mixer circuitry for upconverting (or modulating) transmit (baseband) signals to radio frequencies before transmission through the antenna 42. The transceiver 28 can include a transmitter (TX) 30 for transmitting radio frequency signals via the radio frequency transmission line path 36 and the front end module 40 through the antenna 42. The antenna 42 can transmit radio frequency signals to external wireless equipment by radiating the radio frequency signals into free space. Figure 2 Examples are merely illustrative. Generally, the transceiver 28 can communicate with a baseband processor, an application processor, a general purpose processor, a microcontroller, a microprocessor, or one or more processors within the circuitry 18. The transceiver circuitry 28 can also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital domain and the analog domain. The transceiver 28 can transmit radio frequency signals through the antenna 42 via the radio frequency transmission line path 36 and the front end module 40 using the transmitter (TX) 30. The antenna 42 can transmit radio frequency signals to external wireless equipment by radiating the radio frequency signals into free space.

[0030] In performing wireless reception, the antenna 42 can receive radio frequency signals from external wireless equipment. The received radio frequency signals can be passed to the transceiver 28 via the radio frequency transmission line path 36 and the front end module 40. The transceiver 28 can include circuitry for receiving signals from the front end module 40 and for converting received radio frequency signals to corresponding baseband signals, such as a receiver (RX) 32. For example, the transceiver 28 can include mixer circuitry for downconverting (or demodulating) received radio frequency signals to baseband frequencies before passing the received signals to the processor 26 through the path 34.

[0031] The front-end module (FEM) 40 can include radio-frequency front-end circuitry that operates on radio-frequency signals communicated (transmitted and / or received) over the radio-frequency transmission line path 36. For example, the FEM 40 can include front-end module (FEM) components such as radio-frequency filter circuitry 44 (e.g., low-pass filters, high-pass filters, notch filters, band-pass filters, multiplexing circuitry, duplexer circuitry, antenna sharing circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio-frequency switches), radio-frequency amplifier circuitry 48 (e.g., one or more power amplifier circuits 50 and / or one or more low-noise amplifier circuits 52), impedance matching circuitry (e.g., circuitry that helps match the impedance of the antenna 42 to the impedance of the radio-frequency transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of the antenna 42), radio-frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on radio-frequency signals transmitted and / or received by the antenna 42. Each of the front-end module components can be mounted to a common (shared) substrate such as a rigid printed circuit board substrate or a flexible printed circuit substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip. If desired, the amplifier circuitry 48 and / or other components in the front-end 40 such as the filter circuitry 44 can also be implemented as part of the transceiver circuitry 28.

[0032] The filter circuitry 44, switching circuitry 46, amplifier circuitry 48, and other circuitry can be disposed along the radio-frequency transmission line path 36, can be incorporated into the FEM 40, and / or can be incorporated into the antenna 42 (e.g., to support antenna tuning, to support operation in desired frequency bands, etc.). These components (sometimes referred to herein as antenna tuning components) can be adjusted (e.g., using the control circuitry 14) to adjust the frequency response and wireless performance of the antenna 42 over time.

[0033] The transceiver 28 can be separate from the front-end module 40. For example, the transceiver 28 can be formed on another substrate such as the main logic board, rigid printed circuit board, or flexible printed circuit of the device 10 that is not part of the front-end module 40. Although shown as being separate from the front-end module 40 for clarity, the transceiver 28 can be incorporated into the front-end module 40 if desired. Figure 1In the example, control circuitry 14 is shown separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18 and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). As an example, portions of processor 26 and / or transceiver 28 (e.g., a host processor on transceiver 28) may form part of control circuitry 14. Control circuitry 14 (e.g., portions of control circuitry 14 formed on processor 26, portions of control circuitry 14 formed on transceiver 28, and / or portions of control circuitry 14 separate from wireless circuitry 24) may provide control signals (e.g., via one or more control paths in device 10) to control the operation of front-end module 40.

[0034] Transceiver circuitry 28 may include processing WLAN communication bands (e.g., (IEEE 802.11) or other WLAN communication bands, such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz) and / or others Wireless LAN transceiver circuitry covering a frequency band (e.g., 1875MHz to 5160MHz); handling 2.4GHz. Wireless personal area network transceiver circuits for frequency bands or other WPAN communication bands; cellular phone transceiver circuits for processing cellular phone frequency bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); near field communication (NFC) transceiver circuits for processing near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuits for processing satellite navigation frequency bands (e.g., GPS band from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.); ultra-wideband (UWB) transceiver circuits for processing communications using the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuits for covering any other desired communication frequency bands of interest.

[0035] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 may be an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole, a combination of these designs, etc. Two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0036] Figure 3 This is a diagram of an exemplary amplifier circuit 100 with improved noise cancellation capability according to some embodiments. Amplifier circuit 100 can represent... Figure 2 One or more amplifiers 52, Figure 2 One or more amplifiers 50 and / or other amplifiers. Amplifier circuit 100 represents an implementation of an RF receiving (low noise) amplifier, sometimes described herein as an example. Figure 3 As shown, the amplifier circuit 100 may include a first amplifier 102-1 and a second amplifier 102-2.

[0037] The first amplifier 102-1 may include a first input transistor M1, a first inductor Ls1, a first cascode transistor M3, and a first transformer 80. Transistors M1 and M3 may be n-type transistors (e.g., n-channel metal-oxide-semiconductor or NMOS transistors). The first input transistor M1 may have a gate terminal coupled to the input terminal IN of the amplifier circuit 100, a drain terminal coupled to the first cascode transistor M3, and a source terminal coupled to the first inductor Ls1. When referring to the conductive terminals of a metal-oxide-semiconductor transistor, the terms "source" and "drain" are sometimes used interchangeably. Therefore, the source terminal and drain terminal are sometimes referred to as "source-drain" terminals (e.g., a transistor having a gate terminal, a first source-drain terminal, and a second source-drain terminal).

[0038] A first inductor Lsl is coupled between the input transistor Ml and a ground supply line 60 (e.g., a ground supply terminal on which a ground supply voltage Vss is provided). The inductor Lsl coupled to the source terminal of the input transistor Ml is sometimes referred to as a source inductor or a source degeneration inductor. A source degeneration inductor can mean and is defined herein as a series inductor coupled to the source terminal of an input transistor. A series capacitor Cin can be coupled at the input terminal IN. An inductor 70 and an adjustable capacitor 72 can be coupled in series between the input terminal IN and the ground line 60. The components Cin, 70, and 72 can optionally be configured as an adjustable input matching circuit (as an example). In general, an input matching network can include one or more capacitors, one or more inductors, and / or other passive or active components.

[0039] A first cascode transistor M3 can have a source terminal coupled to the input transistor Ml, a gate terminal configured to receive a bias voltage Vbias, and a drain terminal coupled to a transformer 80. The cascode transistor M3 is optional (e.g., the transistor M3 can be omitted from the amplifier 102-1). The transformer 80 is sometimes referred to as an output transformer or a load transformer. The transformer 80 can include a primary coil (winding) 80p and a secondary coil (winding) 80s. The primary coil 80p can have a first terminal coupled to the cascode transistor M3 and a second terminal coupled to a positive supply line 62 (e.g., a positive supply terminal on which a positive supply voltage Vdd is provided). The secondary coil 80s can be coupled to a corresponding mixer, such as a quadrature (Q) mixer 90. The quadrature mixer 90 can be configured to receive an oscillating signal LOq and can be configured to output a corresponding quadrature signal Q. A quadrature mixer 90 configured in this way can sometimes be referred to herein as a quadrature demodulator.

[0040] A second amplifier 102-2 can include a second input transistor M2, a second inductor Ls2, a second cascode transistor M4, and a second transformer 82. The transistors M2 and M4 can be n-type transistors (e.g., n-channel metal-oxide-semiconductor or NMOS transistors). The second input transistor M2 can have a gate terminal coupled to the input terminal IN of the amplifier circuit 100, a drain terminal coupled to the second cascode transistor M4, and a source terminal coupled to the second inductor Ls2. The second inductor Ls2 can be coupled between the input transistor M2 and the ground line 60. The inductor Ls2 coupled to the source terminal of the input transistor M2 is sometimes referred to as a source inductor or a source degeneration inductor. The inductors Lsl and Ls2 can be identical in shape and can have the same inductance value.

[0041] The second cascode transistor M2 can have a source terminal coupled to the input transistor M2, a gate terminal configured to receive a bias voltage Vbias, and a drain terminal coupled to the transformer 82. The cascode transistor M4 is optional (e.g., the transistor M4 can be omitted from the amplifier 102-2). The transformer 82 is sometimes referred to as an output transformer or a load transformer. The transformer 82 can include a primary winding 82p and a secondary winding 82s. The primary winding 82p can have a first terminal coupled to the cascode transistor M4 and a second terminal coupled to the positive supply rail 62. The secondary winding 82s can be coupled to a corresponding mixer, such as an in-phase (I) mixer 92. The quadrature mixer 92 can be configured to receive the oscillating signal LOi and can be configured to output a corresponding in-phase signal I. The oscillating signal LOi can be phase shifted (offset) by 90 degrees with respect to the signal LOq. The in-phase mixer 92 configured in this way can sometimes be referred to herein as an in-phase demodulator.

[0042] With care, the amplifier circuit 100 can be susceptible to noise, which can degrade its performance. According to some embodiments, the amplifier circuit 100 can include a differential capacitor Cs_diff having a first terminal coupled to the source terminal of the first input transistor Ml and having a second terminal coupled to the source terminal of the second input transistor M2 (e.g., the capacitor Cs_diff can be coupled between the source inductors Lsl and Ls2). Assuming that the components between the amplifiers 102-1 and 102-2 are matched, then any signals amplified by the amplifiers 102-1 and 102-2 should have the same amplitude and phase. Since these signals are common mode, the differential capacitor Cs_diff will appear invisible to the incoming radio frequency signals, so the addition of the capacitor Cs_diff will advantageously not affect the gain, input reflection coefficient, third order intercept point, or other performance metrics of the amplifier circuit 100.

[0043] Conversely, capacitor Cs_diff will be visible to any differential signal transmitted through amplifier circuit 100. According to some embodiments, capacitor Cs_diff can be configured to resonate with the differential source degenerate inductors. Assuming inductors Ls1 and Ls2 have the same inductance value Ls, capacitor Cs_diff and the two source inductors can be configured to resonate at frequencies that are functions of Cs_diff and 2*Ls. In practice, input transistors M1 and M2 may exhibit noise that is uncorrelated with each other. Noise may include common-mode noise and differential noise. Capacitor Cs_diff, resonating with the source inductors, can provide high impedance at the source nodes of the input transistors and can technically advantageously and beneficially eliminate the differential noise associated with input transistors M1 and M2 (e.g., by ensuring that any differential noise energy circulating through source inductors Ls1 and Ls2 does not flow into the input transistors).

[0044] Figure 7 It is a graph of the noise figure as a function of the operating frequency. For example... Figure 7 As shown, amplifier circuit 300 can exhibit a noise figure distribution 300, where the minimum value is aligned with frequency f*. Frequency f* can be equal to the resonant frequency, which is a function of capacitance Cs_diff and 2*Ls. With this configuration, the noise figure of amplifier circuit 100 can be minimized at frequency f*. If desired, the capacitance of differential capacitor Cs_diff can optionally be adjustable to tune or shift frequency f*. Therefore, in some embodiments, capacitor Cs_diff can be a tunable capacitor, an adjustable capacitor, a programmable capacitor, a group / array of switchable capacitors, or other types of adjustable capacitor circuitry.

[0045] The source impedance of amplifier circuit 100, viewed from the source terminals of input transistors M1 and M2 downwards, can be expressed as follows:

[0046] Zcm = jωLs / 2 (1)

[0047] Zdm = (jω*2Ls) / (1 -ω 2* 2Ls*Cs_diff) (2)

[0048] where Zcm in equation 1 represents the common mode source impedance of the input transistors, Zdm in equation 2 represents the differential mode source impedance of the input transistors, Ls represents the inductance of each of the source inductors Lsl and Ls2, and Cs_diff represents the capacitance of the differential capacitor. Since only Zdm is a function of Cs_diff (while Zcm is not a function of Cs_diff), this allows Zcm and Zdm to be controlled independently, providing improved flexibility in the design of the amplifier circuit 100. Thus, the capacitor Cs_diff is sometimes referred to herein as a noise cancellation circuit or component.

[0049] Figure 3 Embodiments of the amplifier circuit 100 are exemplary in which the amplifier circuit 100 is provided with a differential capacitor Cs_diff configured to reduce the noise of the circuit 100. Figure 4 Another embodiment of the amplifier circuit 100 is shown in which the first source inductor Lsl is magnetically coupled to the second source inductor Ls2 (see, e.g., as shown by the magnetic coupling arrow 100). In contrast to the embodiment of Figure 3 Figure 4 The amplifier circuit 100 of the embodiment of Figure 4 does not include a differential capacitor Cs_diff. Figure 3 The remaining structure of the amplifier circuit 100 of the embodiment of

[0050] As shown in Figure 4 , the first source inductor Lsl can be magnetically or inductively coupled to the second source inductor Ls2 with a coupling factor km. The source impedance of the amplifier circuit 100 when looking down from the source terminals of the input transistors Ml and M2 can be expressed as follows:

[0051] Zcm = (1 + km)*jcoLs / 2 (3)

[0052] Zdm = 2(1 - km)*jcoLs (4)

[0053] where Zcm in equation 3 represents the common mode source impedance of the input transistors, Zdm in equation 4 represents the differential mode source impedance of the input transistors, and Ls represents the inductance of each of the source inductors Lsl and Ls2. Since both Zcm and Zdm are functions of the coupling factor km, the magnetic coupling between the two source inductors can also be tuned to independently control Zcm and Zdm.

[0054] The amount of magnetic coupling between the inductors Lsl and Ls2 (e.g., the value of the coupling factor km) can be tuned by the amount of overlap between the two inductors. Figure 5 ​is a side view showing partially overlapping source inductors Lsl and Ls2 according to some embodiments. As shown Figure 5 As shown, an interconnect stack such as interconnect stack 202 can be formed on semiconductor substrate 200. As an example, semiconductor substrate 200 can be a p-type (p-doped) semiconductor substrate. Interconnect stack 202 can include alternating wiring layers and via layers. Each wiring layer can include conductive (metal) wiring paths formed in a dielectric material layer. Each via layer can include conductive (metal) vias formed in a dielectric material layer. Thus, interconnect stack 202 is sometimes referred to as a dielectric stack (e.g., an interconnect stack having conductive wiring paths formed within a dielectric material such as silicon dioxide). The conductive wiring paths and via structures can be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, metal alloys, combinations of metals, and / or other types of conductive materials. The metal wiring and via structures can form an electrical network for interconnecting various components within an integrated circuit die or chip together.

[0055] In the example of Figure 5 , inductor Lsl can be formed in a first metal wiring layer, while inductor Ls2 is formed in a second metal wiring layer. Inductors Lsl and Ls2 can each be implemented as a coil having windings with any number of turns (e.g., only one turn, partial turns, two or more turns, three or more turns, four or more turns, etc.), any winding pattern (e.g., a spiral winding pattern, a figure-8 winding pattern, etc.), and any suitable shape (e.g., circular, octagonal, rectangular, square, hexagonal, etc.). Inductors Lsl and Ls2 can partially overlap (see partially overlapping portion 204). Figure 5 The example of is illustrative in which inductors Lsl and Ls2 are each shown as having only a single layer of conductive material. If desired, Lsl and Ls2 can each be implemented as a coil structure having two or more layers or three or more layers of conductive material. In other embodiments, Ls2 can be formed above Lsl in dielectric stack 202.

[0056] Figure 5 The partially overlapping arrangement of Figure 6 may provide a relatively low amount of magnetic coupling. According to another embodiment, source inductors Lsl and Ls2 can completely overlap (e.g., see Figure 6 As shown, inductors Lsl and Ls2 can be horizontally aligned such that the footprint of inductor Lsl coincides with the footprint of inductor Ls2. In general, inductors Lsl and Ls2 can each be implemented as a coil having windings with any number of turns, any winding pattern, and any suitable shape. Figure 6An example of FIG. 1 is illustrative in which inductors Lsl and Ls2 are each shown as having only a single layer of conductive material. If desired, Lsl and Ls2 can each be implemented as a coil structure having two or more layers or three or more layers of conductive material. In other embodiments, Ls2 can be formed above Lsl in the dielectric stack 202. Figure 6 The fully overlapping arrangement of FIG. 1 can provide a large amount of magnetic coupling to improve noise cancellation capabilities.

[0057] The methods and operations described above in connection with Figures 1 to 4 The methods and operations described above in connection with Figure 1 may be performed by components of the device 10 using software, firmware, and / or hardware (e.g., special-purpose circuitry or hardware). Software code for performing these operations can be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more of the components of the device 10 (e.g., the storage circuitry 16 and / or the wireless communication circuitry 24 of the device 10). This software code can sometimes be referred to as software, data, instructions, program instructions, or code. The non-transitory computer-readable storage medium can include a drive, a non-volatile memory such as a non-volatile random access memory (NVRAM), a removable flash drive or other removable medium, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium can be executed by processing circuitry (e.g., processing circuitry 18 in the wireless circuitry 24, etc.) on one or more of the components of the device 10. The processing circuitry can include a microprocessor, an application processor, a digital signal processor, a central processing unit (CPU), a special-purpose integrated circuit, or other processing circuitry. Figure 1 The methods and operations described above in connection with

[0058] According to an embodiment, the circuit comprises: a first input transistor having a gate terminal coupled to an input terminal; a second input transistor having a gate terminal coupled to the input terminal; a first inductor coupled to a source terminal of the first input transistor; and a capacitor having a first terminal coupled to the source terminal of the first input transistor and having a second terminal coupled to a source terminal of the second input transistor.

[0059] According to another embodiment, the circuit optionally comprises a second inductor coupled between the source terminal of the second input transistor and a power supply line.

[0060] According to another embodiment, the circuit optionally comprises an input matching network coupled to the input terminal.

[0061] According to another embodiment, the circuit optionally includes a first transformer having a first primary coil coupled to the first input transistor.

[0062] According to another embodiment, the circuit optionally includes a second transformer having a second primary coil coupled to the second input transistor.

[0063] According to another embodiment, the circuit optionally includes a first cascode transistor coupled between the first primary coil and the first input transistor, and optionally a second cascode transistor coupled between the second primary coil and the second input transistor.

[0064] According to another embodiment, the circuit optionally includes a first mixer coupled to a first secondary coil of the first transformer, and optionally a second mixer coupled to a second secondary coil of the second transformer.

[0065] According to another embodiment, the first mixer is optionally configured to receive a first oscillation signal, and the second mixer is optionally configured to receive a second oscillation signal different from the first oscillation signal, wherein the first oscillation signal and the second oscillation signal are optionally offset in phase by 90 degrees.

[0066] According to another embodiment, the capacitor is optionally configured to resonate with the first inductor and the second inductor.

[0067] According to another embodiment, the first input transistor and the second input transistor optionally include a differential-mode source impedance based on an inductance of the first inductor or the second inductor and a capacitance of the capacitor, and optionally a common-mode source impedance based on the inductance of the first inductor or the second inductor and not based on the capacitance of the capacitor.

[0068] According to an embodiment, a circuit includes a first amplifier having a first source-degeneration inductor, a second amplifier having a second source-degeneration inductor, and a noise cancellation circuit coupled between the first source-degeneration inductor and the second source-degeneration inductor.

[0069] According to another embodiment, the first amplifier optionally includes a first input transistor coupled in series with the first source-degeneration inductor, the first input transistor optionally having a gate terminal coupled to an input terminal, the second amplifier optionally includes a second input transistor coupled in series with the second source-degeneration inductor, and the second input transistor has a gate terminal coupled to the input terminal.

[0070] According to another embodiment, the noise cancellation circuit optionally includes a capacitor coupled across a source terminal of the first input transistor and a source terminal of the second input transistor.

[0071] According to another embodiment, the first amplifier optionally includes a first transformer coupled to the first input transistor, and the second amplifier optionally includes a second transformer coupled to the second input transistor.

[0072] According to another embodiment, the circuit optionally includes a first demodulator coupled to the first transformer and a second demodulator coupled to the second transformer.

[0073] According to an embodiment, the circuit includes a first amplifier having a first input, a second amplifier having a second input shorted to the first input, and a differential noise cancellation circuit coupled between the first amplifier and the second amplifier.

[0074] According to another embodiment, the differential noise cancellation circuit optionally includes a capacitor.

[0075] According to another embodiment, the first amplifier optionally includes a first input transistor and a first inductor optionally coupled to a source terminal of the first input transistor.

[0076] According to another embodiment, the second amplifier optionally includes a second input transistor and a second inductor optionally coupled to a source terminal of the second input transistor.

[0077] According to another embodiment, the differential noise cancellation circuit optionally includes a first terminal coupled to a first node disposed between the first input transistor and the first inductor, and a second terminal optionally coupled to a second node disposed between the second input transistor and the second inductor.

[0078] According to an embodiment, an amplifier circuit includes a first input transistor having a gate terminal coupled to an input terminal, a second input transistor having a gate terminal coupled to the input terminal, a first inductor coupled to a source terminal of the first input transistor, and a second inductor coupled to a source terminal of the second input transistor, wherein the second inductor is magnetically coupled to the first inductor.

[0079] According to another embodiment, the second inductor is optionally magnetically coupled to the first inductor according to a magnetic coupling coefficient, and the first input transistor and the second input transistor optionally exhibit source impedances based on the magnetic coupling coefficient.

[0080] According to another embodiment, the second inductor is optionally magnetically coupled to the first inductor with a magnetic coupling coefficient, and the magnetic coupling coefficient is optionally based on an amount of overlap between the first inductor and the second inductor.

[0081] According to another embodiment, the first inductor optionally has a first footprint, and the second inductor optionally has a second footprint that overlaps the first footprint.

[0082] According to another embodiment, the amplifier circuit optionally includes a series capacitor coupled between the input terminal and gate terminals of the first input transistor and the second input transistor.

[0083] According to another embodiment, the amplifier circuit optionally includes a first transformer having a first primary coil coupled to the first input transistor.

[0084] According to another embodiment, the amplifier circuit optionally includes a second transformer having a second primary coil coupled to the second input transistor.

[0085] According to another embodiment, the amplifier circuit optionally includes a first common- source common-gate transistor coupled between the first primary coil and the first input transistor, and a second common-source common-gate transistor coupled between the second primary coil and the second input transistor.

[0086] According to another embodiment, the amplifier circuit optionally includes a first mixer coupled to a first secondary coil of the first transformer, and a second mixer coupled to a second secondary coil of the second transformer.

[0087] According to another embodiment, the first mixer is optionally configured to receive a first oscillation signal, and the second mixer is optionally configured to receive a second oscillation signal different from the first oscillation signal, wherein the first oscillation signal and the second oscillation signal are optionally offset in phase by 90 degrees.

[0088] According to an embodiment, a circuit includes: a first amplifier configured to receive a radio frequency signal and having a first source degeneration inductor; and a second amplifier configured to receive the radio frequency signal and having a second source degeneration inductor magnetically coupled to the first source degeneration inductor via a magnetic coupling coefficient, the first amplifier and the second amplifier having a source impedance based on the magnetic coupling coefficient.

[0089] According to another embodiment, the first source degeneration inductor optionally has a first footprint, wherein the second source degeneration inductor optionally has a second footprint that at least partially overlaps the first footprint by an overlap amount, and the magnetic coupling coefficient is optionally based on the overlap amount.

[0090] According to another implementation, the first amplifier optionally includes a first input transistor having a source terminal directly coupled to the first source degeneration inductor, and the second amplifier optionally includes a second input transistor having a source terminal directly coupled to the second source degeneration inductor.

[0091] According to another implementation, the first amplifier optionally includes a first transformer coupled in series with the first input transistor, and the second amplifier optionally includes a second transformer coupled in series with the second input transistor.

[0092] According to another implementation, the circuit optionally includes a first mixer having an input coupled to the first transformer, and a second mixer having an input coupled to the second transformer.

[0093] According to an implementation, a circuit includes: a first amplifier having a first input and a first passive electrical component; and a second amplifier having a second input shorted to the first input and having a second passive electrical component magnetically coupled to the first passive electrical component for canceling differential noise associated with the first amplifier and the second amplifier.

[0094] According to another implementation, the first passive electrical component optionally includes a first inductor, and the second passive electrical component optionally includes a second inductor.

[0095] According to another implementation, the first inductor optionally has a first footprint, and the second inductor optionally has a second footprint at least partially overlapping the first footprint.

[0096] According to another implementation, the first amplifier optionally includes a first input transistor coupled in series with the first passive electrical component, and the second amplifier optionally includes a second input transistor coupled in series with the second passive electrical component.

[0097] According to another implementation, the first amplifier optionally includes a first transformer coupled in series with the first input transistor, and the second amplifier optionally includes a second transformer coupled in series with the second input transistor.

[0098] The foregoing is merely illustrative and various modifications can be made to the implementations described. Such implementations can be implemented individually, or in any combination so desired.

[0099] It is well understood that the use of personally identifiable information should follow privacy policies and practices that are generally recognized as satisfying or exceeding industry or government requirements for maintaining the privacy of users. In particular, personally identifiable information data should be managed and handled in a manner that minimizes risks from unauthorized or improper access or use, and privacy responsibilities should be clearly outlined in dealings with users to authorize use.

Claims

1. A circuit, the circuit comprising: a first input transistor having a gate terminal coupled to an input terminal; a second input transistor having a gate terminal coupled to the input terminal; a first inductor coupled to a source terminal of the first input transistor; and a capacitor having a first terminal coupled to the source terminal of the first input transistor and having a second terminal coupled to a source terminal of the second input transistor.

2. The circuit of claim 1, the circuit further comprising: a second inductor coupled between the source terminal of the second input transistor and a power supply line.

3. The circuit of claim 2, the circuit further comprising: an input matching network coupled to the input terminal.

4. The circuit of claim 2, the circuit further comprising: a first transformer having a first primary coil coupled to the first input transistor.

5. The circuit of claim 4, the circuit further comprising: a second transformer having a second primary coil coupled to the second input transistor.

6. The circuit of claim 5, the circuit further comprising: a first cascode transistor coupled between the first primary coil and the first input transistor; and a second cascode transistor coupled between the second primary coil and the second input transistor.

7. The circuit of claim 5, the circuit further comprising: a first mixer coupled to a first secondary coil of the first transformer; and a second mixer coupled to a second secondary coil of the second transformer.

8. The circuit of claim 7, wherein: the first mixer is configured to receive a first oscillation signal; and the second mixer is configured to receive a second oscillation signal different from the first oscillation signal, wherein the first oscillation signal and the second oscillation signal are offset in phase by 90 degrees.

9. The circuit of claim 2, wherein the capacitor is configured to resonate with the first inductor and the second inductor.

10. The circuit of claim 2, wherein the first input transistor and the second input transistor comprise: a differential-mode source impedance based on an inductance of the first inductor or the second inductor and a capacitance of the capacitor; and a common-mode source impedance based on the inductance of the first inductor or the second inductor and not based on the capacitance of the capacitor.

11. A circuit, the circuit comprising: a first amplifier having a first source-degeneration inductor; a second amplifier having a second source-degeneration inductor; and a noise cancellation circuit coupled between the first source-degeneration inductor and the second source-degeneration inductor. ​ ​ ​ ​ ​ 12. The circuit of claim 11, wherein: the first amplifier includes a first input transistor coupled in series with the first source degeneration inductor; the first input transistor has a gate terminal coupled to an input terminal; the second amplifier includes a second input transistor coupled in series with the second source degeneration inductor; and the second input transistor has a gate terminal coupled to the input terminal.

13. The circuit of claim 12, wherein the noise cancellation circuit includes a capacitor coupled across source terminals of the first input transistor and the second input transistor.

14. The circuit of claim 12, wherein: the first amplifier further includes a first transformer coupled to the first input transistor; and the second amplifier further includes a second transformer coupled to the second input transistor.

15. The circuit of claim 14, further comprising: a first demodulator coupled to the first transformer; and a second demodulator coupled to the second transformer.

16. A circuit, comprising: a first amplifier having a first input terminal; a second amplifier having a second input terminal shorted to the first input terminal; and a differential noise cancellation circuit coupled between the first amplifier and the second amplifier.

17. The circuit of claim 16, wherein the differential noise cancellation circuit includes a capacitor.

18. The circuit of claim 16, wherein the first amplifier includes: a first input transistor; and a first inductor coupled to a source terminal of the first input transistor.

19. The circuit of claim 18, wherein the second amplifier includes: a second input transistor; and a second inductor coupled to a source terminal of the second input transistor.

20. The circuit of claim 19, wherein the differential noise cancellation circuit includes: a first terminal coupled to a first node disposed between the first input transistor and the first inductor; and a second terminal coupled to a second node disposed between the second input transistor and the second inductor. ​ ​ ​ ​ ​ ​

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