Low-voltage reset circuit and electronic chip

Abstract

The invention provides a low-voltage reset circuit and an electronic chip. The low voltage reset circuit includes first and second branches. The first branch comprises a first PMOS (P-channel Metal Oxide Semiconductor) sub-tube, a second PMOS sub-tube, a bipolar semiconductor tube and a first NMOS (N-channel Metal Oxide Semiconductor) tube, the first PMOS sub-tube and the second PMOS sub-tube are connected in parallel, a source electrode of the first PMOS sub-tube and a source electrode of the second PMOS sub-tube are connected together, a grid electrode of the first PMOS sub-tube and a grid electrode of the second PMOS sub-tube are connected to the ground, a drain electrode of the first PMOS sub-tube is connected to the ground through the bipolar semiconductor tube, and a drain electrode of the second PMOS sub-tube is connected to the ground through the NMOS tube. The grid electrode and the drain electrode of the first NMOS tube are in short circuit connection with the drain electrode of the second sub PMOS tube, and the source electrode of the first NMOS tube is grounded. The second branch comprises a second PMOS tube and a second NMOS tube, the source electrode of the second PMOS tube is connected with the power supply voltage, the grid electrode of the second PMOS tube is connected with the drain electrode of the first sub PMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube. According to the invention, the discreteness problem that the low-voltage reset threshold drifts along with the process can be greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a low-voltage reset circuit and an electronic chip. BACKGROUND

[0002] At present, a low-voltage reset (LVR) circuit is mainly applied to a microcontroller (MCU) and a digital-analog hybrid integrated circuit, and mainly functions to monitor whether a chip power supply is lower than a certain threshold value in real time, so as to send a reset signal. When a power supply voltage abnormally drops, the low-voltage reset circuit generates a reset level to reset the chip, so as to ensure the stability of all internal digital logic, and also to timely process and store relevant data to prevent confusion and loss. The low-voltage reset circuit also plays an initializing role for analog and digital circuits in a chip power-on process.

[0003] The low-voltage reset circuit is an important circuit module indispensable to a chip, but it mainly monitors the power-on and power-off of the chip power supply, so it often needs to adopt a simple circuit structure, a small number of components, a small layout area, and a relatively stable reset threshold value. At present, there are many types of low-voltage reset circuits, and a resistor voltage dividing and reference voltage comparison mode is adopted. Although the reset threshold value of this mode will not be scattered due to production process drift, a comparator and a reference voltage are needed, the circuit structure is complex, and the power consumption is also high. SUMMARY

[0004] The purpose of the embodiment of the present application is to provide a low-voltage reset circuit and an electronic chip, which can greatly improve the problem of the dispersion of the low-voltage reset threshold value with process drift.

[0005] One aspect of the embodiments of the present application provides a low-voltage reset circuit. The low-voltage reset circuit includes a first branch and a second branch. The first branch is connected between a power supply voltage and a ground, and is configured to generate a first bias current. The first branch includes a first sub PMOS transistor and a second sub PMOS transistor, a bipolar transistor, and a first NMOS transistor, the first sub PMOS transistor and the second sub PMOS transistor are connected in parallel, a source of the first sub PMOS transistor and a source of the second sub PMOS transistor are connected together, a gate of the first sub PMOS transistor and a gate of the second sub PMOS transistor are connected together and connected to the ground, a drain of the first sub PMOS transistor is connected to the ground through the bipolar transistor, a gate of the first NMOS transistor and a drain of the first NMOS transistor are shorted to a drain of the second sub PMOS transistor, and a source of the first NMOS transistor is connected to the ground. The second branch is connected between the power supply voltage and the ground, and is configured to monitor the power supply voltage and output an output voltage. The second branch includes a second PMOS transistor and a second NMOS transistor, wherein a source of the second PMOS transistor is connected to the power supply voltage, a gate of the second PMOS transistor is connected to a drain of the first sub PMOS transistor, a drain of the second PMOS transistor is connected to a drain of the second NMOS transistor, a source of the second NMOS transistor is connected to the ground, and a gate of the second NMOS transistor is connected to a gate of the first NMOS transistor.

[0006] Further, the bipolar transistor includes a PNP transistor, an emitter of the PNP transistor is connected to a drain of the first sub PMOS transistor, and a base of the PNP transistor and a collector of the PNP transistor are shorted to the ground.

[0007] Further, the bipolar transistor includes an NPN transistor, a base of the NPN transistor and a collector of the NPN transistor are shorted to a drain of the first sub PMOS transistor, and an emitter of the NPN transistor is connected to the ground.

[0008] Further, the bipolar transistor includes a diode, an anode of the diode is connected to a drain of the first sub PMOS transistor, and a cathode of the diode is connected to the ground.

[0009] Further, the low-voltage reset circuit further includes a third branch. The third branch is connected between the power supply voltage and the ground, and is configured to shape the output voltage.

[0010] Further, the first branch, the second branch, and the third branch are connected to the power supply voltage through a first resistor and connected to the ground through a first capacitor.

[0011] Further, the third branch includes a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor, wherein the gate of the third PMOS transistor and the gate of the third NMOS transistor are connected to the drain of the second PMOS transistor, the drain of the third PMOS transistor and the drain of the third NMOS transistor are connected, the source of the third PMOS transistor is connected to the power supply voltage, and the source of the third NMOS transistor is grounded; the gate of the fourth PMOS transistor and the gate of the fourth NMOS transistor are connected to the drain of the third PMOS transistor, the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are connected and connected to an output terminal for outputting the output voltage, the source of the fourth PMOS transistor is connected to the power supply voltage, and the source of the fourth NMOS transistor is grounded.

[0012] Further, the first branch includes a plurality of first PMOS transistors connected in series, wherein the drain and the source of adjacent two first PMOS transistors are connected, the gates of the plurality of first PMOS transistors are all grounded, the source of the first first PMOS transistor is connected to the power supply voltage, and the last first PMOS transistor includes the first sub PMOS transistor and the second sub PMOS transistor.

[0013] Further, the first PMOS transistor adopts an inverse ratio transistor, and the gate length of the inverse ratio transistor is greater than the gate width.

[0014] Another aspect of the embodiments of the present application provides an electronic chip. The electronic chip includes the low-voltage reset circuit as described above.

[0015] The low-voltage reset circuit of one or more embodiments of the present application can greatly improve the discreteness problem of the low-voltage reset threshold with process drift by adding a bipolar transistor, and maintains the simplicity of the circuit structure, has the advantages of small number of components, small layout area, extremely low power consumption and working independence. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 FIG. 1 is a structural schematic diagram of a low-voltage reset circuit in the related art.

[0017] Figure 2 FIG. 2 is a waveform relationship between the power supply voltage VDD and the output voltage LVR_OUT in the low-voltage reset circuit shown in FIG. 1. Figure 1

[0018] Figure 3 FIG. 3 is a structural schematic diagram of a low-voltage reset circuit of one embodiment of the present application.

[0019] Figure 4 FIG. 4 is a waveform schematic diagram of the output voltage of the low-voltage reset circuit of one embodiment of the present application before and after shaping.​

[0020] Figure 5 This is a schematic diagram of the structure of a low-voltage reset circuit according to another embodiment of this application.

[0021] Figure 6 This is a schematic diagram of the structure of a low-voltage reset circuit according to another embodiment of this application. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0023] Figure 1 A schematic diagram of a low-voltage reset circuit 10 in related technologies is shown. For example... Figure 1 As shown, the low-voltage reset circuit 10 has a simple circuit structure, requires no comparator or reference voltage, can independently perform low-voltage detection, and has low power consumption. However, its disadvantage is that the low-voltage reset threshold V... LVR Its dispersion is relatively large due to the drift of the production process.

[0024] exist Figure 1 In the low-voltage reset circuit 10 shown, as the power supply voltage VDD starts to rise from 0V to the normal operating voltage, the low-voltage reset circuit 10 will detect the voltage state of the power supply voltage VDD in real time and output the high and low levels of the output voltage LVR_OUT.

[0025] Figure 2 The waveform relationship between the power supply voltage VDD and the output voltage LVR_OUT is revealed. (Refer to reference...) Figure 2 As shown, when the power supply voltage VDD is less than the low voltage reset threshold V LVR When the power supply voltage VDD is greater than the low voltage reset threshold V, the output voltage LVR_OUT will be low; when the power supply voltage VDD is greater than the low voltage reset threshold V, the output voltage LVR_OUT will be low. LVR When the voltage drops from the normal operating voltage VDD to 0V, the output voltage LVR_OUT will switch from high to low.

[0026] exist Figure 1 In this circuit, the first PMOS transistors P1_1 to P1_n and the first NMOS transistor N1 form a path from the power supply voltage VDD to ground GND (representing the signal ground terminal, generally 0V), which is used to generate the first bias current I. BIAS1The gate and drain of the first NMOS transistor N1 are shorted, and the first bias current I BIAS1 is mirrored to the second NMOS transistor N2 to generate the theoretical second bias current I BIAS2 . At this time, the high and low of the output voltage LVR_OUT output level mainly depends on the working current I N2 of the second branch composed of the second PMOS transistor P2 and the second NMOS transistor N2. BIAS2 Compared with the theoretical second bias current I

[0027] For MOS transistors, the relationship between the gate-source voltage V GS and the drain current I D is as follows:

[0028]

[0029] Where μ represents the carrier mobility, C OX represents the gate oxide unit capacitance, V TH represents the gate opening voltage, and these three parameters are related to the production process and device type; L represents the gate length, and W represents the gate width, and these two parameters are related to the size design.

[0030] For the branch composed of the second PMOS transistor P2 and the second NMOS transistor N2 of the Figure 1 circuit, the voltage between the power supply voltage VDD and the ground GND is equal to the sum of the source-gate voltage V SG_P2 of the second PMOS transistor P2 and the gate-source voltage V GS_N2 of the second NMOS transistor N2, that is:

[0031]

[0032] Where μ P2 and μ N2 represent the carrier mobilities of the second PMOS transistor P2 and the second NMOS transistor N2, respectively, C OX_P2 and C OX_N2 represent the gate oxide unit capacitances of the second PMOS transistor P2 and the second NMOS transistor N2, respectively, V TH_p2 and V TH_N2 represent the gate opening voltages of the second PMOS transistor P2 and the second NMOS transistor N2, respectively; L P2 and L N2 represent the gate lengths of the second PMOS transistor P2 and the second NMOS transistor N2, respectively, and W P2 and W N2 represent the gate widths of the second PMOS transistor P2 and the second NMOS transistor N2, respectively.

[0033] As can be seen from the above formula, the operating current I of the branch composed of the second PMOS transistor P2 and the second NMOS transistor N2 is... N2 It has a positive trend relationship with the power supply voltage VDD.

[0034] When the operating current I N2 Equal to the theoretical second bias current I BIAS2 When the output voltage LVR_OUT is flipped, the power supply voltage VDD is at the low voltage reset threshold V. LVR Therefore, we can obtain:

[0035]

[0036] As can be seen from the above formula, the low voltage reset threshold V LVR Not only with the second bias current I BIAS2 and design parameters L / W (specifically, the gate aspect ratio L of the second PMOS transistor P2). P2 / W P2 The gate aspect ratio L of the second NMOS transistor N2 N2 / W N2 Besides being related to the process parameters, it is also related to other process-sensitive parameters, especially the turn-on voltage V. TH Parameters (specifically, the gate turn-on voltage V of the second PMOS transistor P2 and the second NMOS transistor N2) TH_p2 and V TH_N2 ).

[0037] Semiconductor manufacturing processes typically exhibit drift. To verify the impact of process drift on circuit performance, simulation models typically include typical and extreme process conditions, such as five process corners: Typical N Typical P (TT), Fast N Fast P (FF), Slow N Slow P (SS), Fast N Slow P (FS), and Slow N Fast P (SF). The simulations using these five process corner models below provide a basic understanding of the circuit performance range.

[0038] Table 1 below gives Figure 1 The low-voltage reset threshold V of the low-voltage reset circuit 10 shown LVR Simulation values ​​at different process angles.

[0039] Table 1

[0040] PROCESS CORNER TT SS FF SF FS V LVR ]]> 1.60V 2.05V 1.15V 1.80V 1.10V

[0041] As shown in Table 1, the low-voltage reset threshold under the typical process TT is designed as 1.60V first. It can be seen from the simulation values that the deviation of the low-voltage reset threshold under the extreme processes SS / FF from the low-voltage reset threshold under the typical process TT is as high as about ±30%. It can be illustrated from this that Figure 1 the low-voltage reset threshold V LVR of the low-voltage reset circuit 10 shown is greatly affected by the process drift, resulting in great numerical discreteness, and thus the application experience of customers is poor.

[0042] Therefore, the present application proposes an improved low-voltage reset circuit to solve the problem of great discreteness of the low-voltage reset threshold V Figure 1 in the low-voltage reset circuit 10 shown above caused by the process drift. LVR

[0043] Figure 3 The structural schematic diagram of the low-voltage reset circuit 20 of one embodiment of the present application is disclosed. As shown in Figure 3 , the low-voltage reset circuit 20 of one embodiment of the present application comprises a first branch and a second branch.

[0044] The first branch is connected between the power supply voltage VDD and the ground GND, and is used for generating a first bias current I BIAS1 . The first branch comprises a first sub-PMOS tube P1_n', a second sub-PMOS tube P0, a bipolar semiconductor tube and a first NMOS tube N1. The first sub-PMOS tube P1_n' and the second sub-PMOS tube P0 are connected in parallel, the source of the first sub-PMOS tube P1_n' and the source of the second sub-PMOS tube P0 are connected together, the gate of the first sub-PMOS tube P1_n' and the gate of the second sub-PMOS tube P0 are connected together and connected to the ground GND, the drain of the first sub-PMOS tube P1_n' is connected to the ground through the bipolar semiconductor tube, the gate and the drain of the first NMOS tube N1 are short-circuited to the drain of the second sub-PMOS tube P0, and the source of the first NMOS tube N1 is grounded GND.

[0045] In Figure 3 the embodiment shown, the bipolar semiconductor tube can comprise a PNP triode PNP1, the emitter of the PNP triode PNP1 is connected to the drain of the first sub-PMOS tube P1_n', and the base and the collector of the PNP triode PNP1 are short-circuited to the ground GND.

[0046] ​The second branch is connected between the power supply voltage VDD and ground GND, and is used to monitor the power supply voltage VDD and output the output voltage LVR_OUT. The second branch includes a second PMOS transistor P2 and a second NMOS transistor N2. The source of the second PMOS transistor P2 is connected to the power supply voltage VDD, the gate of the second PMOS transistor P2 is connected to the drain of the first sub-PMOS transistor P1_n', the drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, the source of the second NMOS transistor N2 is grounded, and the gate of the second NMOS transistor N2 is connected to the gate of the first NMOS transistor N1.

[0047] In some embodiments, the first branch includes multiple first PMOS transistors P1_1 to P1_n connected in series, wherein the drain and source of two adjacent first PMOS transistors are connected, the gates of the multiple first PMOS transistors P1_1 to P1_n are all grounded, the source of the first first PMOS transistor P1_1 is connected to the power supply voltage VDD, and the last first PMOS transistor P1_n includes a first sub-PMOS transistor P1_n' and a second sub-PMOS transistor P0. The series connection of the multiple first PMOS transistors P1_1 to P1_n can be equivalent to a very large resistor, thereby generating a very low bias current and realizing a low-power design.

[0048] In some embodiments, the first PMOS transistors P1_1 to P1_n can be depth-inverting transistors, where the gate length is greater than the gate width. This allows for a smaller path current when forming the power-to-ground path, reducing circuit power consumption and saving layout area.

[0049] By shorting the gate and drain of the first NMOS transistor N1, the first bias current I can be applied. BIAS1 A portion of the current is mirrored to the second NMOS transistor N2 to generate the second bias current I of the second branch. BIAS2＇ .

[0050] exist Figure 3 In the middle, Figure 1 The last PMOS transistor P1_n in the circuit is decomposed into two parallel sub-PMOS transistors P1_n' and P0. Since the first sub-PMOS transistors P1_n' and P0 are connected in parallel, and their drain voltages are approximately equal, the first bias current I of the first branch can be determined based on the ratio of their gate width-to-length ratio (W / L). BIAS1 The two parts are split into two, one for generating the emitter-junction voltage V of PNP transistor PNP1. EB_PNP1 The theoretical second bias current I of the second branch BIAS2＇ .

[0051] and Figure 1The circuit analysis is similar; the voltage between the power supply voltage VDD and ground GND is equal to the source-gate voltage V of the second PMOS transistor P2. SG_P2 The emitter junction voltage V of PNP transistor PNP1 EB_PNP1 The sum is:

[0052]

[0053] Similarly, when the operating current I of the second branch... N2 Equal to the theoretical second bias current I of the second branch BIAS2＇ When the output voltage LVR_OUT flips, the power supply voltage VDD becomes the low voltage reset threshold V. LVR Therefore, we can obtain:

[0054]

[0055] In the above formula, V EB_PNP1 The forward bias voltage of the semiconductor PN junction of a PNP transistor PNP1 is related to the emitter current I. E The relation is shown below:

[0056]

[0057] Among them, I S Let represent the dark saturation current, q represent the electron charge, k represent the Boltzmann constant (1.38064852E-23 joules / Kelvin), T represent the absolute temperature (Kelvin), and I represent the electron charge. S It is only related to the bandgap of the semiconductor material and the temperature.

[0058] Therefore, the emitter junction voltage V of PNP transistor PNP1 can be seen. EB_PNP1 Mainly related to emitter current I E It is related, and it follows a natural logarithmic relationship, but it is independent of the manufacturing process. In other words, the emitter junction voltage V... EB_PNP1 Almost unaffected by emitter current I E The voltage is relatively stable due to changes in the production process.

[0059] Therefore, the low-voltage reset threshold V in the low-voltage reset circuit 20 of this application LVR Compared to Figure 1 The low-voltage reset circuit 10 shown eliminates the gate-source voltage V of the second NMOS transistor N2. GS_N2 The resulting process drift effect.

[0060] Table 2 below gives Figure 3 The low-voltage reset threshold V of the low-voltage reset circuit 20 shown LVR Simulation values ​​at different process angles.

[0061] Table 2

[0062] PROCESS CORNER TT SS FF SF FS V LVR ]]> 1.60V 1.74V 1.47V 1.51V 1.69V

[0063] As shown in Table 2, the low-voltage reset threshold under the typical process TT is also designed as 1.60V here. From the simulation values, it can be seen that the low-voltage reset threshold V LVR under the extreme processes SS and FF is controlled within 10% of the change of the low-voltage reset threshold V LVR under the typical process TT, and the low-voltage reset threshold V Figure 1 under the extreme processes SS and FF is controlled within 20% of the low-voltage reset threshold V LVR under the typical process TT. The discreteness of the low-voltage reset threshold V LVR with process drift is reduced by nearly 70%.

[0064] The low-voltage reset circuit 20 of the present application is based on the low-voltage reset circuit 10 shown in Figure 1 by adding a PNP transistor PNP1, which can greatly improve the problem of large discreteness of the low-voltage reset threshold V LVR caused by process drift, while maintaining the simplicity, independence and very low power consumption of the original Figure 1 circuit.

[0065] Continuing to refer to Figure 3 , in some embodiments, the low-voltage reset circuit 20 of the present application can also include a third branch. The third branch is connected between the power supply voltage VDD and the ground GND, and is used to shape the output voltage LVR_OUT.

[0066] Figure 4 The waveform diagrams of the output voltage LVR_OUT of the low-voltage reset circuit 20 of an embodiment of the present application before and after shaping are disclosed. As shown in Figure 4 , waveform C1 refers to the waveform diagram of the output voltage LVR_OUT without shaping by the third branch, and waveform C2 refers to the waveform diagram of the output voltage LVR_OUT after shaping by the third branch. From the comparison of waveforms C1 and C2, it can be seen that before shaping by the third branch, the output voltage LVR_OUT signal is relatively flat, while after shaping by the third branch, the slope of the output voltage LVR_OUT signal changing from low to high or from high to low becomes steeper. The shaped output voltage LVR_OUT signal is more obvious, which is more conducive to subsequent signal processing.

[0067] In some embodiments, the third branch includes a third PMOS transistor P3, a third NMOS transistor N3, a fourth PMOS transistor P4, and a fourth NMOS transistor N4. The gate of the third PMOS transistor P3 and the gate of the third NMOS transistor N3 are connected to the drain of the second PMOS transistor P2, the drain of the third PMOS transistor P3 and the drain of the third NMOS transistor N3 are connected, the source of the third PMOS transistor P3 is connected to the power supply voltage VDD, and the source of the third NMOS transistor N3 is connected to the ground GND. The gate of the fourth PMOS transistor P4 and the gate of the fourth NMOS transistor N4 are connected to the drain of the third PMOS transistor P3, the drain of the fourth PMOS transistor P4 and the drain of the fourth NMOS transistor N4 are connected and connected to an output terminal for outputting an output voltage LVR_OUT, the source of the fourth PMOS transistor P4 is connected to the power supply voltage VDD, and the source of the fourth NMOS transistor N4 is connected to the ground GND.

[0068] Optionally, the first branch, the second branch, and the third branch are all connected to the power supply voltage VDD through a first resistor R1 and are also connected to the ground GND through a first capacitor C1. The first resistor R1 and the first capacitor C1 constitute a low-pass filter circuit, so that high-frequency interference signals in the power supply voltage VDD can be filtered out.

[0069] Figure 5 A structural schematic diagram of a low-voltage reset circuit 30 of another embodiment of the present application is disclosed. As shown in Figure 5 The bipolar semiconductor transistor of the present application can include an NPN transistor NPN1. The base and the collector of the NPN transistor NPN1 are shorted to the drain of the first sub-PMOS transistor P1_n' and the gate of the second PMOS transistor P2, and the emitter of the NPN transistor NPN1 is connected to the ground GND.

[0070] Figure 5 The low-voltage reset circuit 30 shown also utilizes the stability of the emitter junction voltage of the NPN transistor NPN1, and can also achieve similar beneficial technical effects as the low-voltage reset circuit 20 shown in Figure 3

[0071] Figure 6 A structural schematic diagram of a low-voltage reset circuit 40 of yet another embodiment of the present application is disclosed. As shown in Figure 6 The bipolar semiconductor transistor of the present application can include a diode D1. The anode of the diode D1 is connected to the drain of the first sub-PMOS transistor P1_n' and the gate of the second PMOS transistor P2, and the cathode of the diode D1 is connected to the ground GND.

[0072] Figure 6 The low-voltage reset circuit 40 shown similarly utilizes the stability of the forward conduction voltage of the diode D1, and can also achieve similar beneficial technical effects as the low-voltage reset circuit 20 shown in Figure 3 ​The low-voltage reset circuit 20 shown has similar beneficial technical effects.

[0073] In the present application Figures 3 to 6 The low-voltage reset circuits 20, 30, 40 shown mainly utilize the stability of the PN junction voltage of bipolar semiconductor tubes (specifically, the emitter junction voltage of semiconductor triodes and the forward conduction voltage of the PN junction of diodes) that is almost not discrete with process drift. In actual design processes, the three types of bipolar semiconductor tubes can be optimally selected in combination with layout levels, occupied areas, and simulation results.

[0074] The low-voltage reset circuits 20, 30, 40 of the present application are based on Figure 1 by adding a bipolar semiconductor tube (for example, a PNP tube, or an NPN tube, or a diode), the low-voltage reset threshold V LVR is greatly improved with respect to the discrete problem with process drift, while maintaining the simple structure of the original circuit, the small layout area, the independence of the circuit operation, and the very low power consumption, and can give customers a good overall experience.

[0075] The present application also provides an electronic chip. The electronic chip includes the low-voltage reset circuit 20, 30, 40 as described above.

[0076] The electronic chip has similar beneficial technical effects to the low-voltage reset circuit 20, 30, 40 described above, and thus will not be described again here.

[0077] The low-voltage reset circuit and the electronic chip provided by the embodiments of the present application are described in detail above. The low-voltage reset circuit and the electronic chip provided by the embodiments of the present application are described in this document by applying specific examples, and the above description of the embodiments is only used to help understand the core idea of the present application, and is not used to limit the present application. It should be noted that, for those skilled in the art, without departing from the spirit and principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications should also fall within the protection scope of the appended claims of the present application.

Claims

1. A low-voltage reset circuit, characterized in that, include: The first branch, connected between the power supply voltage and ground, is used to generate a first bias current. The first branch includes a first sub-PMOS transistor, a second sub-PMOS transistor, a bipolar transistor, and a first NMOS transistor. The first sub-PMOS transistor and the second sub-PMOS transistor are connected in parallel. The source of the first sub-PMOS transistor and the source of the second sub-PMOS transistor are connected together. The gate of the first sub-PMOS transistor and the gate of the second sub-PMOS transistor are connected together and connected to ground. The drain of the first sub-PMOS transistor is connected to ground through the bipolar transistor. The gate and drain of the first NMOS transistor are shorted to the drain of the second sub-PMOS transistor. The source of the first NMOS transistor is grounded. The second branch is connected between the power supply voltage and ground, and is used to monitor the power supply voltage and output the output voltage. The second branch includes a second PMOS transistor and a second NMOS transistor. The source of the second PMOS transistor is connected to the power supply voltage, the gate of the second PMOS transistor is connected to the drain of the first sub-PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor.

2. The low-voltage reset circuit as described in claim 1, characterized in that, The bipolar semiconductor transistor includes a PNP transistor, the emitter of which is connected to the drain of the first sub-PMOS transistor, and the base and collector of which are shorted to ground.

3. The low-voltage reset circuit as described in claim 1, characterized in that, The bipolar semiconductor transistor includes an NPN transistor, the base and collector of which are shorted to the drain of the first sub-PMOS transistor, and the emitter of which is connected to ground.

4. The low-voltage reset circuit as described in claim 1, characterized in that, The bipolar semiconductor transistor includes a diode, the anode of which is connected to the drain of the first sub-PMOS transistor, and the cathode of which is connected to ground.

5. The low-voltage reset circuit as described in claim 1, characterized in that, Also includes: The third branch is connected between the power supply voltage and ground, and is used to shape the output voltage.

6. The low-voltage reset circuit as described in claim 5, characterized in that, The first branch, the second branch, and the third branch are all connected to the power supply voltage through a first resistor and also connected to ground through a first capacitor.

7. The low-voltage reset circuit as described in claim 5, characterized in that, The third branch includes a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor, and a fourth NMOS transistor. The gates of the third PMOS transistor and the third NMOS transistor are connected to the drain of the second PMOS transistor. The drains of the third PMOS transistor and the third NMOS transistor are connected together. The source of the third PMOS transistor is connected to the power supply voltage, and the source of the third NMOS transistor is grounded. The gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to the drain of the third PMOS transistor. The drains of the fourth PMOS transistor and the fourth NMOS transistor are connected and connected to the output terminal for outputting the output voltage. The source of the fourth PMOS transistor is connected to the power supply voltage, and the source of the fourth NMOS transistor is grounded.

8. The low-voltage reset circuit as described in any one of claims 1 to 7, characterized in that, The first branch includes a plurality of first PMOS transistors connected in series, wherein the drain and source of two adjacent first PMOS transistors are connected, the gates of the plurality of first PMOS transistors are all grounded, the source of the first first PMOS transistor is connected to the power supply voltage, and the last first PMOS transistor includes a first sub-PMOS transistor and a second sub-PMOS transistor.

9. The low-voltage reset circuit as described in claim 8, characterized in that, The first PMOS transistor is an inverted ratio transistor, and the gate length of the inverted ratio transistor is greater than the gate width.

10. An electronic chip, characterized in that, Includes the low-voltage reset circuit as described in any one of claims 1 to 9.

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