Wide-voltage PMOS (P-channel Metal Oxide Semiconductor) driving circuit and method

Abstract

The invention discloses a wide-voltage PMOS driving circuit and method, and the circuit comprises a power tube MP, and also comprises a high-voltage DC source which is connected with the source electrode of the power tube MP and is used for providing a high-voltage DC voltage; the level shifting module is connected with the high-voltage direct current source and is used for generating a reference ground voltage VSS2 of a high-voltage domain; the control module is used for receiving and processing an external control signal Drv0 to generate a first driving signal, a second driving signal and a third driving signal; the driving module comprises a first auxiliary pull-down unit, a second auxiliary pull-down unit and an auxiliary pull-up unit, and the first auxiliary pull-down unit and the second auxiliary pull-down unit are both connected with the control module and the grid electrode of the power tube MP and used for controlling conduction of the power tube MP according to the first driving signal and the second driving signal; and the auxiliary pull-up unit is connected with the control module and the grid electrode of the power tube MP, and is used for controlling the turn-off of the power tube MP according to the third driving signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit design, in particular to a wide voltage PMOS driving circuit and method. BACKGROUND

[0002] In a power system such as a wide voltage input DC-DC converter, a high-side PMOS power tube is often used for switching control. However, since the source of the PMOS power tube is in the high voltage domain, while the traditional control signal usually works in the low voltage domain, it cannot directly drive the high-side PMOS power tube, so the control signal needs to be lifted to the high voltage domain. However, due to the level isolation between high and low voltage domains and different reference grounds, the gate drive level of the high-side is difficult to accurately control, that is, the gate-source voltage Vgs of the PMOS power tube is difficult to stably control, which affects the reliable turn-on and turn-off of the device and limits the efficiency and stability of the system. SUMMARY

[0003] The purpose of the present application is to provide a wide voltage PMOS driving circuit and method to accurately control the gate voltage of the high-side PMOS power tube, stabilize the gate-source voltage Vgs of the PMOS power tube, and improve the turn-on reliability of the device and the overall efficiency and stability of the system.

[0004] To achieve the above purpose, the present application discloses the following technical scheme: The first aspect of the present application provides a wide voltage PMOS driving circuit, including a power tube MP, the circuit further comprising: a high voltage DC source connected to the source of the power tube MP for providing a high voltage DC voltage; a level shift module connected to the high voltage DC source for generating a reference ground voltage VSS2 in the high voltage domain; a control module for receiving and processing an external control signal Drv0 to generate a first drive signal, a second drive signal and a third drive signal; a driving module including a first auxiliary pull-down unit, a second auxiliary pull-down unit and an auxiliary pull-up unit, the first auxiliary pull-down unit and the second auxiliary pull-down unit are both connected to the control module and the gate of the power tube MP, for controlling the turn-on and turn-off of the power tube MP according to the first drive signal and the second drive signal; the auxiliary pull-up unit is connected to the control module and the gate of the power tube MP, for controlling the turn-off of the power tube MP according to the third drive signal.

[0005] Optionally, when the external control signal Drv0 is high, the control module generates the first drive signal, so that the first auxiliary pull-down unit is turned on and the gate voltage of the power tube MP is pulled low; When the gate voltage of the power tube MP decreases by a preset voltage value, the control module generates the second driving signal, the second auxiliary pull-down unit is turned on, the first auxiliary pull-down unit is turned off, so that the gate voltage of the power tube MP further decreases to the reference ground voltage VSS2, thereby ensuring that the power tube MP is in a fully on state, and reducing the on resistance; When the external control signal Drv0 is low, the control module generates the third driving signal, so that the auxiliary pull-up unit is turned on, thereby turning off the power tube MP.

[0006] Optionally, the high-voltage direct-current source includes a first capacitor C1, a first end of the first capacitor C1 being connected to a direct-current voltage VCC, and a second end of the first capacitor C1 being grounded.

[0007] Optionally, the control module includes a signal conversion unit, and the signal conversion unit includes: a first LS circuit, an input end of the first LS circuit receiving the external control signal Drv0, and an output end of the first LS circuit outputting a third driving signal, the first LS circuit being used to convert a low-voltage domain signal into a high-voltage domain signal, and the signal logic state being unchanged; a second LS circuit, the second LS circuit being used to convert a high-voltage domain signal into a low-voltage domain signal, and the signal logic state being unchanged.

[0008] Optionally, the control module further includes a logic unit, and the logic unit includes a first AND gate AND1, a second AND gate AND2, a first NOT gate NOT1, a second NOT gate NOT2, and a Schmitt circuit. An input end of the Schmitt circuit is connected to a gate of the power tube MP, and an output end of the Schmitt circuit is connected to an input end of the second NOT gate NOT2; An output end of the second NOT gate NOT2 is connected to an input end of the second LS circuit, and the output end of the second NOT gate NOT2 is further connected to an input end of the first NOT gate NOT1; An output end of the first NOT gate NOT1 is connected to a first input end of the first AND gate AND1; A second input end of the first AND gate AND1 is connected to an output end of the first LS circuit, and an output end of the first AND gate AND1 is connected to the second auxiliary pull-down unit; A first input end of the second AND gate AND2 is connected to an output end of the second LS circuit, a second input end of the second AND gate AND2 is connected to the external control signal Drv0, and an output end of the second AND gate AND2 is connected to the first auxiliary pull-down unit.

[0009] Optionally, the driving module further includes: The auxiliary pull-up unit comprises a first PMOS tube MP1, the source of the first PMOS tube MP1 is connected to the high-voltage direct-current source, the gate is connected to the output of the first LS circuit, and the drain is connected to the gate of the power tube MP; the first PMOS tube MP1 is turned on when receiving the third driving signal, so that the power tube MP is disconnected.

[0010] Optionally, the first auxiliary pull-down unit comprises a first NMOS tube MN1, the gate of the first NMOS tube MN1 is connected to the output of the second AND gate AND2, the drain of the first NMOS tube MN1 is connected to the gate of the power tube MP, and the source is grounded. The second auxiliary pull-down unit comprises a second NMOS tube MN2, the gate of the second NMOS tube MN2 is connected to the output of the first AND gate AND1, the drain of the second NMOS tube MN2 is connected to the gate of the power tube MP, and the source is connected to the level shift module.

[0011] Optionally, the level shift module further comprises a second capacitor C2, a constant current source I, a second PMOS tube MP2 and a third PMOS tube MP3 which are current mirrors, a third NMOS tube MN3 and a fourth NMOS tube MN4 which are current mirrors, a first resistor R1 and a voltage stabilizing tube Z1. In the level shift module, the direct-current voltage VCC is connected to the first resistor R1, the second PMOS tube MP2 and the fourth NMOS tube MN4 to the ground in sequence; the direct-current voltage VCC is also connected to the voltage stabilizing tube Z1 and the third PMOS tube MP3 to the ground in sequence; the first end of the second capacitor C2 is connected to the direct-current voltage VCC, and the second end is connected to the reference ground voltage VSS2 and the source of the second NMOS tube MN2. The gate of the second PMOS tube MP2 is connected to the gate of the third PMOS tube MP3 and the drain of the second PMOS tube MP2; the gate of the third NMOS tube MN3 is connected to the gate of the fourth NMOS tube MN4 and the drain of the third NMOS tube MN3; the drain of the third NMOS tube MN3 is also connected to the constant current source I.

[0012] Optionally, the voltage stabilizing value of the voltage stabilizing tube Z1 is greater than the turn-on threshold voltage of the power tube MP and less than the breakdown voltage of the power tube MP. The preset voltage value is the input voltage variation amount of the Schmitt circuit output converted from low level to high level.

[0013] Optionally, the first capacitor C1 is an external capacitor, the second capacitor C2 is an internal integrated capacitor, and the capacitance of the first capacitor C1 is greater than the capacitance of the second capacitor C2.

[0014] The second aspect of the application provides a wide-voltage PMOS driving method for the wide-voltage PMOS driving circuit. The control module receives an external control signal Drv0; When the external control signal Drv0 is high, the control module generates a first driving signal to turn on the first auxiliary pull-down unit and pull down the gate voltage of the power transistor MP; When the gate voltage of the power transistor MP decreases by a preset voltage value, the control module generates a second driving signal to turn on the second auxiliary pull-down unit and turn off the first auxiliary pull-down unit, so that the gate voltage of the power transistor MP further decreases to a reference ground voltage VSS2, thereby ensuring that the power transistor MP is in a fully on state and reducing the on resistance; When the external control signal Drv0 is low, the control module generates a third driving signal to turn on the auxiliary pull-up unit, so that the power transistor MP is turned off.

[0015] The effects provided in the summary are only the effects of the embodiments, not all the effects of the application. One of the above technical solutions has the following advantages or beneficial effects: The wide-voltage PMOS driving circuit provided by the embodiments of the application adopts a two-stage auxiliary pull-down structure, and realizes phased pull-down of the gate voltage of the power transistor MP through cascade control of the first auxiliary pull-down unit and the second auxiliary pull-down unit. The first auxiliary pull-down unit is turned on by the first driving signal to realize rapid decrease of the gate voltage of the power transistor MP by a preset voltage value, and then the second auxiliary pull-down unit is turned on by the second driving signal to complete accurate pull-down to a target voltage, thereby ensuring that the gate-source voltage Vgs of the power transistor MP reaches the amplitude required for sufficient conduction, effectively reducing the on resistance, reducing system power consumption, and improving the conduction performance of the power transistor and the energy efficiency of the power supply system.

[0016] Further, on the basis of improving the conduction capability of the power tube MP, the application further enhances the driving stability and system integration of the overall circuit. The control module adopts the design of combining the level shift circuit with the logic control unit, not only realizes the reliable conversion of the low-voltage control signal to the high-voltage domain, but also ensures the timing accuracy and response consistency of the driving signal through the collaborative control of Schmidt circuit, logic gate and the like, effectively avoiding the problems of false turn-on or false turn-off. The level shift module generates a stable high-voltage domain reference ground voltage VSS2 by introducing constant current source, current mirror and voltage stabilizing tube and the like structure, and realizes the phased accurate control of the gate voltage by combining the synergistic effect of the external large capacitor and the built-in small capacitor, which effectively controls the chip area and cost while taking into account the conduction performance. The overall circuit scheme of the application has strong driving capability, high control accuracy and low power consumption, and is particularly suitable for power control application scenarios such as wide input voltage range and high-side PMOS tube driving. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

[0018] Figure 1 A preliminary iterative topology structure diagram of a wide-voltage PMOS driving circuit according to an embodiment of the application is shown; Figure 2 A structural block diagram of a wide-voltage PMOS driving circuit according to an embodiment of the application is shown; Figure 3 A topology diagram of a wide-voltage PMOS driving circuit according to an embodiment of the application is shown; Figure 4 A flowchart of a wide-voltage PMOS driving method according to an embodiment of the application is shown. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical scheme and advantages of the application clearer, the application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and do not limit the application.

[0020] It is to be understood that the references used herein to "one embodiment", "an embodiment", "example embodiment", etc. do not necessarily all refer to the same embodiment, although they can. Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of other embodiments.

[0021] In addition, a technical term or a scientific term used in the specification and the following claims is used to refer to a specific component or part, and those skilled in the art can understand that a manufacturer can use different names or terms to refer to the same component or part. The specification and the following claims do not distinguish components or parts by name difference, but by functional difference. Throughout the specification and the following claims, "including" and "containing" are open terms, and should be interpreted as "including but not limited to". In addition, the term "connected" herein includes any direct and indirect electrical connection means. Indirect electrical connection means includes connection through other devices.

[0022] To solve the problems in the prior art, the inventors first designed a preliminary iterative topology of a wide-voltage PMOS driving circuit as shown in Figure 1 As shown in Figure 1 The preliminary iterative wide-voltage PMOS driving circuit includes a third LS circuit, the input end of which is connected to an external control signal Drv0, and the output end of which is connected to the gate of the first PMOS transistor MP1 and the gate of the second NMOS transistor MN2, respectively, for controlling the conduction and turn-off of the first PMOS transistor MP1 and the second NMOS transistor MN2.

[0023] Figure 1 The circuit shown in the figure can preliminarily solve the problem that the driving level of the gate of the conventional high-side PMOS transistor is difficult to accurately control. The circuit converts the external control signal Drv0 in the low-voltage domain to the high-voltage domain through the third LS circuit, thereby achieving effective driving control of the high-side PMOS power transistor MP. The external control signal Drv0 is converted by the third LS circuit, which can control the conduction state of the first PMOS transistor MP1 and the switching behavior of the second NMOS transistor MN2, thereby achieving dynamic adjustment of the gate voltage of the power transistor MP. In the above manner, Figure 1 The circuit accurately maps the low-voltage control signal to the high-voltage domain under wide-voltage input conditions, so that the high-side PMOS transistor can obtain a suitable gate-source voltage difference Vgs in different input voltage ranges, thereby achieving basic conduction and turn-off control and improving the adaptability and control flexibility of the system.

[0024] However, the inventors found in the research process that when the external control signal DRV0 is high, the third LS circuit outputs a high level, the first PMOS transistor MP1 is cut off, and the gate voltage of the power transistor MP is pulled down to the reference ground voltage VSS2 of the high-voltage domain by the second NMOS transistor MN2 at the moment when the second NMOS transistor MN2 is turned on. The second capacitor C2 and the parasitic gate-source capacitor Cgs form a discharge loop with the second NMOS transistor MN2. In this process, the parasitic gate-source capacitor Cgs will extract charges from the second capacitor C2, causing the voltage of the second capacitor C2 to drop rapidly. Since the second capacitor C2 is an internal integrated capacitor of the chip, its capacity is limited (about 10 pF, for example), and the rapid voltage drop of the second capacitor C2 is more obvious during the discharging process, which causes the reference ground voltage VSS2 of the high-voltage domain to rise, the gate voltage of the PMOS power transistor MP to fluctuate, and the power transistor MP to fail to reach the maximum conduction state, thereby increasing the on-resistance, increasing the system power consumption, and affecting the conversion efficiency and circuit performance. If the voltage fluctuation problem is alleviated by increasing the capacity of the second capacitor C2, more chip area will be sacrificed, resulting in increased cost, which is not conducive to integration and popularization.

[0025] Therefore, the inventors further optimize the above preliminary scheme, and on the basis of comprehensive consideration of chip area, cost, and electrical performance, the final technical scheme of the present application is proposed, which effectively stabilizes the gate voltage of the PMOS power transistor during conduction without significantly increasing the chip area, so that Vgs=VCC-VSS2, the amplitude of Vgs is stabilized, the on-resistance is reduced, the system power consumption is reduced, and the conduction capability, the overall working efficiency and stability of the system are improved.

[0026] Figure 2 A structural block diagram of a wide-voltage PMOS driving circuit according to an embodiment of the present application is shown. As shown in FIG. 1, the wide-voltage PMOS driving circuit comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first voltage source VCC, a second voltage source VSS1, a third voltage source VSS2, a fourth voltage source VSS3, a first control signal DRV0, a second control signal DRV1, a third control signal DRV2, and a fourth control signal DRV3. Figure 2As shown, the wide-voltage PMOS driving circuit includes a power tube MP, a high-voltage direct current source 100, a level shift module 200, a control module 300, and a driving module 400. The high-voltage direct current source 100 is connected to the source of the power tube MP and is configured to provide a high-voltage direct current voltage. The level shift module 200 is connected to the high-voltage direct current source 100 and is configured to generate a reference ground voltage VSS2 in a high-voltage domain. The control module 300 is configured to receive and process an external control signal Drv0 and generate a first driving signal, a second driving signal, and a third driving signal. The driving module 400 includes a first auxiliary pull-down unit 410, a second auxiliary pull-down unit 420, and an auxiliary pull-up unit 430. The first auxiliary pull-down unit 410 and the second auxiliary pull-down unit 420 are both connected to the control module 300 and the gate of the power tube MP and are configured to control the stable conduction of the power tube MP according to the first driving signal and the second driving signal. The auxiliary pull-up unit 430 is connected to the control module 300 and the gate of the power tube MP and is configured to control the turn-off of the power tube MP according to the third driving signal.

[0027] Figure 3 A wide-voltage PMOS driving circuit topology according to an embodiment of the present application is shown. As shown in FIG. 1, the wide-voltage PMOS driving circuit includes a power tube MP, a high-voltage direct current source 100, a level shift module 200, a control module 300, and a driving module 400. Figure 3 As shown, the high-voltage direct current source 100 of the wide-voltage PMOS driving circuit includes a first capacitor C1, a first end of the first capacitor C1 is connected to a direct current voltage VCC, and a second end of the first capacitor C1 is grounded VSS1, i.e., a reference ground voltage VSS1 in a low-voltage domain. The level shift module 200 includes a second capacitor C2, a first end of the second capacitor C2 is connected to the direct current voltage VCC, and a second end of the second capacitor C2 is connected to a reference ground voltage VSS2, i.e., a reference ground voltage VSS2 in a high-voltage domain. In an embodiment, the high-voltage direct current source 100 is composed of a front-stage circuit and the first capacitor C1, wherein the front-stage circuit is not shown in the figure and only needs to be a circuit capable of outputting a high-voltage direct current voltage VCC, the voltage range of the VCC can be selected as 6V to 40V, which is used to meet the driving requirements in different application scenarios. Figure 3

[0028] ​Specifically, when the external control signal Drv0 is high, the control module 300 generates a first driving signal, and the first auxiliary pull-down unit 410 is turned on when receiving the first driving signal, so that the parasitic gate-source capacitance Cgs of the power tube MP forms a loop with the first capacitor C1, and the gate voltage of the power tube MP is pulled down. When the gate voltage of the power tube MP drops by a preset voltage value, the control module 300 generates a second driving signal, and the second auxiliary pull-down unit 420 is turned on when receiving the second driving signal, so that the parasitic gate-source capacitance Cgs of the power tube MP forms a loop with the second capacitor C2, and the gate voltage of the power tube MP is continuously pulled down. When the gate voltage of the power tube MP further drops to the reference ground voltage VSS2, the voltage of the second capacitor C2 is small, and the VSS2 voltage will not rise, so as to ensure that the gate-source voltage Vgs of the power tube MP can reach the maximum, Vgs=VCC-VSS2, so as to realize the full conduction of the power tube MP and effectively reduce the on-resistance. When the external control signal Drv0 turns to low, the control module 300 generates a third driving signal, and the auxiliary pull-up unit 430 is turned on when receiving the third driving signal, so that the gate-source voltage of the power tube MP is less than the turn-on voltage Vth, and the power tube MP is turned off.

[0029] According to the wide-voltage PMOS driving circuit, the gate-source voltage of the power tube MP is controlled in stages, which can quickly and effectively realize stable conduction and low on-resistance. Specifically, the first auxiliary pull-down unit 410 and the second auxiliary pull-down unit 420 in the driving module 400 respond to different driving signals and sequentially make the gate voltage of the power tube MP drop in stages. First, under the action of the first driving signal, the first auxiliary pull-down unit 410 is turned on, so that the gate voltage of the power tube MP drops by a preset voltage value, and the voltage is greatly reduced. Then, under the action of the second driving signal, the second auxiliary pull-down unit 420 is turned on, so that the gate voltage of the power tube MP further drops to the reference ground voltage VSS2, and the Vgs of the power tube MP reaches the maximum amplitude Vgs=VCC-VSS2, and the on-resistance of the power tube MP is reduced. The control strategy of the present application not only ensures the reliable conduction of the power tube MP, but also effectively reduces the on-resistance of the power tube MP by reasonably controlling the change of the gate voltage in the conduction process, reduces the power consumption, and improves the conduction performance of the power tube and the energy efficiency of the power supply system.

[0030] In one embodiment, the first capacitor C1 is an external capacitor used as an energy storage capacitor for the VCC voltage. It is typically externally mounted on the system board to stabilize the high-voltage DC voltage VCC. The first capacitor C1 has a relatively large capacitance, such as 100μF, to improve the system's power supply stability. The second capacitor C2 is an integrated capacitor within the chip. Due to limitations in chip manufacturing cost and area, its capacitance is typically small, generally designed to be 10pF. This small-capacity second capacitor C2 helps limit the reference ground voltage VSS2 in the high-voltage domain from rising drastically during the power transistor's conduction process. This ensures that the voltage difference between VCC and VSS2 remains stable at the Zener diode Z1's regulated voltage, thereby ensuring that the gate-source voltage of the power transistor MP reaches its maximum and reducing the on-resistance of the power transistor MP.

[0031] In one embodiment, reference Figure 3 The control module 300 of the wide-voltage PMOS drive circuit includes a signal conversion unit 310, which includes a first LS circuit and a second LS circuit. The input of the first LS circuit receives an external control signal Drv0, and the output outputs a third drive signal, used to convert the low-voltage domain signal into a high-voltage domain signal, while maintaining the signal logic state. The second LS circuit is used to convert the high-voltage domain signal into a low-voltage domain signal, while maintaining the signal logic state.

[0032] The first and second LS circuits can be implemented using existing level shifter circuits, and the relevant designs are existing technology, so they will not be described in detail here. The external control signal Drv0 is used to control the turn-on and turn-off of the PMOS power devices, and its reference voltage is the reference ground voltage VSS1 in the low voltage domain.

[0033] In one embodiment, reference Figure 3, the control module 300 further comprises a logic unit 320, the logic unit 320 comprising a first AND gate AND1, a second AND gate AND2, a first NOT gate NOT1, a second NOT gate NOT2 and a Schmitt circuit. The drive module 400 further comprises a first auxiliary pull-down unit 410, a second auxiliary pull-down unit 420 and an auxiliary pull-up unit 430. An input terminal of the Schmitt circuit is connected to a gate of the power transistor MP, and an output terminal of the Schmitt circuit is connected to an input terminal of the second NOT gate NOT2. An output terminal of the second NOT gate NOT2 is connected to an input terminal of the second LS circuit, and the output terminal of the second NOT gate NOT2 is also connected to an input terminal of the first NOT gate NOT1. An output terminal of the first NOT gate NOT1 is connected to a first input terminal of the first AND gate AND1. A second input terminal of the first AND gate AND1 is connected to an output terminal of the first LS circuit, and an output terminal of the first AND gate AND1 is connected to the second auxiliary pull-down unit 420. A first input terminal of the second AND gate AND2 is connected to an output terminal of the second LS circuit, a second input terminal of the second AND gate AND2 is connected to an external control signal Drv0, and an output terminal of the second AND gate AND2 is connected to the first auxiliary pull-down unit 410.

[0034] wherein the first AND gate AND1, the first NOT gate NOT1, the second NOT gate NOT2 and the Schmitt circuit all work in a high-voltage domain, and the input and output voltages thereof are all logic levels of the high-voltage domain. The Schmitt circuit belongs to the prior art, and will not be described here.

[0035] In one embodiment, with reference to Figure 3 , the auxiliary pull-up unit 430 comprises a first PMOS transistor MP1, a source of the first PMOS transistor MP1 being connected to a high-voltage direct-current source 100, a gate of the first PMOS transistor MP1 being connected to an output terminal of the first LS circuit, and a drain of the first PMOS transistor MP1 being connected to a gate of the power transistor MP. The first PMOS transistor MP1 is turned on when receiving a third drive signal, so as to turn off the power transistor MP.

[0036] In one embodiment, with reference to Figure 3 , the first auxiliary pull-down unit 410 comprises a first NMOS transistor MN1, a gate of the first NMOS transistor MN1 being connected to an output terminal of the second AND gate AND2, a drain of the first NMOS transistor MN1 being connected to the gate of the power transistor MP, and a source of the first NMOS transistor MN1 being grounded VSS1. The second auxiliary pull-down unit 420 comprises a second NMOS transistor MN2, a gate of the second NMOS transistor MN2 being connected to an output terminal of the first AND gate AND1, a drain of the second NMOS transistor MN2 being connected to the gate of the power transistor MP, and a source of the second NMOS transistor MN2 being connected to a reference ground voltage VSS2 of the level shift module 200.

[0037] In one embodiment, with reference to Figure 3The level shift module 200 further comprises a constant current source I, a second PMOS transistor MP2 and a third PMOS transistor MP3 which are current mirrors, a third NMOS transistor MN3 and a fourth NMOS transistor MN4 which are current mirrors, a first resistor R1 and a Zener diode Z1. In the level shift module 200, a direct current voltage VCC is connected to the first resistor R1, the second PMOS transistor MP2 and the fourth NMOS transistor MN4 to ground in sequence, and the direct current voltage VCC is further connected to the Zener diode Z1 and the third PMOS transistor MP3 to ground. The gate of the second PMOS transistor MP2 is connected to the gate of the third PMOS transistor MP3 and the drain of the second PMOS transistor MP2. The gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4 and the drain of the third NMOS transistor MN3, and the drain of the third NMOS transistor MN3 is further connected to the constant current source I.

[0038] In an embodiment, the Zener voltage of the Zener diode Z1 is greater than the threshold voltage Vth of the power transistor MP and less than the breakdown voltage BVGS of the power transistor MP. In this embodiment, the Zener voltage of the Zener diode Z1 can be designed to be about 5V to meet the requirement.

[0039] In an embodiment, the preset voltage value is the input voltage variation of the Schmidt circuit output from low level to high level, and the optional preset voltage value can be set to be between 70% and 90% of VCC-VSS2.

[0040] According to the above embodiment, the working principle of the wide-voltage PMOS driving circuit is as follows: when the external control signal DRV0 is low, the first LS circuit outputs low level, i.e., the third driving signal is generated, the first PMOS transistor MP1 is turned on, the first AND gate outputs low level, and the second NMOS transistor MN2 is cut off. At this time, the Schmidt circuit detects that the gate voltage of the power transistor MP is high, and the Schmidt output is low, which is converted to high level by the second NOT gate NOT2 and then outputted by the second LS circuit. Since the external control signal DRV0 is low, the second AND gate AND2 outputs low level, and the first NMOS transistor MN1 is in the off state. At this time, the first PMOS transistor MP1 is turned on, so that the gate-source voltage Vgs of the power transistor MP is 0V, and the power transistor MP is in the off state.

[0041] When the external control signal DRV0 is high, the first LS circuit outputs a high level, making the first PMOS transistor MP1 off. At this time, the Schmitt trigger output is still low, the second NOT gate NOT2 outputs a high level, the first NOT gate NOT1 outputs a low level, and the first AND gate AND1 outputs a low level, so the second NMOS transistor MN2 remains in the off state. At the same time, the second LS circuit outputs a high level, and since DRV0 is high, the second AND gate AND2 outputs a high level, i.e., the first drive signal is generated, so that the first NMOS transistor MN1 is turned on. At this time, the first NMOS transistor MN1 pulls down the gate voltage of the power transistor MP to the ground voltage VSS1, so that the first capacitor C1, the parasitic gate-source capacitor Cgs, and the first NMOS transistor MN1 form a loop, and the parasitic gate-source capacitor Cgs extracts charges from the first capacitor C1. Since the first capacitor C1 is a large-capacity capacitor externally connected on the system board, its voltage is stable and will not fluctuate significantly due to changes in charge. As the gate voltage of the power transistor MP decreases, when it decreases by a preset voltage value, which is 4V in the present embodiment, the output of the Schmitt trigger changes from low to high, and then the second NOT gate NOT2 outputs a low level, and the second LS circuit outputs a low level, causing the second AND gate AND2 to output a low level, and the first NMOS transistor MN1 is turned off.

[0042] At the same time, the first NOT gate NOT1 outputs a high level, and at this time the first AND gate AND1 has both inputs as high levels, outputting a high level, i.e., the second drive signal is generated, controlling the second NMOS transistor MN2 to turn on. At this moment, the gate voltage of the power transistor MP is further pulled down to the reference ground voltage VSS2 by the second NMOS transistor MN2, so that the parasitic gate-source capacitor Cgs, the second NMOS transistor MN2, and the second capacitor C2 form a loop, and the parasitic gate-source capacitor Cgs continues to extract charges from the second capacitor C2, pulling the gate voltage of the power transistor MP down to the reference ground voltage VSS2. Since the gate voltage of the power transistor MP has been pulled down by the first capacitor C1 by a preset voltage value of 4V before this stage, it only needs to continue to decrease by about 1V to make the gate-source voltage difference Vgs of the power transistor MP reach the maximum amplitude of 5V=VCC-VSS2. This process extracts a small amount of charge from the second capacitor C2, and the voltage across the second capacitor C2 hardly decreases, so the reference ground voltage VSS2 does not move up, ensuring that the power transistor MP has the largest possible gate-source voltage difference Vgs when it is turned on, thereby reducing its on-resistance and effectively reducing the on-loss of the power transistor, thereby reducing the power consumption of the system during operation and improving the overall efficiency of the system.

[0043] According to the above embodiment, by adopting a two-stage pull-down control strategy, the gate voltage of the power tube MP is first lowered by a preset voltage value by using the external large-capacity first capacitor C1, and then the gate voltage is further lowered to the reference ground voltage VSS2 by the small-capacity second capacitor C2. Since the main charge extraction process is completed by the first capacitor C1, the second capacitor C2 is only used for slight voltage adjustment, which greatly reduces the voltage fluctuation on the second capacitor C2, effectively avoids the large drift of the high-voltage domain reference potential VSS2, thereby ensuring that the gate-source voltage Vgs of the power tube MP reaches the maximum when the power tube MP is turned on, thereby reducing the on-resistance. The technical scheme of the present application not only improves the driving capability and on effect of the power tube MP, but also significantly reduces the on-resistance, reduces the system power consumption, and enhances the stability and reliability of the circuit under wide voltage working conditions.

[0044] Figure 4 A flowchart of a wide-voltage PMOS driving method according to an embodiment of the present application is shown. As shown in the figure, the method comprises the following steps: Figure 4 Step S100, receiving an external control signal Drv0 by a control module.

[0045] Step S200, when the external control signal Drv0 is high, the control module generates a first driving signal to turn on the first auxiliary pull-down unit and lower the gate voltage of the power tube MP.

[0046] Step S300, when the gate voltage of the power tube MP is lowered by a preset voltage value, the control module generates a second driving signal to turn on the second auxiliary pull-down unit and turn off the first auxiliary pull-down unit, so that the gate voltage of the power tube MP is further lowered to the reference ground voltage VSS2, thereby ensuring that the power tube MP is in a fully on state and reducing the on-resistance.

[0047] In this step, after the gate voltage of the power tube MP is lowered by a preset voltage value, the Schmidt output of the logic unit 320 is triggered to flip to high level, and after logic operation, the second driving signal is generated.

[0048] Step S400, when the external control signal Drv0 is low, the control module generates a third driving signal to turn on the auxiliary pull-up unit, so that the power tube MP is turned off.

[0049] In this step, when the external control signal Drv0 is low, the control module 300 generates a third driving signal to drive the auxiliary pull-up unit 430 to turn on, so that the gate-source voltage of the power tube MP approaches 0V and the power tube MP is turned off.

[0050] In the above wide-voltage PMOS driving method, the specific implementation of each step is described with reference to the related content of the above embodiment of the wide-voltage PMOS driving circuit, which will not be described in detail here.​

[0051] Each technical feature of the above-described embodiments can be combined with any other technical feature, and for the sake of brevity, not all possible combinations are described, but it is understood that the scope of the present disclosure encompasses all such possible combinations.

[0052] The above-described embodiments are merely representative of several embodiments of the present disclosure, and the description is relatively specific and detailed, but should not be construed as limiting the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present disclosure, a number of modifications and improvements can be made, which are all within the scope of the present disclosure. Therefore, the scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A wide-voltage PMOS driver circuit, comprising: The circuit comprises a power tube MP, and further comprises: a high-voltage direct-current source connected to a source of the power tube MP, configured to provide a high-voltage direct-current voltage; a level shift module connected to the high-voltage direct-current source, configured to generate a reference ground voltage VSS2 in a high-voltage domain; a control module configured to receive and process an external control signal Drv0, and generate a first driving signal, a second driving signal and a third driving signal; a driving module comprising a first auxiliary pull-down unit, a second auxiliary pull-down unit and an auxiliary pull-up unit, wherein the first auxiliary pull-down unit and the second auxiliary pull-down unit are both connected to the control module and a gate of the power tube MP, and are configured to control conduction of the power tube MP according to the first driving signal and the second driving signal; and the auxiliary pull-up unit is connected to the control module and the gate of the power tube MP, and is configured to control turn-off of the power tube MP according to the third driving signal.

2. The wide-voltage PMOS driver circuit of claim 1, wherein, When the external control signal Drv0 is at a high level, the control module generates the first driving signal, so that the first auxiliary pull-down unit is turned on, and a gate voltage of the power tube MP is pulled low; When the gate voltage of the power tube MP decreases by a preset voltage value, the control module generates the second driving signal, the second auxiliary pull-down unit is turned on, and the first auxiliary pull-down unit is turned off, so that the gate voltage of the power tube MP further decreases to the reference ground voltage VSS2, thereby ensuring that the power tube MP is in a fully-conductive state and reducing on-resistance; When the external control signal Drv0 is at a low level, the control module generates the third driving signal, so that the auxiliary pull-up unit is turned on, and the power tube MP is turned off.

3. The wide-voltage PMOS driver circuit of claim 2, wherein, The high-voltage direct-current source comprises a first capacitor C1, a first end of the first capacitor C1 is connected to a direct-current voltage VCC, and a second end of the first capacitor C1 is grounded.

4. The wide-voltage PMOS driver circuit of claim 3, wherein, The control module comprises a signal conversion unit, and the signal conversion unit comprises: a first LS circuit, an input end of the first LS circuit receives the external control signal Drv0, and an output end of the first LS circuit outputs the third driving signal, the first LS circuit is configured to convert a low-voltage domain signal into a high-voltage domain signal, and a signal logic state is unchanged; a second LS circuit configured to convert a high-voltage domain signal into a low-voltage domain signal, and a signal logic state is unchanged.

5. The wide-voltage PMOS driver circuit of claim 4, wherein, The control module further comprises a logic unit, and the logic unit comprises a first AND gate AND1, a second AND gate AND2, a first NOT gate NOT1, a second NOT gate NOT2 and a Schmitt circuit; an input end of the Schmitt circuit is connected to the gate of the power tube MP, and an output end of the Schmitt circuit is connected to an input end of the second NOT gate NOT2; an output end of the second NOT gate NOT2 is connected to an input end of the second LS circuit, and the output end of the second NOT gate NOT2 is further connected to an input end of the first NOT gate NOT1; an output end of the first NOT gate NOT1 is connected to a first input end of the first AND gate AND1; a second input end of the first AND gate AND1 is connected to an output end of the first LS circuit, and an output end of the first AND gate AND1 is connected to the second auxiliary pull-down unit; The first input end of the second AND gate AND2 is connected to the output end of the second LS circuit, the second input end of the second AND gate AND2 is connected to the external control signal Drv0, and the output end of the second AND gate AND2 is connected to the first auxiliary pull-down unit.

6. The wide-voltage PMOS driver circuit of claim 5, wherein, The auxiliary pull-up unit comprises a first PMOS tube MP1, the source of the first PMOS tube MP1 is connected to the high-voltage direct-current source, the gate is connected to the output end of the first LS circuit, and the drain is connected to the gate of the power tube MP; the first PMOS tube MP1 is turned on when receiving the third driving signal, so that the power tube MP is disconnected; The first auxiliary pull-down unit comprises a first NMOS tube MN1, the gate of the first NMOS tube MN1 is connected to the output end of the second AND gate AND2, the drain of the first NMOS tube MN1 is connected to the gate of the power tube MP, and the source is grounded; The second auxiliary pull-down unit comprises a second NMOS tube MN2, the gate of the second NMOS tube MN2 is connected to the output end of the first AND gate AND1, the drain of the second NMOS tube MN2 is connected to the gate of the power tube MP, and the source is connected to the reference ground voltage VSS2 of the level shift module.

7. The wide-voltage PMOS driver circuit of claim 6, wherein, The level shift module comprises a second capacitor C2, a constant current source I, a second PMOS tube MP2 and a third PMOS tube MP3 which are current mirrors, a third NMOS tube MN3 and a fourth NMOS tube MN4 which are current mirrors, a first resistor R1 and a voltage stabilizing tube Z1; In the level shift module, the direct-current voltage VCC is connected to the first resistor R1, the second PMOS tube MP2 and the fourth NMOS tube MN4 to the ground in turn; the direct-current voltage VCC is also connected to the voltage stabilizing tube Z1 and the third PMOS tube MP3 to the ground in turn; the first end of the second capacitor C2 is connected to the direct-current voltage VCC, and the second end is connected to the reference ground voltage VSS2 and the source of the second NMOS tube MN2; The gate of the second PMOS tube MP2 is connected to the gate of the third PMOS tube MP3 and the drain of the second PMOS tube MP2; the gate of the third NMOS tube MN3 is connected to the gate of the fourth NMOS tube MN4 and the drain of the third NMOS tube MN3; the drain of the third NMOS tube MN3 is also connected to the constant current source I.

8. The wide-voltage PMOS driver circuit of claim 7, wherein, The voltage stabilizing value of the voltage stabilizing tube Z1 is greater than the opening threshold voltage of the power tube MP and less than the breakdown voltage of the power tube MP; The preset voltage value is the input voltage variation amount of the Schmitt circuit output converted from low level to high level.

9. The wide-voltage PMOS driver circuit of claim 8, wherein, The first capacitor C1 is an external capacitor, the second capacitor C2 is an internal integrated capacitor, and the capacitance of the first capacitor C1 is greater than that of the second capacitor C2.

10. A wide-voltage PMOS driving method for the wide-voltage PMOS driving circuit according to any one of claims 1 to 9, characterized by, The method comprises: receiving an external control signal Drv0 through a control module; When the external control signal Drv0 is high, the control module generates a first driving signal, so that a first auxiliary pull-down unit is turned on, and a gate voltage of a power transistor MP is pulled down; When the gate voltage of the power transistor MP is lowered by a preset voltage value, the control module generates a second driving signal, so that a second auxiliary pull-down unit is turned on, and the first auxiliary pull-down unit is turned off, so that the gate voltage of the power transistor MP is further lowered to a reference ground voltage VSS2, thereby ensuring that the power transistor MP is in a fully on state, and reducing an on resistance; When the external control signal Drv0 is low, the control module generates a third driving signal, so that an auxiliary pull-up unit is turned on, and the power transistor MP is turned off.

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