Signal processing method, communication circuit and switching power supply type charger

Abstract

The invention relates to a signal processing method, a communication circuit and a switching power supply type charger. The method comprises the following steps: sampling a received signal based on a preset time interval; determining count values of a high level and a low level sampled on the signal in the sampling window; determining the level state of the signal in the sampling window according to a first comparison result of the count values of the high level and the low level in the sampling window; and generating a level flipping signal according to the level state of the signal in the previous sampling window and the level state of the signal in the current sampling window. According to the invention, the problem of weak anti-interference capability of the single-line communication circuit is solved, so that the single-line communication circuit can accurately detect level flip under a high-interference condition, and the anti-interference capability of the single-line communication circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a signal processing method, a communication circuit and a switching power supply type charger. BACKGROUND

[0002] The existing products (such as two-wheeled vehicle chargers, electric tool battery pack chargers, etc.) often need to use single-line communication due to cost constraints or limitations of their own interfaces. In related technologies, a universal asynchronous receiver / transmitter (UART) protocol is used to share TX (transmission) and RX (reception) communication lines to realize a half-duplex single-line communication mode. However, in a high-noise scene close to a relay, a switching power supply, etc., a single-line communication circuit is easily disturbed by noise, leading to misjudgment of a received signal. At present, no effective solution has been proposed for this problem. SUMMARY

[0003] The present application provides a signal processing method, a communication circuit and a switching power supply type charger, which at least solve the problem of weak anti-interference ability of a single-line communication circuit.

[0004] A signal processing method, the method comprising: sampling a received signal based on a preset time interval; determining count values of high and low levels sampled on the signal within a sampling window; determining a level state of the signal in the sampling window according to a first comparison result of the count values of the high and low levels within the sampling window; and generating a level flip signal according to the level state of the signal in a previous sampling window and the level state of the current sampling window.

[0005] In some embodiments, the determination of the level state of the signal in the sampling window according to the first comparison result of the count values of the high and low levels within the sampling window comprises: if the count value of the high level sampled within the sampling window is greater than or equal to the count value of the low level, determining that the signal is in a high level state in the sampling window; and if the count value of the high level sampled within the sampling window is less than the count value of the low level, determining that the signal is in a low level state in the sampling window; and the generation of the level flip signal according to the level state of the signal in the previous sampling window and the level state of the current sampling window comprises: if the signal is in a low level state in the previous sampling window and in a high level state in the current sampling window, generating a first level flip signal; and if the signal is in a high level state in the previous sampling window and in a low level state in the current sampling window, generating a second level flip signal.

[0006] In some embodiments, the method further comprises: determining a second comparison result of the total count of the high level and the low level sampled in a current logic period, and determining a logic state corresponding to the current logic period according to the second comparison result; wherein the logic period is a duration between two adjacent first level flip signals or second level flip signals sampled.

[0007] In some embodiments, the method further comprises: generating a modified signal according to the logic state corresponding to each logic period.

[0008] In some embodiments, the window width of the sampling window is 1 / N of the total sampling times of the signal in each logic period, and N is an integer greater than or equal to 10.

[0009] A communication circuit, comprising: a receiving module and a processing module; the processing module comprises a timing control unit, a sampling unit, a counting unit, a comparison unit and a flip signal generation unit; wherein the signal input end of the receiving module is electrically connected with the communication port, and the signal output end is electrically connected with the sampling unit; the receiving module is used for receiving a signal; the timing control unit is electrically connected with the sampling unit, and the timing control unit is used for generating a sampling trigger signal of a preset time interval; the sampling unit is used for sampling the signal when receiving the sampling trigger signal; the counting unit is electrically connected with the sampling unit, and the counting unit is used for determining the count values of the high level and the low level sampled on the signal in the sampling window; the comparison unit is electrically connected with the counting unit, and the comparison unit is used for determining the level state of the signal in the sampling window according to a first comparison result of the count values of the high level and the low level in the sampling window; the flip signal generation unit is electrically connected with the comparison unit, and the flip signal generation unit is used for generating a level flip signal according to the level state of the signal in the previous sampling window and the level state of the current sampling window.

[0010] In some embodiments, the processing module further comprises a logic state determination unit; the counting unit is further used for determining the total count of the high level and the low level sampled in a current logic period, and the logic period is a duration between two adjacent first level flip signals or second level flip signals sampled; the logic state determination unit is electrically connected with the counting unit, and the logic state determination unit is used for determining a second comparison result of the total count of the high level and the low level sampled in the current logic period, and determining a logic state corresponding to the current logic period according to the second comparison result.

[0011] In some embodiments, the processing module further comprises a trimming signal generating unit electrically connected to the logic state determining unit, the trimming signal generating unit being configured to generate a trimmed signal according to the logic state corresponding to each logic period.

[0012] In some embodiments, the window width of the sampling window is 1 / N of the total number of sampling times of the signal in each logic period, N being an integer greater than or equal to 10; the logic period is the duration between adjacent first level flip-flop signals or second level flip-flop signals.

[0013] In some embodiments, the communication circuit further comprises a sending module and an overvoltage protection module; a signal input end of the sending module is connected to a signal output end of the processing module, a signal output end of the sending module is electrically connected to the communication interface, and the sending module is configured to send signals; the overvoltage protection module is connected in parallel between the signal input end and the signal output end of the sending module; the overvoltage protection module is configured to control the sending module to remain in a high-impedance state when the voltage of the communication interface is higher than a set value.

[0014] In some embodiments, the circuit further comprises a power supply VCC and a resistor R1, the resistor R1 being connected in series between the power supply VCC and the communication interface; the sending module comprises a resistor R5, a resistor R6, a resistor R9, and a switch tube Q3; one end of the resistor R5 is electrically connected to the signal output end of the processing module, and the other end is electrically connected to the control end of the switch tube Q3; one end of the resistor R6 is electrically connected to the control end of the switch tube Q3, and the other end is electrically connected to the ground end; one end of the resistor R9 is electrically connected to the communication interface, and the other end is electrically connected to the input end of the switch tube Q3; the output end of the switch tube Q3 is electrically connected to the ground end; the overvoltage protection module comprises a resistor R7, a resistor R8, and a switch tube Q1; one end of the resistor R7 is electrically connected to the communication interface, and the other end is electrically connected to the control end of the switch tube Q1; one end of the resistor R8 is electrically connected to the control end of the switch tube Q1, and the other end is electrically connected to the ground end; the input end of the switch tube Q1 is electrically connected to the control end of the receiving module, and the output end is electrically connected to the ground end.

[0015] A switching power supply type charger, the charger comprising the above communication circuit.

[0016] The signal processing method, the communication circuit and the switching power supply type charger provided by the application sample the received signal based on a preset time interval; determine the count values of the high level and the low level sampled on the signal in the sampling window; determine the level state of the signal in the sampling window according to the first comparison result of the count values of the high level and the low level in the sampling window; and generate the level flip signal according to the level state of the signal in the previous sampling window and the level state of the current sampling window, so as to solve the problem of weak anti-interference ability of the single-wire communication circuit, make it also able to accurately detect the level flip under high interference condition, and improve the anti-interference ability of the single-wire communication circuit. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other embodiments can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0018] Figure 1 A zero-return code protocol provided by the application is shown.

[0019] Figure 2 Another zero-return code protocol provided by the application is shown.

[0020] Figure 3 A flowchart of a signal processing method provided by the application is shown.

[0021] Figure 4 A structural schematic diagram of a communication circuit provided by the application is shown.

[0022] Figure 5 A structural schematic diagram of an analog circuit of the processing module 42 provided by the application is shown.

[0023] Figure 6 A structural schematic diagram of another communication circuit provided by the application is shown.

[0024] Figure 7 A structural schematic diagram of still another communication circuit provided by the application is shown.

[0025] Figure 8 A structural schematic diagram of a single-wire communication circuit provided by the application is shown.

[0026] Figure 9 A circuit topology diagram of the single-wire communication circuit provided by the application is shown. DETAILED DESCRIPTION

[0027] Embodiments of the present application will be described below in greater detail with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is understood that the present application can be carried out in various forms and should not be construed as being limited to the embodiments set forth herein, but rather should be construed to encompass all alternatives and modifications falling within the scope of the present application. It is understood that the drawings and embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of the present application.

[0028] In the present embodiment, the single-wire UART communication uses one bidirectional pin for both data transmission and reception, and the transmitting device and the receiving device are connected to the same signal line via the transceiver pin, which needs to be able to support bidirectional communication. The signal line generally follows the common standard of UART communication, such as TTL level (0V for logic 0 and 5V for logic 1) or CMOS level. However, it is understood that the specific level standard used may vary depending on the device and application scenario.

[0029] In the single-wire UART communication, the start bit is a logic 0 level lasting one bit time, which is used to identify the beginning of a data frame. The transmitter generates the start bit by pulling the signal line from high to low, and the receiver starts reading the subsequent data bits at the agreed baud rate after detecting the low-level transition. In the present embodiment, the start bit is also used to determine the starting point of a logic period, for example, when the start bit transmission ends as the starting point of a logic period, thereby ensuring that the receiving data processing for anti-interference purposes has a suitable logic period.

[0030] In the single-wire UART communication, the stop bit is a logic 1 level of 1 bit or more, which marks the end of data transmission. The transmitter will keep the signal line at a high level after sending the data bits and optional check bits, with a duration of the bit time specified by the stop bit.

[0031] In the single-wire UART communication of the present embodiment, Return-to-Zero (RZ) is used to represent data 0 and data 1. Return-to-Zero is an encoding method in which the signal level is restored to zero within one symbol, and it is a binary information encoding method that uses pulses of different polarities to represent binary "1" and "0", respectively. In the 0 code, the duration of the low level is greater than that of the high level, and in the 1 code, the duration of the high level is greater than that of the low level. It should be noted that the present scheme does not limit the specific protocol of Return-to-Zero, and the protocol can be, for example, as shown in Figure 1 where the high level of each symbol is restored to zero and then lasts for a certain period of time, or as shown in Figure 2 where the high level of each symbol is restored to zero to indicate the end of the symbol transmission.

[0032] It can be seen that the key to accurately identifying the logic state of a symbol is to accurately identify the level flip position. In the related art, an edge detection flip-flop is usually used to detect the rising edge or falling edge of a signal to output a level flip signal. However, in a single-wire UART communication in a strong interference scene such as a charger, due to the strict level and baud rate detection requirements, in the case of a charger working at high power or external electromagnetic compatibility (EMC) interference, there are many level transition glitches in the period, and the conventional detection method is easily affected by the instantaneous interference signal and detection errors occur, and a complete period cannot be simply determined by the conventional method of rising edge, falling edge and the like, so that the logic corresponding to each bit cannot be accurately determined, resulting in a problem of serious packet loss or even unable to normally communicate.

[0033] Therefore, the present application provides a signal processing method to accurately detect the level flip signal in a strong interference scene, effectively improving the anti-interference ability of the circuit. The present application will be specifically introduced as follows: Figure 3 A flowchart of a signal processing method provided by the present application is shown, which includes the following steps: Step S301, sampling the received signal based on a preset time interval.

[0034] Step S302, determining the count values of the high level and low level sampled on the signal in the sampling window.

[0035] Step S303, determining the level state of the signal in the sampling window according to the first comparison result of the count values of the high level and low level in the sampling window.

[0036] Step S304, generating a level flip signal according to the level state of the signal in the previous sampling window and the level state of the current sampling window.

[0037] Compared with the related art, the above-mentioned step of counting the sampled high level and low level in the sampling window, and then determining the level state of the signal in the sampling window according to the comparison result of the count values, can accurately identify the level state of the signal in the sampling window even if there is an instantaneous interference signal causing one or several sampling errors. If the level state in the two consecutive sampling windows changes, it is considered that the level has flipped, and then the level flip signal is accurately generated. The above-mentioned scheme avoids the influence of the instantaneous interference signal, and improves the anti-interference ability of the communication circuit, especially the single-wire communication circuit.

[0038] In some embodiments, the step 303 is implemented by comparing the count values of the high and low levels to determine the level state of the signal in the sampling window. For example, if the count value of the high level sampled in the sampling window is greater than or equal to the count value of the low level, it is determined that the signal is in the high level state in the sampling window; if the count value of the high level sampled in the sampling window is less than the count value of the low level, it is determined that the signal is in the low level state in the sampling window. By using the count value comparison method, the above functions can be implemented by using a counter and a comparator, which is simple and low in cost.

[0039] The level flip signals are of two forms, one is a rising edge signal used to represent that the signal flips from a low level state to a high level state, and the other is a falling edge signal used to represent that the signal flips from a high level state to a low level state. In order to distinguish the rising edge and falling edge signals, when performing the step S304, if the signal is in a low level state in the last sampling window and in a high level state in the current sampling window, a first level flip signal (i.e., a rising edge signal) is generated; if the signal is in a high level state in the last sampling window and in a low level state in the current sampling window, a second level flip signal (i.e., a falling edge signal) is generated. Further, if the signal is in the same level state in the last sampling window and in the current sampling window, a third level signal can also be generated to represent that the signal does not flip.

[0040] It can be understood that after the above rising edge signal and falling edge signal are accurately identified, the data bits such as start bits, stop bits and data transmission process can be accurately identified according to the identified level flip signals.

[0041] For the data bits, the identification of the data bits refers to identifying the logic state corresponding to the data bit (symbol). It is continued to refer to Figure 1 and Figure 2 For any symbol formed by a return-to-zero code, it starts with a rising edge, experiences a falling edge and finally ends with a rising edge in a symbol (as shown in Figure 1 ), or it starts with a falling edge, experiences a rising edge and finally ends with a falling edge in a symbol (as shown in Figure 2 ), therefore, the logic period corresponding to a symbol refers to the duration between the adjacent first level flip signal (rising edge signal) or second level flip signal (falling edge signal) sampled. In Figure 1 or Figure 2In any one symbol, since the duty cycle of high level is greater than that of low level in the symbol of logic 1, the total count value of high level state will be higher than that of low level state in the total count value of high level and low level sampled in the symbol of logic 1 (including multiple sampling windows). Therefore, according to the second comparison result of the total count value of high level and low level sampled in the current logic period, it can be determined whether the logic state corresponding to the current logic period is logic 1 or logic 0.

[0042] In the above embodiment, the window width of the sampling window is 1 / N of the total sampling number of the signal in each logic period, and N is an integer greater than or equal to 10. For example, the total sampling number of the signal in a certain logic period is 100, and N is 10. Then, the sampling number corresponding to each sampling window is 10, that is, 10 sampling points. Since the signal system often has a certain degree of deviation, for example, the deviation at the sending end causes the clock of the signal to be larger than the standard clock, and the total sampling number obtained by sampling the signal based on the standard clock at the receiving end is assumed to be 120 (only an example value), and N is 10. Then, the sampling number corresponding to each sampling window is 12. It can be seen that in some embodiments, the window width of the sampling window can be adaptively adjusted according to the deviation of the sending end system to ensure that the sampling number of any one symbol is N. In other embodiments, the window width of the sampling window can be fixed by pre-setting. Still taking the standard clock sampling number of one symbol as 100 as an example, assuming that the sampling window is set to 10, then 10 level states are recognized by using 10 sampling windows to sample the symbol sent by the sending end without deviation under the standard clock. After the deviation of the sending end system, 12 level states are recognized by using 12 sampling windows to sample the symbol sent by the sending end under the standard clock.

[0043] In some embodiments, after identifying the logic state corresponding to each logic period, the data information can be identified according to the logic states. In other embodiments, it can be desired to recover the signal without interference for subsequent system processing. In this case, a modified signal can be generated according to the logic state corresponding to each logic period. The modified signal is a signal not affected by external interference signals.

[0044] Compared with the single-wire UART communication in the related art, the single-point sampling on one period in the related art is prone to be misjudged by noise interference. The above embodiment samples and counts the high level and the low level of one data bit period multiple times, determines the logic 1 and 0 by comparing the count numbers of the high level and the low level, and the count has the advantage that the level glitch is not prone to affect the final logic determination in a strong interference state, and only a long-term interference can flip the logic, thereby improving the anti-interference capability of the communication circuit.

[0045] The application also provides a communication circuit for implementing the above signal processing method. Figure 4 FIG. 1 is a structural schematic diagram of a communication circuit of the application, which comprises a receiving module 41 and a processing module 42; the processing module 42 comprises a timing control unit 421, a sampling unit 422, a counting unit 423, a comparison unit 424 and a flip signal generation unit 425.

[0046] The signal input end of the receiving module 41 is electrically connected with the communication port 40, and the signal output end is electrically connected with the sampling unit 422, and the receiving module 41 is used for receiving a signal.

[0047] The timing control unit 421 is electrically connected with the sampling unit 422, and the timing control unit 421 is used for generating a sampling trigger signal of a preset time interval.

[0048] The sampling unit 422 is used for sampling a signal when receiving the sampling trigger signal.

[0049] The counting unit 423 is electrically connected with the sampling unit 422, and the counting unit 423 is used for determining the count values of the high level and the low level sampled by the sampling unit on the signal in the sampling window.

[0050] The comparison unit 424 is electrically connected with the counting unit 423, and the comparison unit 424 is used for determining the level state of the signal in the sampling window according to the first comparison result of the count values of the high level and the low level in the sampling window.

[0051] The flip signal generation unit 425 is electrically connected with the comparison unit 424, and the flip signal generation unit 425 is used for generating a level flip signal according to the level state of the signal in the previous sampling window and the level state of the current sampling window.

[0052] The above processing module 42 can be realized by a digital circuit, for example, realized by an FPGA or a DSP, and further realizes the functional modules including the timing control unit 421, the sampling unit 422, the counting unit 423, the comparison unit 424 and the flip signal generation unit 425.

[0053] Compared with the related art, the communication circuit can count the high level and low level in the sampling window, and determine the level state of the signal in the sampling window according to the comparison result of the count values, so that even if the transient interference signal causes one or several times of sampling error, the level state of the signal in the sampling window can be accurately identified according to the comparison result of the count values of the high level and low level in the whole sampling window. If the level state in the two continuous sampling windows changes, it is considered that the level flips, and then the level flip signal is accurately generated. By using the communication circuit, the influence of the transient interference signal is avoided, so that the level flip can be accurately detected under the high interference condition, and the anti-interference ability of the communication circuit, especially the single-wire communication circuit, is improved.

[0054] The processing module 42 is realized by an analog circuit. Figure 5 The structure schematic diagram of the processing module 42 analog circuit provided in the application is shown, and the following will be specifically introduced.

[0055] The sampling clock generator 51 is used to realize the timing control unit 421. In some embodiments, the sampling clock generator 51 includes a 555 timer connected to a non-stable oscillator to generate a sampling pulse SMP_TICK.

[0056] The sampling unit 422 includes a sampling switch 52, a holding capacitor 53 and an operational amplifier 54. The sampling switch 52 can be a high-speed analog switch, and the parameters thereof can be, for example, a conduction resistance of 2.5Ω and an opening time of 8ns to meet the sampling requirements. The holding capacitor 53 can use an operational amplifier 54 as a buffer to output a sampling signal. The sampling window length can be counted by a binary counter on SMP_TICK, and a WINDOW_END positive pulse is generated after N pulses are counted and the signal is reset. N is hard-set by a code switch or a resistance network.

[0057] The counting unit 423 includes a switch 55, a high-level integrator 56 and a low-level integrator 57. In the application, “time-voltage” conversion is used instead of digital counting, and the two operational amplifier integrators are only turned on to integrate in the high-level state or the low-level state. The switch 55 is driven by the output level state of the operational amplifier 54, and when the high-level state is turned on, the high-level integrator 56 is charged, and when the low-level state is turned on, the low-level integrator 57 is charged.

[0058] The comparison unit 424 is implemented as a window comparator using the high-speed comparator 58. When the voltage of the high-level integrator 56 is higher than the voltage of the low-level integrator 57 within the sampling window, a high-level state is output. When the voltage of the low-level integrator 57 is higher than the voltage of the high-level integrator 56 within the sampling window, a low-level state is output.

[0059] The level state of the signal within the sampling window is determined by comparing the high-level count value and the low-level count value using the processing module. For example, if the count value of the high-level sampled within the sampling window is greater than or equal to the count value of the low-level, it is determined that the signal is in a high-level state within the sampling window. If the count value of the high-level sampled within the sampling window is less than the count value of the low-level, it is determined that the signal is in a low-level state within the sampling window. The count value comparison method uses a counter and a comparator to achieve the above functions, and the implementation is simple and low in cost.

[0060] The flip signal generation unit 425 is implemented by a double D flip-flop 59. The D terminal of the double D flip-flop 59 is connected to the output terminal of the high-speed comparator 58, and the CLK terminal is connected to the WINDOW_END of the sampling unit 422. In the double D flip-flop 59, the level determination result of the previous sampling window is stored in the Q terminal, and then the signals of the D terminal and the Q terminal are sent to the XOR gate to perform XOR operation on the level determination result of the previous sampling window and the determination result of the current sampling window to generate the level flip signal EDGE_PULSE.

[0061] The level flip signal has two forms, one is a rising edge signal used to represent that the signal flips from a low-level state to a high-level state, and the other is a falling edge signal used to represent that the signal flips from a high-level state to a low-level state. In order to distinguish the rising edge signal and the falling edge signal, in the flip signal generation unit 425, if the signal is in a low-level state in the previous sampling window and is in a high-level state in the current sampling window, a first level flip signal (i.e., a rising edge signal) is generated. If the signal is in a high-level state in the previous sampling window and is in a low-level state in the current sampling window, a second level flip signal (i.e., a falling edge signal) is generated. Further, if the signal is in the same level state in the previous sampling window and the current sampling window, the flip signal generation unit 425 can also generate a third level signal to represent that the signal does not flip.

[0062] It can be understood that after the rising edge signal and the falling edge signal are accurately identified, the data bits such as the start bit, the stop bit, and the data transmission process can be accurately identified according to the identified level flip signals.

[0063] For the data bit, the identification of the data bit refers to identifying the logic state corresponding to the data bit (symbol). It is continued to be referred to that Figure 1 and Figure 2For any one symbol encoded by the zero-return code, it starts with a rising edge within a symbol, experiences a falling edge, and ends with a rising edge (as shown in Figure 1 ); or it starts with a falling edge within a symbol, experiences a rising edge, and ends with a falling edge (as shown in Figure 2 ); therefore, the logic period corresponding to one symbol refers to the duration between the adjacent two first-level flip-flop signals (rising edge signals) or second-level flip-flop signals (falling edge signals) sampled. Figure 1 Or Figure 2 In any one symbol, since the duty ratio of the high level in the logic 1 symbol is greater than that of the low level, the total count value of the high level state will be higher than that of the low level state in the logic 1 symbol (including multiple sampling windows). Therefore, according to the second comparison result of the total count value of the high level and the low level sampled in the current logic period, it can be determined whether the logic state corresponding to the current logic period is logic 1 or logic 0.

[0064] The above WINDOW_END is also used to reset the high-level integrator 56 and the low-level integrator 57 after the end of the judgment of one sampling window, so as to prepare for the judgment of the next sampling window.

[0065] Figure 6 Another structure of the communication circuit provided by the present application is shown in the structural schematic diagram, and the processing module 42 further includes a logic state determination unit 426.

[0066] The counting unit 423 is further used to determine the total count value of the high level and the low level sampled in the current logic period. The counting unit 423 is used to analog circuit implementation of the total count value of the high level and the low level as Figure 5 in the counting unit 423, the difference is that the high-level integrator and the low-level integrator are not reset by the WINDOW_END signal, but are reset by the logic period end flag CYCLE_END. The CYCLE_END signal can be realized by a 2-way 74HC123 monostable processing chip, the rising edge trigger channel of which outputs the first-level flip-flop signal, and the falling edge trigger channel outputs the second-level flip-flop signal. The two-way pulses are combined into the CYCLE_END signal as the trigger signal for resetting the counting unit and comparing the comparator.

[0067] The logic state determination unit 426 is electrically connected with the counting unit 423, and the logic state determination unit 426 is used to determine the second comparison result of the total count value of the high level and the low level sampled in the current logic period, and determine the logic state corresponding to the current logic period according to the second comparison result.

[0068] The logic state determining unit 426 can be implemented by a high-speed comparator, which has a similar implementation principle as the comparison unit 424, and thus will not be described here.

[0069] After identifying the logic state corresponding to each logic period, the data information can be identified according to the logic states. In some embodiments, it can be desired to restore the signal without interference for subsequent system processing, in which case, a modified signal can be generated according to the logic state corresponding to each logic period. Figure 7 Another structure of the communication circuit provided by the present application is shown in the structural schematic diagram, the processing module 42 further includes a modified signal generating unit 427, which is electrically connected with the logic state determining unit 426, and is configured to generate a modified signal according to the logic state corresponding to each logic period.

[0070] In some embodiments, the modified signal generating unit 427 can be implemented by a period gate, a polarity selection switch, and a double-channel Schmitt trigger: a gate with the same width as the logic period is generated, the high level or low level is connected to the output end according to the logic state by the polarity selection switch during the gate period, and a clean signal is obtained after shaping by the double-channel Schmitt trigger; the gate falls, and all integrators are reset immediately and the signal processing of the next logic period is started.

[0071] In the above embodiments, the window width of the sampling window is 1 / N of the total sampling times of the signal in each logic period, and N is an integer greater than or equal to 10. The logic period is the duration between the adjacent two first level flip signals or second level flip signals sampled. The first level flip signal is used to represent the signal flipping from the low level state to the high level state, and the second level flip signal is used to represent the signal flipping from the high level state to the low level state.

[0072] In the above embodiments, the window width of the sampling window is 1 / N of the total number of samplings of the signal in each logical period, and N is an integer greater than or equal to 10. For example, the total number of samplings of the signal in a certain logical period is 100, and N is 10. Then, the number of samplings corresponding to each sampling window is 10, that is, 10 sampling points. Because there is a certain degree of deviation in the signal system, for example, the deviation at the sending end causes the clock of the signal to be larger than the standard clock, and the same signal with one symbol is sampled based on the standard clock at the receiving end to obtain a total number of samplings of 120 (only an example value). Then, N is 10, and the number of samplings corresponding to each sampling window is 12. It can be seen that, in some embodiments, the window width of the sampling window can be adaptively adjusted according to the deviation of the sending end system to ensure that the number of window samplings for any one symbol is N. In other embodiments, the window width of the sampling window can be fixed in size by pre-setting. Still taking the number of samplings of the signal with one symbol under the standard clock as 100 as an example, if the sampling window is set to 10, then 10 sampling windows are used to sample and identify 10 level states of the symbol sent by the sending end under the standard clock. After the deviation of the sending end system, 12 sampling windows are used to sample and identify 12 level states of the symbol sent by the sending end under the standard clock.

[0073] The application also provides a single-wire communication circuit, Figure 8 A structural schematic diagram of a single-wire communication circuit provided by the application is shown, which comprises a receiving module 41 and a processing module 42, and further comprises a sending module 43 and an overvoltage protection module 44. The signal input end of the sending module 43 is connected with the signal output end of the processing module 42, the signal output end of the sending module 43 is electrically connected with the communication interface 40, and the sending module 43 is used for sending signals; the overvoltage protection module 44 is connected in parallel between the signal input end and the signal output end of the sending module 43; and the overvoltage protection module 44 is used for controlling the sending module 43 to keep a high resistance state when the voltage of the communication interface 40 is higher than a set value.

[0074] The communication interface described above is connected with only one communication line, and the receiving module 41 and the sending module 43 share the one communication line connected by the communication interface to realize the transmission and reception of data in a half-duplex mode. The receiving module 41 and the sending module 43 can use a switch tube as a voltage conversion and electrical isolation device to realize the transmission of signals with the same frequency and phase or the same frequency and opposite phase on the communication line to the processing module 42, and the transmission of signals with the same frequency and phase or the same frequency and opposite phase sent by the processing module 42 to the communication line.

[0075] Compared with the single-wire UART communication in the related art, the single-point sampling in one period in the related art is prone to be misjudged by noise interference. The above embodiment samples and counts the high level and the low level of one data bit period multiple times, and judges the logic 1 and 0 by comparing the count numbers of the high level and the low level. The advantage of the counting is that the level glitch is not prone to affect the final logic judgment in the strong interference state, and only the continuous long interference can flip the logic, thereby improving the anti-interference capability of the communication circuit.

[0076] In the sending module 43, after the control end thereof is subjected to the leading communication signal (high level) sent by the processing module 42, the sending end and the ground end thereof are conducted. At this time, if the voltage on the communication line is too high (for example, 20V), it will be very likely to break the components between the sending end and the ground end, causing the sending module 43 to be damaged. By using the single-wire communication circuit provided in the application, the overvoltage protection module 44 is connected between the communication interface 40 and the control end of the sending module 43. When the voltage of the communication interface 40 (that is, the voltage on the communication line) exceeds the set value, the overvoltage protection module 44 pulls down the voltage of the control end of the sending module 43, so that the sending end and the ground end of the sending module 43 cannot be conducted, thereby realizing the protection of the components of the sending module 43, and effectively prolonging the service life of the single-wire communication circuit.

[0077] Figure 9 The circuit topology of the single-wire communication circuit provided in the application is shown. The embodiments of the application will be described and explained below with reference to the circuit topology. Figure 9 The circuit topology is shown.

[0078] In the Figure 9 COM pin is the communication interface 40. TX is the sending terminal of the processing module 42, also known as the communication sending pin. RX is the receiving terminal of the processing module 42, also known as the communication receiving pin.

[0079] In the embodiment, the sending end, the receiving end and the control end are defined as follows: In the embodiment, the sending end and the receiving end are determined by the flow direction of the main signal or current. For example, in the sending module, the terminal connected with the processing module is called the receiving end of the sending module, and the terminal connected with the communication line is called the sending end of the sending module. In the switch tube, the terminal close to the ground end in the main circuit is called the output end, and the terminal far away from the ground end is called the input end. The terminal for receiving the control signal to control the on-off of the main circuit is called the control end. In addition, in the receiving module and the sending module, the input end of the receiving module and the sending module is used to control the on-off of the switch tube, and is also called the control end because the input signal and the output signal are electrically isolated by the switch tube.

[0080] In some embodiments, the bidirectional serial communication interface terminal is connected to the positive power supply through the first resistor R1, so that the bidirectional serial communication interface terminal maintains a high level when no data is transmitted or received, to meet the requirements of the UART protocol.

[0081] In some embodiments, the receiving module 41 includes a resistor R2, a resistor R3, a resistor R4, and a switch tube Q2. One end of the resistor R2 is connected to the bidirectional serial communication interface terminal, and the other end is connected to the control end of the switch tube Q2. One end of the resistor R3 is connected to the ground, and the other end is connected to the control end of the switch tube Q2. One end of the resistor R4 is connected to the positive power supply, and the other end is connected to the input end of the switch tube Q2. The output end of the switch tube Q2 is connected to the ground, and the input end is connected to the receiving terminal of the processing module. Reference Figure 9 When the COM pin is at a high level, the COM pin is divided by R2 and R3 to make Q2 conductive and RX low. That is, when the COM pin logic level is 1, RX is 0. When the COM pin is at a low level, Q2 is cut off, that is, when the COM pin logic level is 0, RX is 1. In this embodiment, the resistance of R2 and R3 is such that the voltage is greater than the turn-on voltage Vth of the switch tube Q2.

[0082] In some embodiments, the receiving module 41 further includes a transient suppression diode D1 connected between the control end of the switch tube Q2 and the ground. The transient suppression diode D1 can be used to protect the switch tube Q2 and the resistors R2 and R3. For example, when a sharp voltage is generated on the communication line, the transient suppression diode D1 is reversely broken down to conduct the sharp current to the ground, and the voltage at the control end of the switch tube Q2 is clamped within a safe voltage range.

[0083] In some embodiments, the sending module 43 includes a resistor R5, a resistor R6, a resistor R9, and a switch tube Q3. One end of the resistor R5 is connected to the output terminal of the processing module, and the other end is connected to the control end of the switch tube Q3. One end of the resistor R6 is connected to the control end of the switch tube Q3, and the other end is connected to the ground. One end of the resistor R9 is connected to the bidirectional serial communication interface terminal, and the other end is connected to the input end of the switch tube Q3. The output end of the switch tube Q3 is connected to the ground. Reference Figure 9 When TX is at a high level, the TX pin is divided by R5 and R6 to make Q3 conductive and COM low. That is, when the TX pin logic level is 1, COM is 0. When the TX pin is at a low level, Q3 is cut off, that is, when the TX pin logic level is 0, COM is 1.

[0084] In some embodiments, the overvoltage protection module 44 comprises: a voltage dividing unit and a switch unit; an input end of the voltage dividing unit is connected with the bidirectional serial communication interface terminal, a grounding output end is connected with the grounding end, and a voltage dividing output end is connected with a control end of the switch unit; an input end of the switch unit is connected with a control end of the sending module, and an output end is connected with the grounding end.

[0085] In order to reduce the cost and select as few components as possible, the voltage dividing unit in the application comprises a resistor R7 and a resistor R8; the switch unit comprises a switch tube Q1; one end of the resistor R7 is connected with the bidirectional serial communication interface terminal, and the other end is connected with a control end of the switch tube Q1; one end of the resistor R8 is connected with the control end of the switch tube Q1, and the other end is connected with the grounding end; an input end of the switch tube Q1 is connected with a control end of the receiving module, and an output end is connected with the grounding end.

[0086] The resistance ratio of R7 and R8 in the overvoltage protection module 44 is adjusted, and the overvoltage protection point of the circuit can be adjusted by the Vth of Q1, and the specific calculation method is as follows: Vovp=Vth×(R8+R7) / R8 For example, when the Vth of Q1 is 1.2V, if R7 and R8 are 100K and 10K respectively, the overvoltage protection point is 13.2V, that is, when the voltage of the COM pin is higher than 13.2V, the overvoltage protection module 44 works, which protects the sending module 43.

[0087] The working logic of the overvoltage protection module 44 is as follows: when the COM pin is externally connected with a large voltage, or the resistor R1 is short-circuited, etc., the COM pin voltage is too high, and the risk of damage to the device in the single-wire communication circuit is that the current through R9 and Q3 after Q3 is turned on exceeds the working limit value of the device, thereby causing burning. Therefore, the overvoltage protection circuit is used to actively close the control pole of Q3 when it is detected that the working voltage of the COM pin is higher than the limit value, so that Q3 is always cut off, thereby ensuring that Q3 and R9 will not be damaged. In the above circuit topology, the function of the overvoltage protection module is realized by the voltage dividing circuit and the characteristics of the turn-on voltage of Q1 transistor itself.

[0088] It can be understood that the overvoltage protection module can also have other forms. In addition, the logic of the level of the TX, RX and COM pins in the application is reversed, and the same logic as the COM pin level can be realized by adding one more transistor level conversion.

[0089] Figure 9 The switch tube shown is an insulated gate enhancement type NMOS tube, and a diode is also connected in reverse between its drain and source. However, the switch tube in the above embodiment is not limited to this, and can also include but is not limited to other bipolar transistors, metal oxide semiconductor field effect tubes, or insulated gate bipolar tubes (IGBT), etc., which are not limited in the application.

[0090] Figure 9 The single-wire communication circuit shown has the advantages of fewer components, simple structure, no need of expensive devices such as optocouplers, low hardware cost and manufacturing cost, and suitability for mass production.

[0091] The application also provides a switching power supply type charger, which may be, for example, an electric vehicle charger, an electric tool battery pack charger, etc., and the charger comprises the communication circuit described above.

[0092] It should be noted that the term "comprising" and its variants in the embodiments of the present application are open and inclusive, i.e., "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modification of "one", "multiple" in the embodiments of the present application is illustrative and not restrictive, and those skilled in the art should understand that, unless otherwise explicitly stated in the context, it should be understood as "one or more".

[0093] The steps described in the method embodiments provided by the embodiments of the present application can be executed in different orders and / or in parallel. In addition, the method embodiments can include additional steps and / or omit the execution of the steps shown. The protection scope of the present application is not limited in this respect.

[0094] The word "embodiment" in the present specification means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The presence of this phrase in various places in the specification does not necessarily mean the same embodiment, nor does it mean independence or alternatives to each other. Each embodiment in the present specification is described in a relevant manner, and the same or similar parts between each embodiment are cross-referenced. In particular, for device, equipment, system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and the relevant parts are referred to the part of the method embodiment.

[0095] The above-described embodiments only express several embodiments of the present application, which are described in a more specific and detailed manner, but should not be understood as a limitation on the protection scope. It should be noted that, for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A signal processing method, characterized by, The method comprises: sampling the received signal based on a preset time interval; determining the count values of high and low levels sampled on the signal within a sampling window; determining the level state of the signal in the sampling window according to a first comparison result of the count values of the high and low levels within the sampling window; generating a level flip signal according to the level state of the signal in the previous sampling window and the level state of the current sampling window.

2. The method of claim 1, wherein, The determination of the level state of the signal in the sampling window according to the first comparison result of the count values of the high and low levels within the sampling window comprises: if the count value of the high level sampled within the sampling window is greater than or equal to the count value of the low level, it is determined that the signal is in a high level state in the sampling window; if the count value of the high level sampled within the sampling window is less than the count value of the low level, it is determined that the signal is in a low level state in the sampling window; The generation of the level flip signal according to the level state of the signal in the previous sampling window and the level state of the current sampling window comprises: if the signal is in a low level state in the previous sampling window and in a high level state in the current sampling window, a first level flip signal is generated; if the signal is in a high level state in the previous sampling window and in a low level state in the current sampling window, a second level flip signal is generated.

3. The method of claim 2, wherein, The method further comprises: determining a second comparison result of the total count values of the high and low levels sampled in a current logic period, and determining a logic state corresponding to the current logic period according to the second comparison result; wherein the logic period is the duration between two adjacent first or second level flip signals sampled.

4. The method of claim 3, wherein, The method further comprises: generating a trimmed signal according to the logic state corresponding to each logic period.

5. The method according to claim 3 or 4, characterized in that, The window width of the sampling window is 1 / N of the total number of samplings of the signal in each logic period, and N is an integer greater than or equal to 10.

6. A communication circuit, characterized by The circuit comprises a receiving module and a processing module; the processing module comprises a timing control unit, a sampling unit, a counting unit, a comparison unit and a flip signal generation unit; wherein, the signal input end of the receiving module is electrically connected with the communication port, and the signal output end is electrically connected with the sampling unit, and the receiving module is used for receiving a signal; the timing control unit is electrically connected with the sampling unit, and the timing control unit is used for generating a sampling trigger signal of a preset time interval; the sampling unit is used for sampling the signal when receiving the sampling trigger signal; the counting unit is electrically connected with the sampling unit, and the counting unit is used for determining the count values of high and low levels sampled on the signal within a sampling window by the sampling unit; The comparison unit is electrically connected with the counting unit, and is configured to determine the level state of the signal in the sampling window according to a first comparison result of the counting values of the high level and the low level in the sampling window. The flip signal generation unit is electrically connected with the comparison unit, and is configured to generate a level flip signal according to the level state of the signal in the previous sampling window and the level state of the signal in the current sampling window.

7. The circuit of claim 6, wherein, The processing module further comprises a logic state determination unit. The counting unit is further configured to determine a total counting value of the high level and the low level sampled in a current logic period, the logic period being a duration between two adjacent first level flip signals or second level flip signals sampled. The logic state determination unit is electrically connected with the counting unit, and is configured to determine a second comparison result of the total counting value of the high level and the low level sampled in the current logic period, and determine a logic state corresponding to the current logic period according to the second comparison result.

8. The circuit of claim 7, wherein, The processing module further comprises a trimming signal generation unit electrically connected with the logic state determination unit, and configured to generate a trimmed signal according to the logic state corresponding to each logic period.

9. The circuit of claim 7 or 8, characterized in that, A window width of the sampling window is 1 / N of a total sampling number of the signal sampled in each logic period, N being an integer greater than or equal to 10.

10. The circuit of claim 6, wherein, The communication circuit further comprises a sending module and an overvoltage protection module. A signal input end of the sending module is connected with a signal output end of the processing module, a signal output end of the sending module is electrically connected with the communication interface, and the sending module is configured to send a signal. The overvoltage protection module is connected in parallel between the signal input end and the signal output end of the sending module, and is configured to control the sending module to keep a high resistance state when a voltage of the communication interface is higher than a set value.

11. The circuit of claim 10, wherein, The circuit further comprises a power supply VCC and a resistor R1, and the resistor R1 is connected in series between the power supply VCC and the communication interface. The sending module comprises a resistor R5, a resistor R6, a resistor R9 and a switch tube Q3, one end of the resistor R5 is electrically connected with the signal output end of the processing module, the other end is electrically connected with a control end of the switch tube Q3, one end of the resistor R6 is electrically connected with the control end of the switch tube Q3, the other end is electrically connected with a ground end, one end of the resistor R9 is electrically connected with the communication interface, the other end is electrically connected with an input end of the switch tube Q3, and an output end of the switch tube Q3 is electrically connected with the ground end. The overvoltage protection module comprises a resistor R7, a resistor R8 and a switch tube Q1, one end of the resistor R7 is electrically connected with the communication interface, the other end is electrically connected with a control end of the switch tube Q1. One end of the resistor R8 is electrically connected with the control end of the switch tube Q1, and the other end is electrically connected with the ground end. The input end of the switch tube Q1 is electrically connected with the control end of the receiving module, and the output end is electrically connected with the ground end.

12. A switching power supply type charger characterized by comprising: The charger comprises the communication circuit as claimed in any one of claims 6 to 11.

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