Ethernet-based time synchronization acquisition method, device, equipment, and media

Abstract

This invention relates to the field of Ethernet communication and digital information transmission technology, and discloses a time synchronization acquisition method, apparatus, device, and medium based on Ethernet. The method includes: acquiring initial network time based on a network time protocol and a precise time protocol; recovering a synchronization clock signal from the Ethernet physical layer signal and generating a trigger pulse signal aligned with the second boundary to generate a second-level reference time; using the trigger pulse signal and the synchronization clock signal to perform high-frequency counting and accumulation to generate nanosecond-level fine time; performing frequency division processing on the synchronization clock signal based on sampling rate configuration parameters to obtain a sampling driving clock; triggering the analog-to-digital conversion unit at the effective transition edge of the sampling driving clock to sample and latch the nanosecond-level fine time to generate a sampling timestamp and outputting it in conjunction with the sampled data. This invention achieves time recovery, time refinement, and sampling time locking through a unified time base, ensuring precise alignment between sampling actions and time counting, and improving the data synchronization accuracy and consistency of distributed acquisition nodes.

Description

Technical Field

[0001] This invention relates to the field of Ethernet communication and digital information transmission technology, and in particular to a time synchronization acquisition method, apparatus, device and medium based on Ethernet. Background Technology

[0002] Distributed synchronous acquisition systems typically consist of multiple acquisition nodes deployed in different locations. Each node needs to synchronously acquire physical quantities or signals under a unified time base. With the widespread application of distributed systems in scenarios such as industrial monitoring, structural health monitoring, and power system measurement, the synchronization accuracy of multiple nodes directly affects the consistency and reliability of the acquired data. Therefore, higher requirements are placed on high-precision time synchronization and high-consistency sampling control.

[0003] Among existing time synchronization technologies, Network Time Protocol (NTP) and Simple Network Clock Synchronization (SNTP) are the most common network time synchronization methods. However, their synchronization accuracy is usually only at the millisecond level, which cannot meet the requirements for microsecond or even nanosecond-level timing consistency. These protocols rely on message round-trip delay estimation. When network load fluctuates or paths change, the time offset will increase significantly, resulting in perceptible time drift for distributed nodes.

[0004] GPS time synchronization can achieve high accuracy, but it is easily affected by factors such as the receiving environment, electromagnetic interference, and antenna deployment conditions, making stability difficult to guarantee. Furthermore, GPS solutions are costly and cannot operate stably indoors, in enclosed environments, or in specific industrial settings, limiting their deployment in many distributed data acquisition applications.

[0005] The IEEE 1588v2 protocol can achieve sub-microsecond time synchronization through a message mechanism, but the quality of time synchronization is still affected by network jitter, hardware timestamp accuracy, and master-slave link stability. Furthermore, this protocol primarily provides time base alignment capabilities, relying on an external clock source for frequency stability, making it difficult to independently ensure a highly stable synchronized clock over long periods.

[0006] Synchronous Ethernet (SyncE) can extract highly stable frequency signals from the physical layer, which is beneficial for improving frequency consistency. However, its mechanism itself does not provide phase synchronization capabilities, and cannot meet the needs of scenarios requiring timestamp alignment and trigger consistency control. Since it only has frequency locking capabilities, the system still needs to rely on other mechanisms to supplement absolute time alignment and nanosecond-level trigger precision control. Summary of the Invention

[0007] The main objective of this invention is to provide a time synchronization acquisition method, apparatus, device, and storage medium based on Ethernet, aiming to solve the technical problem that existing technologies cannot simultaneously obtain high-precision time synchronization and strict alignment sampling actions among distributed acquisition nodes, making it difficult to achieve nanosecond-level synchronous acquisition based on a unified time base.

[0008] To achieve the above objectives, the present invention provides a time synchronization acquisition method based on Ethernet, comprising:

[0009] The data acquisition instrument communicates with the central control device based on the network time protocol and interacts with it based on the precision time protocol to obtain the initial network time.

[0010] The processing unit in the data acquisition instrument drives the physical layer interface unit to recover the synchronous clock signal from the Ethernet physical layer signal and generate a trigger pulse signal aligned with the second boundary, thereby generating a second-level reference time based on the initial network time.

[0011] Using the trigger pulse signal as a reset signal and the synchronization clock signal as a counting drive source, high-frequency counting accumulation is performed based on the second-level reference time to generate nanosecond-level fine time.

[0012] Receive sampling rate configuration parameters, and perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameters to obtain the sampling drive clock;

[0013] At the effective transition edge of the sampling drive clock, the sampling action is executed by controlling the analog-to-digital conversion unit, and the nanosecond-level fine time is latched to generate a sampling timestamp. The sampled data is then combined with the sampling timestamp and output.

[0014] Furthermore, to achieve the above objectives, the present invention provides an Ethernet-based time synchronization acquisition device, comprising:

[0015] The time synchronization communication module is used to communicate with the central control equipment through the data acquisition instrument based on the network time protocol, and to interact based on the precision time protocol to obtain the initial network time;

[0016] The physical layer clock recovery module is used to drive the physical layer interface unit in the data acquisition instrument to recover the synchronous clock signal from the Ethernet physical layer signal and generate a trigger pulse signal aligned with the second boundary, and generate a second-level reference time based on the initial network time.

[0017] The high-precision timing module is used to use the trigger pulse signal as a reset signal and the synchronous clock signal as a counting drive source to perform high-frequency counting accumulation based on the second-level reference time to generate nanosecond-level fine time.

[0018] A sampling clock generation module is used to receive sampling rate configuration parameters and perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameters to obtain a sampling drive clock.

[0019] The data acquisition and timestamp module is used to control the analog-to-digital conversion unit to perform sampling actions at the effective transition edge of the sampling driving clock, and to latch the nanosecond-level fine time to generate a sampling timestamp, and then combine the sampled data with the sampling timestamp for output.

[0020] Furthermore, to achieve the above objectives, the present invention also provides a computer device, the computer device including a memory, a processor, and an Ethernet-based time synchronization acquisition program stored in the memory and executable on the processor, wherein when the Ethernet-based time synchronization acquisition program is executed by the processor, it implements the steps of the Ethernet-based time synchronization acquisition method as described above.

[0021] Furthermore, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing an Ethernet-based time synchronization acquisition program, wherein the Ethernet-based time synchronization acquisition program, when executed by a processor, implements the steps of the Ethernet-based time synchronization acquisition method as described above.

[0022] Beneficial Effects: This invention relates to the field of Ethernet communication and digital information transmission technology, and discloses a time synchronization acquisition method, apparatus, device, and medium based on Ethernet, including: acquiring initial network time based on network time protocol and precise time protocol; recovering the synchronization clock signal from the Ethernet physical layer signal and generating a trigger pulse signal aligned with the second boundary to generate a second-level reference time; using the trigger pulse signal and the synchronization clock signal to perform high-frequency counting accumulation to generate nanosecond-level fine time; performing frequency division processing on the synchronization clock signal based on sampling rate configuration parameters to obtain a sampling driving clock; triggering the analog-to-digital conversion unit to sample and latch the nanosecond-level fine time at the effective transition edge of the sampling driving clock to generate a sampling timestamp; and combining the sampled data with the sampling timestamp for output. This invention achieves time recovery, time refinement, and sampling time locking through a unified time base, enabling precise alignment between sampling actions and time counting, and improving the data synchronization accuracy and consistency of distributed acquisition nodes. Attached Figure Description

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0024] Figure 1 This is a schematic diagram of an application environment for an Ethernet-based time synchronization acquisition method according to an embodiment of the present invention;

[0025] Figure 2This is a flowchart illustrating an embodiment of the Ethernet-based time synchronization acquisition method of the present invention;

[0026] Figure 3 This is a schematic diagram of the functional modules of a preferred embodiment of the Ethernet-based time synchronization acquisition device of the present invention;

[0027] Figure 4 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention;

[0028] Figure 5 This is another structural schematic diagram of a computer device according to one embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of a distributed precise synchronization acquisition system based on an Ethernet-based time synchronization acquisition device in one embodiment of the present invention;

[0030] Figure 7 This is a functional diagram illustrating the internal modules of the data acquisition instrument in one embodiment of the Ethernet-based time synchronization acquisition device of the present invention.

[0031] Figure 8 This is a schematic diagram of nanosecond-level fine time generation timing in one embodiment of the Ethernet-based time synchronization acquisition method of the present invention. Detailed Implementation

[0032] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0033] The Ethernet-based time synchronization acquisition method provided in this invention can be applied to, for example... Figure 1 In this application environment, the client communicates with the server via a network. The server can obtain the initial network time from the client based on the network time protocol and the precision time protocol; recover the synchronization clock signal from the Ethernet physical layer signal and generate a trigger pulse signal aligned with the second boundary to generate a second-level reference time; use the trigger pulse signal and the synchronization clock signal to perform high-frequency counting accumulation to generate nanosecond-level fine time; perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameters to obtain the sampling driving clock; trigger the analog-to-digital conversion unit to sample and latch the nanosecond-level fine time on the effective transition edge of the sampling driving clock to generate a sampling timestamp, and combine the sampled data with the sampling timestamp for output. This invention achieves time recovery, time refinement, and sampling time locking through a unified time base, ensuring precise alignment between sampling actions and time counting, and improving the data synchronization accuracy and consistency of distributed acquisition nodes. The client can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. The server can be implemented using a standalone server or a server cluster composed of multiple servers. The invention will be described in detail below through specific embodiments.

[0034] Please see Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of the Ethernet-based time synchronization acquisition method provided by the present invention. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0035] like Figure 2 As shown, the Ethernet-based time synchronization acquisition method proposed in this invention includes the following steps:

[0036] S10 communicates with the central control device via a data acquisition instrument based on the network time protocol and interacts with it based on the precision time protocol to obtain the initial network time.

[0037] In this embodiment, the data acquisition instrument communicates with the central control device based on the Network Time Protocol (NTP) and interacts with it based on the Precision Time Protocol (PTP) to obtain the initial network time. First, a communication link is established with the central control device via an Ethernet interface. This interface is responsible for message sending and receiving, link status maintenance, and data parsing, providing basic support for subsequent time interaction. The NTP provides multiple time fields in the communication to derive propagation delay and local time offset. The processing unit reads these fields from the received messages and derives the initial time offset based on the local counter status.

[0038] Precision time protocols are used to further improve the accuracy of time interaction. This protocol relies on a hardware-level timestamp mechanism to record the actual arrival and transmission times of messages. The timestamps are typically generated by a dedicated timestamp engine within the physical layer interface. The engine generates timestamps based on the relationship between frame boundary moments and local clock counts. The timestamp values ​​are directly related to the frequency stability of the local oscillator; therefore, the local clock state needs to be considered before parsing.

[0039] The central control unit acts as a time reference node in the precise time protocol interaction, transmitting reference time information to the acquisition instruments through bidirectional message exchange. The processing unit combines the request sending time, request receiving time, response sending time, and response receiving time to derive the link delay and calculate the offset of the local clock relative to the reference clock. The offset is corrected through frequency compensation and phase adjustment operations. This correction process can be applied to the digital clock synthesizer or the controllable oscillator to form a more stable local timing basis.

[0040] After completing delay compensation, frequency correction, and phase adjustment, the processing unit merges the corrected timestamp with the local timing status to generate a unified time reference value. This value serves as the initial network time for subsequent clock recovery and high-frequency counting, and includes link calibration information, delay compensation, and local calibration results. Maintaining a fixed delay during packet forwarding helps ensure stable timestamp calculation, thereby improving the reliability of the initial network time.

[0041] This embodiment combines the coarse time reference provided by the Network Time Protocol with the hardware-level time stamp of the Precision Time Protocol, and forms a unified initial network time through delay compensation, frequency correction and phase adjustment, so that the acquisition instrument can obtain a stable and reliable time reference, which facilitates maintaining cross-node consistency in subsequent synchronization recovery and fine timing stages.

[0042] S20, the processing unit in the data acquisition instrument drives the physical layer interface unit to recover the synchronous clock signal from the Ethernet physical layer signal and generate a trigger pulse signal aligned with the second boundary, and generate a second-level reference time based on the initial network time;

[0043] In this embodiment, the process by which the processing unit in the data acquisition instrument drives the physical layer interface unit to recover the synchronization clock signal from the Ethernet physical layer signal is based on the processing unit's configuration and control capabilities over the physical layer interface. The processing unit first writes initialization control information to the physical layer interface unit. This information includes an enable instruction for the clock recovery function, register loading parameters, and a link monitoring switch, enabling the physical layer interface to extract frequency components from the encoded stream when receiving Ethernet data frames. After digital decoding, the internal bitstream converter of the Ethernet physical layer signal uses the encoding characteristics to deduce the frequency characteristics of the physical layer and recover a stable clock signal. This clock signal is used to construct the subsequent timing system.

[0044] The timestamp engine in the physical layer interface performs cycle counting based on the recovered clock signal. Cycle counting captures the rising edge of the clock signal and determines the corresponding position of the second boundary by accumulating a counter. The second boundary is typically derived from the second information in the initial network time. After the processing unit loads the initial network time, the physical layer interface estimates the second boundary time based on the changing trend of the second information and outputs a trigger pulse signal at the corresponding position. The trigger pulse signal consists of fixed-width digital pulses used to establish a unified second starting point in the time system, providing a synchronization reference for different modules.

[0045] After receiving the synchronization clock signal and the trigger pulse signal, the processing unit generates a second-level reference time by combining the timing relationship between these two signals with the initial network time value. The generation process of the second-level reference time includes mapping the second count in the initial network time to the time position of the trigger pulse, incorporating the time advance rate provided by the synchronization clock signal into the calculation, and constructing a continuous time expression structure spanning multiple seconds using a digital representation. The second-level reference time provides a unified time starting point for subsequent high-frequency counting, and its structure includes second count information, cross-second status indicators, and displacement parameters associated with the synchronization clock frequency.

[0046] This embodiment utilizes physical layer signals to restore the synchronous clock and establishes a unified second boundary with trigger pulses. Then, it combines the initial network time to generate a continuous and unified second-level reference time, enabling the time system to have an accurate starting point and a stable advance rate. This provides a reliable foundation for subsequent nanosecond-level timing and achieves time consistency in cross-node environments.

[0047] S30, using the trigger pulse signal as a reset signal and the synchronization clock signal as a counting drive source, high-frequency counting accumulation is performed based on the second-level reference time to generate nanosecond-level fine time;

[0048] In this embodiment, the trigger pulse signal is used as a reset signal because the physical layer interface unit extracts the second boundary transition from the Ethernet physical layer signal. This pulse is sent to the counting circuit in the hardware link via a synchronizer or digital trigger logic to clear the counting register structure, ensuring that the counting start point is consistent with the whole second boundary. The reset mechanism can be implemented by synchronous clearing, asynchronous clearing, or edge-triggered clearing, and is executed using a register array, digital logic, or timer internal unit depending on the hardware structure.

[0049] The synchronous clock signal, used as the counting drive source, utilizes a continuous high-frequency beat recovered from the physical layer. This beat, stabilized by a clock tree or phase-locked loop, is input to the clock terminal of the counting circuit. Each transition edge triggers the count accumulation, causing the offset within seconds to increase at a fixed frequency. The counting logic can be implemented in a synchronous counter, timer channel, or on-chip counting module of the FPGA, each structure guaranteeing monotonically increasing characteristics at high frequencies.

[0050] High-frequency counting accumulation based on a second-level reference time involves establishing a mapping relationship between coarse-grained time and second-level offsets. The second-level reference time is determined by a combination of the initial network time and second-level boundary trigger events, providing an integer time reference for subsequent counting. The count value, as an offset, needs to undergo overflow detection and register update logic processing, and is converted to nanosecond units based on the synchronization clock frequency.

[0051] The process of generating nanosecond-level fine time combines the second-level reference time with the converted offset into a unified format, for example, storing the second value in the high-order bits and the nanosecond offset in the low-order bits. The time field can use a 64-bit or higher bit width, and the combination is completed by hardware or software according to a unified rule. The final time is recorded in the data output path to mark the acquisition timing. The above links form a continuous chain: the trigger pulse defines the starting point, the synchronization clock provides the stepping clock, the high-frequency counter generates the offset, and the second-level reference time and the offset are combined to obtain the nanosecond-level time.

[0052] This embodiment achieves stable nanosecond-level time recording capability by aligning trigger pulses to integer seconds, generating high-frequency offsets with a synchronization clock, and accumulating these offsets on a second-level reference time. This enables consistent time reference across devices. The system maintains high accuracy and consistency under different networks, hardware architectures, and sampling conditions, meeting the requirements of high-speed data acquisition for precise time stamping.

[0053] S40, Receive sampling rate configuration parameters, and perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameters to obtain a sampling drive clock;

[0054] In this embodiment, receiving the sampling rate configuration parameter involves inputting a digital configuration value provided by an external control unit or internal strategy module into the processing unit. This configuration value is used to limit the target sampling rate. The sampling rate configuration parameter typically exists as a register value, a communication message field, a configuration file parameter, or is dynamically passed at runtime. Its source can be a host scheduling system, sensor driver logic, or task configuration module. After entering the processing unit, the sampling rate configuration parameter needs to undergo validity verification, such as range judgment, data bit width judgment, or boundary restriction processing, to avoid exceeding the hardware counting capacity or generating sampling periods that cannot meet synchronization requirements.

[0055] The synchronization clock signal, serving as the clock source to be divided, has its frequency output by the physical layer recovery circuit or stabilized by a phase-locked loop, forming the high-frequency basis of the entire acquisition system. This clock is typically significantly higher than the target sampling rate, therefore it must be reduced to the sampling drive clock used to control the instantaneous sampling. The input edge of the synchronization clock signal enters the frequency division calculation logic after passing through the input synchronization module, used to maintain phase stability and counting continuity.

[0056] The process of frequency division based on the sampling rate configuration parameter essentially maps the sampling rate to an integer or approximately integer multiple of the synchronous clock frequency. To achieve this relationship, the processing unit calculates the division coefficient based on the ratio of the synchronous clock frequency to the sampling rate configuration parameter and stores it in a hardware register or internal cache. The division coefficient determines the counting endpoint of the frequency divider counter. When the counter reaches its endpoint value, it is reset to zero, and a sampling drive pulse is output. The calculated division coefficient can be used as the direct counting endpoint in the hardware, or it can be processed by correction logic to reduce errors caused by clock frequency offsets or sampling rate changes.

[0057] The process of obtaining the sampling drive clock relies on a frequency divider counter continuously counting the synchronous clock signal. Each synchronous clock edge triggers the counter to increment, and when the counter reaches the value specified by the frequency division factor, a sampling drive edge is generated and the counter is reset. The sampling drive clock can be in pulse form, a square wave with a controllable duty cycle, or a trigger signal type defined by the downstream sampling module. The generation of the sampling drive clock needs to ensure periodic stability, phase continuity, and precise edges so that subsequent sampling actions can be accurately correlated with nanosecond-level fine timing.

[0058] This embodiment achieves a stable relationship between the adjustable sampling rate and the high-frequency synchronous clock by mapping the sampling rate configuration parameter to the frequency division of the synchronous clock signal, ensuring that the acquisition action remains synchronized with the time system. This mechanism makes the sampling period configurable and consistent with the time reference, avoiding sampling offset caused by clock drift or frequency mismatch.

[0059] S50, at the effective transition edge of the sampling drive clock, the sampling action is executed by controlling the analog-to-digital conversion unit, and the nanosecond-level fine time is latched to generate a sampling timestamp, and the sampling data is combined with the sampling timestamp for output.

[0060] In this embodiment, the effective transition edge of the sampling drive clock is the timing reference for triggering the sampling action. This transition edge typically originates from the sampling drive clock generated in the previous stage and can be either a rising edge or a falling edge, the specific form of which is determined by the hardware configuration. The effective transition edge represents a unique marker of the sampling instant; therefore, it needs to pass through an edge detection module before entering the sampling control circuit to convert continuous high and low levels into discrete transition events, ensuring that the input signal does not generate multiple erroneous triggers due to jitter.

[0061] After the valid transition edge of the sampling drive clock occurs, the sampling control circuit sends a sampling action command to the analog-to-digital converter (ADC). The sampling action is the process by which the ADC obtains the instantaneous voltage from the analog input channel and performs quantization. This quantization process can rely on a sample-and-hold circuit or an internal sampling network to obtain a stable input signal, which is then fed into a comparator array or successive approximation module for digitization. After the sampling action is completed, the raw sampled data is output and written to the data path's buffer structure, awaiting timestamp binding.

[0062] Nanosecond-level fine-grained time is generated by a high-frequency counting link, and its value is latched at the sampling moment using a timestamp latch. The latching process synchronously captures the current nanosecond-level fine-grained time into a fixed register structure, ensuring that the time information generated during sampling does not change as the counter continues to accumulate. This latching behavior guarantees a one-to-one correspondence between sampled data and time information and avoids time drift caused by processing delays.

[0063] The sampling timestamp generation process includes format conversion, transforming the latched nanosecond-level fine-grained time into a unified time expression format used by the system. This could be achieved by using the high-order bits for seconds and the low-order bits for nanosecond offsets, or by employing a fixed-length binary time field. The generated sampling timestamps are absolute and alignable, allowing for cross-device comparison with timestamps from other nodes.

[0064] The combined output of sampled data and sampling timestamps binds these two types of information together to form a transmittable data structure. This binding operation can be achieved through parallel concatenation, structured encapsulation, or circular buffer writing, ensuring that the collected data possesses complete temporal attributes before entering the transmission channel. The final product of the combined output is organized into a sampled data packet, containing sampled values, sampling timestamps, and necessary identification fields for subsequent channel identification.

[0065] This embodiment achieves fully synchronized acquisition and output of time and data by triggering the sampling action on the effective transition edge of the sampling drive clock and simultaneously latching nanosecond-level fine time. This mechanism ensures that the sampling point strictly corresponds to the time base, avoiding errors caused by sampling action delays or time latch offsets.

[0066] In one embodiment, step S10 above includes:

[0067] S101, the data acquisition instrument receives the Ethernet power supply signal through the Ethernet interface, and the power management unit converts the Ethernet power supply signal to generate the working voltage, and uses the working voltage to put the data acquisition instrument into the ready-to-work state.

[0068] S102, initiate Network Time Protocol service through central control device and send time synchronization request to network switch, and obtain coarse time reference by processing time synchronization request through network switch;

[0069] S103, the processing unit in the data acquisition instrument establishes a two-way dialogue with the network switch based on the precise time protocol, and uses the coarse time reference to exchange time message requests and responses;

[0070] S104, using the network switch as an intermediary node, forwarding relevant messages of the Network Time Protocol and the Precision Time Protocol, and calculating the intermediate path delay based on the request and response exchanges of the time messages;

[0071] S105, the processing unit parses the precise time protocol message to extract timestamp information, and uses the timestamp information and the intermediate path delay to correct the frequency deviation and phase shift of the local clock, and generates corrected time data;

[0072] S106, determine the network transmission delay compensation value by measuring the round-trip time multiple times, and apply the delay compensation value to the corrected time data to generate compensated time data;

[0073] S107, the processing unit generates an initial network time by executing a time synchronization algorithm based on the compensated time data and the local clock state.

[0074] In this embodiment, when the data acquisition instrument communicates with the central control device based on the Network Time Protocol (NTP) and obtains the initial network time, it first relies on the Ethernet interface to access the wired network. The Ethernet interface serves as both a data link and can carry Ethernet power supply signals. The Ethernet power supply signal transmits DC energy and data signals at the physical layer through differential pairs. The Ethernet interface isolates the line side from the device side through transformer coupling and magnetic devices before introducing the power supply section into the power management unit. The power management unit internally includes a rectifier circuit, a DC / DC converter, voltage detection, and power-on timing control logic. It converts the input Ethernet power supply signal into multiple stable operating voltages, such as providing the digital core voltage for the processing unit, the analog voltage for the physical layer interface, and independent voltage rails for the memory and clock chip. After detecting that each voltage is within the acceptable range and remains stable, the power management unit releases the reset control of the processing unit and peripherals through reset control logic, putting the data acquisition instrument into a ready-to-work state. In this state, the processing unit has completed bootstrapping and basic peripheral initialization, but has not yet executed the synchronous acquisition task.

[0075] Central control equipment typically deploys a time service program. Within this program, a Network Time Protocol (NTP) service listens on a preset port, maintaining a high-precision local clock or synchronizing with an upstream time source. The central control equipment periodically or under external triggering constructs time synchronization request-response logic, receiving requests from multiple data acquisition instruments and filling the response message with the current time field and relevant timestamps according to the NTP format. Time synchronization requests are sent from the data acquisition instruments to the network switch, which forwards them according to its forwarding table and may queue the messages. After processing, the time synchronization request arrives at the central control equipment and is parsed by the time service program. The central control equipment generates a response message with current time information based on the request content and arrival time, which is then forwarded back to the data acquisition instruments via the network switch. The data acquisition instruments parse the response within their processing unit, comparing the time field in the message with their local received time to obtain a coarse time reference. This reference time typically achieves millisecond to sub-millisecond accuracy, providing an initial time range for subsequent high-precision synchronization and narrowing the difference between the local time and the target time to a smaller interval.

[0076] After obtaining a coarse time reference, the processing unit in the data acquisition instrument initiates the precise time protocol stack. The processing unit establishes a precise time protocol session with the network switch via sockets or raw Ethernet frames, periodically sending synchronization messages and delay measurement messages according to the protocol specifications, and receiving corresponding responses from the network switch. The coarse time reference is used to initialize the local timer, ensuring that the precise time protocol calculations are based on a timeline aligned to the second level, thereby reducing the impact of large offsets on timestamp calculations. The processing unit records its own transmission time each time a synchronization message is sent, and records its own reception time when receiving messages from the network switch. Simultaneously, it reads the peer timestamp carried in the message, forming a set of time message request and response exchange data for subsequent delay and offset calculations.

[0077] Network switches act as intermediary nodes in the entire time synchronization process. On one hand, they forward Network Time Protocol (NTP) messages to ensure the smooth operation of the coarse time reference link; on the other hand, they forward precise time protocol synchronization messages and delay measurement messages. When hardware timestamping capabilities are available, they generate high-precision timestamps when packets enter and leave the port and insert them into the packet fields. These timestamps allow the calculation of the intermediate path delay from the central control device to the data acquisition instrument. The intermediate path delay calculation is typically based on the uplink and downlink time differences and symmetry assumptions. The processing unit combines the timestamps from the sending and receiving directions to calculate the link propagation time and queuing time components, thereby distinguishing the propagation delay introduced by the network from the local clock offset.

[0078] After receiving the time message and intermediate path delay, the processing unit performs in-depth analysis of the precise time protocol message. The precise time protocol message contains multiple timestamp fields, such as the peer's sending time, the local receiving time, the local sending delay request time, and the peer receiving delay request time. The processing unit substitutes these timestamps and intermediate path delays into the clock skew calculation model. In this model, the difference between the local clock reading and the reference clock reading can be decomposed into frequency deviation and phase offset. The frequency deviation corresponds to the proportional error between the local oscillator frequency and the target frequency, which can be compensated for by adjusting the digital time base counting step or controlling the control word of the programmable oscillator. The phase offset corresponds to the instantaneous difference between the two time readings at the current moment, which can be corrected through one-time offset correction or segmented gradual alignment. The processing unit periodically updates the frequency and phase parameters in the control loop to form corrected time data. The corrected time data, reflected on the time axis, has removed most of the static deviation and single propagation error.

[0079] In dynamic network environments, link queuing delays and switching processing delays fluctuate with load changes. To further mitigate this impact, the processing unit performs multiple round-trip time (RTT) measurements. Each RTT measurement involves sending a set of precise time protocol request messages and waiting for corresponding responses. Upon arrival, the single RTT is calculated using the send and receive timestamps. The series of RTT values ​​obtained from multiple measurements can be processed statistically, such as using sliding window averaging, weighted averaging, median filtering, or robust statistical methods that exclude outliers, to determine the network transmission delay compensation value. The network transmission delay compensation value reflects the average propagation characteristics of the link over a given period and can offset some of the deviations caused by short-term congestion or queuing jitter. The processing unit applies the network transmission delay compensation value to the previously obtained corrected time data, further correcting the dynamic errors of the propagation path on the time axis to obtain the compensated time data.

[0080] The compensated time data needs further processing in conjunction with the local clock state. The local clock state can include the frequency stability of the local oscillator, temperature drift estimation, historical deviation statistics, and current lock-in status. In the time synchronization algorithm, the processing unit uses the compensated time data as an external reference and the local clock state as a control constraint, achieving time convergence through discrete-time control laws, phase-locked loop structures, or digital filter structures. The algorithm can introduce a limiting slope for the time deviation to prevent excessive time jumps from causing anomalies in upper-layer services. It can also dynamically adjust the convergence speed based on the local clock quality, relaxing the correction frequency under high-quality oscillator conditions and increasing the correction frequency under low-quality oscillator conditions. Through continuous iterative adjustments, the local clock gradually converges to the compensated time data, reaching a steady-state deviation within a preset threshold. In this state, the time reading given by the processing unit is the initial network time, which is used as a unified time reference for subsequent second-level reference time generation, high-frequency counting accumulation, and sampling timestamp generation.

[0081] This embodiment utilizes a time acquisition mechanism that combines the aforementioned network time protocol and precise time protocol. After power-on, the data acquisition instrument first uses the Ethernet power supply signal and power management unit to quickly enter a stable preparation state. Then, it obtains a coarse time reference in a short time through the network time protocol, allowing the local time axis to quickly fall into the vicinity of the target time. Based on this, it exchanges time messages bidirectionally with the network switch through the precise time protocol. It uses timestamp information and intermediate path delay to separate and correct the local clock frequency deviation and phase offset. At the same time, it estimates the network transmission delay compensation value through multiple round-trip time measurements and applies it to the corrected time data. Then, it combines the local clock state to execute a time synchronization algorithm to generate the initial network time. Thus, even under conditions of network jitter and link delay fluctuations, it can still obtain a high-precision, stable initial network time that is consistent with the central control equipment. This provides a reliable time reference for subsequent second-level reference time generation and nanosecond-level fine time calculation, improving the synchronization accuracy and robustness of the distributed synchronous acquisition system in multi-node scenarios.

[0082] In one embodiment, step S20 above includes:

[0083] S201, the processing unit in the data acquisition instrument sends a configuration command to the physical layer interface unit to start the clock recovery function;

[0084] S202, extract clock information from the Ethernet physical layer signal through the physical layer interface unit, and generate a synchronization clock signal based on the clock information;

[0085] S203, the time stamp engine in the physical layer interface unit monitors the period count of the synchronization clock signal and generates a trigger pulse signal aligned with the second boundary at the corresponding time of the second boundary;

[0086] S204, the processing unit receives the synchronization clock signal and the trigger pulse signal;

[0087] S205, the processing unit performs clock synchronization calculations to generate synchronization time data based on the initial network time, the synchronization clock signal, and the trigger pulse signal;

[0088] S206, the processing unit applies frequency calibration and phase adjustment algorithms to process the synchronization time data to generate a second-level reference time.

[0089] In this embodiment, when the processing unit in the data acquisition instrument drives the physical layer interface unit to recover the synchronization clock signal from the Ethernet physical layer signal, the processing unit first needs to issue a configuration command to activate the clock recovery function inside the physical layer interface unit. The configuration command is typically written to registers via the management interface. The processing unit determines whether the physical layer interface unit has completed power-on self-test, link establishment, and baseband initialization based on its internal state machine. After the configuration command takes effect, the physical layer interface unit enters the clock recovery state. In this state, symbol boundaries are extracted based on the voltage transition characteristics of the Ethernet differential signal, and a stable sampling clock is constructed using a phase-locked loop and a clock recovery circuit. The source of the clock recovery function relies on the embedded clock structure in the Ethernet physical layer protocol. The bit stream on the differential lines has sufficient transition information at the symbol level, enabling the physical layer interface to derive an accurate clock frequency without an additional independent clock.

[0090] After extracting the symbol-level time base, the physical layer interface unit generates a synchronization clock signal through frequency multiplication, phase filtering, and jitter suppression circuits. This synchronization clock signal can reach frequencies in the hundreds of megahertz range, and its stability is closely related to the frequency divider ratio, voltage-controlled oscillator characteristics, and loop bandwidth in the phase-locked loop (PLL) structure. Once the link stabilizes, the synchronization clock signal exhibits low period jitter and frequency drift, providing a reliable high-frequency drive source for subsequent time base generation.

[0091] The timestamp engine within the physical layer interface unit continuously counts while the synchronization clock signal is stable. The timestamp engine records each rising or falling edge of the clock using a periodic counting method and identifies the time corresponding to the second boundary based on the overflow pattern of the count value. The second boundary typically originates from the second field in a precise time protocol message or a calculated target time axis. After identifying the expected position of the second boundary, the timestamp engine generates a trigger pulse signal within a very small time window before and after the counter reaches that position. The generation mechanism of the trigger pulse signal involves circuit logic such as delay compensation, phase approximation control, and count overflow prediction, ensuring that the trigger pulse signal is strictly aligned with the second-level time axis.

[0092] After the processing unit outputs the synchronization clock signal and trigger pulse signal from the physical layer interface unit, it connects these signals to the internal logic module through a high-speed input channel, and performs edge detection, time capture, and signal consistency analysis. The synchronization clock signal and trigger pulse signal are integrated by the processing unit into an input sequence for time calculation. Based on these inputs, the processing unit determines the time start point, counting step size, and pulse validity, thereby constructing a reference time frame.

[0093] When the processing unit performs clock synchronization calculations by combining the initial network time, the synchronization clock signal, and the trigger pulse signal, it establishes a mapping between the second-level timescale and the synchronization clock cycle count by defining a time axis mapping relationship. The initial network time provides the absolute time reference, the trigger pulse determines the second-level boundary position, and the count increment of the synchronization clock signal constitutes the intra-second time resolution. The processing unit combines the cycle count value with the initial network time to map the cycle count to a continuous time value. The clock synchronization calculation involves time offset estimation, phase matching function, cycle continuity check, and jitter filtering to improve the stability and continuity of the intra-second time scale. Due to the extremely high frequency of the synchronization clock signal, the calculation steps must use fixed-point arithmetic and hardware acceleration structures to process the cycle count to avoid time drift caused by accumulated errors.

[0094] After the synchronization time data is generated, the processing unit applies frequency calibration and phase adjustment algorithms to further process the data. Frequency calibration addresses minute frequency deviations in the synchronization clock signal by adjusting the time accumulation rate to compensate for time drift caused by oscillator offset. The phase adjustment algorithm eliminates minute time errors caused by incomplete phase alignment of the trigger pulses. By establishing a phase adjustment factor, the synchronization time data is remapped to a more precise time axis, ensuring absolute consistency of time values ​​at second boundaries. Frequency calibration and phase adjustment typically employ digital phase-locked loops, proportional-integral regulators, or reference error feedback mechanisms to ensure the stability of the second-level reference time over long-term operation. The second-level reference time formed after frequency calibration and phase adjustment forms the foundation for subsequent nanosecond-level fine-grained time, determining the long-term consistency and cross-node synchronization of the entire distributed synchronization link.

[0095] This embodiment utilizes the aforementioned synchronous clock signal recovery and second-boundary trigger pulse generation mechanism. The data acquisition instrument, aided by the highly stable synchronous clock recovered from the physical layer, constructs a high-precision time scale for the entire system. The second-level alignment capability of the trigger pulse allows the processing unit to update the time axis at precise boundary moments, avoiding accumulated errors during second switching. Clock synchronization calculation, combining the initial network time, synchronous clock cycle count, and trigger pulse timing, ensures that the second-level reference time possesses both absolute time reference and high-frequency time resolution. Through the combined effects of frequency calibration and phase adjustment, the second-level reference time maintains high consistency across all distributed nodes in the network, providing a stable, accurate, and cross-node-consistent time foundation for subsequent nanosecond-level time accumulation and sampling timestamp generation. This significantly improves the time synchronization performance and anti-interference capability of the distributed synchronous acquisition system under complex network conditions.

[0096] In one embodiment, step S30 above includes:

[0097] S301, the rising edge of the trigger pulse signal is detected by the synchronous timer module, and the counter register is initialized;

[0098] S302, using the synchronous clock signal as the driving source, the counter register performs a counting accumulation operation on each rising edge of the synchronous clock signal to generate a count value;

[0099] S303, Read the current count value of the counter register and convert the count value into a nanosecond-level time offset;

[0100] S304, perform an arithmetic sum of the second-level reference time and the nanosecond-level time offset to generate an unverified nanosecond-level fine time;

[0101] S305, monitor abnormal situations during the counting and accumulation operation, perform validity checks on the unverified nanosecond-level fine time, and generate a verified nanosecond-level fine time.

[0102] In this embodiment, when the trigger pulse signal is used as a reset signal, the synchronous timer module first needs to detect the rising edge of the trigger pulse signal. The trigger pulse signal originates from the preceding second-level pulse generation logic, whose level transition characteristics can exhibit stable edge characteristics at the second level of the time axis. The synchronous timer module typically captures this rising edge through an edge detection circuit. The edge detection circuit uses an asynchronous synchronous flip-flop link and dedicated comparison logic to avoid errors introduced by metastability, and immediately executes the internal reset path after detecting the rising edge. The reset path initializes the counter register, clearing the register or setting it to a defined starting value, so that the time counting restarts from a uniform second-level boundary.

[0103] After initialization, the counter register performs high-frequency counting and accumulation driven by the synchronous clock signal. The frequency of the synchronous clock signal is typically in the range of tens to hundreds of megahertz, and its stability depends on the physical layer recovery mechanism and subsequent filtering processing. The counter register triggers the accumulation logic on each rising edge of the synchronous clock signal, ensuring that the count value increases strictly according to the period of the synchronous clock signal. The accumulation process is performed by a hardware fixed-point adder, guaranteeing a definite time accuracy even at high frequencies. The counter bit width is usually selected during the system design phase, covering the required counting range within a second-level time period.

[0104] During the counting process, the current count value of the counter register needs to be read periodically and converted into a nanosecond-level time offset. This conversion is achieved by multiplying the count value by the period of the synchronization clock signal or by mapping it to a table. The period of the synchronization clock signal is determined by the preceding recovery mechanism; for example, if the synchronization clock signal frequency is 125MHz, each counting step corresponds to approximately 8 nanoseconds. The conversion circuit maps the count value to a time offset using a multiplier or a hardware logic table, enabling the periodic counting to directly reflect the actual nanosecond-level time position within a second-level time interval.

[0105] The arithmetic addition of a second-level reference time and a nanosecond-level time offset constitutes an unverified nanosecond-level fine-grained time. The second-level reference time provides an absolute second-level starting point, while the nanosecond-level time offset provides high-resolution subdivision within seconds. These two are combined using an additive mapping method to form a continuous time axis. The addition operation is generally based on a fixed-point format to reduce numerical jitter, and the introduced time values ​​must satisfy cross-cycle continuity checks to avoid time jumps caused by counter update lag or jitter.

[0106] To ensure the reliability of nanosecond-level fine-grained time, anomalies during the high-frequency counting and accumulation process need to be continuously monitored. Anomalies include loss of synchronization clock signal, abnormal trigger pulse jitter, counter register overflow, and count jumps that do not conform to period continuity. The monitoring module identifies anomalies based on logic comparators, period prediction models, and high-speed sampling feedback mechanisms. If behavior inconsistent with the expected timeline is detected, the unverified nanosecond-level fine-grained time needs to be investigated. A consensus algorithm is used to verify whether the time value forms a continuous sequence with the second-level reference time, period count, and preceding and following time segments. Verified nanosecond-level fine-grained time is generated after completing the above consistency checks and can be used by the subsequent sampling timestamp module. The verification process combines edge time prediction, counter step size comparison, and adjacent time difference verification mechanisms to ensure the reliability of the time value under both static and dynamic conditions.

[0107] This embodiment constructs a high-frequency counting link using trigger pulses and a synchronization clock, enabling time counting to form a continuous, stable time scale with nanosecond-level resolution based on a second-level reference time. Edge detection and counter initialization ensure the consistency of the time starting point for each second boundary, high-frequency accumulation ensures sufficient time resolution within seconds, and the count value conversion mechanism provides nanosecond-level time accuracy. Anomaly monitoring and time verification mechanisms further ensure reliable time output even under electromagnetic interference, link jitter, or transient anomalies.

[0108] In one embodiment, step S40 above includes:

[0109] S401 receives sampling rate configuration parameters from the central control device via the configuration interface;

[0110] S402, calculate the frequency division coefficient based on the sampling rate configuration parameters and the frequency of the synchronization clock signal;

[0111] S403, Use the frequency division coefficient to configure the operating parameters of the programmable frequency divider;

[0112] S404, The synchronous clock signal is divided into integers by the programmable frequency divider to generate a divided clock signal;

[0113] S405, optimize the duty cycle of the frequency-divided clock signal to generate an optimized clock signal;

[0114] S406, Real-time monitoring of the stability of the optimized clock signal, and generation of a verified sampling drive clock;

[0115] S407, the verified sampling drive clock is distributed to each data acquisition channel.

[0116] In this embodiment, when the sampling rate configuration parameter is received through the configuration interface, it is necessary to ensure that the configuration interface can stably transmit numerical parameters. The configuration interface is typically implemented based on a serial connection, Ethernet management channel, or field-programmable communication link, and includes an input buffer, parameter parsing module, and data verification circuitry in hardware. The sampling rate configuration parameter is essentially a control parameter defining the sampling period or sampling frequency. Its source is the operation and management logic of the central control device, and it carries necessary identification and verification fields during transmission to ensure accurate parsing by the device being acquired. After receiving this parameter, the processing unit checks the numerical range, format, and sampling system capabilities to confirm that a reasonable frequency division relationship can be formed between the sampling rate and the synchronous clock signal frequency.

[0117] The frequency division factor is calculated based on the sampling rate configuration parameter and the synchronization clock signal frequency. The synchronization clock signal frequency is typically 125 MHz, 156.25 MHz, or other high-frequency stable clocks recovered by the physical layer. The calculation process relies on a fixed-point arithmetic unit or embedded multipliers and dividers to generate the frequency division factor suitable for the frequency divider control through integer division, proportional conversion, or fixed coefficient mapping. The calculation module needs to consider the integer ratio or approximate ratio between the target output frequency corresponding to the sampling rate parameter and the synchronization clock signal frequency, and determine whether fractional frequency division compensation is needed based on different hardware architectures. After the calculation is completed, the frequency division factor is sent to the configuration path of the programmable frequency divider via registers.

[0118] The operating parameters of a programmable frequency divider are determined by the division factor. A programmable frequency divider typically includes multiple control registers, an internal logic counter link, and a clock output buffer structure. Its function is to determine, based on the division factor, how many clock cycles the synchronous clock signal needs to be divided into before outputting a complete sampling drive pulse. The configuration process includes parameter writing, register updating, division mode latching, and output clock stability detection to ensure the divider enters an output state consistent with the calculated parameters. During operation, the programmable frequency divider strictly generates new clock signals cyclically according to its internal counter, ensuring the sampling drive clock maintains frequency consistency with the sampling rate configuration parameters.

[0119] After the synchronous clock signal undergoes integer division in the frequency divider, it generates a lower-frequency clock signal with a period consistent with the sampling rate. This signal requires a clearly defined high-level duration and low-level duration in its timing structure. However, the duty cycle of the initial division result may not meet the timing requirements of the sampling circuit, thus requiring further duty cycle optimization. Duty cycle optimization is achieved through pulse width adjustment circuits, asymmetric gating logic, or duty cycle calibration modules, so that the output clock forms a waveform structure between high and low levels that is more suitable for analog front-end sampling circuits, digital input circuits, or analog-to-digital converter drivers, reducing clock distortion and overshoot.

[0120] The optimized clock signal needs to undergo stability monitoring before being used as the sampling drive clock. Stability monitoring includes frequency stability analysis, duty cycle continuity assessment, adjacent cycle consistency detection, and clock edge jitter analysis. The monitoring module acquires clock parameters for consecutive cycles using a time base meter or clock quality detection circuit, compares them with expected values, and determines whether there are sudden drifts, irregular edge transitions, or duty cycle instability. Stability monitoring ensures that the clock meets the time accuracy requirements of the sampling system, thus forming a verified sampling drive clock.

[0121] The validated sampling drive clock needs to be distributed to multiple data acquisition channels. The distribution link typically relies on clock tree structures, low phase noise clock buffers, or fan-out stage driver circuits to output the same clock source to multiple sampling units with the same delay path. During the distribution process, inter-channel delay differences, fan-out load capacity, electromagnetic interference suppression, and timing matching issues of cable or PCB traces must be considered.

[0122] This embodiment achieves high stability of the sampling drive clock by analyzing sampling rate configuration parameters, calculating frequency division coefficients, configuring programmable frequency dividers, optimizing clock duty cycles, monitoring clock stability, and finally distributing the clock. The sampling drive clock generated by frequency division of the synchronous clock signal meets the requirements of the sampling system in terms of frequency, waveform, and phase characteristics, thus ensuring time consistency across the acquisition channels.

[0123] In one embodiment, step S402 includes:

[0124] S4021, The parameter verification module checks the rationality and validity of the sampling rate configuration parameters and generates valid sampling rate parameters;

[0125] S4022, the frequency division ratio calculation unit performs an integer division operation based on the effective sampling rate parameter and the frequency of the synchronous clock signal to generate the basic frequency division ratio;

[0126] S4023, Calculate the fractional frequency division compensation value based on the basic frequency division ratio;

[0127] S4024, using the basic frequency division ratio and the fractional frequency division compensation value, the basic frequency division ratio and the fractional frequency division compensation value are added together by addition to generate the frequency division coefficient.

[0128] In this embodiment, the sampling rate configuration parameter describes the desired sampling frequency or sampling period, generally expressed in Hertz or time intervals. It is generated by the central control device based on the bandwidth requirements, signal spectrum characteristics, and data throughput capabilities of the application scenario, and transmitted to the data acquisition side via the communication channel. The synchronization clock signal frequency originates from the physical layer clock recovery circuit and serves as the time reference for the entire acquisition system. In an Ethernet environment, it is typically a fixed high-frequency clock, such as 125MHz or 156.25MHz. After receiving the sampling rate configuration parameter, the parameter verification module performs format checks, value range checks, and hardware resource matching checks on the parameter based on the preset allowed sampling rate range, the upper limit of integer division capability, the highest sampling frequency supported by the analog-to-digital converter, and the relationship between the synchronization clock signal frequency and the sampling rate. For example, when the synchronization clock signal frequency is 125MHz, the parameter verification module determines whether the sampling rate configuration parameter can be obtained through integer division or division with decimal compensation, which can be analyzed through table lookup, interval judgment, or inequality constraints. After successful verification, valid sampling rate parameters are generated, and illegal parameters are marked as errors, thus blocking subsequent frequency division calculations.

[0129] The frequency division ratio calculation unit takes the effective sampling rate parameter and the synchronous clock signal frequency as input and generates the basic frequency division ratio through integer division. The integer division operation can be implemented by a hardware divider, a shift-add structure, or lookup table logic. Its calculation objective is to determine how many synchronous clock signal cycles are needed to output a sampling drive pulse. The basic frequency division ratio is an integer value, representing an approximation of the ideal sampling frequency under the condition of considering only integer frequency division constraints. In practical applications, the synchronous clock signal frequency and the target sampling rate are not necessarily strictly integer multiples, therefore using only integer frequency division will introduce frequency errors. To reduce this error, a fractional frequency division compensation value needs to be introduced. The fractional frequency division compensation value is calculated based on the residual between the basic frequency division ratio and the target sampling rate. It can be obtained by comparing the target sampling frequency with the actual sampling frequency obtained from the basic frequency division ratio, and the deviation is converted into a compensation parameter suitable for clock modulation or period interpolation. The compensation value can correspond to a fixed-length period interpolation table or the increment value in a fractional frequency division accumulator, used to equalize the sampling frequency over a long time scale, making the average sampling rate approach the target sampling rate.

[0130] The frequency division factor is obtained by combining the base division ratio and the fractional division compensation value through addition. This addition is not limited to simple numerical summation but also includes a cycle-by-cycle accumulation process within the hardware structure. The base division ratio defines the main division rhythm of the counter, while the fractional division compensation value periodically changes the output interval through an accumulation register or phase accumulator, thereby adjusting the actual output frequency over multiple division cycles. The frequency division factor can be represented as a comprehensive control parameter containing both integer and fractional parts, which is then passed to the control unit in a programmable frequency divider or digital phase-locked loop.

[0131] This embodiment introduces a parameter verification module, a frequency division ratio calculation unit, and a fractional frequency division compensation calculation mechanism, using the frequency division coefficient as a unified control parameter. It refines the relationship between the sampling rate configuration parameter and the synchronization clock signal frequency into a combination of an integer frequency division part and a fractional compensation part. While ensuring the sampling rate remains within the hardware's supported range, it reduces the frequency deviation between the synchronization clock signal frequency and the target sampling rate. This makes the sampling drive clock closer to the desired sampling rate during long-term operation, thereby improving the consistency and frequency accuracy of the sampling time interval. This provides a stable and reliable time foundation for subsequent high-precision synchronous acquisition and cross-node data alignment.

[0132] In one embodiment, step S50 above includes:

[0133] S501, the sampling control circuit detects the valid transition edge of the sampling drive clock and generates a sampling trigger signal;

[0134] S502, under the control of the sampling trigger signal, performs analog-to-digital conversion on the analog input signal through the analog-to-digital conversion unit to generate raw sampling data;

[0135] S503, the nanosecond-level fine time is latched at the valid moment of the sampling trigger signal by the timestamp latch to generate the original timestamp;

[0136] S504, the original sampling data is stored in a data buffer to generate buffered sampling data;

[0137] S505, convert the original timestamp into a standard format sampling timestamp, bind the buffered sampling data with the standard format sampling timestamp, and generate sampling data with sampling timestamp;

[0138] S506, verify the correct correlation of the sampled data with sampling timestamp, generate a verified sampling data packet, and output the verified sampling data packet to the data transmission channel.

[0139] In this embodiment, the effective transition edge of the sampling drive clock refers to the level transition boundary selected as the trigger reference in the sampling drive clock waveform. It can be a rising edge transitioning from a low level to a high level or a falling edge transitioning from a high level to a low level, selected by the configuration register or control instruction during the system initialization phase. The sampling control circuit receives the sampling drive clock signal, continuously reads the clock waveform through the edge detection unit, identifies the level change point by comparing the previous sample value with the current sample value, and immediately pulls up or flips a short pulse signal in the internal trigger logic when a pre-set effective transition edge is matched. This short pulse is the sampling trigger signal. The sampling trigger signal closely follows the effective transition edge of the sampling drive clock in time and is distributed to the analog-to-digital conversion unit and the timestamp latch through the synchronous trigger path, so that both refer to the same trigger event at the same time.

[0140] After receiving the sampling trigger signal, the analog-to-digital converter (ADC) performs sample-and-hold and quantization conversion on the analog input signal during the valid period of the trigger signal. The front-end sample-and-hold circuit locks the instantaneous value of the analog input signal onto the sampling capacitor when the trigger arrives. Subsequently, the internal comparator array or successive approximation structure divides the level intervals step by step according to the reference voltage, mapping the analog amplitude to the corresponding digital code to form the raw sampled data. The raw sampled data can use a fixed word width format, such as 16-bit or 24-bit, and is output on the local bus according to the channel number and sampling order. To ensure consistency between the sampling time and the timestamp, the trigger terminal of the ADC and the sampling trigger signal generated by the sampling control circuit maintain a single source, avoiding additional gating or logic retiring.

[0141] The timestamp latch and sampling control circuit maintain time alignment by sharing the same sampling trigger signal. At the boundary moment when the sampling trigger signal is valid, the timestamp latch reads the current nanosecond-level fine time from the high-precision timing link, combines the second-level reference part of the counter output with the nanosecond offset part into a complete time value, and writes it to the latch register at once. The latched data remains unchanged during subsequent data packaging and output processes, preventing time drift caused by continued counting. The value written to the latch register is the original timestamp, which can be stored internally using second and nanosecond fields in groups, or using a uniform fixed-width binary count value.

[0142] The data buffer, located between the analog-to-digital conversion unit output and the packing logic, receives raw sampled data and forms a sequential queue in local storage. The data buffer can employ a dual-port RAM, a circular buffer, or a FIFO structure. On the write end, raw sampled data is written sequentially according to the sampling trigger order; on the read end, buffered sampled data is output in chronological order. The buffering mechanism absorbs the data rate difference between the sampling and data transmission sides, ensuring that sampling points are not lost during subsequent timestamp binding and integrity verification, and preventing the sampling order from being disrupted by momentary bus congestion. The buffered sampled data internally includes an address index or sequence count value, facilitating a one-to-one correspondence with the corresponding timestamp record.

[0143] After being latched, the raw timestamp enters the format conversion path, during which the internal count representation is converted into a standard format sampled timestamp. The standard format sampled timestamp can use an encoding method consistent with the network time synchronization system; for example, the integer second field uses an unsigned integer to represent the cumulative number of seconds since the start time, and the nanosecond field uses a fixed-width integer to represent the nanosecond offset within the current second. Alternatively, it can use a unified 64-bit or 96-bit extended time encoding to meet the wide-range time representation requirements of long-running scenarios. During the format conversion process, the system performs carry normalization on the second and nanosecond fields to avoid nanosecond field overflow or encoding inconsistencies, resulting in a sampled time reference that can be directly used for cross-node alignment and protocol interaction.

[0144] Sampling data with sampling timestamps is generated through a binding process. The binding logic reads the buffered sampling data from the data buffer and simultaneously reads the standard format sampling timestamp from the timestamp format conversion path. Based on the sequential index or internal tag of the sampling trigger event, it combines a single sample value with its corresponding timestamp into a record. The combination method can use a structured field arrangement, such as including channel identifier, sampling sequence number, sample value, and sampling timestamp in a single record, or it can use a binary frame structure, placing the timestamp field in the frame header and the sample data array in the frame body. After binding, the resulting sampling data with sampling timestamps retains the original sample values ​​while adding precise time information.

[0145] The correlation verification process checks the sampled data with sampling timestamps and generates sampling data packets. The verification logic can perform monotonicity checks on continuously recorded sampling timestamps, verifying whether the time strictly increases according to the sampling order or meets the expected sampling interval range. It can also verify the mapping relationship between channel identifiers and sampling timestamps to prevent time overlap errors between different channels. Furthermore, it can perform cross-comparisons with sampling trigger counts, data buffer depths, and local counter values ​​to confirm that each trigger event generates a corresponding sampling record and timestamp record. The verified data is reorganized into sampling data packets, with frame sequence numbers, channel set identifiers, and brief verification fields added to the header to facilitate further link verification on the data transmission channel. After successful verification, the sampling data packets are output through the data transmission channel, which can be an Ethernet interface, a high-speed serial interface, or a backplane bus interface. During transmission, the boundaries of the sampling data packets are maintained, providing a clearly structured input for upper-layer time alignment and cross-node analysis.

[0146] Example Description: In a distributed synchronous data acquisition scenario, a central PC, PoE & PTP switches, and multiple data acquisition instruments are physically interconnected via Ethernet. Each data acquisition instrument includes an RJ45 interface, a PHY chip supporting synchronous Ethernet and the IEEE 1588 protocol, a power supply unit, a SoC chip with embedded ARM and FPGA, and an ADC unit. These components together constitute the time synchronization link, clock generation link, and data acquisition link of the acquisition device. The embedded ARM provides data pass-through, PTP service, and timed triggering service functions. The FPGA internally implements a synchronization timer module, a sampling clock generation module, a data acquisition module, and a data processing module, undertaking key logic in the subsequent synchronization and acquisition process.

[0147] After system startup, the data acquisition instrument first receives the Ethernet power supply signal via the RJ45 interface. This signal travels through the network cable to the acquisition device, where the power management unit converts it into operating voltage, putting the acquisition device into a ready-to-work state. Subsequently, the PC control unit initiates a Network Time Protocol (NTP) service to the PoE & PTP switch. The switch obtains a coarse time reference based on the PC's time synchronization request; this coarse time is used as the initial time parameter for subsequent precise time protocol interactions. The processing unit within the data acquisition instrument, specifically the embedded ARM, establishes a two-way dialogue with the switch via the precise time protocol, executing a complete time message interaction process including request and response messages. The switch, acting as an intermediary node, forwards NTP and precise time protocol related messages, creating a round-trip path between the PC, switch, and acquisition device. The processing unit calculates the intermediate path delay based on the delay variation between the round-trip messages. The processing unit extracts timestamp information from the precise time protocol messages and, combined with the intermediate path delay, corrects the frequency deviation and phase offset of the local clock to obtain corrected time data. Through multiple round-trip time measurements, the processing unit further determines the network transmission delay compensation value and applies this compensation to the corrected time data, thereby generating compensated time data. Based on the compensated time data, the processing unit combines the local clock state to execute a time synchronization algorithm to obtain the initial network time, which is the starting point for all subsequent time calculations of the system.

[0148] After acquiring the initial network time, the data acquisition instrument internally drives the physical layer interface unit (PHY chip) through the processing unit to initiate the clock recovery function. This extracts the frequency information for synchronization from the Ethernet PHY signal and regenerates the synchronization clock signal Sync_clk. The timestamp engine within the PHY unit monitors the period count of the synchronization clock signal and outputs a trigger pulse signal aligned with the second boundary when it detects the corresponding second boundary. This generates a pulse at the precise moment of the second transition. After receiving the synchronization clock signal and the trigger pulse signal, the processing unit uses the initial network time as a reference and combines it with the two timing signals to perform clock synchronization calculations. Through frequency calibration and phase adjustment, it generates a second-level reference time, providing a stable second-level reference for subsequent nanosecond-level precise time calculations.

[0149] After obtaining the second-level reference time, the synchronous timer module in the FPGA begins running a counting process driven by a trigger pulse signal. The effective rising edge of the trigger pulse signal acts as a reset signal, clearing the counter register to zero at the second boundary. The synchronous clock signal, Sync_clk, serves as the driving source, triggering a counting accumulation operation on each rising edge, causing the count value to continuously increase, equivalent to a nanosecond-level time offset. When the count value recorded in the counter register is read, it is converted into a nanosecond-level time offset and arithmetically superimposed with the second-level reference time to generate an unverified nanosecond-level fine time. The synchronous timer module performs anomaly monitoring on this fine time, including the integrity of the count transitions, the continuity of the synchronous clock, and the consistency of the trigger boundary. When the verification passes, it outputs the nanosecond-level fine time as a time reference for subsequent sampling timestamp latching.

[0150] Once the high-precision time link is stable, the processing unit receives the sampling rate configuration parameters from the central control device. The parameter verification module checks the numerical range, resolution, and compatibility with the current synchronization clock signal frequency of the sampling rate parameters to obtain the effective sampling rate parameters. The frequency division ratio calculation unit performs integer division with the synchronization clock signal frequency based on the effective sampling rate parameters to obtain the basic frequency division ratio. Simultaneously, it calculates the fractional frequency division compensation value and adds the two to generate the frequency division coefficient. The frequency division coefficient is written into the programmable frequency divider, causing it to operate according to the coefficient and perform integer frequency division on the synchronization clock signal. The frequency-divided clock signal undergoes duty cycle optimization circuitry to adjust waveform symmetry and edge stability. After stability testing, a sampling drive clock is generated. The sampling drive clock is distributed to each acquisition channel within the data acquisition instrument, enabling all channels to perform sampling based on a unified time reference.

[0151] After the sampling drive clock Samp_clk is stably output, the sampling control circuit generates a sampling trigger signal when a valid edge is detected on the valid transition edge of Samp_clk. This triggers the analog-to-digital converter (ADC) to perform analog-to-digital conversion on the analog input signal, generating the raw sampled data. The timestamp latch synchronously latches nanosecond-level fine-grained time at the valid moment of the sampling trigger signal, forming the raw timestamp. The data buffer temporarily stores the sampled data, allowing the data stream to automatically adapt to subsequent binding processes. The raw timestamp is converted to a standard format sampling timestamp and bound to the buffered sampled data, forming a data structure with timestamps. The system performs correlation verification to ensure that each sampling timestamp corresponds one-to-one with the sampled data and that the time link is continuous. Verified data is assembled into a sampling data packet and output to the data transmission channel.

[0152] Ultimately, the host computer software arranges the time series of multiple acquisition nodes in a unified manner based on the nanosecond-level fine time in the sampling data packet, realizing synchronous acquisition between multiple nodes with nanosecond-level precision. This enables the distributed acquisition system to obtain consistent time stamping capabilities across nodes in scenarios such as vibration monitoring, underwater acoustic detection, and ultra-high-speed industrial detection.

[0153] This embodiment generates a unified sampling trigger signal on the effective transition edge of the sampling drive clock. Under the same trigger event, it drives the analog-to-digital conversion unit to acquire analog input signals and drives the timestamp latch to read nanosecond-level fine time. Combined with data buffering, standard format timestamp conversion, binding, and correlation verification, the sampled data and sampling timestamps are organized into a structured sampled data packet. This can maintain a strict correspondence between the sampling time and the time base under high sampling rate and high data throughput conditions, reduce the risk of mismatch between sampled values ​​and timestamps, improve the time alignment accuracy across channels and across nodes, and provide a highly reliable time-stamped data foundation for subsequent signal reconstruction, event localization, and multi-node collaborative analysis in a distributed precise synchronous acquisition system.

[0154] In one embodiment, an Ethernet-based time synchronization acquisition device is provided, which corresponds one-to-one with the Ethernet-based time synchronization acquisition method described in the above embodiments. (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the functional modules of a preferred embodiment of the Ethernet-based time synchronization acquisition device of the present invention. The modules include a time synchronization communication module 10, a physical layer clock recovery module 20, a high-precision timing module 30, a sampling clock generation module 40, and a data acquisition and timestamp module 50. Detailed descriptions of each functional module are as follows:

[0155] The time synchronization communication module 10 is used to communicate with the central control device through the data acquisition instrument based on the network time protocol, and to interact based on the precision time protocol to obtain the initial network time.

[0156] The physical layer clock recovery module 20 is used to drive the physical layer interface unit in the data acquisition instrument to recover the synchronous clock signal from the Ethernet physical layer signal and generate a trigger pulse signal aligned with the second boundary, and generate a second-level reference time based on the initial network time.

[0157] The high-precision timing module 30 is used to use the trigger pulse signal as a reset signal and the synchronous clock signal as a counting drive source to perform high-frequency counting accumulation based on the second-level reference time to generate nanosecond-level fine time.

[0158] The sampling clock generation module 40 is used to receive sampling rate configuration parameters and perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameters to obtain a sampling drive clock.

[0159] The data acquisition and timestamp module 50 is used to control the analog-to-digital conversion unit to perform sampling actions at the effective transition edge of the sampling driving clock, and to latch the nanosecond-level fine time to generate a sampling timestamp, and to combine the sampled data with the sampling timestamp for output.

[0160] For specific limitations regarding the Ethernet-based time synchronization acquisition device, please refer to the aforementioned limitations on the Ethernet-based time synchronization acquisition method, which will not be repeated here. Each module in the aforementioned Ethernet-based time synchronization acquisition device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0161] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 4 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile and / or volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external clients via a network connection. When the computer program is executed by the processor, it implements the functions or steps of a server-side time synchronization acquisition method based on Ethernet.

[0162] In one embodiment, a computer device is provided, which may be a client, and its internal structure diagram may be as follows: Figure 5 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with an external server via a network connection. When the computer program is executed by the processor, it implements the functions or steps of a client-side time synchronization acquisition method based on Ethernet.

[0163] In one embodiment, an Ethernet-based time synchronization acquisition device is provided. This Ethernet-based time synchronization acquisition device is deployed in a distributed precise synchronization acquisition system, and the schematic diagram of the distributed precise synchronization acquisition system can be shown as follows. Figure 6 As shown. (Refer to...) Figure 6 , Figure 6 This diagram illustrates the architecture of a distributed, precise synchronous acquisition system based on an Ethernet-based time synchronization acquisition device in one embodiment. The system connects a central PC control unit, a PoE & PTP switch, and multiple data acquisition instruments to the same network via Ethernet. The central PC control unit is responsible for running time services and host computer acquisition software, providing a unified time reference for the PoE & PTP switch, and centrally managing the acquisition results. The PoE & PTP switch provides operating voltage to each data acquisition instrument via Ethernet power supply and also supports time and frequency signals for IEEE 1588 and Synchronous Ethernet, forming a unified time and frequency reference on the network side. Multiple data acquisition instruments are distributed in different physical locations and connected to the PoE & PTP switch via network cables. They perform synchronous sampling under the unified time reference and transmit the acquired data with sampling timestamps back to the central PC control unit via the network for subsequent display, storage, and analysis.

[0164] In one embodiment, an Ethernet-based time synchronization acquisition device is provided. This device can take the form of a data acquisition instrument, and its internal module configuration diagram is shown below. Figure 7 As shown. Reference Figure 7 , Figure 7This diagram illustrates the internal module configuration of a data acquisition instrument in one embodiment of an Ethernet-based time synchronization acquisition device. The data acquisition instrument includes an RJ45 interface for implementing Ethernet physical connectivity and data transmission / reception, a PHY chip integrating PoE, SyncE, and PTP functions, a power supply unit that converts Ethernet power signals into multiple stable DC voltages, a SoC chip integrating an embedded ARM processing unit and an FPGA logic unit, and an ADC unit for acquiring analog signals. The RJ45 interface is connected to the PHY chip, introducing differential signals from the external network side into the internal physical layer circuitry via the Ethernet data link and providing necessary interface resources for the PHY chip. The PHY chip recovers clock information from the network data stream, outputs a synchronization clock signal Sync_clk and a trigger pulse signal Trigger, and interacts with the embedded ARM in the SoC chip via a MAC interface, while simultaneously supplying power to the power supply unit through the PoE port. The power supply unit obtains input energy from the PoE power supply channel, and after isolation, rectification, and voltage regulation, provides matching operating voltages to the PHY chip, SoC chip, and ADC unit. The embedded ARM processor runs a time synchronization program, configures the PHY registers and FPGA registers, and manages the parameters and operating status of the synchronous timer module, sampling clock generation module, and data acquisition module within the FPGA. During time synchronization, it generates a time quantity corresponding to a second-level reference time, marked as Time1 in the diagram. On the FPGA side, nanosecond-level fine time is generated based on the synchronization clock signal Sync_clk and the trigger pulse signal Trigger, marked as Time2 in the diagram. The sampling clock generation module generates a sampling clock Samp_clk, which drives the ADC unit to perform analog-to-digital conversion. The digital sampling result is output through the ADC data path. After completing the sampling timestamp binding, the data processing logic generates a timestamped acquisition time quantity, marked as Time3 in the diagram, and then sends the acquisition data carrying Time3 to the embedded ARM processor for packaging and uploading.

[0165] In one embodiment, an Ethernet-based time synchronization acquisition method is provided to achieve nanosecond-level fine-grained time generation. The timing diagram of its nanosecond-level fine-grained time generation can be shown as follows: Figure 8As shown in the diagram, Time1 represents the second-level reference time axis, forming time intervals T11 and T12 between the rising edges of two adjacent Trigger pulses. T11 corresponds to the duration of the first second, and T12 corresponds to the duration of the second second. Trigger is a trigger pulse signal that aligns with the second boundary, with each rising edge marking the start of a new second. Sync_clk is a synchronization clock signal that maintains a stable periodic output between two adjacent Triggers, represented by a square wave sequence to indicate continuous clock cycles. Time2 represents the nanosecond-level fine time axis, further dividing each time interval of Time1 into multiple finer time slices. In the diagram, these time slices are represented by T21, T22, T23…T2n, reflecting the continuous time points discretely divided according to the Sync_clk period within the same second. When the rising edge of the Trigger arrives, the synchronization timer module clears its internal counter register to zero and stores the current second-level reference time Time1 as the start time of that second in the register. Subsequently, it drives the counter to increment on each rising edge of Sync_clk, calculates the nanosecond-level time offset based on the ratio between the count value and the Sync_clk period, and superimposes it onto the corresponding T11 or T12 interval, thereby sequentially forming a series of nanosecond-level fine time outputs such as T21, T22, T23 up to T2n on the Time2 axis, providing a continuous and high-precision time reference for the generation of subsequent sampling timestamps.

Claims

1. A time synchronization acquisition method based on Ethernet, characterized in that, Includes the following steps: The data acquisition instrument communicates with the central control device based on the Network Time Protocol (NTP) and interacts with it based on the Precision Time Protocol (PTP) to obtain the initial network time. This includes: receiving an Ethernet power supply signal through the Ethernet interface of the data acquisition instrument; having the power management unit convert the Ethernet power supply signal to generate a working voltage; using the working voltage to put the data acquisition instrument into a ready-to-work state; initiating a NTP service through the central control device and sending a time synchronization request to the network switch; having the network switch process the time synchronization request to obtain a coarse time reference; and having the processing unit in the data acquisition instrument establish a two-way dialogue with the network switch based on the PTP, using the coarse time reference for time messaging. The system exchanges requests and responses, using the network switch as an intermediary node to forward relevant messages of the Network Time Protocol (NTP) and Precision Time Protocol (PTP). Based on the request and response exchanges of the time messages, it calculates the intermediate path delay. The processing unit parses the PTP messages to extract timestamp information, uses the timestamp information and the intermediate path delay to correct the frequency deviation and phase offset of the local clock, and generates corrected time data. It determines the network transmission delay compensation value through multiple round-trip time measurements, applies the delay compensation value to the corrected time data, and generates compensated time data. Based on the compensated time data and the local clock state, the processing unit executes a time synchronization algorithm to generate the initial network time. The processing unit in the data acquisition instrument drives the physical layer interface unit to recover the synchronous clock signal from the Ethernet physical layer signal and generate a trigger pulse signal aligned with the second boundary, thereby generating a second-level reference time based on the initial network time. Using the trigger pulse signal as a reset signal and the synchronization clock signal as a counting drive source, high-frequency counting accumulation is performed based on the second-level reference time to generate nanosecond-level fine time. Receive sampling rate configuration parameters, and perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameters to obtain the sampling drive clock; At the effective transition edge of the sampling drive clock, the sampling action is executed by controlling the analog-to-digital conversion unit, and the nanosecond-level fine time is latched to generate a sampling timestamp. The sampled data is then combined with the sampling timestamp and output.

2. The Ethernet-based time synchronization acquisition method as described in claim 1, characterized in that, The data acquisition instrument's processing unit drives the physical layer interface unit to recover the synchronization clock signal from the Ethernet physical layer signal and generate a trigger pulse signal aligned with the second boundary. Based on the initial network time, a second-level reference time is generated, including: The clock recovery function is activated by sending a configuration command to the physical layer interface unit through the processing unit in the data acquisition instrument. The physical layer interface unit extracts clock information from the Ethernet physical layer signal and generates a synchronization clock signal based on the clock information. The time stamp engine in the physical layer interface unit monitors the period count of the synchronization clock signal and generates a trigger pulse signal aligned with the second boundary at the corresponding time of the second boundary. The processing unit receives the synchronization clock signal and the trigger pulse signal. The processing unit performs clock synchronization calculations to generate synchronization time data based on the initial network time, the synchronization clock signal, and the trigger pulse signal. The processing unit applies frequency calibration and phase adjustment algorithms to process the synchronization time data, generating a second-level reference time.

3. The Ethernet-based time synchronization acquisition method as described in claim 1, characterized in that, Using the trigger pulse signal as a reset signal and the synchronization clock signal as a counting drive source, high-frequency counting and accumulation are performed based on the second-level reference time to generate nanosecond-level fine time, including: The rising edge of the trigger pulse signal is detected by the synchronous timer module, and the counter register is initialized. The counter register uses the synchronous clock signal as the driving source to perform a counting and accumulation operation on each rising edge of the synchronous clock signal to generate a count value. Read the current count value of the counter register and convert the count value into a nanosecond-level time offset; The second-level reference time is arithmetically added to the nanosecond-level time offset to generate an unverified nanosecond-level fine time. Monitor for abnormal situations during the counting and accumulation operation, perform validity checks on the unverified nanosecond-level fine time, and generate verified nanosecond-level fine time.

4. The Ethernet-based time synchronization acquisition method as described in claim 1, characterized in that, Receiving sampling rate configuration parameters, and performing frequency division processing on the synchronization clock signal based on the sampling rate configuration parameters to obtain a sampling drive clock, including: Receive sampling rate configuration parameters from the central control device through the configuration interface; Calculate the frequency division coefficient based on the sampling rate configuration parameters and the frequency of the synchronous clock signal; Use the frequency division coefficients to configure the operating parameters of the programmable frequency divider; The synchronous clock signal is divided into integers by the programmable frequency divider to generate a divided clock signal. The duty cycle of the frequency-divided clock signal is optimized to generate an optimized clock signal; The stability of the optimized clock signal is monitored in real time, and a verified sampling drive clock is generated. The verified sampling drive clock is distributed to each data acquisition channel.

5. The Ethernet-based time synchronization acquisition method as described in claim 4, characterized in that, The frequency division coefficient is calculated based on the sampling rate configuration parameters and the frequency of the synchronization clock signal, including: The parameter verification module checks the rationality and validity of the sampling rate configuration parameters and generates valid sampling rate parameters. The frequency division ratio calculation unit performs an integer division operation based on the effective sampling rate parameter and the frequency of the synchronous clock signal to generate the basic frequency division ratio. Calculate the fractional frequency division compensation value based on the aforementioned basic frequency division ratio; Using the base division ratio and the fractional division compensation value, the base division ratio and the fractional division compensation value are added together by addition to generate the division coefficient.

6. The Ethernet-based time synchronization acquisition method as described in claim 1, characterized in that, At the effective transition edge of the sampling drive clock, the analog-to-digital conversion unit is controlled to perform a sampling action, and the nanosecond-level fine time is latched to generate a sampling timestamp. The sampled data is then combined with the sampling timestamp and output, including: The sampling control circuit detects the valid transition edge of the sampling drive clock and generates a sampling trigger signal. The analog-to-digital conversion unit performs analog-to-digital conversion on the analog input signal under the control of the sampling trigger signal to generate the original sampling data. The original timestamp is generated by latching the nanosecond-level fine time at the valid moment of the sampling trigger signal using a timestamp latch. The original sampled data is stored in a data buffer to generate buffered sampled data. The original timestamp is converted into a standard format sampling timestamp, and the buffered sampling data is bound to the standard format sampling timestamp to generate sampling data with sampling timestamp; Verify the correct correlation of the sampled data with sampling timestamps, generate a verified sampling data packet, and output the verified sampling data packet to the data transmission channel.

7. A time synchronization acquisition device based on Ethernet, characterized in that, The Ethernet-based time synchronization acquisition device includes: The time synchronization communication module is used to communicate with the central control device via the data acquisition instrument based on the Network Time Protocol (NTP) and to interact based on the Precision Time Protocol (PTP) to obtain the initial network time. This includes: receiving an Ethernet power supply signal through the Ethernet interface of the data acquisition instrument; having the power management unit convert the Ethernet power supply signal to generate a working voltage; using the working voltage to put the data acquisition instrument into a ready-to-work state; initiating a NTP service through the central control device and sending a time synchronization request to the network switch; having the network switch process the time synchronization request to obtain a coarse time reference; and having the processing unit in the data acquisition instrument establish a two-way dialogue with the network switch based on the PTP, using the coarse time reference. The system performs request and response exchanges for time messages, uses the network switch as an intermediary node to forward relevant messages of the Network Time Protocol (NTP) and Precision Time Protocol (PTP), calculates intermediate path delays based on the request and response exchanges, parses PTP messages to extract timestamp information using the processing unit, uses the timestamp information and intermediate path delays to correct the frequency deviation and phase offset of the local clock, generates corrected time data, determines the network transmission delay compensation value through multiple round-trip time measurements, applies the delay compensation value to the corrected time data, generates compensated time data, and the processing unit executes a time synchronization algorithm based on the compensated time data and the local clock state to generate the initial network time. The physical layer clock recovery module is used to drive the physical layer interface unit in the data acquisition instrument to recover the synchronous clock signal from the Ethernet physical layer signal and generate a trigger pulse signal aligned with the second boundary, and generate a second-level reference time based on the initial network time. The high-precision timing module is used to use the trigger pulse signal as a reset signal and the synchronous clock signal as a counting drive source to perform high-frequency counting accumulation based on the second-level reference time to generate nanosecond-level fine time. A sampling clock generation module is used to receive sampling rate configuration parameters and perform frequency division processing on the synchronization clock signal based on the sampling rate configuration parameters to obtain a sampling drive clock. The data acquisition and timestamp module is used to control the analog-to-digital conversion unit to perform sampling actions at the effective transition edge of the sampling driving clock, and to latch the nanosecond-level fine time to generate a sampling timestamp, and then combine the sampled data with the sampling timestamp for output.

8. A computer device, characterized in that, The computer device includes a memory, a processor, and an Ethernet-based time synchronization acquisition program stored in the memory and executable on the processor. When the Ethernet-based time synchronization acquisition program is executed by the processor, it implements the steps of the Ethernet-based time synchronization acquisition method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The storage medium stores an Ethernet-based time synchronization acquisition program, which, when executed by a processor, implements the steps of the Ethernet-based time synchronization acquisition method as described in any one of claims 1-6.

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