Nanoscale heater structure and manufacturing method thereof

Abstract

The invention provides a nanoscale heater structure and a manufacturing method thereof. In the nanoscale heater structure, a heating wire is arranged to be a conductive plug in a through hole layer in a chip metal interconnection structure, and a liquid storage tank is arranged adjacent to the heating wire and is formed in a groove in a dielectric layer above the metal interconnection structure. According to the manufacturing method, a standard semiconductor back-end process is utilized, and the heater and the liquid storage tank are integrated on the same chip by forming the conductive plug and etching the dielectric layer. According to the invention, the heating wire and the liquid storage tank are directly integrated in the chip, the tungsten plug in the standard subsequent interconnection process is used as a heating element, expensive precious metal materials such as platinum are not needed, and additional special sputtering process and packaging process are not needed, so that the integration level of the system is greatly improved, and the manufacturing cost is remarkably reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a nanometer-scale heater structure and a manufacturing method thereof. BACKGROUND

[0002] Micro-heater is a key component in micro-electro-mechanical system (MEMS) and lab-on-a-chip, which is widely used in micro-fluidic, biochemical reaction, gas sensing and material analysis, etc. for precise temperature control and heating of micro-liquid or gas.

[0003] In the prior art, a conventional micro-heater usually adopts a discrete design, i.e. the control circuit part of the heater and the cavity part for performing heating function are manufactured separately. The heating element is usually formed by sputtering platinum (Pt), nickel-chromium alloy (Ni-Cr) or other noble metal or special alloy material on a substrate to form a heating resistor wire, and then packaged and integrated with an independent control chip through wire bonding or flip-chip bonding.

[0004] However, the conventional technical solution has the following defects: first, the separated structure of the control part and the heating cavity leads to low overall integration, large system volume, and limits its development in highly integrated and miniaturized applications; second, the noble metal material such as platinum used in the heating element is costly, and its sputtering process is a special process which needs to be performed on different special equipment than the standard semiconductor interconnection line process (such as CMOS post-process), increasing the complexity of the manufacturing process and production cost; finally, the separated components need additional packaging process for integration, which further increases the cost and potential failure risk.

[0005] Therefore, there is an urgent need in the industry for a nanometer-scale heater structure with high integration, low cost and compatible with standard semiconductor process, and a manufacturing method thereof. SUMMARY

[0006] The present application aims to provide a nanometer-scale heater structure and a manufacturing method thereof, to solve the problems of low integration, high cost and complex process of the micro-heater in the prior art.

[0007] To achieve the above object and other related objects, the present application provides a nanometer-scale heater structure, comprising:

[0008] a substrate, a metal interconnection structure disposed on the substrate, the metal interconnection structure comprising a metal layer and a via layer, a heating wire disposed as a conductive plug in the via layer of the metal interconnection structure, a dielectric layer disposed above the metal interconnection structure, the dielectric layer comprising a first passivation layer, and a liquid storage tank formed as a groove in the dielectric layer, wherein the heating wire is disposed adjacent to the sidewall of the liquid storage tank.

[0009] Preferably, the electrically conductive plug is a tungsten plug.

[0010] Preferably, the tungsten plug further comprises a titanium layer and / or a titanium nitride layer as a buried layer.

[0011] Preferably, the heating wire comprises a plurality of electrically conductive plugs, and the plurality of electrically conductive plugs are arranged around the liquid reservoir.

[0012] Preferably, the spacing between the plurality of electrically conductive plugs and the sidewall of the liquid reservoir is 0.5-1 microns.

[0013] Preferably, the spacing between adjacent electrically conductive plugs is 0.3-0.8 microns.

[0014] Preferably, the main component of the metal layer in the metal interconnection structure is aluminum.

[0015] Preferably, the liquid reservoir penetrates the first passivation layer and extends into the intermetallic dielectric layer of the metal interconnection structure to increase the depth of the liquid reservoir.

[0016] The present application also provides a method for manufacturing a chip-level heater, comprising the following steps:

[0017] Step 1: forming a metal interconnection structure on a substrate, the metal interconnection structure comprising a metal layer and a via layer, and forming electrically conductive plugs in the via layer as a heating wire;

[0018] Step 2: forming a dielectric layer comprising a first passivation layer on the metal interconnection structure; and

[0019] Step 3: etching the dielectric layer to form a liquid reservoir at the adjacent position of the heating wire.

[0020] Preferably, in Step 1, the electrically conductive plug is a tungsten plug.

[0021] Preferably, in Step 1, the step of forming the tungsten plug further comprises: depositing a titanium layer and / or a titanium nitride layer as a buried layer before depositing tungsten.

[0022] Preferably, in Step 1, the heating wire comprises a plurality of electrically conductive plugs, and the plurality of electrically conductive plugs are arranged around the predetermined formation area of the liquid reservoir.

[0023] Preferably, in Step 1, the electrically conductive plug is used to connect the top metal layer and the internal metal layer of the next layer of the top metal layer.

[0024] Preferably, in Step 1, the main component of the metal layer in the metal interconnection structure is aluminum.

[0025] Preferably, in Step 2, the main component of the first passivation layer is silicon dioxide.

[0026] Preferably, the step of etching the dielectric layer to form the reservoir in step three comprises: coating a photoresist layer on the dielectric layer; exposing and developing the photoresist layer by using a mask to define the area of the reservoir; and removing the dielectric layer in the defined area by using a dry etching process to form the reservoir.

[0027] Preferably, the method further comprises: step four, depositing a second passivation layer after forming the reservoir.

[0028] Preferably, in step four, the second passivation layer comprises an oxide film or a nitride oxide film.

[0029] Preferably, the method further comprises: step five, etching the dielectric layer and the second passivation layer to form a pad opening, the pad opening exposing a pad in the metal interconnection structure.

[0030] As described above, the nanometer-scale heater structure and the manufacturing method thereof have the following beneficial effects:

[0031] The present application integrates the heating wire and the reservoir directly into the chip, uses the tungsten plug in the standard back-end interconnection process as the heating element, does not need the expensive precious metal material such as platinum, and does not need the additional special sputtering process and packaging process, thereby greatly improving the integration of the system and significantly reducing the manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A flowchart of a chip-level heater manufacturing method according to an embodiment of the present application is shown in FIG. 1;

[0033] Figure 2 A cross-sectional view of a structure after forming the conductive plug according to an embodiment of the present application is shown in FIG. 2;

[0034] Figure 3 A cross-sectional view of a structure after depositing the first passivation layer according to an embodiment of the present application is shown in FIG. 3;

[0035] Figure 4 A cross-sectional view of a structure after defining the area of the reservoir according to an embodiment of the present application is shown in FIG. 4;

[0036] Figure 5 A cross-sectional view of a structure after forming the reservoir according to an embodiment of the present application is shown in FIG. 5;

[0037] Figure 6 A cross-sectional view of a structure after depositing the second passivation layer according to an embodiment of the present application is shown in FIG. 6;

[0038] Figure 7 A cross-sectional view of a structure after forming the pad opening according to an embodiment of the present application is shown in FIG. 7;

[0039] Figure 8 Fig. 1 is a schematic top view of a nanoscale heater structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] Other advantages and benefits of the present application will become apparent to those skilled in the art, upon reading the following with reference to the associated drawings, in which:

[0041] Reference will now be made to the drawings, wherein: Figure 6 The present application provides a nanoscale heater structure, comprising:

[0042] a substrate; a metal interconnect structure disposed on the substrate, the metal interconnect structure comprising a metal layer and a via layer; a heating wire 104 disposed as a conductive plug within the via layer of the metal interconnect structure; a dielectric layer disposed above the metal interconnect structure, the dielectric layer comprising a first passivation 106; and a reservoir 108 formed as a recess in the dielectric layer; wherein the heating wire 104 is disposed adjacent to a sidewall of the reservoir 108.

[0043] In particular, the metal interconnect structure is a multi-layer stack formed over a substrate (typically a silicon wafer containing front-end devices such as transistors), also known as a back-end-of-line (BEOL) structure. The structure typically includes one or more layers of horizontally routed metal layers, and via layers for electrically connecting different metal layers in the vertical direction. The metal interconnect structure can include an inter-metal layer 102 (Inter metal) formed over an inter-layer dielectric layer 101 (ILD), and one or more layers of an inter-metal dielectric layer 103 (IMD) for isolating different metal layers from each other. For example, the inter-layer dielectric layer 101 (ILD) can be silicon dioxide (SiO2), phosphor-silicon glass (PSG), boron-phosphor-silicon glass (BPSG), or the like formed by plasma-enhanced chemical vapor deposition (PECVD). In order to reduce the parasitic capacitance between metal wires, thereby reducing the RC delay of signals and improving the operating speed of the chip, the inter-metal dielectric layer 103 (IMD) is typically made of low dielectric constant materials or ultra-low dielectric constant materials. These materials can include, but are not limited to, carbon-doped silicon oxide (SiCOH), fluorinated amorphous carbon, or various porous low dielectric constant materials formed by introducing nanoscale pores into the material. The via layer is a conductive plug or via formed in the inter-metal dielectric layer 103 for vertically connecting the metal layers above and below. The top layer of the structure is typically a top metal layer 105 (Top metal) for high-current wiring or as a pad 110. In the present application, the heating wire 104 is formed using the via or conductive plug in the standard back-end process, for example, using the via (tungsten plug) connecting the inter-metal layer 102 and the top metal layer 105 as a heating element. This multi-layer structure also allows the height of the overall structure to be flexibly designed by stacking different inter-metal dielectric layers (e.g., IMD1 and IMD2), providing convenience for adjusting the depth of the reservoir 108.

[0044] In some embodiments, the main component of the metal layer in the metal interconnect structure is aluminum.

[0045] In some embodiments, the conductive plug is a tungsten plug.

[0046] In some embodiments, the tungsten plug further includes a titanium layer and / or a titanium nitride layer as a buried layer. Such a buried layer structure, for example, titanium as an adhesion layer and titanium nitride as a barrier layer, can significantly enhance the adhesion of tungsten to the surrounding medium and prevent tungsten from diffusing in subsequent high-temperature processes, thereby ensuring the long-term reliability and stability of the electrical performance of the heating wire 104.

[0047] In some embodiments, referring to Figure 8The heating wire 104 includes a plurality of conductive plugs, which are arranged around the liquid storage tank 108. This surrounding arrangement can uniformly transfer heat from the periphery to the central area of the liquid storage tank 108, avoiding local overheating or uneven heating problems, and can improve the heating efficiency and temperature uniformity for biochemical reactions or sensing applications that require precise temperature control.

[0048] In some embodiments, the spacing between the plurality of conductive plugs and the sidewall of the liquid storage tank 108 is 0.5-1 microns.

[0049] In some embodiments, the spacing between adjacent conductive plugs is 0.3-0.8 microns.

[0050] In some embodiments, the liquid storage tank 108 penetrates the first passivation layer 106 and extends into the intermetallic dielectric layer 103 of the metal interconnection structure to increase the depth of the liquid storage tank 108. By adjusting the etching depth using a multi-layer dielectric layer stack, the volume of the liquid storage tank 108 can be flexibly increased to meet the liquid sample volume requirements in different application scenarios without major changes to the process flow.

[0051] Referring to Figure 1 , the present application also provides a method for manufacturing a chip-level heater, comprising the following steps:

[0052] Step 1: Form a metal interconnection structure on a substrate, which includes a metal layer and a via layer, and form conductive plugs in the via layer as heating wires 104, forming a structure as shown in Figure 2 .

[0053] In some embodiments, in step 1, the conductive plugs are tungsten plugs.

[0054] In some embodiments, in step 1, the step of forming tungsten plugs further includes: depositing a titanium layer and / or a titanium nitride layer as a buried layer before depositing tungsten.

[0055] In some embodiments, referring to Figure 8 , in step 1, the heating wire 104 includes a plurality of conductive plugs, and the plurality of conductive plugs are formed around the predetermined formation area of the liquid storage tank 108.

[0056] In some embodiments, in step 1, the conductive plugs are used to connect the top metal layer 105 and the internal metal layer 102 of the next layer below the top metal layer 105.

[0057] In some embodiments, in step 1, the main component of the metal layer in the metal interconnection structure is aluminum.

[0058] Step 2: Form a dielectric layer including a first passivation layer 106 on the metal interconnection structure, forming a structure as shown in Figure 3 .

[0059] In some embodiments, in step two, the first passivation layer 106 is mainly composed of silicon dioxide.

[0060] In step three, the dielectric layer is etched to form a reservoir 108 adjacent to the heating wire 104, forming a structure as shown in FIG. 2B. Figure 5

[0061] In some embodiments, in step three, the step of etching the dielectric layer to form the reservoir 108 includes: coating a photoresist layer 107 on the dielectric layer; exposing and developing the photoresist layer 107 using a mask to define the area of the reservoir 108, forming a structure as shown in FIG. 2C; and using a dry etching process to remove the dielectric layer in the defined area, thereby forming the reservoir 108. Figure 4

[0062] In some embodiments, the method further includes: step four, after forming the reservoir 108, depositing a second passivation layer 109, forming a structure as shown in FIG. 2D. Figure 6

[0063] In some embodiments, in step four, the second passivation layer 109 includes an oxide film or a nitride oxide film. The second passivation layer 109 not only protects the exposed inner wall of the reservoir 108, but also provides the final mechanical and chemical protection to the entire chip surface, enhancing the durability of the device in the actual application environment.

[0064] In some embodiments, the method further includes: step five, etching the dielectric layer and the second passivation layer 109 to form a pad opening, which exposes the pad 110 in the metal interconnection structure, forming a structure as shown in FIG. 2E. This step enables the chip to be electrically connected to the external circuit, thereby providing a driving current or voltage for the heating wire 104. Figure 7

[0065] Through the above steps, the heating element (i.e., the heating wire 104) and the reservoir cavity (i.e., the reservoir 108) can be integrated on the same chip, achieving a high degree of integration that traditional separate devices cannot match. Since the heating wire 104 is made of a standard conductive plug in the back-end process, without introducing special processes and machines such as sputtering of noble metals, the entire manufacturing method is fully compatible with existing semiconductor process platforms (such as CMOS process), significantly simplifying the manufacturing process, reducing production costs, and improving product yield and reliability.

[0066] ​​​​It is to be noted that the drawings provided in the present embodiment only schematically illustrate the basic concept of the present application, and thus only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The shape, number and ratio of each component in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0067] The above-described embodiments only illustratively explain the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed in the present application should be covered by the claims of the present application.

Claims

1. A nanoscale heater structure, characterized by, The method comprises: a substrate; a metal interconnection structure disposed on the substrate, the metal interconnection structure comprising a metal layer and a via layer; a heating wire disposed as a conductive plug in the via layer of the metal interconnection structure; a dielectric layer disposed above the metal interconnection structure, the dielectric layer comprising a first passivation layer; and a liquid reservoir formed as a recess in the dielectric layer; wherein the heating wire is disposed adjacent to a sidewall of the liquid reservoir.

2. The nanoscale heater structure of claim 1, wherein: The conductive plug is a tungsten plug.

3. The nanoscale heater structure of claim 2, wherein: The tungsten plug further comprises a titanium layer and / or a titanium nitride layer as a buried layer.

4. The nanoscale heater structure of claim 1, wherein: The heating wire comprises a plurality of conductive plugs disposed around the liquid reservoir.

5. The nanoscale heater structure of claim 4, wherein: The spacing between the plurality of conductive plugs and the sidewall of the liquid reservoir is 0.5-1 microns.

6. The nanoscale heater structure of claim 4, wherein: The spacing between adjacent conductive plugs is 0.3-0.8 microns.

7. The nanoscale heater structure of claim 1, wherein: The metal layer in the metal interconnection structure is mainly composed of aluminum.

8. The nanoscale heater structure of claim 1, wherein: The liquid reservoir penetrates through the first passivation layer and extends into an intermetallic dielectric layer of the metal interconnection structure to increase the depth of the liquid reservoir.

9. A method of fabricating a nanoscale heater structure, comprising: The method comprises: Step 1: forming a metal interconnection structure on a substrate, the metal interconnection structure comprising a metal layer and a via layer, and forming a conductive plug in the via layer as a heating wire; Step 2: forming a dielectric layer comprising a first passivation layer on the metal interconnection structure; Step 3: etching the dielectric layer to form a liquid reservoir adjacent to the heating wire.

10. The method of claim 9, wherein: In Step 1, the conductive plug is a tungsten plug.

11. The method of claim 10, wherein: In Step 1, the step of forming the tungsten plug further comprises: depositing a titanium layer and / or a titanium nitride layer as a buried layer before depositing tungsten.

12. The method of claim 9, wherein: In Step 1, the heating wire comprises a plurality of conductive plugs, and the plurality of conductive plugs are formed around a predetermined formation area of the liquid reservoir.

13. The method of claim 9, wherein: In Step 1, the conductive plug is used to connect a top metal layer and an internal metal layer of a layer below the top metal layer.

14. The method of claim 9, wherein: In Step 1, the metal layer in the metal interconnection structure is mainly composed of aluminum.

15. The method of claim 9, wherein: In Step 2, the first passivation layer is mainly composed of silicon dioxide.

16. The method of claim 9, wherein: In Step 3, the step of etching the dielectric layer to form a liquid reservoir comprises: coating a photoresist layer on the dielectric layer; exposing and developing the photoresist layer using a mask to define the area of the liquid reservoir; and using a dry etching process to remove the dielectric layer in the defined area to form the liquid reservoir.

17. The method of claim 9, wherein: The method further comprises Step 4: after forming the liquid reservoir, depositing a second passivation layer.

18. The method of claim 17, wherein: In Step 4, the second passivation layer comprises an oxide film or a nitride oxide film.

19. The method of claim 17, wherein: The method further comprises Step 5: etching the dielectric layer and the second passivation layer to form a pad opening that exposes a pad in the metal interconnection structure.

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