Magnetoresistive random access memory layout structure

Abstract

The invention discloses a magnetic resistance type random access memory layout structure, each memory cell comprises a first word line, a third word line and a second word line which are sequentially arranged on a substrate at intervals and extend towards a first direction to cross an active area, a first magnetic tunnel junction located in a semiconductor back section metal layer, and a second magnetic tunnel junction located in a semiconductor back section metal layer, a second magnetic tunnel junction located in the semiconductor back-segment metal layer, one end of which is connected to the third active region and the other end of which is connected to a first bit line, and a second magnetic tunnel junction located in the semiconductor back-segment metal layer, one end of which is connected to the third active region and the other end of which is connected to a second bit line, wherein the first bit line and the second bit line are located at different metal levels in the semiconductor back-end metal layer, and a source line is connected to the first active region and the fourth active region.

Description

TECHNICAL FIELD

[0001] The present application relates to a layout structure of a magnetoresistive random access memory (MRAM), and more particularly to a layout structure of a MRAM having bitlines located at different metal levels. BACKGROUND

[0002] Magnetoresistive random access memory (MRAM) has been a new type of memory that has received much attention in recent years. MRAM integrates the advantages of various types of memory, such as comparable access speed to static random access memory (SRAM), non-volatility and low power consumption to flash memory, high density and durability to dynamic random access memory (DRAM), and can be manufactured in the current semiconductor back-end manufacturing process, thus having the potential to become the main memory in semiconductor chips. The storage element of MRAM is generally arranged in a level between upper and lower interconnection structures, which can include a magnetic tunneling junction (MTJ) structure, and is coupled with one or more transistors to control the switching of the circuit during read and write operations. Unlike conventional memory that stores data by storing electric charge, the operation of MRAM is to control the magnetization direction of the MTJ by applying an external magnetic field to the MTJ to obtain different tunneling magnetoresistive (TMR), thereby defining different storage states, so as to store digital data.

[0003] In response to the continuous miniaturization needs of various electronic products today, how to arrange more storage elements in a limited layout area and reduce the size of the storage cell and improve the layout efficiency through circuit design is the direction of research in the industry. In particular, as the size of the storage cell is reduced, it becomes increasingly difficult to arrange the same number of bitlines in the same metal level, which may violate the design rules. Therefore, how to change the layout design of the memory circuit to overcome this problem has become a topic that needs to be researched and developed by those skilled in the art today, in order to enable MRAM to be more widely and maturely applied in the field of memory. SUMMARY

[0004] In view of the current trend of miniaturization of memory cells and the demand for increasing memory capacity per unit layout area, the present invention proposes a novel circuit and layout structure for a magnetoresistive random access memory (MRAM), which is characterized in that the bit lines connected to the memory cells are designed in different metal levels, so that the size of the memory cells will not be limited by the minimum design specification of the bit lines, thereby improving the memory capacity per unit layout area.

[0005] The present invention proposes a magnetoresistive random access memory layout structure having a plurality of memory cells, wherein each memory cell comprises: a substrate having a plurality of active regions formed thereon; a first word line, a third word line and a second word line sequentially and spaced apart in a second direction on the substrate and extending in a first direction across the active regions, wherein the active regions outside the first word line are first active regions, the active regions between the first word line and the third word line are second active regions, the active regions between the third word line and the second word line are third active regions, and the active regions outside the second word line are fourth active regions; a first magnetic tunnel junction in a semiconductor back-end-of-line layer and connected at one end to the second active regions and at the other end to a first bit line; a second magnetic tunnel junction in the semiconductor back-end-of-line layer and connected at one end to the third active regions and at the other end to a second bit line, wherein the first bit line and the second bit line are in different metal levels in the semiconductor back-end-of-line layer; and a source line connected to the first active regions and the fourth active regions, wherein the source line, the first bit line and the second bit line extend in the second direction.

[0006] Such objects of the present invention and other objects, which will become apparent during the course of the following description, are achieved by preferred embodiments of the present invention described below with reference to the accompanying drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, explain the principles of the invention. In the drawings:

[0008] Figure 1 a circuit diagram of a magnetoresistive random access memory cell (MRAM cell) in a preferred embodiment of the present invention;

[0009] Figure 2 a layout structure of active regions and a first metal layer (M1) of an MRAM in a preferred embodiment of the present invention;

[0010] Figure 3A schematic diagram of the layout structure of the active region, the second metal layer (M2), and the magnetic tunnel junction (MTJ) of the MRAM in a preferred embodiment of the present application;

[0011] Figure 4 A schematic diagram of the layout structure of the active region and the third metal layer (M3) of the MRAM in a preferred embodiment of the present application;

[0012] Figure 5 A schematic diagram of the layout structure of the active region and the fourth metal layer (M4) of the MRAM in a preferred embodiment of the present application; and

[0013] Figure 6 A schematic diagram of the layout structure of the bit lines located at different metal levels in a preferred embodiment of the present application.

[0014] Symbol explanation

[0015] 100 substrate

[0016] A1 (first) active region

[0017] A2 (second) active region

[0018] A3 (third) active region

[0019] A4 (fourth) active region

[0020] BL1 (first) bit line

[0021] BL2 (second) bit line

[0022] C1, C2 storage cell

[0023] CT contact

[0024] D1 first direction

[0025] D2 second direction

[0026] M1 first metal layer

[0027] M2 second metal layer

[0028] M3 third metal layer

[0029] M4 fourth metal layer

[0030] MTJ1 (first) magnetic tunnel junction

[0031] MTJ2 (second) magnetic tunnel junction

[0032] N1 first node

[0033] N2 second node

[0034] P1 First Pattern

[0035] P2 Second Pattern

[0036] P3 Third Pattern

[0037] S1 First line segment

[0038] S2 Second segment

[0039] SL source line

[0040] T1 (first) transistor

[0041] T2 (second) transistor

[0042] T3 (Third) Transistor

[0043] V1~V3 guide hole components

[0044] WL1 (First) Word Line

[0045] WL2 (Second) Word Line

[0046] WL3 (Third) Word Line Detailed Implementation

[0047] The present invention will be described in detail below with reference to the accompanying drawings, which form part of the invention and illustrate specific embodiments by which the invention can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. For the sake of simplicity and convenience, the scale and proportion of certain parts in the drawings may be deliberately reduced or exaggerated. Other embodiments or structural, logical, and electrical variations may be employed in the invention without departing from its scope. Therefore, the following detailed description should not be viewed in a limiting manner, and the scope of the invention will be defined by the appended claims.

[0048] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" implies not only being "directly" on something but also includes being "on" something with an intervening feature or layer. Similarly, "above" or "above" implies not only being "above" or "above" something but also being "above" or "above" something without an intervening feature or layer (i.e., directly on something). Furthermore, spatially related terms such as "below," "under," "lower part," "above," and "upper part" are used herein for descriptive convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0049] As used herein, the term "substrate" refers to a material to which a subsequent material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0050] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope less than the scope of an underlying or overlying structure. Further, a layer can be a region of a homogenous or inhomogenous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between or between any horizontal pair of top and bottom surfaces of a continuous structure. A layer can extend level, vertically, and / or along an inclined surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0051] Readers will further appreciate that the terms "comprise", "comprising", "include", "including", and the like are typically used herein to indicate the presence of stated features, integers, steps, or components, but not to the exclusion of one or more other features, integers, steps, components, or groups thereof. Furthermore, it is understood that where the application, or any features thereof, is / are defined or claimed in the singular, plural forms can be included therein without limitation to a single structure or element unless such contexts clearly require it. It is further noted that the claims can be drafted to exclude any elements or steps from the application as "optional". Such drafts, however, apply only to specific claims and do not affect others that can not be specifically referred to in the same way.

[0052] Readers will further appreciate that the terms "comprise", "comprising", "include", "including", and the like are typically used herein to indicate the presence of stated features, integers, steps, or components, but not to the exclusion of one or more other features, integers, steps, components, or groups thereof. Furthermore, it is understood that where the application, or any features thereof, is / are defined or claimed in the singular, plural forms can be included therein without limitation to a single structure or element unless such contexts clearly require it. It is further noted that the claims can be drafted to exclude any elements or steps from the application as "optional". Such drafts, however, apply only to specific claims and do not affect others that can not be specifically referred to in the same way.

[0053] Reference is first made to Figure 1Figure 1 is a circuit diagram of a magnetic random access memory (MRAM) according to a preferred embodiment of the present application. This embodiment will illustrate the components of the MRAM circuit of the present application and the connection relationship therebetween in terms of a 3T2M (three transistors and two memory elements) architecture MRAM memory cell. It is noted, however, that although the memory cell shown in the embodiment has two memory elements, it can contain more memory elements in actual applications, without being limited thereto. The scope of the present application will be defined by the appended claims.

[0054] The MRAM circuit of the present application comprises a plurality of memory cells, which can be regularly arranged into a memory cell array or block in a layout plane and can share some word lines and bit lines. For the sake of clarity and simplicity, Figure 1 The circuit will be illustrated in terms of a single memory cell Cl, and other memory cells in the MRAM have the same or similar structure. As shown in Figure 1 Each memory cell Cl is composed of three transistors T1, T2, T3 and two memory elements, i.e. magnetic tunnel junctions MTJ1, MTJ2. In addition, each memory cell Cl has two bit lines BL1, BL2 and three word lines WL1~WL3. In the embodiment, the first transistor T1, the third transistor T3 and the second transistor T2 are connected in series, i.e. the source / drain electrodes thereof are connected to each other. In the circuit level, the gates of the first transistor T1, the second transistor T2 and the third transistor T3 are connected to the first word line WL1, the second word line WL2 and the third word line WL3, respectively, which are the gates of the corresponding transistors in the actual structure.

[0055] Referring back to Figure 1In an embodiment, the connection between the first transistor Tl and the third transistor T3 is a first node Nl (or called storage node), the connection between the second transistor T2 and the third transistor T3 is a second node N2, and the other end of the first transistor Tl and the third transistor T2 is connected to a common source line SL. The first node Nl and the second node N2 are connected to a first magnetic tunnel junction MTJl and a second magnetic tunnel junction MTJ2 respectively, which are the components responsible for storing data in the MRAM of the present application. More specifically, in the embodiment of the present application, one end of the first magnetic tunnel junction MTJl is coupled to the first node Nl and the other end is coupled to a first bit line BLl. One end of the second magnetic tunnel junction MTJ2 is coupled to the second node N2 and the other end is coupled to a second bit line BL2. Furthermore, in the embodiment of the present application, every three word lines can be used as a group to control the transistor switches of all the memory cells in the corresponding storage row (horizontal row), and the source line can be shared by all the memory cells in the corresponding storage column (vertical row). It should be noted that although only two magnetic tunnel junctions are shown in the figure, in other embodiments, more than one magnetic tunnel junction storage element in series can be connected to each node to achieve more storage states and larger memory capacity in a unit layout area.

[0056] Having described the MRAM circuit architecture of the present application, the following will sequentially describe Figures 2 to 6 the overlapping patterns of the constituent components of the MRAM of the present application on the layout planes of the actual levels, so that the reader can better understand the specific structure of the MRAM of the present application.

[0057] Please refer to Figure 2This is a layout structure of the active region and the first metal layer (M1) of the MRAM according to a preferred embodiment of the present invention. As shown in the figure, the MRAM of the present invention is disposed on a semiconductor substrate 100. The substrate 100 may be a silicon substrate, in which active regions with different conductivity can be pre-formed using an ion implantation process, and the different active regions are separated by a shallow trench isolation (STI) structure made of silicon oxide. Multiple word lines extend across these active regions, thus dividing these active regions into different sub-active regions. Specifically, taking this embodiment as an example, a first bit line WL1, a third bit line WL3, and a second bit line WL2 are arranged at intervals in a horizontal second direction D2 and extend across multiple active regions in a horizontal first direction D1. Thus, each active region can be divided into a first active region A1, a second active region A2, a third active region A3, and a fourth active region A4. The second direction D2 is preferably orthogonal to the first direction D1. As shown in the figure, the active region located outside the first character line WL1 is the first active region A1; the active region located between the first character line WL1 and the third character line WL3 is the second active region A2; the active region located between the second character line WL2 and the third character line WL3 is the third active region A3; and the active region located outside the second character line WL2 is the fourth active region A4. These four active regions A1 to A4 are arranged sequentially in the second direction D2.

[0058] Rereference Figure 2 In this embodiment, active regions A1-A4 serve as the source or drain of the transistor. Specifically, the first word line WL1 serves as the first transistor T1 ( Figure 1 The gate of the first transistor T1 has active regions A1 and A2 on both sides serving as the source and drain of the second transistor T1, respectively. The second word line WL2 serves as the gate of the second transistor T2. Figure 1 The gate of the transistor T2 has active regions A3 and A4 on either side serving as the drain and source of the second transistor T2, respectively. As for the third word line WL3, it serves as the drain and source of the third transistor T3. Figure 1 The gate of the first transistor T1 and the active regions A2 and A3 on both sides are considered as the source and drain of the third transistor T3. With this design, the first transistor T1 and the third transistor T3 ( Figure 1 The second transistor T2 and the third transistor T3 share the same active region A2 (i.e., represent the two being connected in series), while the second transistor T2 and the third transistor T3 ( Figure 1 They share the same active region A3 (i.e., representing that the two are connected in series). Furthermore, the sources of the first transistor T1 or the second transistor T2 of two adjacent memory cells in the first direction D1 (i.e., the first active region A1 or the fourth active region A4) can be connected and shared. Figure 2For example, the first active region A1 or the fourth active region A4 of the storage unit C1 on the left half and the storage unit C2 on the right half can share a common source, but not limited thereto.

[0059] Referring back to Figure 2 The semiconductor substrate 100 has a first metal layer M1 above the word lines WL1-WL3, which can be the first metal layer level in the semiconductor back end of line (BEOL) interconnects. In this embodiment, the first metal layer M1 includes a source line SL and a plurality of first patterns P1. The source line SL is preferably located between every two storage units (e.g., C1, C2) adjacent to each other in the first direction D1, and extends in the second direction D2 across the plurality of word lines WL1-WL3. The patterns and features on the two storage units are mirror-symmetrical with the source line SL as the center line. The first active region A1 or the fourth active region A4 of the two storage units C1, C2 can be connected to the source line SL in the first metal layer M1 through a contact CT, respectively. On the other hand, the second active region A2 and the third active region A3 of the storage unit can have the first pattern P1, respectively, which is mirror-symmetrical with the third word line WL3 as the center line, and preferably does not overlap the third word line WL3 in the direction perpendicular to the substrate. The second active region A2 and the third active region A3 can be connected to the first pattern P1 in the first metal layer M1 through a contact CT, respectively, and further connected to a higher metal layer or structure through the first pattern P1.

[0060] Referring back to Figure 3 which is the layout of the active region, the second metal layer M2, and the magnetic tunnel junction (MTJ) of the MRAM according to the preferred embodiment of the present application. It is noted that the first metal layer M1 is omitted in this figure to avoid confusion with the layers, and only the patterns of the active region, the second metal layer, and the magnetic tunnel junction are shown. As shown, the first metal layer M1 has a second metal layer M2 above it, which can also be a metal layer in the semiconductor BEOL interconnects. In this embodiment, the second metal layer M2 includes a plurality of second patterns P2. Specifically, the second active region A2 and the third active region A3 of each storage unit can have a second pattern P2, respectively, which is connected to the corresponding first pattern P1 through a via V1, respectively. On the other hand, the second pattern P2 can be connected to a corresponding magnetic tunnel junction through a via V2. For example, for the storage unit C1, the second pattern P2 on the second active region A2 is connected to the first pattern P1 through the via V1, and further connected to the magnetic tunnel junction MTJ1 through the first pattern P1 and the contact CT (not shown in this figure) in the first metal layer M1. The second pattern P2 on the third active region A3 is connected to the first pattern P1 through the via V1, and further connected to the magnetic tunnel junction MTJ2 through the first pattern P1 and the contact CT (not shown in this figure) in the first metal layer M1. Figure 2The second pattern P2 connects downwards to the second active region A2, and the second pattern P2 connects upwards to the first magnetic tunnel junction MTJ1 through the guide hole V2. These connection points are... Figure 1 The first node N1 in the memory cell C1. Similarly, the second pattern P2 on the third active region A3 of the memory cell C1 is connected downward to the first pattern P1 through the guide hole V1, and then connected to the contact CT via the first pattern P1. Figure 2 The second pattern P2 connects downwards to the third active region A3, and upwards to the second magnetic tunnel junction MTJ2 via the guide hole V2. These connection points are... Figure 1 The second node N2 in the array.

[0061] Rereference Figure 3 Magnetic tunneling junctions MTJ1 and MTJ2, as memory elements in an MRAM structure, are preferably disposed in the interconnect metal structure of the semiconductor back-end fabrication process, and can be compatiblely integrated into current mature CMOS fabrication processes. In this embodiment of the invention, magnetic tunneling junctions MTJ1 and MTJ2 are preferably disposed between the second metal layer M2 and the third metal layer M3. Figure 4 The vias V2 are inserted between the memory cells C1 and C2, and connected to the upper metal layers or structures via the vias V2. The first magnetic tunneling junction (MTJ1) is positioned closer to the outer side of the memory cell in the first direction D1 on the layout plane, while the second magnetic tunneling junction (MTJ2) is positioned closer to the boundary between the two memory cells C1 and C2 in the first direction D1 on the layout plane. The second magnetic tunneling junctions (MTJ2) of the two memory cells C1 and C2 can even be designed to partially overlap in the second direction D2. This demonstrates the effect of the bitline design of the present invention in reducing the size of the memory cell at different levels, which will be further explained in subsequent embodiments.

[0062] Please refer to Figure 4 This figure shows the layout structure of the active region and the third metal layer M3 of the MRAM according to a preferred embodiment of the present invention. Note that, to avoid layer confusion, the aforementioned first metal layer M1 and second metal layer M2 are omitted in this figure; only the active region, the third metal layer, and the magnetic tunneling junction pattern are shown. As shown, a third metal layer M3 is located above the second metal layer M2, which can belong to a metal layer in the semiconductor back-end interconnect structure. In this embodiment, the third metal layer M3 includes a first line BL1 and a third pattern P3. Preferably, the third pattern P3 is located between every two adjacent memory cells (e.g., C1, C2) in the first direction D1, with each memory cell having a corresponding third pattern P3. Specifically, in this embodiment, the boundary between two memory cells C1, C2 (i.e.,...) Figure 2The third metal layer M3 has two third patterns P3, which are mirror-symmetrical with respect to the third word line WL3. The third pattern P3 located at the lower part of the figure belongs to the storage unit C1, which downwardly receives the second magnetic tunnel junction MTJ2 near the boundary of the two units via the via V2. The third pattern P3 located at the upper part of the figure belongs to the storage unit C2, which downwardly receives another second magnetic tunnel junction MTJ2 near the boundary of the two units via the via V2. On the other hand, the first bit line BL1 in the third metal layer M3 is respectively arranged outside the two storage units C1, C2, which are mirror-symmetrical with respect to the boundary of the two storage units C1, C2 (the position of the source line SL) and extend to the second direction D2 beyond the plurality of word lines WL1~WL3. The first bit line BL1 downwardly receives the first magnetic tunnel junction MTJ1 near the outside of the two units via the via V2. As can be seen from the figure, in the embodiment of the present application, the second magnetic tunnel junction MTJ2 is not connected to the corresponding bit line in the third metal layer M3 as the first magnetic tunnel junction MTJ1 in the prior art. This is an important technical feature of the present application.

[0063] Please refer to Figure 5 , which is the layout structure of the active region and the fourth metal layer M4 of the MRAM according to the preferred embodiment of the present application. It should be noted that in order to avoid confusion of the layers, the first metal layer M1, the second metal layer M2 and the third metal layer M3 described above are omitted in this figure, and only the patterns of the active region, the fourth metal layer and the magnetic tunnel junction are shown. As shown in the figure, above the third metal layer M3 is a fourth metal layer M4, which can also belong to a metal layer in the semiconductor back-end interconnection structure. In this embodiment, the fourth metal layer M4 only includes the pattern of the second bit line BL2. In the embodiment of the present application, the second bit line BL2 is a bit line for connecting the second magnetic tunnel junction MTJ2 described above, which is designed differently from the first bit line BL1 and has a first segment S1 extending to the first direction D1 and a second segment S2 extending to the second direction D2. The second segment S2 of the second bit line BL2 can completely overlap or partially overlap the first bit line BL1 in the third metal layer M3 below, both of which extend to the second direction D2 to an external circuit, such as a column decoder circuit. One end of the first segment S1 of the second bit line BL2 is connected to the second segment S2, and the other end extends to the first direction D1 above the position of the third pattern P3 (or above the second magnetic tunnel junction MTJ2) of the third metal layer M3 at the boundary of the two storage units C1, C2, so as to be connected to the third pattern P3 via the via V3. Figure 4

[0064] Now please refer to Figure 6 ​, which clearly shows the relative positions and overlapping relationship of the first bit line BL1 and the second bit line BL2 in different metal levels in the layout plane. According to the MTJ layout design and the bit line design described in the foregoing embodiments, it can be understood that in the embodiments of the present application, the two magnetic tunnel junctions MTJ1, MTJ2 in the same memory cell are respectively connected to the first bit line BL1 and the second bit line BL2 in different metal levels, wherein the first bit line BL1 and the second bit line BL2 generally overlap in the vertical direction, but the second bit line BL2 additionally has a first line segment S1 extending in the first direction D1, which can wire the circuit of the second bit line BL2 to the position of the second magnetic tunnel junction MTJ2 of the memory cell to be connected thereto. With this design, the first bit line BL1 and the second bit line BL2 do not need to occupy the layout plane area of the same level as in the prior art, and they can be arranged in different metal levels without violating the minimum design specification, so that the layout position of the second magnetic tunnel junction MTJ2 does not need to be adjusted according to the position of the second bit line BL2, and the size of the memory cell can be adjusted accordingly. As can be seen from the figure, the positions of the two second magnetic tunnel junctions MTJ2 at the boundary between the two memory cells C1, C2 can even be designed to partially overlap in the second direction D2, so that the miniaturization of the memory cell is realized, which is the efficacy and progressiveness of the present application.

[0065] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall be within the scope of the present application.

Claims

1. A magnetoresistive random access memory layout structure having a plurality of memory cells, wherein each memory cell comprises: a substrate having a plurality of active regions formed thereon; a first word line, a third word line, and a second word line sequentially and spaced apart in a second direction on the substrate and extending in a first direction beyond the active regions, wherein the active regions outside the first word line are first active regions, the active regions between the first word line and the third word line are second active regions, the active regions between the third word line and the second word line are third active regions, and the active regions outside the second word line are fourth active regions; a first magnetic tunnel junction in a semiconductor back end of line layer and connected at one end to the second active regions and at another end to a first bit line; a second magnetic tunnel junction in the semiconductor back end of line layer and connected at one end to the third active regions and at another end to a second bit line, wherein the first bit line and the second bit line are in different metal levels in the semiconductor back end of line layer; and a source line connected to the first active regions and the fourth active regions, wherein the source line, the first bit line, and the second bit line extend in the second direction.

2. The magnetoresistive random access memory layout structure of claim 1, wherein the semiconductor back end of line layer comprises, sequentially from the substrate and in a vertical direction perpendicular to the substrate, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer, the source line is in the first metal layer, the first bit line is in the third metal layer, the second bit line is in the fourth metal layer, and the first magnetic tunnel junction and the second magnetic tunnel junction are between the second metal layer and the third metal layer.

3. The magnetoresistive random access memory layout structure of claim 2, wherein the second metal layer and the third metal layer are connected by a via, and the first magnetic tunnel junction and the second magnetic tunnel junction are in the via, respectively.

4. The magnetoresistive random access memory layout structure of claim 2, wherein the first magnetic tunnel junction and the second magnetic tunnel junction are connected to the second active regions and the third active regions, respectively, by first patterns in the first metal layer, the two first patterns being on the same side of the source line and mirror symmetric in the second direction with the third word line as a center line.

5. The magnetoresistive random access memory layout structure of claim 4, wherein the two first patterns and a first pattern of another memory cell adjacent in the first direction are mirror symmetric in the first direction with the source line as a center line.

6. The magnetoresistive random access memory layout structure of claim 4, wherein the source line is on a boundary of the memory cells, and the second magnetic tunnel junction and a second magnetic tunnel junction of another memory cell adjacent in the first direction partially overlap the source line in the vertical direction. ​ 7. The MRAM layout structure of claim 2, wherein the first MTJ and the second MTJ are connected to the second active region and the third active region, respectively, through a second pattern in the second metal layer, the first MTJ and the second MTJ fully overlap the corresponding second pattern in the vertical direction, respectively.

8. The MRAM layout structure of claim 2, wherein the third metal layer further comprises a third pattern, the second MTJ is connected to the third active region through the third pattern, the third pattern fully overlaps the second MTJ in the vertical direction.

9. The MRAM layout structure of claim 8, wherein the third pattern and a third pattern of another memory cell adjacent to the memory cell in the first direction are mirror symmetric in the second direction with the third word line as the mirror line, the first bit line and a first bit line of the another memory cell are mirror symmetric in the first direction with the third pattern as the mirror line.

10. The MRAM layout structure of claim 2, wherein the second direction is orthogonal to the first direction, the second bit line has a first line segment extending in the first direction and a second line segment extending in the second direction, the second line segment overlaps the first bit line in the vertical direction, the first line segment overlaps the second MTJ in the vertical direction.

11. The MRAM layout structure of claim 1, wherein the first active region is connected to a first active region of another memory cell adjacent to the memory cell in the first direction, the fourth active region is connected to a fourth active region of the another memory cell.

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