Manufacturing method of variable capacitance SGT transistor and SGT transistor

Abstract

The invention relates to the semiconductor technology, and discloses a manufacturing method of a variable capacitance SGT transistor and the SGT transistor, and the method comprises the steps: manufacturing a dielectric layer on the upper surface of a main body, and respectively manufacturing a corresponding source contact hole and a corresponding grid contact hole at different layout positions of the main body; manufacturing a front metal layer on the upper surface of the main body, and etching the front metal layer to respectively form a source communicated with the source contact hole, a main grid communicated with the main grid contact hole and an auxiliary grid communicated with the auxiliary grid contact hole; manufacturing a back metal layer on the back of the main body as a drain to obtain an SGT transistor; wherein the main grid electrode is connected with the auxiliary grid electrode, and when the auxiliary grid electrode is disconnected with the source electrode, the SGT transistor has a first capacitance value; when the main grid electrode and the auxiliary grid electrode are disconnected and the auxiliary grid electrode is connected with the source electrode, the SGT transistor has a second capacitance value; the first capacitance value is greater than the second capacitance value. The invention aims to realize the manufacturing of the variable capacitance SGT transistor so as to adapt to the requirements of different application scenes on the input capacitance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a manufacturing method of a variable-capacitance SGT transistor and a variable-capacitance SGT transistor. BACKGROUND

[0002] When a shielded gate trench transistor (SGT transistor) is used in different applications, different requirements are imposed on the input capacitance (Ciss) of the device. For example, in the application of motor drive, the requirement on the input capacitance is not very high, while in the application of synchronous rectification, the input capacitance is required to be as small as possible to reduce switching loss and suppress power spikes. At present, most of the SGT transistors on the market have a fixed input capacitance value, which is difficult to meet the diversified requirements of different application scenarios on the input capacitance.

[0003] The above content is only used to assist in understanding the technical solutions of the present application and does not mean that the above content is prior art. SUMMARY

[0004] The main purpose of the present application is to provide a manufacturing method of a variable-capacitance SGT transistor and a variable-capacitance SGT transistor, which aims to realize the manufacturing of a variable-capacitance SGT transistor, so that the SGT transistor can be switched between different capacitance values to adapt to the requirements of different application scenarios on the input capacitance.

[0005] To achieve the above purpose, the present application provides a manufacturing method of a variable-capacitance SGT transistor, comprising the following steps: A substrate with multiple trenches is provided, which has an overlying oxide layer; wherein a first polysilicon and a second polysilicon disposed above the first polysilicon are arranged in each trench, and the first polysilicon and the second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon and the inner wall of the trench are separated by an oxide layer; A first doped region and a second doped region with different doping types are formed in the adjacent sides of each trench in a stacked manner; After a dielectric layer is made on the upper surface of the main body, corresponding source contact holes and gate contact holes are made at different layout positions of the main body; wherein the source contact holes are used to expose the first doped region; the gate contact holes are used to expose the second polysilicon, and the gate contact holes are further divided into main gate contact holes and auxiliary gate contact holes, which are located above different trenches; A front metal layer is made on the upper surface of the main body, and the front metal layer is etched to form a source electrode connected to the source contact holes, a main gate electrode connected to the main gate contact holes, and an auxiliary gate electrode connected to the auxiliary gate contact holes; The back metal layer is made on the back of the main body as a drain to obtain the SGT transistor; when the main gate and the auxiliary gate are connected and the auxiliary gate is disconnected with the source, the SGT transistor has a first capacitance value; when the main gate is disconnected with the auxiliary gate and the auxiliary gate is connected with the source, the SGT transistor has a second capacitance value; the first capacitance value is greater than the second capacitance value.

[0006] Optionally, the method for manufacturing the SGT transistor with variable capacitance further comprises: The trench below the main gate contact hole is recorded as a first trench, and the remaining trenches except the first trench are second trenches below the auxiliary gate contact hole; The greater the ratio of the first trench to the total number of trenches is, the greater the ratio of the second capacitance value to the first capacitance value is.

[0007] Optionally, after the step of making the back metal layer on the back of the main body as a drain to obtain the SGT transistor, the method further comprises: When wire bonding for packaging the SGT transistor, the auxiliary gate is connected with any one of the main gate and the source through the wire to select the capacitance value of the SGT transistor.

[0008] Optionally, the substrate with multiple trenches and an overlying oxide layer comprises: After forming the first oxide layer on the substrate, etching the first oxide layer and part of the substrate to form multiple trenches; After growing the second oxide layer on the inner surface of each trench, filling the first polysilicon, and making the top of the first polysilicon lower than the top of the trench; Removing the top part of the first oxide layer and the top part of the second oxide layer, so that the top part of the first polysilicon protrudes from the second oxide layer; Growing a third oxide layer on the top surface of the main body, and making the top part of the first polysilicon wrapped by the third oxide layer form a protruding structure; Filling the second polysilicon on the third oxide layer in each trench, and making the top of the second polysilicon lower than the top of the trench.

[0009] Optionally, the method for manufacturing the SGT transistor with variable capacitance further comprises: In the process of manufacturing the first polysilicon, thin film technology is used to deposit 7000-10000 Å of polysilicon, and the polysilicon is etched to remove the polysilicon above the trench and make the top of the polysilicon in each trench lower than the top of the trench to obtain the first polysilicon; And / or, in the process of making the second polysilicon, 5000-8000 angstroms of polysilicon is deposited using a thin film process, and the polysilicon is etched to remove the polysilicon above the trenches and to make the top of the polysilicon in each trench lower than the top of the trench, thereby obtaining the second polysilicon.

[0010] Optionally, the depth of the trench is 5-6 microns. And / or, the height difference between the top of the first polysilicon and the top of the trench is 1.0-1.4 microns. And / or, the height difference between the top of the second polysilicon and the top of the trench is 0.1-0.18 microns.

[0011] Optionally, the method for making the SGT transistor of the variable capacitor further comprises: When the source contact hole and the gate contact hole are respectively made at different layout positions of the main body, a shield gate contact hole is also made at the corresponding position, wherein the shield gate contact hole is used to expose the first polysilicon; When the source is made, the source is also made to communicate with the shield gate contact hole.

[0012] Optionally, after the step of making the dielectric layer on the upper surface of the main body, and respectively making the source contact hole and the gate contact hole at different layout positions of the main body, the method further comprises: After the same type of dopant is injected on the upper surface of the first doped region in the source contact hole, a rapid thermal annealing process is performed to form a corresponding doped contact region.

[0013] Optionally, the substrate is an N-type silicon substrate; and the step of forming the first doped region and the second doped region with different doping types in a stacked manner on the adjacent sides of each trench comprises: P+ ions are injected on the surface of the substrate on the adjacent sides of each trench using an ion implantation process, and a P-type well region is formed as the first doped region after furnace tube annealing; An active region is exposed using a photolithography process, N+ ions are injected above each P-type well region, and an N-type source region is formed as the second doped region after furnace tube annealing.

[0014] To achieve the above-mentioned purposes, the application further provides a variable capacitor SGT transistor made by the method for making the variable capacitor SGT transistor.

[0015] The present application provides a method for fabricating a variable-capacitance SGT transistor and a variable-capacitance SGT transistor. By setting a main gate and a sub-gate that connect polysilicon in different trenches, and by changing the connection between the main gate, the sub-gate and the source, the SGT transistor can switch between different capacitance values, thereby obtaining a variable-capacitance SGT transistor to flexibly adapt to the input capacitance requirements of the SGT transistor in different application scenarios.

[0016] Furthermore, compared to existing SGT transistor structures, the process flow of this SGT transistor structure is compatible with existing processes, enabling the addition of variable capacitors to the same chip. When the SGT transistor is applied to different fields, the capacitance value can be adjusted during the packaging wire bonding process, which can reduce R&D and production costs, better match the application, and achieve the goal of multiple uses for a single chip, making it very flexible and convenient. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the fabrication steps of a variable capacitor SGT transistor in one embodiment of this application; Figure 2 This is a schematic diagram of the fabrication process of a variable capacitor SGT transistor in one embodiment of this application; Figure 3 This is a schematic diagram of another fabrication process of the variable capacitor SGT transistor in one embodiment of this application; Figure 4 This is a schematic diagram of another fabrication process of a variable capacitor SGT transistor in one embodiment of this application; Figure 5 This is a top view showing the device layout of a variable-capacitance SGT transistor in one embodiment of this application; Figure 6 This is a top view of the device layout of a variable capacitor SGT transistor without a source in one embodiment of this application; Figure 7 In one embodiment of this application, the SGT transistor is... Figure 5 Structural cross-section diagram at the location of section AA; Figure 8 In one embodiment of this application, the SGT transistor is... Figure 5 Structural cross-section view at the location of section AB; Figure 9 In one embodiment of this application, the SGT transistor is... Figure 5 Structural cross-section diagram at the location of section AC; Figure 10 In one embodiment of this application, the SGT transistor is... Figure 5 Structural cross-section view at the location of section AD; Figure 11A schematic diagram of a package wire bonding method of the SGT transistor of the variable capacitor in an embodiment of the present application; Figure 12 A schematic diagram of another package wire bonding method of the SGT transistor of the variable capacitor in an embodiment of the present application.

[0018] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, in which the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the accompanying drawings are exemplary and are intended to explain the present application, and cannot be understood as limiting the present application. All other embodiments obtained by those skilled in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0020] In addition, if the description of "first", "second" and the like is involved in the present application, it is only for the purpose of description (such as for distinguishing the same or similar features), and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that the technical solutions can be realized by those skilled in the art. When the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the scope of protection required by the present application.

[0021] Reference Figure 1 In an embodiment, the manufacturing method of the SGT transistor of the variable capacitor includes: Step S10, providing a substrate with multiple trenches and an overlying oxide layer; wherein each trench is provided with a first polysilicon and a second polysilicon disposed on the first polysilicon, the first polysilicon and the second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon and the inner wall of the trench are separated by an oxide layer; Step S20, forming a first doped region and a second doped region with different doping types in a stacked manner on the adjacent sides of each trench; Step S30, after manufacturing a dielectric layer on the upper surface of the main body, manufacturing corresponding source contact holes and gate contact holes at different layout positions of the main body; wherein the source contact holes are used to expose the first doped region; the gate contact holes are used to expose the second polysilicon, and the gate contact holes are further divided into main gate contact holes and auxiliary gate contact holes, the main gate contact holes and the auxiliary gate contact holes are located above different trenches; Step S40, a front metal layer is made on the top surface of the body, and the front metal layer is etched to form a source electrode connected to the source contact hole, a main gate electrode connected to the main gate contact hole, and a sub gate electrode connected to the sub gate contact hole, respectively; Step S50, a back metal layer is made on the back surface of the body as a drain electrode, to obtain an SGT transistor; when the main gate electrode and the sub gate electrode are connected and the sub gate electrode is disconnected from the source electrode, the SGT transistor has a first capacitance value; when the main gate electrode is disconnected from the sub gate electrode and the sub gate electrode is connected to the source electrode, the SGT transistor has a second capacitance value; the first capacitance value is greater than the second capacitance value.

[0022] In this embodiment, as described in step S10, a suitable semiconductor substrate (such as a silicon substrate) is selected, and an oxide layer (such as silicon dioxide) is grown on the surface of the substrate. The oxide layer can be formed by thermal oxidation or other processes, which serves as a certain protection and mask in the subsequent etching process. Figure 2

[0023] A photoresist is coated on the surface of the oxide layer, and exposure and development operations are performed through a photomask, to form openings on the photoresist corresponding to the required trench pattern. Using a photolithography process, the oxide layer and part of the substrate are etched through the photoresist openings. After etching is completed, the photoresist is removed, and a plurality of trenches are obtained.

[0024] Then, using thermal oxidation or chemical vapor deposition (CVD) or other methods, the oxide layer is continuously grown on the inner surface of each trench, so that the oxide layer serves as an insulating layer between the shielding gate and the substrate.

[0025] A thin film deposition process is used to fill the first polysilicon on the oxide layer in the trench, and the top of the first polysilicon is lower than the top of the trench. The first polysilicon will serve as a shielding gate polysilicon, which will shield the electric field in the transistor.

[0026] Optionally, an oxide layer is grown on the surface of the first polysilicon as an isolation layer between the first polysilicon and the subsequently filled second polysilicon.

[0027] Optionally, a thin film deposition process is used to fill the second polysilicon in each trench, and the top of the second polysilicon is lower than the top of the trench. At this time, the first polysilicon and the second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon, and the inner wall of the trench are also separated by an oxide layer.

[0028] As described in step S20, referring to Figure 3 , a photoresist is coated on the surface of the substrate, and a region requiring to be doped (i.e., the top part of the substrate adjacent to each trench or between each trench) is defined on the adjacent side of the trench through a photolithography process.

[0029] ​The ion implantation technology is used to implant specific type of impurity ions into defined area to form the first doped region. For example, if P-type doped region is needed, boron (B) ions can be implanted; if N-type doped region is needed, phosphorus (P) or arsenic (As) ions can be implanted.

[0030] On the first doped region, ion implantation is performed again to implant impurity ions of different type from the first doped region to form the second doped region which is stacked with the first doped region and has different doping type.

[0031] Optionally, after ion implantation, annealing treatment is performed to activate the implanted impurities and repair the lattice damage caused by ion implantation.

[0032] As described in step S30, a dielectric layer is made on the main body upper surface (including the oxide layer and the second polysilicon) using chemical vapor deposition or other methods. The dielectric layer can be silicon dioxide, silicon nitride or other insulating material, which is used to further isolate different conductive layers.

[0033] Optionally, the dielectric layer of 7000-10000 Å is deposited using thin film process.

[0034] Optionally, photoresist is coated on the surface of the dielectric layer, and exposure and development operations are performed through the photoetching mask to form the patterns of the source contact hole and the gate contact hole on the photoresist respectively.

[0035] Optionally, referring to Figure 4 , etching process is adopted to etch the dielectric layer, the oxide layer on the substrate and the second doped region on the top of the substrate through the photoresist opening to form the source contact hole for exposing the first doped region.

[0036] Similarly, etching process is adopted to etch the dielectric layer above different trenches through the photoresist opening to form the gate contact hole for exposing the second polysilicon. Moreover, the gate contact hole is divided into the main gate contact hole and the auxiliary gate contact hole, and the main gate contact hole and the auxiliary gate contact hole are located above different trenches.

[0037] Among them, referring to Figure 5 and Figure 6 (for the convenience of displaying the layout position of related devices, Figure 6 the source is not shown), after screening the trenches to which the main gate contact hole and the auxiliary gate contact hole belong, the opening position of the main gate contact hole and the auxiliary gate contact hole can be determined according to the expected position of the subsequent main gate and auxiliary gate.

[0038] Optionally, every two trenches are selected as the first trench, and the two trenches between the two adjacent first trenches are selected as the second trench; wherein the main gate contact hole is located above the second trench, and the auxiliary gate contact hole is located above the first trench.

[0039] Optionally, two sub-gate contact holes can be arranged in the same first groove; and two main-gate contact holes can be arranged in the same second groove.

[0040] As described in step S40, a front metal layer is made on the top surface of the main body by using physical vapor deposition (PVD), chemical vapor deposition (CVD) or the like, and the metal material can be aluminum, copper or other metal with good conductivity.

[0041] Optionally, the CVD or PVD thin film process is used to deposit titanium / nitride titanium / tungsten / aluminum in sequence as the front metal layer.

[0042] Referring to Figure 5 , Figures 7 to 10 The photoresist pattern is transferred to the metal layer by using etching process (such as wet etching or dry etching), and the unnecessary metal part is removed to form the source electrode connected to the source contact hole, the main-gate electrode connected to the main-gate contact hole and the sub-gate electrode connected to the sub-gate contact hole, respectively.

[0043] Optionally, for the layout position of the main-gate contact hole, after the corresponding metal layer is filled in each main-gate contact hole, the metal strip above the metal layer in each main-gate contact hole is reserved as the main-gate electrode in the process of etching the metal layer, and the main-gate electrode is separated from other metal layers, so that the main-gate electrode connected to each main-gate contact hole through metal filling is made; similarly, for the layout position of the sub-gate contact hole, after the corresponding metal layer is filled in each sub-gate contact hole, the metal strip above the metal layer in each sub-gate contact hole is reserved as the sub-gate electrode in the process of etching the metal layer, and the sub-gate electrode is separated from other metal layers, so that the sub-gate electrode connected to each sub-gate contact hole through metal filling is made; and after the main-gate electrode and the sub-gate electrode are made, the remaining metal layer can be used to make the source electrode.

[0044] In this way, the front metal layer originally formed by metal deposition can be divided into the source electrode, the main-gate electrode and the sub-gate electrode.

[0045] As described in step S50, the back surface of the main body is thinned, ground, polished and the like to ensure the flatness of the back surface and facilitate the subsequent making of the metal layer.

[0046] A metal layer is deposited on the back surface of the substrate by using PVD or CVD method as the drain electrode. Optionally, the metal material is the same as that of the front metal layer.

[0047] The SGT transistor thus made has a first capacitance value when the main-gate electrode and the sub-gate electrode are connected and the sub-gate electrode is disconnected from the source electrode, and has a second capacitance value when the main-gate electrode and the sub-gate electrode are disconnected and the sub-gate electrode is connected to the source electrode, and the first capacitance value is greater than the second capacitance value.

[0048] The main gate is the gate control terminal of the transistor, and the auxiliary gate is the variable gate control terminal. Figure 11 When the auxiliary gate is connected to the main gate terminal (while the auxiliary gate is disconnected from the source), it is equivalent to all the cells on the chip being normally open, and the cell utilization rate is 100% (equivalent to the conventional SGT transistor, that is, all the second polysilicon is connected and used as the gate control terminal), which has the highest first capacitance value; Figure 12 When the auxiliary gate is disconnected from the main gate control terminal and connected to the source, it is equivalent to a part of the cells on the chip being "short-circuited", and the cell utilization rate is less than 100%. At this time, the input capacitance of the chip is a second capacitance value less than the first capacitance value, that is, the input capacitance of the chip is effectively reduced, and the reduction amplitude is basically consistent with the proportion of the "short-circuited" cells. In addition, the on-resistance will slightly increase, and a reasonable compromise should be considered according to the application situation.

[0049] Taking a 100V N-type SGT transistor as an example, its on-resistance reference value is 3.3 milliohms. When 50% of the cells on the chip are "grounded" (that is, the main gate and the auxiliary gate are disconnected, and the auxiliary gate is connected to the source), the on-resistance increases to about 4.15 milliohms (increased by about 25%), but the input capacitance is reduced to about 50% of the original. This can better meet the requirements of the on-resistance, but for application ends with very strict requirements on the size of the input capacitance, it can realize wide-range adjustment of the input capacitance on the same chip (set the proportion of the grounded cells according to actual needs), expand more application scenarios, and greatly reduce production costs.

[0050] Optionally, according to different voltage platforms, such as 30V / 40V / 60V SGT products, a certain proportion of the cells on the chip are "grounded" (that is, the main gate and the auxiliary gate are disconnected, and the auxiliary gate is connected to the source) by the above design method, and the on-resistance increases by a further reduced amplitude (30V~60V SGT products mainly have low on-resistance), thereby obtaining a more cost-effective variable capacitance adjustment effect. That is, the lower the voltage platform of the product, the less the on-resistance will increase after the same proportion of cells are grounded.

[0051] In an embodiment, the main gate and the auxiliary gate connected to the polysilicon in different trenches are provided, and by changing the connection mode between the main gate, the auxiliary gate and the source, the SGT transistor is switched between different capacitance values, thereby obtaining a variable capacitance SGT transistor to flexibly adapt to the requirements of different application scenarios on the input capacitance of the SGT transistor.

[0052] Compared with the existing SGT transistor structure, the process flow of the SGT transistor structure can be compatible with the existing process, and the design of adding a variable capacitor on the same chip can be realized. When the SGT transistor is applied to different fields, by adjusting the size of the capacitor during packaging and wiring, the research and production costs can be reduced, the application end can be better matched, the purpose of one chip for multiple purposes can be achieved, and the flexibility and convenience are very high.

[0053] In an embodiment, based on the above embodiment, the manufacturing method of the SGT transistor of the variable capacitor further comprises: The trench under the main gate contact hole is referred to as a first trench, and the remaining trenches other than the first trench are second trenches under the auxiliary gate contact hole. The greater the ratio of the first trench to the total number of trenches, the greater the ratio of the second capacitance value to the first capacitance value.

[0054] In this embodiment, after the source contact hole and the gate contact hole are manufactured, the gate contact hole is divided into a main gate contact hole and an auxiliary gate contact hole, and the main gate contact hole and the auxiliary gate contact hole are located above different trenches. At this time, the trench under the main gate contact hole is defined as a first trench, and the remaining trenches other than the first trench are defined as second trenches, which are located below the auxiliary gate contact hole.

[0055] In this way, there is a specific relationship between the ratio of the number of first trenches to the total number of trenches and the capacitance value. Specifically, the greater the ratio of the first trench to the total number of trenches, the greater the ratio of the second capacitance value to the first capacitance value.

[0056] From the physical principle point of view, the capacitance value of the SGT transistor is closely related to the layout and connection mode of the trench. Different connection states of the main gate and the auxiliary gate will make the transistor present different capacitance values, i.e. the first capacitance value (when the auxiliary gate is connected to the main gate and the auxiliary gate is disconnected from the source) and the second capacitance value (when the main gate is disconnected from the auxiliary gate and the auxiliary gate is connected to the source). The first trench and the second trench are connected to the main gate contact hole and the auxiliary gate contact hole respectively, and they have different contributions to the capacitance in different connection states. When the number of first trenches increases, it means that the proportion of the part connected to the main gate in the whole structure increases. In the state that the main gate is disconnected from the auxiliary gate and the auxiliary gate is connected to the source, the overall capacitance characteristics of the transistor are relatively reduced by the influence of the first trench, so that the proportion of the second capacitance value to the first capacitance value increases.

[0057] In practical applications, the variable capacitance characteristics of the SGT transistor can be precisely controlled by adjusting the number ratio of the first grooves and the second grooves according to specific circuit requirements. For example, if a larger capacitance variation range is required, the ratio of the first grooves to the total number of grooves can be appropriately reduced; if it is desired that the capacitance value change relatively less in different connection states, the ratio of the first grooves to the total number of grooves can be increased. This helps to improve the adaptability and performance of the SGT transistor in various circuits.

[0058] In an embodiment, on the basis of the above-mentioned embodiment, after the step of manufacturing the back metal layer on the back of the body as the drain of the SGT transistor, the method further comprises: When wire bonding for the SGT transistor package, the auxiliary gate is connected to either the main gate or the source by the wire to select the capacitance value of the SGT transistor.

[0059] In this embodiment, wire bonding is a key step in the semiconductor device manufacturing process, mainly responsible for electrically connecting the electrodes inside the chip to the external pins to realize signal transmission and power supply between the chip and the external circuit.

[0060] In the wire bonding process, the wire is used to connect the auxiliary gate to the main gate or the source. According to the previous manufacturing method, when the main gate and the auxiliary gate are connected and the auxiliary gate is disconnected from the source, the SGT transistor has a first capacitance value; when the main gate and the auxiliary gate are disconnected and the auxiliary gate is connected to the source, the SGT transistor has a second capacitance value, and the first capacitance value is greater than the second capacitance value.

[0061] Optionally, referring to Figure 11 When the SGT transistor needs to exhibit the first capacitance value, the auxiliary gate is connected to the main gate by the wire. This connection mode makes the main gate and the auxiliary gate form an electrical conduction, while the auxiliary gate is in a disconnected state with the source, so that the transistor is in a working state with the first capacitance value.

[0062] Optionally, referring to Figure 12 If the SGT transistor needs to exhibit the second capacitance value, the auxiliary gate is connected to the source by the wire. At this time, the main gate and the auxiliary gate are disconnected, the auxiliary gate is connected to the source, and the transistor enters a working state with the second capacitance value.

[0063] This way of selecting the capacitance value through the wire bonding connection during packaging brings great flexibility to the practical application of SGT transistors. In different circuit application scenarios, different capacitance values may be needed to meet specific performance requirements. For example, in some circuits that need to switch capacitance characteristics according to different working modes, the appropriate wire bonding connection mode can be selected according to the specific needs during the packaging stage, without the need for large-scale adjustment of the transistor manufacturing process. This not only improves production efficiency and reduces costs, but also enables SGT transistors to better adapt to diversified market demands.

[0064] In an embodiment, on the basis of the above embodiment, the substrate with multiple trenches and an overlying oxide layer is provided; wherein each trench is provided with a first polysilicon and a second polysilicon disposed on the first polysilicon, and the first polysilicon and the second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon, and the inner wall of the trench are separated by an oxide layer. The steps include: After forming the first oxide layer on the substrate, etching the first oxide layer and part of the substrate to form multiple trenches; After growing the second oxide layer on the inner surface of each trench, filling the first polysilicon, and making the top of the first polysilicon lower than the top of the trench; Removing the first oxide layer and the top part of the second oxide layer, so that the top part of the first polysilicon protrudes from the second oxide layer; Growing a third oxide layer on the top surface of the main body, and making the top part of the first polysilicon wrapped by the third oxide layer form a protruding structure; Filling the second polysilicon on the third oxide layer in each trench, and making the top of the second polysilicon lower than the top of the trench.

[0065] In this embodiment, first, select a suitable substrate material, which is usually a semiconductor material such as silicon (Si). Place the substrate in an oxidation furnace in a high-temperature environment, and introduce an oxidizing gas such as oxygen (O2) or water vapor (H2O). Oxygen or water vapor chemically reacts with silicon atoms on the surface of the substrate to form silicon dioxide (SiO2), thereby forming a uniform first oxide layer on the upper surface of the substrate. The role of this first oxide layer is to act as a mask layer in the subsequent etching process to protect part of the substrate area from being etched.

[0066] Optionally, deposit 1500-5000 Å of the first oxide layer on the upper surface of the substrate.

[0067] The photoresist is coated on the first oxide layer by using a photolithography process. The photoresist is exposed through a photomask, and after development and other steps, the photoresist will form openings in the areas that need to be etched. Then, using an etching process (such as reactive ion etching), the first oxide layer is etched with the photoresist as a mask, removing the first oxide layer at the openings and exposing the underlying substrate. Next, the exposed part of the substrate is etched using the etching process, forming multiple trenches on the substrate. The size, shape, and spacing of these trenches are precisely controlled according to the specific SGT transistor design requirements.

[0068] Optionally, the depth of the trench is 5-6 μm to ensure that the space in the trench is sufficient to accommodate the subsequent structures to be made.

[0069] Optionally, the substrate with the etched trench is placed in an oxidation furnace for further oxidation treatment. On the inner surface of each trench (including the sidewall and bottom of the trench), silicon atoms react with the oxidizing gas to grow a second oxide layer. This second oxide layer serves as an insulating barrier to prevent the subsequently filled first polysilicon from directly contacting the substrate inside the trench, thereby avoiding leakage and other problems.

[0070] The second oxide layer is a thick oxide layer with a thickness in the range of 4000-6000 Å.

[0071] Optionally, a silicon-containing gas such as silane (SiH4) is introduced into the reaction chamber by chemical vapor deposition or other methods. Under high temperature conditions, silane decomposes and silicon atoms are deposited in the trench to fill the trench and perform polysilicon filling.

[0072] Optionally, during the process of making the first polysilicon, thin film technology is used to deposit 7000-10000 Å of polysilicon, and the polysilicon is etched to remove the polysilicon above the trench and to make the top of the polysilicon in each trench lower than the top of the trench, resulting in the first polysilicon as the shield gate polysilicon. The height difference between the top of the first polysilicon and the top of the trench needs to meet the space required for subsequent fabrication of the second polysilicon.

[0073] Optionally, the photolithography process is used to expose the pattern of the shield gate polysilicon (first polysilicon) and the dry etching process is used to etch the first polysilicon, so that the top of the first polysilicon is below the top of the substrate. The height difference is controlled to be 1.0-1.4 μm.

[0074] Optionally, a suitable etchant (such as hydrofluoric acid solution) is used for wet etching of the first oxide layer. Due to the difference in material properties between the first oxide layer and the second oxide layer and the substrate, the first oxide layer is selectively removed during etching, while the second oxide layer and the substrate are basically unaffected.

[0075] Optionally, the top part of the second oxide layer is etched by using the etching process. By precisely controlling the etching time and etching parameters, the top part of the first polysilicon protrudes from the second oxide layer (i.e. the oxide layer above and near the top of the first polysilicon is removed).

[0076] The main body after the above processing is placed in an oxidation furnace for oxidation treatment. A third oxide layer is grown on the upper surface of the main body (including the protruding top part of the first polysilicon and the part of the trench where the oxide layer has been removed). The third oxide layer serves as a gate oxide layer and covers the top part of the first polysilicon, the sidewall of the trench above the second oxide layer, and the upper surface of the substrate without the trench.

[0077] Optionally, the third oxide layer is a thin oxide layer with a thickness of 500-1000 Å.

[0078] Since the top part of the first polysilicon protrudes, during the growth of the third oxide layer, the top part of the first polysilicon wrapped by the third oxide layer forms a protruding structure. This protruding structure plays an important role in improving the electrical performance of the SGT transistor.

[0079] The second polysilicon is filled in each trench above the third oxide layer by using chemical vapor deposition or other methods.

[0080] Optionally, during the fabrication of the second polysilicon, a thin film process is used to deposit 5000-8000 Å of polysilicon, and the polysilicon is etched to remove the polysilicon above the trench and make the top of the polysilicon in each trench lower than the top of the trench, thereby obtaining the second polysilicon as the gate polysilicon.

[0081] Optionally, the height difference between the top of the second polysilicon and the top of the trench is 0.1-0.18 um.

[0082] In this way, a multilayer structure composed of the first polysilicon, the second oxide layer, the third oxide layer, and the second polysilicon is formed in the trench, laying a foundation for further fabrication of the SGT transistor.

[0083] The first polysilicon serves as a shielding gate polysilicon, and the second polysilicon serves as a gate polysilicon. When the second polysilicon is fabricated on the protruding structure formed on the top part of the first polysilicon wrapped by the third oxide layer, the second polysilicon will nest and wrap the protruding structure. When the second polysilicon nests and wraps the protruding structure of the top part of the first polysilicon wrapped by the third oxide layer, this unique structure has multiple effects on the electrical performance of the SGT transistor: (1) In the SGT transistor, the first polysilicon acts as a shield gate polysilicon, which shields the electric field. When the second polysilicon is nested around the protruding structure of the first polysilicon, it is equivalent to increasing the effectiveness of the shielding layer. The shield gate can effectively block the electric field coupling path between the gate and the drain, significantly reducing the gate-drain capacitance. The reduction of gate-drain capacitance can reduce the charging and discharging time of the transistor during switching, improve the switching speed, and reduce the switching loss. This is particularly important for high-frequency applications, such as in switching power supplies, radio frequency power amplifiers, etc. It can improve the efficiency and performance of the circuit.

[0084] (2) The second polysilicon acts as a gate polysilicon to control the conduction and cutoff of the channel. By nesting around the protruding structure of the first polysilicon, the second polysilicon can more effectively control the electric field distribution in the channel region. The protruding structure can increase the coupling area between the gate and the channel, so that the gate voltage can more accurately control the carrier concentration in the channel. Enhanced gate control capability can make the threshold voltage of the transistor more stable, reduce subthreshold leakage. When the transistor is turned on, it can form a conductive channel more quickly, increasing the on-current; when the transistor is turned off, it can more effectively suppress the leakage current, reducing static power consumption.

[0085] (3) The shielding effect of the first polysilicon and the nested structure of the second polysilicon can improve the electric field distribution inside the transistor. When the transistor is subjected to high voltage, the electric field will be redistributed inside the device to avoid local electric field concentration. The protruding structure and the nested wrapping method can make the electric field more evenly distributed throughout the structure, reducing the electric field peak. Uniform electric field distribution can increase the breakdown voltage of the transistor, allowing it to work safely at higher voltages. This is crucial for high-voltage transistors, such as in the power electronics field, where high-breakdown-voltage transistors can be used to achieve higher voltage levels for power conversion and control.

[0086] (4) By improving the gate control capability and optimizing the electric field distribution, the channel resistance can be more effectively reduced when the transistor is turned on. The nested wrapping of the second polysilicon around the protruding structure of the first polysilicon can increase the effective width of the channel, allowing more carriers to pass through the channel, thereby reducing the on-resistance. The reduction of on-resistance can reduce the power loss of the transistor in the on-state, improving the efficiency of the transistor. In high-power applications, reducing on-resistance can significantly reduce heat generation, improving the reliability and stability of the system.

[0087] In an embodiment, based on the above embodiment, the method for manufacturing a variable capacitance SGT transistor further comprises: When the source contact hole and the gate contact hole are respectively manufactured at different layout positions of the main body, a shield gate contact hole is also manufactured at the corresponding position; wherein the shield gate contact hole is used to expose the first polysilicon; The source electrode is also connected to the shield gate contact hole.

[0088] In this embodiment, the shield gate contact hole is made at a specific position while the source contact hole and the gate contact hole are made at different layout positions of the main body. The opening position of the shield gate contact hole needs to avoid the opening position of the gate contact hole.

[0089] Optionally, referring to Figure 6 The shield gate contact hole can be arranged for each trench in sequence at the central axis perpendicular to the longitudinal arrangement direction of the trench (corresponding to the AD cross section).

[0090] Optionally, referring to Figure 10 The first polysilicon and the functional layer above the first polysilicon are removed by etching at the opening position of the selected shield gate contact hole, so as to obtain the shield gate contact hole for exposing the first polysilicon of each trench.

[0091] In the process of making the source electrode, the source electrode needs to be connected to the shield gate contact hole in addition to the source contact hole. The pattern of the source electrode is defined on the front metal layer using a photolithography process, including the part connected to the source contact hole and the shield gate contact hole. The source electrode pattern is transferred to the photoresist through a photomask, and after development, the front metal layer is etched with the photoresist as a mask. The etching process removes the unnecessary metal part, leaving the source electrode pattern connected to the source contact hole and the shield gate contact hole.

[0092] By connecting the source electrode to the first polysilicon through the shield gate contact hole, the electrical performance of the SGT transistor can be improved. The first polysilicon as a shield gate can better control the electric field distribution after being connected to the source electrode, reduce the on-resistance and switching loss of the transistor, and improve the efficiency and reliability of the transistor.

[0093] In an embodiment, based on the above embodiment, after the step of making the source contact hole and the gate contact hole at different layout positions of the main body after making the dielectric layer on the upper surface of the main body, the method further comprises: After injecting the same type of dopant on the upper surface of the first doped region in the source contact hole, a rapid thermal annealing process is performed to form a corresponding doped contact region.

[0094] In this embodiment, the injection operation of the same type of dopant is performed on the upper surface of the first doped region in the already made source contact hole. The same type of dopant refers to the same type of impurity element as the first doped region. For example, if the first doped region is N-type doped (usually doped with phosphorus or other elements), the injected dopant is also N-type impurity; if the first doped region is P-type doped (usually doped with boron or other elements), the injected dopant is also P-type impurity.

[0095] The purpose of this step is to further increase the doping concentration on the upper surface of the first doped region. By increasing the doping concentration, the contact resistance can be reduced, enabling better electrical connection between the subsequently formed electrode and the first doped region, reducing energy loss during signal transmission, and improving the performance of the transistor, such as increasing its switching speed and reducing power consumption.

[0096] After the implantation of the same type of dopant is completed, a rapid thermal annealing process is performed on the entire body. Rapid thermal annealing is a process that heats the material to a high temperature in a short time and then rapidly cools it down.

[0097] During this process, the high-temperature environment can promote the uniform distribution of the implanted dopant in the lattice, repairing the lattice damage caused by ion implantation. During the ion implantation process, high-energy ions will collide with lattice atoms, causing defects in the lattice structure, which can affect the electrical properties of the material. Rapid thermal annealing can rearrange the lattice atoms and restore the integrity of the lattice.

[0098] At the same time, high temperature can also activate the implanted dopant, making it an effective carrier source, further improving the conductivity of the upper surface of the first doped region. After rapid thermal annealing, a corresponding doped contact region will be formed on the upper surface of the first doped region, which has good electrical properties and provides a high-quality contact interface for the subsequent fabrication of the source, thereby optimizing the performance of the entire SGT transistor.

[0099] In an embodiment, based on the above embodiment, the substrate is an N-type silicon substrate; and the step of forming the first doped region and the second doped region with different doping types in a stacked manner on the adjacent sides of each trench comprises: P+ ions are implanted on the surface of the substrate adjacent to each trench using an ion implantation process, and after furnace tube annealing, a P-type well region is formed as the first doped region; An active region is exposed using a photolithography process, N+ ions are implanted above each P-type well region, and after furnace tube annealing, an N-type source region is formed as the second doped region.

[0100] In this embodiment, when a 100V N-type SGT transistor is needed, an N-type silicon substrate can be selected as the substrate.

[0101] Optionally, referring to Figure 4 , Figure 7 and Figure 10In the process of making the first doped region, P+ ions are implanted into the substrate surface adjacent to each trench using an ion implantation process. The substrate here is an N-type silicon substrate, and the P+ ions are typically boron (B) ions or other positively charged impurity ions (i.e., P-type impurities such as boron are implanted). Ion implantation is a technique for precisely controlling the incorporation of impurities, in which an ion beam is accelerated to have sufficient energy to penetrate the substrate surface and enter the silicon lattice to a certain depth.

[0102] The implantation adjacent to the trenches is selected to form the desired P-type regions at specific locations to meet the structural and performance requirements of the transistor.

[0103] After implanting the P+ ions, furnace tube annealing is required. Furnace tube annealing is a process in which the substrate is placed in a high-temperature furnace tube and heated under certain temperature and atmosphere conditions. The main purposes of annealing are twofold: first, to activate the implanted P+ ions so that they become effective acceptor impurities capable of generating holes in the silicon lattice, thereby forming P-type conductivity characteristics; second, to repair the damage to the silicon lattice caused during ion implantation. During ion implantation, high-energy ions will collide with silicon atoms, causing defects in the lattice structure that can affect the electrical properties of the material. Annealing allows the lattice atoms to rearrange and restore the integrity of the lattice. After furnace tube annealing, P-type well regions are formed on the substrate surface adjacent to the trenches, serving as the first doped region.

[0104] The active region is exposed using a photolithography process, which precisely defines the area to be processed next on the substrate surface through exposure and development steps. In this process, photoresist is applied to the substrate surface, and then a specific pattern is exposed to the photoresist through a mask. After development, the desired pattern remains on the photoresist, exposing the active region, which is the area where N+ ions will be implanted next.

[0105] N+ ions are implanted above each P-type well region, i.e., in the exposed active region. N+ ions are typically phosphorus (P) ions or arsenic (As) ions or other negatively charged impurity ions (e.g., N-type impurities such as arsenic are implanted). The purpose of implanting N+ ions is to form N-type regions above the P-type well regions, serving as the source regions of the transistors.

[0106] After implanting the N+ ions, furnace tube annealing is again required. Similar to the annealing after implanting P+ ions, this annealing is also intended to activate the implanted N+ ions so that they become effective donor impurities capable of generating electrons in the silicon lattice, thereby forming N-type conductivity characteristics, while repairing lattice damage. After furnace tube annealing, N-type source regions are formed above each P-type well region, serving as the second doped region.

[0107] In this way, the first doped region (P-type well region) and the second doped region (N-type source region) with different doping types are successfully formed in the trench adjacent sides in a stacked manner, laying a foundation for subsequent manufacturing of the source and other structures of the SGT transistor.

[0108] Of course, after the source contact hole is manufactured, P+ ions can be further implanted in the hole, and after rapid thermal annealing, a P-type contact region is formed on the upper surface of the P-type well region.

[0109] In addition, the present application also provides a variable-capacitance SGT transistor, which is manufactured by the manufacturing method of the variable-capacitance SGT transistor as described in the above embodiments.

[0110] Since the variable-capacitance SGT transistor adopts all the technical solutions of the above embodiments, it at least has all the technical effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0111] In summary, for the manufacturing method of the variable-capacitance SGT transistor and the variable-capacitance SGT transistor provided in the embodiments of the present application, the main gate and the auxiliary gate of the polysilicon in different trenches are connected, and by changing the connection mode between the main gate, the auxiliary gate and the source, the SGT transistor is switched between different capacitance values, so that the variable-capacitance SGT transistor is obtained, which can flexibly adapt to the requirements of different application scenarios for the input capacitance of the SGT transistor.

[0112] And compared with the existing SGT transistor structure, the process flow of the SGT transistor structure is compatible with the existing process, and the design of variable capacitance can be realized on the same chip. When the SGT transistor is applied to different fields, the size of the capacitance can be adjusted when packaging and wiring, which can not only reduce the research and production cost, but also better match the application end, achieve the purpose of one chip for multiple purposes, and is very flexible and convenient.

[0113] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, devices, articles or methods including a series of elements not only include those elements, but also include other elements not explicitly listed, or include elements inherent to such processes, devices, articles or methods. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, device, article or method including the element.

[0114] The above merely provides the preferred embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structure or equivalent flowchart transformation based on the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method of fabricating a variable capacitance SGT transistor, comprising: include: A substrate with multiple trenches covered by an oxide layer is provided; wherein each trench contains a first polysilicon and a second polysilicon disposed on the first polysilicon, the first polysilicon and the second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon and the inner wall of the trench are separated by an oxide layer. First and second doped regions of different doping types are formed on the adjacent sides of each trench; After fabricating a dielectric layer on the upper surface of the main body, corresponding source contact holes and gate contact holes are fabricated at different layout positions of the main body; wherein, the source contact holes are used to expose the first doped region; the gate contact holes are used to expose the second polysilicon, and the gate contact holes are further divided into main gate contact holes and sub-gate contact holes, which are located above different trenches. A front metal layer is fabricated on the upper surface of the main body, and the front metal layer is etched to form the source electrode that connects to the source contact hole, the main gate electrode that connects to the main gate contact hole, and the sub-gate electrode that connects to the sub-gate contact hole. A back metal layer is fabricated on the back side of the main body as the drain to obtain an SGT transistor; wherein, when the main gate and the sub-gate are connected and the sub-gate is disconnected from the source, the SGT transistor has a first capacitance value; when the main gate and the sub-gate are disconnected and the sub-gate is connected to the source, the SGT transistor has a second capacitance value; the first capacitance value is greater than the second capacitance value.

2. The method of claim 1, wherein the SGT transistor is a variable capacitance SGT transistor. The method for fabricating the variable capacitor SGT transistor further includes: The groove located below the main gate contact hole is designated as the first groove, and the remaining grooves other than the first groove are designated as the second groove located below the secondary gate contact hole. The larger the ratio of the first trench to the total number of trenches, the larger the ratio of the second capacitance value to the first capacitance value.

3. The method of claim 1 or 2, wherein the step of forming the SGT transistor is performed by a method comprising: forming a first gate electrode on the substrate; forming a second gate electrode on the substrate; and forming a third gate electrode on the substrate. After the step of fabricating a back metal layer as a drain on the back side of the main body to obtain the SGT transistor, the method further includes: When bonding wires to an SGT transistor package, the sub-gate is connected to either the main gate or the source via wire bonding to select the capacitance value of the SGT transistor.

4. The method of claim 1, wherein the SGT transistor is a variable capacitance SGT transistor. The step of providing a substrate with multiple trenches covered by an oxide layer, wherein each trench contains a first polysilicon and a second polysilicon disposed on top of the first polysilicon, the first polysilicon and the second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon and the inner wall of the trench are separated by an oxide layer, includes: After forming the first oxide layer on the substrate, the first oxide layer and part of the substrate are etched to form multiple trenches; After growing a second oxide layer on the inner surface of each trench, the first polysilicon is filled in, and the top of the first polysilicon is lower than the top of the trench. Remove the first oxide layer and remove the top portion of the second oxide layer, so that the top portion of the first polysilicon protrudes from the second oxide layer; A third oxide layer is grown on the upper surface of the substrate, and a protruding structure is formed on the top portion of the first polysilicon encased in the third oxide layer. A second polysilicon layer is filled on top of the third oxide layer in each trench, with the top of the second polysilicon layer lower than the top of the trench.

5. The method for fabricating a variable-capacitance SGT transistor as described in claim 4, characterized in that, The method for fabricating the variable capacitor SGT transistor further includes: In the process of making the first polysilicon, 7000-10000 angstroms of polysilicon is deposited using a thin film process, and the polysilicon is etched to remove the polysilicon above the trenches and to make the top of the polysilicon in each trench lower than the top of the trench, thereby obtaining the first polysilicon; And / or, in the process of making the second polysilicon, 5000-8000 angstroms of polysilicon is deposited using a thin film process, and the polysilicon is etched to remove the polysilicon above the trenches and to make the top of the polysilicon in each trench lower than the top of the trench, thereby obtaining the second polysilicon.

6. The method of claim 1, 4 or 5, wherein the SGT transistor is a variable capacitance SGT transistor. The depth of the trench is 5-6 microns; And / or, the height difference between the top of the first polysilicon and the top of the trench is 1.0-1.4 microns; And / or, the height difference between the top of the second polysilicon and the top of the trench is 0.1-0.18 microns.

7. The method of claim 1, wherein the SGT transistor is a variable capacitance SGT transistor. The method for making the SGT transistor of the variable capacitor further comprises: When the source contact hole and the gate contact hole are respectively made at different layout positions of the main body, a shield gate contact hole is also made at the corresponding position, wherein the shield gate contact hole is used to expose the first polysilicon; When the source is made, the source is also connected to the shield gate contact hole.

8. The method of claim 1, wherein the SGT transistor is a variable capacitance SGT transistor. After the step of making the dielectric layer on the upper surface of the main body, and then making the source contact hole and the gate contact hole at different layout positions of the main body, the method further comprises: After injecting the same type of dopant on the upper surface of the first doped region in the source contact hole, a rapid thermal annealing process is performed to form a corresponding doped contact region.

9. The method of claim 1 or 8, wherein the SGT transistor is a variable capacitance SGT transistor. The substrate is an N-type silicon substrate; The step of forming the first doped region and the second doped region with different doping types in a stacked manner on the adjacent sides of each trench comprises: P+ ions are injected on the surface of the substrate on the adjacent sides of each trench using an ion implantation process, and a P-type well region is formed as the first doped region after furnace tube annealing; An active region is exposed using a photolithography process, N+ ions are injected above each P-type well region, and an N-type source region is formed as the second doped region after furnace tube annealing.

10. A variable capacitance SGT transistor, characterized by, The SGT transistor is made by the method for making the SGT transistor of the variable capacitor according to any one of claims 1-9.

Images