Bipolar PNP tube and integrated circuit
By employing a fully isolated structure in the PNP transistor, increasing the PN junction concentration and avoiding parasitic structures, the problem of abnormal operation of the PNP transistor at high temperatures and negative potentials is solved, thus achieving circuit stability and reliability.
Patent Information
- Application Number
- CN202511690781.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-01-20
AI Technical Summary
In ultra-high voltage processes, PNP transistors are prone to accidental activation at high temperatures, leading to abnormal circuit operation, especially under negative voltage conditions where parasitic NPN transistors may conduct.
Design a bipolar PNP transistor where the base, collector, and emitter are located within a fully isolated region formed by a deep N-well, an N-type buried layer, and a P-type groove-type isolation region. This reduces reverse leakage current by increasing the PN junction concentration and avoids parasitic structures of the PNP transistor at negative potential nodes.
It effectively reduces the reverse leakage current of PNP transistors at high temperatures, avoids false turn-on, ensures normal operation of the circuit under high temperature and negative potential conditions, and improves the stability and reliability of integrated circuits.
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Figure CN121368174A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a bipolar PNP transistor and integrated circuit. Background Technology
[0002] Bipolar PNP transistors are common semiconductor devices widely used in various integrated circuits. For example... Figure 1a The diagram shows the structure of a conventional bipolar PNP device. In some ultra-high voltage processes, such as the 700V BCD process (BCD specifically refers to the technology of simultaneously manufacturing analog circuits (bipolar), digital logic / control circuits (CMOS), and high-voltage / high-power devices (DMOS) on a single chip), the substrate material or epitaxial layer has a relatively low density to achieve the ultra-high voltage of 700V. Figure 1a The parasitic diode D1 between the N-well region (NW) and the silicon substrate (Psub) exhibits a significantly higher reverse leakage current (I1) at high temperatures compared to conventional low-voltage processes, reaching hundreds of nA at temperatures above 100°C. Figure 1b As shown, this can cause the PNP transistor M1 to turn on incorrectly when it should be turned off, resulting in an abnormal current in the microampere range at the collector C, causing abnormal circuit operation. Additionally, in some circuits, a negative voltage state exists, such as... Figure 1a and 1c As shown, the N-well region NW of the negative voltage node, the silicon substrate Psub, and the base B of the PNP form a parasitic NPN transistor M2 that conducts, generating a current I2. This can also cause the PNP transistor M1 to turn on erroneously, resulting in abnormal circuit operation.
[0003] Therefore, how to solve the problem of PNP tubes turning on erroneously at high temperatures in ultra-high voltage processes, leading to abnormal circuit operation, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] This invention provides a bipolar PNP transistor and integrated circuit, which solves the problem in related technologies where PNP transistors may turn on erroneously at high temperatures during ultra-high voltage processes, leading to abnormal circuit operation.
[0005] As a first aspect of the present invention, a bipolar PNP transistor is provided, comprising: silicon substrate; An N-type buried layer is located within the silicon substrate and extends from the upper surface of the silicon substrate into the interior of the silicon substrate. The depth of the N-type buried layer is less than the depth of the silicon substrate, and the cross-sectional width of the N-type buried layer is less than the cross-sectional width of the silicon substrate. An epitaxial layer is located on the upper surface of the silicon substrate and covers the upper surface of the silicon substrate; A P-type recessed isolation region is located in the epitaxial layer and corresponds to the upper surface of the N-type buried layer; An N-well region is located in the recessed region formed by the P-type recessed isolation region and is surrounded by the P-type recessed isolation region; A deep N-well region is located in the epitaxial layer and is arranged around the P-type recessed isolation region, and the deep N-well region and the P-type recessed isolation region are both located on the upper surface of the N-type buried layer; A first P+ region, a second P+ region, a first N+ region and a P- region are arranged in the N-well region, the P- region is separated from the first P+ region and arranged around the first P+ region, the first N+ region is separated from the P- region and arranged around the P- region, and the second P+ region is located in the P- region; A third P+ region is arranged in the P-type recessed isolation region, and the third P+ region is separated from the first N+ region and arranged around the first N+ region; A second N+ region is arranged in the deep N-well region, and the second N+ region is separated from the third P+ region and arranged around the third P+ region; The first P+ region is formed as an emitter region of the bipolar PNP tube, the P- region is formed as a collector region of the bipolar PNP tube, and the N-well region is formed as a base region of the bipolar PNP tube.
[0006] Further, the P-type recessed isolation region includes a deep P-type well region located on the upper surface of the N-type buried layer and a P-well region located on the upper surface of the deep P-type well region and arranged around the N-well region.
[0007] Further, the third P+ region is located in the P-well region.
[0008] Further, the bipolar PNP tube further includes a field oxide layer formed on the upper surface of the epitaxial layer.
[0009] Further, the field oxide layer includes a first field oxide region between the first N+ region and the P- region, a second field oxide region between the first N+ region and the third P+ region, a third field oxide region between the third P+ region and the second N+ region, and a fourth field oxide region on the periphery of the second N+ region.
[0010] Further, the first P+ region is an emitter region lead-out end of the bipolar PNP tube, the second P+ region is a collector region lead-out end of the bipolar PNP tube, the first N+ region is a base region lead-out end of the bipolar PNP tube, the third P+ region is a 0 potential lead-out end of the bipolar PNP tube, and the second N+ region is a power supply potential lead-out end of the bipolar PNP tube.
[0011] Further, the shape of the first P+ region includes any one of a circle, a square, and a polygon.
[0012] As another aspect of the present application, there is provided an integrated circuit including the bipolar PNP transistor according to any one of claims 1 to 7.
[0013] The bipolar PNP transistor according to the present application solves the problem of abnormal operation of the PNP transistor at high temperature in a 700V super-high voltage process by forming the base, the collector, and the emitter of the PNP transistor in a full isolation region formed of a deep N well, an N-type buried layer, and a P-type groove-type isolation region, and by making the reverse leakage current of a parasitic diode formed of the base region N well and the P-type groove-type isolation region of the PNP transistor much smaller than the reverse leakage current of a parasitic diode formed of a conventional N well and a silicon substrate at high temperature. Also, since the three poles of the PNP transistor are formed in a full isolation structure, there is no parasitic structure between the three poles of the PNP transistor and a negative potential node of a circuit, and thus the influence of the negative potential on the PNP transistor is avoided, and the problem of abnormal operation of the PNP transistor in a circuit operating in a state in which a negative potential exists is solved. BRIEF DESCRIPTION OF DRAWINGS
[0014] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate embodiments of the present application and explain the principles of the present application together with the specific embodiments described below.
[0015] Figure 1a FIG. 1 is a diagram of a conventional structure of a bipolar PNP device.
[0016] Figure 1b FIG. 2 is a diagram of a PNP transistor and a parasitic diode shown in FIG. 1. Figure 1a
[0017] Figure 1c Figure 1a
[0018] Figure 2 FIG. 6 is a cross-sectional view of a bipolar PNP transistor according to the present application.
[0019] Figure 3 FIG. 7 is a top view of one embodiment of a bipolar PNP transistor according to the present application.
[0020] Figure 4 FIG. 8 is a top view of another embodiment of a bipolar PNP transistor according to the present application.
[0021] Figure 5 FIG. 9 is a top view of still another embodiment of a bipolar PNP transistor according to the present application. DETAILED DESCRIPTION
[0022] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0023] In order for those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present application.
[0024] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0025] In the present embodiment, a bipolar PNP transistor is provided, Figure 2 is a cross-sectional view of the bipolar PNP transistor provided according to the embodiment of the present application, Figure 3 is a top view of the bipolar PNP transistor provided according to the embodiment of the present application, as Figure 2 and Figure 3 shown, comprising: a silicon substrate 0; an N-type buried layer 2 located in the silicon substrate 0 and extending from the upper surface of the silicon substrate 0 to the interior of the silicon substrate 0, the depth of the N-type buried layer 2 being less than the depth of the silicon substrate 0, and the cross-sectional width of the N-type buried layer 2 being less than the cross-sectional width of the silicon substrate 0; an epitaxial layer 1 located on the upper surface of the silicon substrate 0 and covering the upper surface of the silicon substrate 0; a P-type recessed isolation region located in the epitaxial layer 1 and corresponding to the upper surface of the N-type buried layer 2; an N-well region 5 located in the recessed region formed by the P-type recessed isolation region and surrounded by the P-type recessed isolation region; a deep N-well region 4 located in the epitaxial layer 1 and arranged around the P-type recessed isolation region, the deep N-well region 4 and the P-type recessed isolation region both being located on the upper surface of the N-type buried layer 2; The first P+ region 11, the second P+ region 10, the first N+ region 7 and the P- region 9 are arranged in the N well region 5, the P- region 9 is spaced apart from and arranged around the first P+ region 11, the first N+ region 7 is spaced apart from and arranged around the P- region 9, and the second P+ region 11 is located in the P- region 9; The third P+ region 12 is arranged in the P-type groove type isolation region, and the third P+ region 12 is spaced apart from and arranged around the first N+ region 7; The second N+ region 8 is arranged in the deep N well region 4, and the second N+ region 8 is spaced apart from and arranged around the third P+ region 12; The first P+ region 11 is formed as an emitter region of the bipolar PNP tube, the P- region 9 is formed as a collector region of the bipolar PNP tube, and the N well region 5 is formed as a base region of the bipolar PNP tube.
[0026] In the embodiment of the present application, the concentration of the P-type groove type isolation region is much greater than the concentration of the substrate 0, and for the reverse leakage current, the greater the concentration, the smaller the reverse leakage current. Based on this, the concentration of the PN junction formed between the N well region and the P-type groove type isolation region in the embodiment of the present application is much greater than the concentration of the PN junction formed between the N well region and the silicon substrate in the prior art. Therefore, the reverse leakage current of the parasitic diode formed between the N well region 5 as the base region of the bipolar PNP tube and the P-type groove type isolation region at high temperature will be much smaller than the reverse leakage current of the parasitic diode formed between the base region N well and the silicon substrate of the conventional PNP at high temperature. Based on this, the PNP tube will not be mis-started when working at high temperature, thereby solving the problem of abnormal working of the conventional PNP tube at high temperature in the prior art. In addition, the N well region 5 as the base region of the bipolar PNP tube is located in the isolation structure formed by the N-type buried layer 2, the deep N well 4 and the P-type groove type isolation region, so that when the bipolar PNP tube is applied in an integrated circuit, there will be no parasitic NPN between the N well region of other negative potential nodes in the circuit and the N well region 5 of the bipolar PNP tube, i.e. there will be no parasitic NPN tube M2 in the circuit in the prior art, so there will be no parasitic current I2, thereby solving the problem of abnormal working of the PNP tube in the negative potential circuit in the prior art. Figure 1c
[0027] Therefore, the bipolar PNP tube provided by the application solves the problem of abnormal working of the PNP tube at high temperature in the 700V super high voltage process by forming the base, the collector and the emitter of the PNP tube in a full isolation region formed by a deep N well, an N-type buried layer and a P-type groove type isolation region, and the reverse leakage current of the parasitic diode formed by the base N well of the PNP tube and the P-type groove type isolation region is much smaller than the reverse leakage current of the parasitic diode formed by the conventional N well and the silicon substrate at high temperature; meanwhile, since the three poles of the PNP tube are formed in a full isolation structure, there is no parasitic structure between the three poles of the PNP tube and the negative potential node of the circuit, and the influence of the negative potential on the PNP tube is avoided, thereby solving the problem of abnormal working of the PNP tube in the circuit with a negative potential.
[0028] In the embodiment of the application, as shown in Figure 2 The P-type groove type isolation region comprises a deep P-type well region 3 and a P well region 6, the deep P-type well region 3 is located on the upper surface of the N-type buried layer 2, and the P well region 6 is located on the upper surface of the deep P-type well region 3 and surrounds the N well region 5.
[0029] Further, the third P+ region 12 is located in the P well region 6.
[0030] It should be understood that the deep P-type well region 3 is located on the upper surface of the N-type buried layer 2, the P-type well region 6 is located on the upper surface of the deep P-type well region 3 and surrounds the N well region 5, and in this structure, a PN junction can be formed between the N well region 5 and the deep P-type well region 3, but since the concentration of the deep P-type well region 3 is much greater than the concentration of the silicon substrate 0, the reverse leakage current of the parasitic diode formed by the N well region 5 and the deep P-type well region 3 at high temperature is much smaller than the reverse leakage current of the parasitic diode formed by the base N well of the conventional PNP and the silicon substrate at high temperature, and based on this, as shown in Figure 1b the leakage current I1 of the parasitic diode D1 at high temperature can be reduced from several hundred nA to several nA, so the bipolar PNP tube of the embodiment of the application will not be mistakenly turned on at high temperature, thereby solving the problem of abnormal working of the conventional PNP tube at high temperature in the prior art. In addition, since the N well 5 in the embodiment of the application is located in the isolation structure composed of the N-type buried layer 2, the deep N well 4 and the deep P-type well region 3, there is no parasitic NPN between the N-type well region of other negative potential nodes in the circuit and the base N well 5 of the bipolar PNP tube, that is, Figure 1c as shown in the parasitic NPN tube M2, so there is also no parasitic current I2, thereby solving the problem of abnormal working of the PNP tube in the circuit with a negative potential.
[0031] Further, the bipolar PNP tube further comprises a field oxide layer formed on the upper surface of the epitaxial layer 1.
[0032] In the embodiment of the present application, the field oxide layer comprises a first field oxide region 20 between the first N+ region 7 and the P- region 9, a second field oxide region 21 between the first N+ region 7 and the third P+ region 12, a third field oxide region 22 between the third P+ region 12 and the second N+ region 8, and a fourth field oxide region 23 outside the second N+ region 8.
[0033] Specifically, the first P+ region 11 is the emitter region lead-out end of the bipolar PNP transistor, the second P+ region 10 is the collector region lead-out end of the bipolar PNP transistor, the first N+ region 7 is the base region lead-out end of the bipolar PNP transistor, the third P+ region 12 is the 0 potential lead-out end of the bipolar PNP transistor, and the second N+ region 8 is the power potential lead-out end of the bipolar PNP transistor.
[0034] It should be understood that the deep N well region 4, the N-type buried layer 2, and the deep P well region 3 constitute an isolation structure; the deep N well region 4 and the N-type buried layer 2 surround the deep P well region 3 on the periphery and the bottom, completely isolating the deep P well region 3 from the silicon substrate 0, and the deep P well region 3 isolates the N well region 5 from the deep N well region 4 and the N-type buried layer 2; the deep N well region 4 is generally connected to a power supply, and the deep P well region 3 is generally connected to a 0 potential in an integrated circuit to achieve an isolation effect; the P well region 6 plays a role in strengthening the isolation; and the N well region 5 forms a base region of a bipolar PNP transistor.
[0035] In addition, the first P+ region 11, the P- region 9, and the first N+ region 7 formed in the N well region 5, the P- region 9 surrounds the first P+ region 11 on the periphery, the first N+ region 7 surrounds the P- region 9 on the periphery (as shown in Figure 3 ), the P- region 9 is a certain distance away from the first P+ region 11 and has an equal distance on the periphery, and the first N+ region 7 is a certain distance away from the P- region 9; in addition, the first field oxide region 20, the second field oxide region 21, the third field oxide region 22, and the fourth field oxide region 23 formed between the P- region 9 and the first N+ region 7, between the first N+ region 7 and the third P+ region 12, between the third P+ region 12 and the second N+ region 8, and outside the second N+ region 8 play a role in isolation.
[0036] In addition, as shown in Figures 3 to 5 , the shape of the first P+ region 11 includes any one of a circle, a square, and a polygon.
[0037] Specifically, as shown in Figure 3 , the shape of the first P+ region 11 is a square; as shown in Figure 4 , the shape of the first P+ region 11 is a circle; and as shown in Figure 5 , the shape of the first P+ region 11 is a polygon.
[0038] The specific shape of the first P+ region 11 can be selected as required, and embodiments of the present application are not limited in this respect.
[0039] As another embodiment of the present application, an integrated circuit is provided, wherein the bipolar PNP transistor described above is included.
[0040] It should be understood that the integrated circuit in embodiments of the present application adopts the bipolar PNP transistor described above, and the problem of false opening does not occur when the PNP transistor works at high temperature, thereby avoiding the problem of abnormal work of the PNP transistor working at high temperature, and further ensuring the stability and reliability of the integrated circuit.
[0041] It should be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited in this respect. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the scope of protection of the present application.
Claims
1. A bipolar PNP transistor, characterized by The bipolar PNP transistor comprises: a silicon substrate; an N-type buried layer located in the silicon substrate and extending from the upper surface of the silicon substrate to the interior of the silicon substrate, the depth of the N-type buried layer being less than the depth of the silicon substrate, and the cross-sectional width of the N-type buried layer being less than the cross-sectional width of the silicon substrate; an epitaxial layer located on the upper surface of the silicon substrate and covering the upper surface of the silicon substrate; a P-type recessed isolation region located in the epitaxial layer and corresponding to the upper surface of the N-type buried layer; an N-well region located in the recessed region formed by the P-type recessed isolation region and surrounded by the P-type recessed isolation region; a deep N-well region located in the epitaxial layer and arranged around the P-type recessed isolation region, the deep N-well region and the P-type recessed isolation region being located on the upper surface of the N-type buried layer; a first P+ region, a second P+ region, a first N+ region and a P- region are arranged in the N-well region, the P- region is spaced apart from and arranged around the first P+ region, the first N+ region is spaced apart from and arranged around the P- region, and the second P+ region is located in the P- region; a third P+ region is arranged in the P-type recessed isolation region, the third P+ region is spaced apart from and arranged around the first N+ region; a second N+ region is arranged in the deep N-well region, the second N+ region is spaced apart from and arranged around the third P+ region; the first P+ region is formed as an emitter region of the bipolar PNP transistor, the P- region is formed as a collector region of the bipolar PNP transistor, and the N-well region is formed as a base region of the bipolar PNP transistor.
2. The bipolar PNP transistor of claim 1, wherein The P-type recessed isolation region comprises a deep P-type well region located on the upper surface of the N-type buried layer and a P-well region located on the upper surface of the deep P-type well region and arranged around the N-well region.
3. The bipolar PNP transistor of claim 2, wherein The third P+ region is located in the P-well region.
4. The bipolar PNP transistor of claim 1, wherein The bipolar PNP transistor further comprises a field oxide layer formed on the upper surface of the epitaxial layer.
5. The bipolar PNP transistor of claim 4, wherein The field oxide layer comprises a first field oxide region located between the first N+ region and the P- region, a second field oxide region located between the first N+ region and the third P+ region, a third field oxide region located between the third P+ region and the second N+ region, and a fourth field oxide region located at the periphery of the second N+ region.
6. The bipolar PNP transistor of claim 1, wherein The first P+ region is an emitter terminal of the bipolar PNP transistor, the second P+ region is a collector terminal of the bipolar PNP transistor, the first N+ region is a base terminal of the bipolar PNP transistor, the third P+ region is a 0 potential terminal of the bipolar PNP transistor, and the second N+ region is a power supply potential terminal of the bipolar PNP transistor.
7. The two-stage PNP transistor according to claim 1, wherein The shape of the first P+ region comprises any one of a circle, a square and a polygon.
8. An integrated circuit, characterized by The bipolar PNP transistor comprises any one of claims 1 to 7.