Control resource set transmission

Abstract

Aspects of the disclosure relate to controlling resource set transmission. In one aspect of the solution of the present disclosure, a terminal device receives a configuration of a first CORESET via a transceiver. Based on the configuration and a predefined number of PRBs to be punctured from the first CORESET, the terminal device determines a second CORESET. Based on the configuration, the terminal device determines a mapping type of CCE-to-REG mapping of the second CORESET. In this manner, the CORESET may be punctured as a CORESET with less PRBs in a suitable method for transmission in a narrow bandwidth channel. A mapping type of a CCE to REG mapping for a PDDCH transmission may be determined. Therefore, the implementation workload of the terminal equipment side is reduced, and the communication performance is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to wireless communications, and more particularly to an apparatus, a processor, a method, and a computer readable medium for control resource set transmission. BACKGROUND

[0002] A wireless communication system can include one or more network communication devices (such as a base station), which can also be referred to as an eNodeB (eNB), a next generation NodeB (gNB), or other suitable terminology. Each network communication device (such as a base station) can support wireless communication for one or more user communication devices, which can also be referred to as user equipment (UE) or other suitable terminology. The wireless communication system can support wireless communication with one or more user communication devices by utilizing resources (e.g., time resources (e.g., symbols, time slots, subframes, frames, etc.) or frequency resources (e.g., subcarriers, carriers)) of the wireless communication system. In addition, the wireless communication system can support wireless communication across various radio access technologies, including third generation (3G) radio access technologies, fourth generation (4G) radio access technologies, fifth generation (5G) radio access technologies, and other suitable radio access technologies beyond 5G (e.g., sixth generation (6G)).

[0003] A minimum bandwidth (BW) of 5MHz channel is defined in Release 15. While New Radio (NR) can support multiple channel bandwidths through flexible numerology, channel bandwidths less than 5MHz are not supported at this time. On the other hand, some operating networks, such as power distribution networks and railway communications, are now seeking to invest in the future by deploying 5G services, but their operating channel BW is lower than 5MHz. Based on this, NR has begun specification work to support channel BWs lower than 5MHz. There are some issues that need to be addressed. SUMMARY

[0004] The present disclosure relates to a method, an apparatus, and a system supporting control resource set transmission.

[0005] Some implementations of the method and apparatus described herein can include receiving, via a transceiver, a configuration of a first control resource set (CORESET), determining a second CORESET based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET, and determining a mapping type of a control resource element (CCE) to resource element group (REG) mapping of the second CORESET based on the configuration. The terminal device can experience a reduction in implementation effort. Thus, the communication performance is improved.

[0006] In some implementations of the methods and apparatuses described herein, the configuration can include a PRB offset indicating one of: a first frequency gap between an un-punctured synchronization signal block (SSB) and the first CORESET; or a second frequency gap between a punctured SSB and the first CORESET.

[0007] Some implementations of the methods and apparatuses described herein can further include determining a frequency location of the second CORESET based on the PRB offset, a predefined number of PRBs to puncture from the first CORESET, and a frequency location of the un-punctured SSB.

[0008] In some implementations of the methods and apparatuses described herein, the PRB offset can be selected from a set of candidate PRB offsets, and the set of candidate PRB offsets can be determined based on the predefined number of PRBs to puncture from the first CORESET.

[0009] In some implementations of the methods and apparatuses described herein, the predefined number of PRBs to puncture from the first CORESET can be the same or different in a case where the first CORESET includes 2 symbols as compared to a case where the first CORESET includes 3 symbols.

[0010] In some implementations of the methods and apparatuses described herein, determining the second CORESET can include one of: puncturing a lowest 2 CCEs or a lowest 6 PRBs of the first CORESET in a case where the first CORESET includes 2 symbols; or puncturing a lowest 2 CCEs or a lowest 4 PRBs of the first CORESET in a case where the first CORESET includes 3 symbols.

[0011] In some implementations of the methods and apparatuses described herein, determining the mapping type can include determining the mapping type to be an interleaved CCE-to-REG mapping or a non-interleaved CCE-to-REG mapping based on a number of symbols of the first CORESET.

[0012] In some implementations of the methods and apparatuses described herein, determining the mapping type based on the number of symbols can include one of: determining the mapping type to be an interleaved CCE-to-REG mapping in a case where the number of symbols is 2; or determining the mapping type to be a non-interleaved CCE-to-REG mapping in a case where the number of symbols is 3.

[0013] Some implementations of the methods and apparatuses described herein can further include determining a shift value for a CCE-to-REG mapping of the second CORESET based on the configuration.

[0014] In some implementations of the method and apparatus described herein, determining the shift value can include determining the shift value based on a mapping type or a number of symbols of the first CORESET.

[0015] In some implementations of the method and apparatus described herein, determining the shift value based on the mapping type can include one of: determining the shift value as an identifier (ID) of a configured cell in which the first CORESET is received in a case that the mapping type is an interleaved CCE-to-REG mapping; or determining the shift value as a predetermined value in a case that the mapping type is a non-interleaved CCE-to-REG mapping.

[0016] In some implementations of the method and apparatus described herein, determining the shift value based on the number of symbols can include one of: determining the shift value as an ID of a configured cell in which the first CORESET is received in a case that the number of symbols is 2; or determining the shift value as a predetermined value in a case that the number of symbols is 3.

[0017] In a second aspect of the solution, a network device can experience improved communication performance by transmitting, via a transceiver, a configuration of a first control resource set (CORESET) to a terminal device; determining a second CORESET based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET; and determining a mapping type of a control resource element (CCE)-to-resource element group (REG) mapping of the second CORESET based on the configuration.

[0018] In some implementations of the method and apparatus described herein, the configuration can include a PRB offset indicating one of: a first frequency gap between a non-punctured synchronization signal block (SSB) and the first CORESET; or a second frequency gap between a punctured SSB and the first CORESET.

[0019] Some implementations of the method and apparatus described herein can further include determining a frequency location of the second CORESET based on the PRB offset, the predefined number of PRBs to be punctured from the first CORESET, and a frequency location of the non-punctured SSB.

[0020] Some implementations of the method and apparatus described herein can further include determining a set of candidate PRB offsets based on the predefined number of PRBs to be punctured from the first CORESET; and selecting the PRB offset from the set of candidate PRB offsets.

[0021] In some implementations of the methods and apparatuses described herein, the predefined number of PRBs to puncture from the first CORESET can be the same or different in the case where the first CORESET includes 2 symbols as in the case where the first CORESET includes 3 symbols.

[0022] In some implementations of the methods and apparatuses described herein, determining the second CORESET can include one of: determining that the lowest 2 CCEs or the lowest 6 PRBs of the first CORESET are to be punctured in the case where the first CORESET includes 2 symbols; or determining that the lowest 2 CCEs or the lowest 4 PRBs of the first CORESET are to be punctured in the case where the first CORESET includes 3 symbols.

[0023] In some implementations of the methods and apparatuses described herein, determining the mapping type can include determining the mapping type to be an interleaved CCE-to-REG mapping or a non-interleaved CCE-to-REG mapping based on the number of symbols of the first CORESET.

[0024] In some implementations of the methods and apparatuses described herein, determining the mapping type based on the number of symbols can include one of: determining the mapping type to be an interleaved CCE-to-REG mapping in the case where the number of symbols is 2; or determining the mapping type to be a non-interleaved CCE-to-REG mapping in the case where the number of symbols is 3.

[0025] Some implementations of the methods and apparatuses described herein can further include determining a shift value for the CCE-to-REG mapping of the second CORESET based on the configuration.

[0026] In some implementations of the methods and apparatuses described herein, determining the shift value can include determining the shift value based on the mapping type or the number of symbols of the first CORESET.

[0027] In some implementations of the methods and apparatuses described herein, determining the shift value based on the mapping type can include one of: determining the shift value to be an identifier (ID) of a configured cell in which the first CORESET is transmitted in the case where the mapping type is an interleaved CCE-to-REG mapping; or determining the shift value to be a predetermined value in the case where the mapping type is a non-interleaved CCE-to-REG mapping.

[0028] In some implementations of the methods and apparatuses described herein, determining the shift value based on the number of symbols can include one of: determining the shift value to be an ID of a configured cell in which the first CORESET is transmitted in the case where the number of symbols is 2; or determining the shift value to be a predetermined value in the case where the number of symbols is 3. BRIEF DESCRIPTION OF DRAWINGS

[0029] FIG. 1A FIG. illustrates an example of a wireless communications system that supports control resource set transmissions in accordance with aspects of the present disclosure.

[0030] FIG. 1B FIG. illustrates an example of a synchronization signal block (SSB) associated with aspects of the present disclosure.

[0031] FIG. 1C FIG. illustrates an example multiplexing pattern of a SSB and a control resource set (CORESET) associated with aspects of the present disclosure.

[0032] FIG. 1D FIG. illustrates an example mapping method of control resource element (CCE) to resource element group (REG) mapping in a CORESET associated with aspects of the present disclosure.

[0033] FIG. 1E FIG. illustrates another example mapping method of CCE to REG mapping in a CORESET associated with aspects of the present disclosure.

[0034] FIG. 1F FIG. illustrates an example CORESET with 4 full CCEs and 2 partial CCEs associated with aspects of the present disclosure.

[0035] FIG. 1G FIG. illustrates an example CORESET with a set of full CCEs associated with aspects of the present disclosure.

[0036] FIG. 2 FIG. illustrates an example signaling diagram illustrating an example process for supporting control resource set transmissions in accordance with aspects of the present disclosure.

[0037] FIG. 3A FIG. illustrates an example multiplexing pattern of a SSB and a CORESET with 2 symbols to support control resource set transmissions in accordance with aspects of the present disclosure.

[0038] FIG. 3B FIG. illustrates another example multiplexing pattern of a SSB and a CORESET with 2 symbols to support control resource set transmissions in accordance with aspects of the present disclosure.

[0039] FIG. 3C FIG. illustrates another example multiplexing pattern of a SSB and a CORESET with 2 symbols to support control resource set transmissions in accordance with aspects of the present disclosure.

[0040] FIG. 3DAnother example multiplexing pattern of an SSB and a CORESET with 2 symbols to support control resource set transmissions is illustrated in accordance with aspects of the present disclosure.

[0041] FIG. 4A An example multiplexing pattern of an SSB and a CORESET with 2 symbols to support control resource set transmissions is illustrated in accordance with aspects of the present disclosure.

[0042] FIG. 4B Another example multiplexing pattern of an SSB and a CORESET with 2 symbols to support control resource set transmissions is illustrated in accordance with aspects of the present disclosure.

[0043] FIG. 4C Another example multiplexing pattern of an SSB and a CORESET with 2 symbols to support control resource set transmissions is illustrated in accordance with aspects of the present disclosure.

[0044] FIG. 4D Another example multiplexing pattern of an SSB and a CORESET with 2 symbols to support control resource set transmissions is illustrated in accordance with aspects of the present disclosure.

[0045] FIG. 5 to FIG. 6 An example of a device that supports control resource set transmissions is illustrated in accordance with aspects of the present disclosure.

[0046] FIG. 7 to FIG. 8 An example of a processor that supports control resource set transmissions is illustrated in accordance with aspects of the present disclosure.

[0047] FIG. 9 to FIG. 10 A flow diagram of a method that supports control resource set transmissions is illustrated in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0048] The principles of the present disclosure will now be described with reference to some embodiments. It should be understood that these embodiments are described for illustrative purposes only and help the understanding of and enablement of the present disclosure, without imposing any limitation on the scope of the present disclosure. The present disclosure described herein can be implemented in various ways other than those described below.

[0049] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0050] References in the disclosure to “one embodiment,” “an example embodiment,” “an embodiment,” and the like, mean that a described embodiment can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of those skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0051] It should be understood that although the terms “first” and “second” and the like can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the embodiments. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed terms.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “has,” “having,” “includes” and / or “including” when used herein, specify the presence of stated features, elements and / or components etc. but do not preclude the presence or addition of one or more other features, elements, components and / or combinations thereof. As used herein, “at least one of ” and “one or more of ” and the like, means at least one of any one of the elements in the list of two or more elements, or at least any two or more of the elements in the list of two or more elements.

[0053] Aspects of the disclosure are described in the context of a wireless communication system.

[0054] FIG. 1AAn example of a wireless communications system 100 that supports control resource set transmissions is illustrated in accordance with aspects of the present disclosure. The wireless communications system 100 can include one or more network entities 102 (also referred to as network equipment (NE)), one or more UEs 104, a core network 106, and a packet data network 108. The wireless communications system 100 can support various radio access technologies. In some implementations, the wireless communications system 100 can be a 4G network, such as an LTE network or a LTE-Advanced (LTE-A) network. In some other implementations, the wireless communications system 100 can be a 5G network, such as an NR network. In other implementations, the wireless communications system 100 can be a combination of 4G and 5G networks, or other suitable radio access technologies, including Institute of Electrical and Electronics Engineers (IEEE) 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20. The wireless communications system 100 can support radio access technologies other than 5G. Further, the wireless communications system 100 can support technologies such as time division multiple access (TDMA), frequency division multiple access (FDMA), or code division multiple access (CDMA), among other technologies.

[0055] The one or more network entities 102 can be dispersed throughout the geographic region to form the wireless communications system 100. One or more of the network entities 102 described herein can be, or include, or can be referred to as, a network node, a base station, a network element, a radio access network (RAN), a base transceiver station, an access point, a NodeB, an eNodeB (eNB), a next generation NodeB (gNB), or other suitable terminology. The network entities 102 and the UEs 104 can communicate via communication links 110, which can be wireless or wired connections. For example, the network entities 102 and the UEs 104 can perform wireless communications (e.g., receive signaling, transmit signaling) over a Uu interface.

[0056] The network entity 102 can provide a geographic coverage area 112 for which the network entity 102 supports service (e.g., voice, video, packet data, messaging, broadcast, etc.) to one or more UEs 104 within the geographic coverage area 112. For example, the network entity 102 and UEs 104 can support wireless communication of signals for service (e.g., voice, video, packet data, messaging, broadcast, etc.) in accordance with one or more wireless access technologies. In some implementations, the network entity 102 can be mobile, such as a satellite associated with a non-terrestrial network. In some implementations, different geographic coverage areas 112 associated with the same or different radio access technologies can overlap, but different geographic coverage areas 112 can be associated with different network entities 102. Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0057] The one or more UEs 104 can be dispersed throughout the geographic region of the wireless communication system 100. A UE 104 can include or can be referred to as a mobile device, wireless device, remote device, remote unit, handset, subscriber device, or some other suitable terminology. In some implementations, a UE 104 can be referred to as a unit, a station, a terminal, or a client, among other examples. Additionally or alternatively, a UE 104 can be referred to as an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a machine type communications (MTC) device, among other examples. In some implementations, a UE 104 can be a stationary unit. In some other implementations, a UE 104 can be a mobile unit.

[0058] The one or more UEs 104 can be devices in different forms or having different capabilities. FIG. 1A Some examples of UEs 104 are illustrated in FIG. 1. A UE 104 can be capable of communicating with various types of devices, such as the network entity 102, other UEs 104, or network devices (e.g., the core network 106, the packet data network 108, a relay device, an integrated access and backhaul (IAB) node, or another network device), as shown in FIG. 1. Additionally or alternatively, a UE 104 can support communication with other network entities 102 or UEs 104 that can act as relays in the wireless communication system 100. FIG. 1A Some examples of UEs 104 are illustrated in FIG. 1. A UE 104 can be capable of communicating with various types of devices, such as the network entity 102, other UEs 104, or network devices (e.g., the core network 106, the packet data network 108, a relay device, an integrated access and backhaul (IAB) node, or another network device), as shown in FIG. 1. Additionally or alternatively, a UE 104 can support communication with other network entities 102 or UEs 104 that can act as relays in the wireless communication system 100.

[0059] The UEs 104 can be configured to connect directly to one another via a device-to-device (D2D) communication link 110. In some implementations, the D2D communication link 110 can be a cellular D2D communication link 110 that utilizes a licensed spectrum (e.g., compared to a wireless local area network (WLAN) communication link that utilizes an unlicensed spectrum). In some implementations, the D2D communication link 110 can be a sidelink communication link 110 that utilizes a shared spectrum (e.g., licensed, unlicensed, or international mobile telecommunications (IMT) frequency spectrum allowed to be used by the cellular industry). In some implementations, the D2D communication link 110 can be a vehicle-to-everything (V2X) communication link 110 that utilizes a shared spectrum (e.g., licensed, unlicensed, or IMT frequency spectrum allowed to be used by the cellular industry). In some implementations, the D2D communication link 110 can be a vehicle-to-vehicle (V2V) communication link 110, a vehicle-to-infrastructure (V2I) communication link 110, or a vehicle-to-pedestrian (V2P) communication link 110 that utilizes a shared spectrum (e.g., licensed, unlicensed, or IMT frequency spectrum allowed to be used by the cellular industry). In some implementations, the D2D communication link 110 can be a cellular V2X (C-V2X) communication link 110. In some implementations, the D2D communication link 110 can be a PC5 interface.

[0060] The network entities 102 can support communication with the core network 106, or with another network entity 102, or both. For example, the network entities 102 can interface with the core network 106 through one or more backhaul links 116 (e.g., via an SI, N2, N3, or another network interface). The network entities 102 can communicate with one another over backhaul links 116 (e.g., via an X2, Xn, or another network interface). In some implementations, the network entities 102 can communicate directly with one another (e.g., between network entities 102). In some other implementations, the network entities 102 can communicate with or indirectly through (e.g., via the core network 106) one another. In some implementations, one or more of the network entities 102 can include subcomponents, such as an access network entity, which can be an example of an access node controller (ANC). The ANC can communicate with one or more UEs 104 through one or more other access network transmission entities (which can be referred to as radio heads, smart radio heads, or transmission reception points (TRPs)).

[0061] In some implementations, the network entities 102 can be configured in a disaggregated architecture that can be configured to utilize a protocol stack that is physically or logically distributed among two or more network entities 102, such as an integrated access backhaul (IAB) network, an open RAN (O-RAN) (e.g., a network configuration sponsored by the O-RAN Alliance), or a virtualized RAN (vRAN) (e.g., a cloud RAN (C-RAN)). For example, the network entities 102 can include one or more of a central unit (CU), a distributed unit (DU), a radio unit (RU), a RAN intelligent controller (RIC) (e.g., a near real-time RIC (near-RT RIC), a non-real-time RIC (non-RT RIC)), a service management and orchestration (SMO) system, or any combination thereof.

[0062] A RU can also be referred to as a radio head, intelligent radio head, remote radio head (RRH), remote radio unit (RRU), or transmission reception point (TRP). In a disaggregated RAN architecture, one or more components of the network entity 102 can be collocated, or one or more components of the network entity 102 can be located at distributed locations (e.g., separate physical locations). In some implementations, one or more network entities 102 of a disaggregated RAN architecture can be implemented as virtual units (e.g., virtual CUs (VCUs), virtual DUs (VDUs), virtual RUs (VRUs)).

[0063] The functional split between the CU, the DU, and the RU can be flexible and can support different functions depending on the functions (e.g., network layer functions, protocol layer functions, baseband functions, radio frequency functions, and any combination thereof) performed at the CU, the DU, or the RU. For example, a functional split of a protocol stack can be employed between the CU and the DU, such that the CU can support one or more layers of the protocol stack and the DU can support one or more different layers of the protocol stack. In some implementations, the CU can host upper layer protocol layer (e.g., layer 3 (L3), layer 2 (L2)) functions and signaling (e.g., radio resource control (RRC), service data adaptation protocol (SDAP), packet data convergence protocol (PDCP)). The CU can be connected to one or more DUs or RUs, and the one or more DUs or RUs can host lower protocol layers, such as layer 1 (LI) (e.g., physical (PHY) layer) or L2 (e.g., radio link control (RLC) layer, medium access control (MAC) layer) functions and signaling, and each can be controlled at least in part by the CU 160.

[0064] Additionally or alternatively, a functional split of a protocol stack can be employed between the DU and the RU, such that the DU can support one or more layers of the protocol stack and the RU can support one or more different layers of the protocol stack. The DU can support one or more different cells (e.g., via one or more RUs). In some implementations, the functional split between the CU and the DU or between the DU and the RU can be within a protocol layer (e.g., some functions of a protocol layer can be performed by one of the CU, the DU, or the RU, while other functions of the protocol layer are performed by a different one of the CU, the DU, or the RU).

[0065] A CU can be further functionally split into a CU control plane (CU-CP) and a CU user plane (CU-UP) function. A CU can be connected to one or more DUs via a midhaul communication link (e.g., Fl, Fl-c, Fl-u), and a DU can be connected to one or more RUs via a front-haul communication link (e.g., a front-haul (FH) interface). In some implementations, a midhaul or front-haul communication link can be implemented according to an interface (e.g., a channel) between layers of a protocol stack supported by respective network entities 102 communicating via such a communication link.

[0066] The core network 106 can support user authentication, access authorization, tracking, connection, and other access, routing, or mobility functions. The core network 106 can be an evolved packet core (EPC) or 5G core (5GC), which can include a control plane entity that manages access and mobility (e.g., a mobility management entity (MME), an access and mobility management function (AMF)) and a user plane entity that routes packets or interconnections to external networks (e.g., a serving gateway (S-GW), a packet data network (PDN) gateway (P-GW), or a user plane function (UPF)). In some implementations, the control plane entity can manage non-access stratum (NAS) functions such as mobility, authentication, and bearer management (e.g., data bearer, signaling bearer, etc.) for one or more UEs 104 served by the one or more network entities 102 associated with the core network 106.

[0067] The core network 106 can communicate with a packet data network 108 through one or more backhaul links 116 (e.g., via SI, N2, N3, or another network interface). The packet data network 108 can include an application server 118. In some implementations, the one or more UEs 104 can communicate with the application server 118 through the core network 106. A UE 104 can establish a session (e.g., a protocol data unit (PDU) session, etc.) with the core network 106 via a network entity 102. The core network 106 can use the established session (e.g., an established PDU session) to route traffic (e.g., control information, data, etc.) between the UE 104 and the application server 118. A PDU session can be an example of a logical connection between the UE 104 and the core network 106 (e.g., one or more network functions of the core network 106).

[0068] In the wireless communication system 100, the network entity 102 and the UE 104 can perform various operations (e.g., wireless communications) using resources (e.g., time resources (e.g., symbols, slots, subframes, frames, etc.) or frequency resources (e.g., subcarriers, carriers)) of the wireless communication system 100. In some implementations, the network entity 102 and the UE 104 can support different resource structures. For example, the network entity 102 and the UE 104 can support different frame structures. In some implementations, such as in 4G, the network entity 102 and the UE 104 can support a single frame structure. In some other implementations, such as in 5G and other suitable radio access technologies, the network entity 102 and the UE 104 can support various frame structures (i.e., multiple frame structures). The network entity 102 and the UE 104 can support various frame structures based on one or more numerologies.

[0069] One or more numerologies can be supported in the wireless communication system 100, and a numerology can include a subcarrier spacing and a cyclic prefix. A first numerology (e.g., a normal cyclic prefix) can be associated with a first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, a first numerology (e.g., a normal cyclic prefix) associated with a first subcarrier spacing (e.g., 15 kHz) can utilize one slot per subframe. μ μ A second numerology (e.g., an extended cyclic prefix) can be associated with a second subcarrier spacing (e.g., 30 kHz) and an extended cyclic prefix. A third numerology (e.g., a normal cyclic prefix) can be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth numerology (e.g., a normal cyclic prefix) can be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth numerology (e.g., a normal cyclic prefix) can be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix. μ μ A second numerology (e.g., an extended cyclic prefix) can be associated with a second subcarrier spacing (e.g., 30 kHz) and an extended cyclic prefix. A third numerology (e.g., a normal cyclic prefix) can be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth numerology (e.g., a normal cyclic prefix) can be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth numerology (e.g., a normal cyclic prefix) can be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix. μ μ A second numerology (e.g., an extended cyclic prefix) can be associated with a second subcarrier spacing (e.g., 30 kHz) and an extended cyclic prefix. A third numerology (e.g., a normal cyclic prefix) can be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth numerology (e.g., a normal cyclic prefix) can be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth numerology (e.g., a normal cyclic prefix) can be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix.

[0070] Time intervals of resources (e.g., communication resources) can be organized as frames, which can also be referred to as radio frames. Each frame can have a duration of, for example, 10 milliseconds (ms). In some implementations, each frame can include multiple subframes. For example, each frame can include 10 subframes, and each subframe can have a duration of, for example, 1 ms. In some implementations, each frame can have the same duration. In some implementations, each subframe of a frame can have the same duration.

[0071] ​​​Additionally or alternatively, time intervals of resources (e.g., communication resources) can be organized as slots, for example. Each slot can include a number (e.g., quantity) of symbols (e.g., OFDM symbols). In some implementations, the number (e.g., quantity) of symbols in a slot can depend on the numerology used. For example, a first numerology, a second numerology, a third numerology, a fourth numerology, and a fifth numerology (i.e., μ = 0, μ = 1, μ = 2, μ = 3, μ = 4) can utilize one slot per subframe, two slots per subframe, four slots per subframe, eight slots per subframe, and 16 slots per subframe, respectively. Each slot can include a number (e.g., quantity) of symbols (e.g., OFDM symbols). In some implementations, the number (e.g., quantity) of slots of a subframe can depend on the numerology. For a normal cyclic prefix, a slot can include 14 symbols. For an extended cyclic prefix (e.g., applicable to 60 kHz subcarrier spacing), a slot can include 12 symbols. The relationship between the number of symbols per slot, the number of slots per subframe, and the number of slots per frame can depend on the numerology for both normal and extended cyclic prefixes. It will be understood that reference to the first numerology (e.g., μ = 0) associated with a first subcarrier spacing (e.g., 15 kHz) can be used interchangeably between subframes and slots.

[0072] In the wireless communications system 100, the electromagnetic (EM) spectrum can be divided into various classes, bands, frequency channels, and so forth. For example, the wireless communications system 100 can support one or more operating bands, such as frequency range designations FR1 (410 MHz - 7.125 GHz), FR2 (24.25 GHz - 52.6 GHz), FR3 (7.125 GHz - 24.25 GHz), FR4 (52.6 GHz - 114.25 GHz), FR4a or FR4-1 (52.6 GHz - 71 GHz), and FR5 (114.25 GHz - 300 GHz). In some implementations, the network entity 102 and the UE 104 can perform wireless communications over one or more operating bands. In some implementations, FR1 can be used by the network entity 102 and the UE 104, and other devices or apparatuses, for cellular communications traffic (e.g., control information, data). In some implementations, FR2 can be used by the network entity 102 and the UE 104, and other devices or apparatuses, for short range, high data rate capabilities.

[0073] FR1 can be associated with one or more numerologies (e.g., at least three numerologies). For example, FR1 can be associated with: a first numerology (e.g., μ = 0) including a 15 kHz subcarrier spacing; a second numerology (e.g., μ = 1) including a 30 kHz subcarrier spacing; and a third numerology (e.g., μ = 2) including a 60 kHz subcarrier spacing. FR2 can be associated with one or more numerologies (e.g., at least two numerologies). For example, FR2 can be associated with: the third numerology (e.g., μ = 2) including a 60 kHz subcarrier spacing; and a fourth numerology (e.g., μ = 3) including a 120 kHz subcarrier spacing.

[0074] A minimum bandwidth of 5 MHz channel is defined in Rel. 15. While NR can support multiple channel bandwidths by flexible numerologies, channel bandwidths less than 5 MHz are not supported at this time. On the other hand, some operating networks, such as power distribution networks and railway communications, are now seeking to invest in the future by deploying 5G services, but their operating channel BW is lower than 5 MHz. Based on this, NR has begun specification work to support channel BWs lower than 5 MHz. One goal is to specify 3 MHz channel BW in some of the NR operating bands (e.g., bands n100, n8, n26, and n28).

[0075] A 3 MHz channel corresponds to 15 physical resource blocks (PRBs). 15 PRBs cannot accommodate some NR channels or signals. FIG. 1B An example of a synchronization signal block (SSB) associated with aspects of the present disclosure is illustrated. The NR synchronization signal and physical broadcast channel (SS / PBCH) block (i.e., SSB) occupies 20 resource blocks (RBs) in the frequency domain, with the primary / secondary synchronization signals (PSS / SSS) occupying 12 RBs (including guard REs) and the PBCH occupying all 20 RBs. Thus, for a 3 MHz BW channel, the PSS / SSS can be transmitted in full, while the PBCH cannot. Some SSB resources need to be punctured from both transmission and reception perspectives. It should be understood that the bandwidth of the channel is not limited to 3 MHz, and embodiments of the present disclosure are equally applicable to other suitable channel bandwidths.

[0076] In addition to SSB, legacy CORESET#0 with a transmission BW of minimum 24 PRBs, which is mainly used to schedule signals such as system information block 1 (SIB1), random access messages, etc. during initial access, cannot be used for 3MHz channel BW. CORESET#0 is configured in PBCH based on CORESET#0 configuration table. One candidate configuration is selected from the table and indicated with CORESET#0 configuration index. According to the indicated configuration index, UE can acquire SSB to CORESET#0 multiplexing pattern, number of CORESET#0 PRBs, number of CORESET#0 symbols, and PRB offset between the lowest CORESET#0 PRB and common resource block (CRB) overlapping with the lowest SSB PRB. Table 1 provides CORESET#0 configuration table for 5MHz minimum channel BW of FR1. Table 1. CORESET#0 configuration table for 5MHz minimum channel BW

[0077] As described in NR, the multiplexing of SSB and CORESET#0 of frequency range 1 follows multiplexing pattern 1, where SSB transmission BW is completely within CORESET#0 transmission BW. FIG. 1C An example multiplexing pattern of SSB and control resource set (CORESET) associated with aspects of the present disclosure is illustrated. As FIG. 1C As shown, the multiplexing pattern of SSB and CORESET#0 is multiplexing pattern 1. The offset in frequency domain between the lowest position of SSB and the lowest position of CORESET#0 is 2 PRBs, and the offset is indicated by CORESET#0 configuration index shown in Table 1. UE first detects SSB, and then can locate CORESET#0 based on the indicated PRB offset.

[0078] As can be seen from Table 1, even the CORESET#0 transmission of minimum 24 PRBs (4.32MHz, 15kHz SCS) is larger than 3MHz channel BW. Therefore, this table cannot be used for 3MHz channel BW. One approach is to acquire 15 PRBs of CORESET#0 for 3MHz channel BW by puncturing legacy 24 PRBs of CORESET#0. The issue of which PRBs in 24 PRBs are punctured for 15 PRBs of CORESET#0 needs to be addressed.

[0079] The basic unit for physical downlink control channel (PDCCH) transmission in a CORESET is a CCE. One CCE corresponds to 6 REGs, each containing one PRB (12 subcarriers) in the frequency domain and 1 symbol in the time domain. REGs are sequentially numbered in a time-first, frequency-second manner in the CORESET. REGs are further grouped into REG bundles in sequence. A UE can assume the same precoding is used for REGs in the same REG bundle, and joint channel estimation should be performed by the UE in REGs in the same REG bundle.

[0080] One CCE is associated with a REG bundle. By definition, a REG bundle i is composed of REGs where L is the REG bundle size, i = 0, 1, …, and is the number of REGs in the CORESET. The CCE-to-REG mapping of a CORESET can be interleaved or non-interleaved and is described by the REG bundle. Specifically, a CCE j is composed of REG bundles where is the interleaver and is defined as follows: r = 0, 1, …, R - 1 c = 0, 1, …, C - 1 where for CORESET#0, it is specified that is the number of PRBs in the frequency domain, is the number of OFDM symbols in the time domain. L is equal to 6, which means that one REG bundle contains 6 REGs, which is the same size as a CCE. R is the interleaver size and is equal to 2. i.e., the identifier (ID) of the cell.

[0081] Thus, with the parameter , the CCE-to-REG mapping is different in different cells, which facilitates randomizing the CCEs contained in PDCCH candidates across cells, which can mitigate inter-cell interference. The first CCE (CCE0) of CORESET#0 is from REG bundle (REGB) Start. Assume the number of REG bundles is K (K is always even for CORESET#0), the CCEs in CORESET#0 are numbered as: - The value "2" (here, the value "2" corresponds to "R" in the formula) maps to REG B X+i, i=0, 1, 2, …, K / 2-1. If X+i > K-1, the CCE numbering continues from REG B 0 in wrap-around fashion; - The value "2" (similarly, the value "2" corresponds to "R" in the formula) maps to REG B X+i+K / 2, i=0, 1, 2, …, K / 2-1. If X+i+K / 2 > K-1, the CCE numbering continues from REG B 0 in wrap-around fashion.

[0082] FIG. 1D And FIG. 1E Figures illustrate two example mapping methods of CCE to REG mapping in CORESET associated with aspects of the present disclosure. FIG. 1D And FIG. 1E shows how CCE to REG is mapped in CORESET#0 with 24 PRBs, 3 symbols, and CORESET#0 consists of 12 REG B groups. In FIG. 1D , n shift = 1, and CCE0 maps to REG B 1, while in FIG. 1E , CCE0 maps to REG B 2, where n shift = 2.

[0083] PDCCH is transmitted in a set of CCEs of a CORESET. The number of CCEs used for PDCCH transmission is also referred to as a particular aggregation level. An aggregation level n supports one or more PDCCH candidates, each candidate containing n CCEs. For PDCCH in CORESET#0, the supported aggregation levels and the maximum number of PDCCH candidates per aggregation level are shown in Table 2 below. Table 2. CCE aggregation levels for CORESET#0

[0084] The CCEs of a candidate of an aggregation level (AL) are determined by a hash function. Tables 3a and 3b show the CCEs in each candidate per aggregation level for CORESET#0 with 2 symbols and 3 symbols, respectively. Table 3a: PDCCH candidates for CORESET#0 (24 PRBs, 2 symbols) Table 3b: PDCCH candidates for CORESET#0 (24 PRBs, 3 symbols)

[0085] For PBCH and CORESET#0 of 3MHz channel BW, PBCH transmission bandwidth is 12 PRBs. The upper 4 PRBs and lower 4 PRBs of NRPBCH of 20 PRBs are punctured. The maximum number of CORESET#0 symbols is 3. The minimum number of CORESET#0 symbols is 2. SSB and CORESET#0 multiplexing mode 1 is used. REG bundle size = 6.

[0086] Both 12 PRBs and 15 PRBs of CORESET#0 are supported. In the case of 12 PRBs, legacy interleaved (R = 2) CORESET CCE to REG mapping is used, where i.e., indicating 12 PRBs need not be punctured.

[0087] In the case of 15 PRBs, CORESET#0 is punctured from 24 PRBs of legacy CORESET#0 of 5MHz channel BW. Both interleaved (legacy interleaver size R = 2) and non-interleaved mapping are supported. Some entries in the configuration table of 3MHz channel BW of CORESET#0 are related to interleaved mapping, while some entries are non-interleaved mapping. A single table of up to 16 entries can accommodate both cases.

[0088] Therefore, when PRBs of 24 PRBs are punctured for CORESET#0 of 15 PRBs, since channel estimation is done per CCE, it is expected that CORESET#0 of 15 PRBs contains a complete set of CCEs of the legacy CORESET#0. FIG. 1F An example of CORESET#0 of 15 PRBs with 4 complete CCEs and 2 partial CCEs is illustrated, which is undesirable, associated with aspects of the present disclosure. FIG. 1G An example of CORESET#0 of 15 PRBs with a complete set of CCEs is illustrated, associated with aspects of the present disclosure.

[0089] Further, for PRB offset, one option is that it indicates the frequency gap between the un-punctured SSB and the un-punctured CORESET#0. Further, it is expected that the same PDCCH detection performance can be achieved across cells, which requires the maximum number of available CCEs of an AL to be the same across cells. According to these requirements, issues of how to locate the 15-PRB CORESET#0 in the frequency domain, which entries correspond to the interleaving in the CORESET#0 configuration table, which entries correspond to the non-interleaving in the CORESET#0 configuration table, and how to perform CCE-to-REG mapping for the 15-PRB CORESET#0 need to be addressed. It should be understood that CORESET#0 is used for illustrative purposes only and does not represent any limitation, and embodiments of the present disclosure are equally applicable to other similar control resource sets.

[0090] In view of the above discussion, embodiments of the present disclosure provide a solution for control resource set transmission. In one aspect of the solution of the present disclosure, a terminal device receives, via a transceiver, a configuration of a first CORESET. Based on the configuration and a predefined number of PRBs to be punctured from the first CORESET, the terminal device determines a second CORESET. Based on the configuration, the terminal device determines a mapping type of CCE-to-REG mapping of the second CORESET. In this way, a CORESET can be punctured to have fewer PRBs in a suitable method for transmission in a narrow bandwidth channel. The mapping type of CCE-to-REG mapping for PDDCH transmission can be determined. Therefore, the implementation workload at the terminal device side is mitigated, and the communication performance is improved. Reference will be made to the following detailed description of the embodiments of the present disclosure. FIG. 2 to FIG. 10 The principles and implementations of the embodiments of the present disclosure are described in detail.

[0091] FIG. 2 An example signaling diagram is illustrated, which illustrates an example process 200 that supports control resource set transmission according to aspects of the present disclosure. The process 200 can involve a first apparatus 210 and a second apparatus 220. The first apparatus 210 can be an example of a UE 104 in FIG. 1A and the second apparatus 220 can be a network entity 102 in FIG. 1A .

[0092] In the example process 200, the first apparatus 210 receives 203, via a transceiver, a configuration 204 of a first CORESET. Accordingly, the second apparatus 220 transmits 205 the configuration 204 of the first CORESET to the first apparatus 210. For example, the first CORESET can be an un-punctured CORESET#0 with 24 PRBs.

[0093] In some embodiments, the configuration 204 can include a PRB offset. The PRB offset can indicate a first frequency gap between the un-punctured SSB and the first CORESET. In some embodiments, the PRB offset can indicate a second frequency gap between the punctured SSB and the first CORESET.

[0094] Based on the configuration 204 and the predefined number of PRBs to puncture from the first CORESET, the first device 210 determines 207 the second CORESET. Based on the configuration and the predefined number of PRBs to puncture from the first CORESET, the second device 220 determines 207 the second CORESET. For example, the second CORESET can be a punctured CORESET#0 with 15 PRBs. In other words, the first device 210 and the second device 220 determine which PRBs of the un-punctured CORESET#0 to puncture.

[0095] In some embodiments, the predefined number of PRBs to puncture from the first CORESET in case the first CORESET includes 2 symbols is the same or different than the predefined number of PRBs to puncture from the first CORESET in case the first CORESET includes 3 symbols. In one example, the number of symbols of the first CORESET is indicated by the configuration 204.

[0096] In some embodiments, the configuration 204 can include an indication of the number of OFDM symbols. To determine the second CORESET, in case the first CORESET includes 2 symbols, the first device 210 can puncture the lowest 2 CCEs or the lowest 6 PRBs of the first CORESET. In some embodiments, to determine the second CORESET, in case the first CORESET includes 3 symbols, the first device 210 can puncture the lowest 2 CCEs or the lowest 4 PRBs of the first CORESET.

[0097] In some embodiments, to determine the second CORESET, in case the first CORESET includes 2 symbols, the second device 220 can puncture the lowest 2 CCEs or the lowest 6 PRBs of the first CORESET. In some embodiments, to determine the second CORESET, in case the first CORESET includes 3 symbols, the second device 220 can puncture the lowest 2 CCEs or the lowest 4 PRBs of the first CORESET.

[0098] In one example, a single PRB level puncturing pattern is defined and a predefined number of PRBs to be punctured from the first CORESET is defined for both CORESET#0 with 2 symbols and CORESET#0 with 3 symbols. To guarantee that the punctured CORESET#0 (i.e., 15 PRBs) contains a complete set of CCEs, the number of punctured PRBs in the low frequency region should be a multiple of 6 so that an integer number of CCEs are punctured for 2 symbols (3 punctured CCEs) or 3 symbols (2 punctured CCEs) and the 15 PRB CORESET#0 starts from the lowest location of a particular CCE and contains a complete set of CCEs. Furthermore, if multiplexing pattern 1 should be maintained between the unpunctured SSB and the unpunctured CORESET#0, puncturing 6 PRBs is one solution that can satisfy these requirements.

[0099] However, puncturing 6 PRBs cannot support fully flexible location of the punctured SSB within the 15 PRB channel BW. FIG. 3A to FIG. 3D Candidate locations of the punctured SSB of 12 PRBs within the channel BW are shown, where 0, 1, 2, and 3 PRBs of the offset between the lowest location of the punctured SSB and the lowest location of the channel BW are shown, respectively. 6 PRBs are punctured from the lowest part of the CORESET#0. As can be seen from the figure, in FIG. 3A to FIG. 3C multiplexing pattern 1 between the unpunctured SSB and the unpunctured CORESET#0 can be maintained. However, in FIG. 3D the unpunctured SSB is not fully located within the BW of the unpunctured CORESET#0, so multiplexing pattern 1 cannot be maintained.

[0100] To maintain multiplexing pattern 1 between the unpunctured SSB and the unpunctured CORESET#0 while supporting flexible location of the punctured SSB within the channel BW, it is proposed that the first device 210 assumes the same number of CCEs in the lowest part of the 24 PRB CORESET#0 are punctured for both the 2 symbol CORESET#0 and the 3 symbol CORESET#0. As one example, for the 2 symbol CORESET#0 with 15 PRBs and the 3 symbol CORESET#0 with 15 PRBs, the lowest 2 CCEs are punctured, which corresponds to 6 PRBs for the 2 symbol unpunctured CORESET#0 and 4 PRBs for the 3 symbol unpunctured CORESET#0.

[0101] In some embodiments, the first device 210 can determine the frequency location of the second CORESET based on the PRB offset, the predefined number of PRBs to be punctured from the first CORESET, and the frequency location of the unpunctured SSB.

[0102] In some embodiments, the second device 220 can determine the frequency location of the second CORESET based on the PRB offset, the predefined number of PRBs to be punctured from the first CORESET, and the frequency location of the unpunctured SSB.

[0103] In one example, to determine the location of the 15-PRB CORESET#0, the first device 210 can be indicated with a PRB offset. The PRB offset can be the frequency gap in the frequency domain between the lowest PRB of the unpunctured SSB and the lowest PRB of the unpunctured CORESET#0. Based on the indicated PRB offset and the punctured PRBs, the first device 210 can obtain the location of the punctured CORESET#0 using the following steps:

[0104] Based on the received PSS / SSS and based on the agreed puncturing pattern of the PBCH (the upper 4 PRBs and the lower 4 PRBs are punctured), the first device 210 can determine the location of the 20-PRB unpunctured SSB. Based on the location of the unpunctured SSB and the indicated PRB offset, the first device 210 can determine the location of the 24-PRB unpunctured CORESET#0. Based on the location of the unpunctured CORESET#0 and the predefined punctured PRBs of CORESET#0, the first device 210 can determine the location of the 15-PRB CORESET#0.

[0105] In some embodiments, the second device 220 can determine a set of candidate PRB offsets based on the predefined number of PRBs to be punctured from the first CORESET. Then, the second device 220 can select a PRB offset from the set of candidate PRB offsets.

[0106] In one example, for a 2-symbol CORESET#0, it still cannot support full flexibility of the PBCH location as shown in FIG. 3A to FIG. 3D For a 3-symbol CORESET#0 with 4 PRBs punctured, full flexibility of the PBCH location can be achieved. FIG. 4A to FIG. 4D The following table illustrates the full flexibility of the PBCH location for a 3-symbol CORESET#0 with 2 punctured CCEs (4 PRBs). Thus, for a 2-symbol CORESET#0, 3 out of 4 candidate locations of the PBCH are supported, while for a 3-symbol CORESET#0, all 4 candidate PBCH locations are supported. If the PBCH is located at a location not supported by the 2-symbol CORESET#0, the second device 220 can configure the 3-symbol CORESET#0.

[0107] The candidate PRB offset for CORESET#0 determination depends on the relative location of SSB and channel BW. Specifically, the PRB offset is equal to the number of punctured CORESET#0 PRBs minus the number of punctured PBCH PRBs and the frequency offset between punctured SSB and channel BW. For a 2-symbol CORESET#0 with 6 punctured PRBs, the supported PRB offsets are {2, 3, 4} PRBs, as shown in FIG. 3A to FIG. 3C For a 3-symbol CORESET#0 with 4 punctured PRBs, the supported PRB offsets are {0, 1, 2, 3} PRBs, as shown in FIG. 4A to FIG. 4D For a 3-symbol CORESET#0 with 4 punctured PRBs, the supported PRB offsets are {0, 1, 2, 3} PRBs, as shown in For a 3-symbol CORESET#0 with 4 punctured PRBs, the supported PRB offsets are {0, 1, 2, 3} PRBs, as shown in

[0108] Based on the configuration, the first apparatus 210 determines 209 a mapping type of a CCE-to-REG mapping of the second CORESET. In some embodiments, to determine the mapping type, the first apparatus 210 can determine the mapping type as an interleaved CCE-to-REG mapping or a non-interleaved CCE-to-REG mapping based on a number of symbols of the first CORESET. In one example, the number of symbols of the first CORESET is indicated by the configuration 204.

[0109] In some embodiments, to determine the mapping type based on the number of symbols, in a case that the number of symbols is 2, the first apparatus 210 can determine the mapping type as the interleaved CCE-to-REG mapping. In some embodiments, to determine the mapping type based on the number of symbols, in a case that the number of symbols is 3, the first apparatus 210 can determine the mapping type as the non-interleaved CCE-to-REG mapping.

[0110] In some embodiments, based on the configuration, the first apparatus 210 can determine a shift value of the CCE-to-REG mapping of the second CORESET. In some embodiments, to determine the shift value, the first apparatus 210 can determine the shift value based on the mapping type or the number of symbols of the first CORESET.

[0111] In some embodiments, to determine the shift value based on the mapping type, in a case that the mapping type is the interleaved CCE-to-REG mapping, the first apparatus 210 can determine the shift value as an ID of a cell in which the configuration of the first CORESET is received. In some embodiments, to determine the shift value based on the mapping type, in a case that the mapping type is the non-interleaved CCE-to-REG mapping, the first apparatus 210 can determine the shift value as a predetermined value.

[0112] In some embodiments, to determine the shift value based on the number of symbols, in case the number of symbols is 2, the first apparatus 210 can determine the shift value as the ID of the cell in which the first CORESET is received, in which the first CORESET is configured. In some embodiments, to determine the shift value based on the number of symbols, in case the number of symbols is 3, the first apparatus 210 can determine the shift value as a predetermined value.

[0113] In one example, it is determined which entries of the CORESET#0 configuration table are used for interleaved CCE-to-REG mapping, and which entries are used for non-interleaved CCE-to-REG mapping. It is assumed that the number of CCEs for CORESET#0 of 2 symbols and 3 symbols is the same. However, it also applies to the case where the number of punctured PRBs for both sizes of CORESET#0 is the same.

[0114] For CORESET#0 of 2 symbols, by reusing the equation of CCE-to-REG mapping and the determined hash function of CCEs in each PDCCH candidate, the non-interleaved CCE-REG mapping and interleaved CCE-REG mapping of CCEs contained in a CORESET of 15 PRBs and each PDCCH candidate can be obtained as follows.

[0115] Table 4 is for non-interleaved CCE-to-REG mapping, and it shows the CCEs contained in CORESET#0 of 2 symbols, and the CCEs of each PDCCH candidate of AL are equal to 4 and 8, respectively, for different n_shift values.

[0116] Table 5 is for interleaved CCE-to-REG mapping, and it shows the CCEs contained in CORESET#0 of 2 symbols, and the CCEs of each PDCCH candidate of AL are equal to 4 and 8, respectively, for different n_shift values. Table 4: Non-interleaved CCE-to-REG mapping for CORESET#0 of 2 symbols Table 5: Interleaved CCE-to-REG mapping for CORESET#0 of 2 symbols

[0117] From Table 4 (non-interleaved CCE-to-REG mapping), it can be seen that the number of available CCEs in a PDCCH candidate with AL=4 can be different for different n_shift values corresponding to different cell IDs. If uniform PDCCH detection and full PDCCH candidates with AL=4 across cells are needed, only entries N_shift mod 8=2 / 3 / 6 / 7 can be used. This requires that n_shift should be modified from a simple cell ID to a form like x=mod(cell ID, 4) and n_shift(x)=2 / 3 / 6 / 7 for x=0 / 1 / 2 / 3.

[0118] From Table 5 (interleaved CCE-to-REG mapping), it can be seen that the number of available CCEs per PDCCH candidate is the same for all n_shift values, thus achieving uniform PDCCH detection performance across cells. However, AL has up to 3 CCEs available, equal to 4 candidates. The actual aggregation levels supported are AL, and in this case, equal to 3 and 5.

[0119] From the tables, it can be seen that for non-interleaved CCE-to-REG mapping, AL equal to 4 and 5 are supported, while for interleaved CCE-to-REG mapping, AL equal to 3 and 5 are supported. Considering that finer link adaptation for PDCCH makes little sense, especially for UEs during initial access (e.g., in legacy CORESET#0, AL equal to 4, 8, and 16), and considering the standard impact of using non-interleaved CCE-to-REG mapping, as shown in Table 4, it is proposed that for 2-symbol punctured CORESET#0, only interleaved CCE-to-REG mapping is supported, and n_shift in CCE-to-REG mapping is equal to the cell ID. The CCE-to-REG mapping and the hashing function for determination of CCEs in each PDCCH candidate can fully follow the defined equations.

[0120] For 3-symbol CORESET#0, we can get the CCEs contained in a 15-PRB CORESET and the non-interleaved CCE-to-REG mapping and interleaved CCE-to-REG mapping of CCEs per PDCCH candidate, as follows.

[0121] Table 6 is for non-interleaved CCE-to-REG mapping, and it summarizes the CCEs contained in a 3-symbol CORESET#0 and the CCEs per candidate of AL for different n_shift values, equal to 4 and 8, respectively.

[0122] Table 7 is for interleaved CCE-to-REG mapping, and it summarizes the CCEs contained in a 3-symbol CORESET#0 and the CCEs per candidate of AL for different n_shift values, equal to 4 and 8, respectively. Table 6: Non-interleaved CCE-to-REG mapping for 3-symbol CORESET#0 Table 7: Interleaved CCE-to-REG mapping for 3-symbol CORESET#0

[0123] From Table 6 (non-interleaved CCE-to-REG mapping), it can be seen that for different n_shift values corresponding to different cell IDs, the number of available CCEs for AL equal to 4 and 8 PDCCH candidates can be different. If our goal is to have uniform PDCCH detection across cells and have full AL equal to 4 PDCCH candidates, while having full AL = 8 candidates, only entries with N_shift mod 12 = 2 can be used in Table 6. This requires that the n_shift value should be modified from being a function of cell ID (as in legacy) to simply n_shift = 2 for all cells.

[0124] From Table 7 (interleaved CCE-to-REG mapping), it can be seen that for different n_shift values corresponding to different cell IDs, the number of available CCEs for AL equal to 4 and 8 PDCCH candidates can be different. If our goal is to have uniform PDCCH detection across cells and have full AL = 4 PDCCH candidates, only entries marked in blue can be used. This requires that the n_shift value should be modified from being a function of cell ID (as in legacy) to a form like x = mod(cell ID, 4) and n_shift(x) = 0 / 2 / 6 / 8 for x = 0 / 1 / 2 / 3.

[0125] From the tables, it can be seen that for non-interleaved CCE-to-REG mapping, AL equal to 4 and 8 are supported, while for interleaved CCE-to-REG mapping, AL equal to 4 and 6 are supported. Non-interleaved CCE-to-REG mapping supports a maximum of 8 AL and two AL = 4 candidates, while interleaved CCE-REG mapping supports a maximum of 6 AL and only 1 AL = 4 candidate. Based on this, and based on similar considerations for 2-symbol CORESET#0, it is proposed that for punctured CORESET#0 of 3 symbols, only non-interleaved CCE-to-REG mapping is supported, and n_shift in the CCE-to-REG mapping is equal to a specific value of 2. The hashing function for determination of CCEs in each PDCCH candidate can follow the defined equation exactly.

[0126] Accordingly, it is proposed to define n_shift differently for a 2-symbol CORESET#0 and a 3-symbol CORESET#0. For a 15-PRB and 2-symbol CORESET#0, n_shift is equal to the cell ID and the interleaved CCE-to-REG mapping is selected. For a 15-PRB and 3-symbol CORESET#0, n_shift is equal to a specific value (e.g., 2) and the non-interleaved CCE-to-REG mapping is selected.

[0127] Based on the configuration, the second device 220 determines 209 a mapping type of the CCE-to-REG mapping of the second CORESET. In some embodiments, to determine the mapping type, the second device 220 can determine the mapping type as the interleaved CCE-to-REG mapping or the non-interleaved CCE-to-REG mapping based on the number of symbols of the first CORESET.

[0128] In some embodiments, to determine the mapping type based on the number of symbols, in a case that the number of symbols is 2, the second device 220 can determine the mapping type as the interleaved CCE-to-REG mapping. In some embodiments, to determine the mapping type based on the number of symbols, in a case that the number of symbols is 3, the first device 210 can determine the mapping type as the non-interleaved CCE-to-REG mapping.

[0129] In some embodiments, based on the configuration, the second device 220 can determine a shift value of the CCE-to-REG mapping of the second CORESET. In some embodiments, to determine the shift value, the second device 220 can determine the shift value based on the mapping type or the number of symbols of the first CORESET.

[0130] In some embodiments, to determine the shift value based on the mapping type, in a case that the mapping type is the interleaved CCE-to-REG mapping, the second device 220 can determine the shift value as an ID of a cell in which the configuration of the first CORESET is received. In some embodiments, to determine the shift value based on the mapping type, in a case that the mapping type is the non-interleaved CCE-to-REG mapping, the second device 220 can determine the shift value as a predetermined value.

[0131] In some embodiments, to determine the shift value based on the number of symbols, in a case that the number of symbols is 2, the second device 220 can determine the shift value as an ID of a cell in which the configuration of the first CORESET is received. In some embodiments, to determine the shift value based on the number of symbols, in a case that the number of symbols is 3, the second device 220 can determine the shift value as a predetermined value.

[0132] In summary, for both 2-symbol CORESET#0 and 3-symbol CORESET#0, a set of same CCEs or REG bundles are punctured from the lower part of the frequency region. For example, for both 2-symbol and 3-symbol CORESET#0, 2 CCEs are punctured, which correspond to 6 PRBs and 4 PRBs punctured, respectively. The separate PRB offset sets for 2-symbol and 3-symbol CORESET#0 are defined based on the number of punctured PRBs to support flexible locations of punctured SSBs within the channel BW. The location of 15-PRB CORESET#0 is determined based on the indicated PRB offset and the number of punctured PRBs. For punctured CORESET#0 of 15 PRBs, n_shift is different for interleaved and non-interleaved CCE-to-REG mapping or for different number of CORESET#0 symbols. For interleaved CCE-to-REG mapping, n_shift depends on the cell ID. For non-interleaved CCE-to-REG mapping, n_shift is a specific value.

[0133] According to aspects of the present disclosure, an example of CORESET#0 configuration table design for 3MHz channel BW is given in Table 8. Here, 15-PRB CORESET#0 is determined by puncturing different colors of 24-PRB CORESET#0 correspond to different CCE-to-REG mapping types. Table 8. CORESET#0 configuration table for 3MHz minimum channel BW

[0134] FIG. 5 An apparatus 500 that supports control resource set transmissions is illustrated in accordance with aspects of the present disclosure. The apparatus 500 can be an example of the first apparatus 210 as described herein. The apparatus 500 can support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The apparatus 500 can include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 502, a memory 504, a transceiver 506, and an optional I / O controller 508. These components can be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses). The processor 502, the memory 504, the transceiver 506, or various combinations thereof can be an example of means for performing various aspects of the present disclosure as described herein. For example, the processor 502, the memory 504, the transceiver 506, or various combinations thereof or components thereof can support a method for performing one or more of the operations described herein.

[0135] The processor 502, the memory 504, the transceiver 506, or various combinations thereof or various components thereof can be an example of means for performing various aspects of the present disclosure as described herein. For example, the processor 502, the memory 504, the transceiver 506, or various combinations thereof or components thereof can support a method for performing one or more of the operations described herein.

[0136] In some implementations, the processor 502, the memory 504, the transceiver 506, or various combinations or components thereof, can be implemented in hardware (e.g., in communication management circuitry). The hardware can include a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. The processor 502 and the memory 504 coupled with the processor 502, in some implementations, can be configured to perform one or more of the functions described herein (e.g., by the processor 502 executing instructions stored in the memory 504).

[0137] For example, the processor 502 can support wireless communication at the device 500, in accordance with examples disclosed herein. The processor 502 can be configured to be operable to support means for receiving, via a transceiver, a configuration of a first control resource set (CORESET), determining, based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET, a second CORESET, and determining, based on the configuration, a mapping type of a control resource element (CCE) to resource element group (REG) mapping of the second CORESET. The processor 502 can also be configured to be operable to support means for other actions described in the present disclosure. FIG. 2

[0138] The processor 502 can include an intelligent hardware device, (e.g., a general- purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some implementations, the processor 502 can be configured to operate a memory array using a memory controller. In some other implementations, a memory controller can be integrated into the processor 502. The processor 502 can be configured to execute computer-readable instructions stored in a memory (e.g., the memory 504) to cause the device 500 to perform various functions of the present disclosure.

[0139] ​The memory 504 can include random access memory (RAM) and read-only memory (ROM). The memory 504 can store computer-readable, computer-executable software including instructions that, when executed, cause the device 500 to perform various functions described herein. The software can be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the software can not be directly executable by the processor 502 but can cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 504 can include a basic I / O system (BIOS), which can control basic hardware or software operation such as the interaction with peripheral components or devices.

[0140] The I / O controller 508 can manage input and output signals for the device 500. The I / O controller 508 can also manage peripherals not integrated into the device 500. In some implementations, the I / O controller 508 can represent a physical connection or port to the external peripherals. In some implementations, the I / O controller 508 can utilize an operating system such as iOS®, ANDROID®, MS WINDOWS®, OS / 2®, UNIX®, LINUX®, or other known operating systems. In some implementations, the I / O controller 508 can be implemented as part of a processor, such as the processor 502. In some implementations, the user can interact with the device 500 via the I / O controller 508 or via hardware components controlled by the I / O controller 508.

[0141] In some implementations, the device 500 can include a single antenna 510. However, in some other implementations, the device 500 can have more than one antenna 510 (i.e., multiple antennas), including multiple antenna panels or antenna arrays, which are capable of concurrently sending or receiving multiple wireless transmissions. The transceiver 506 can communicate bi-directionally, via the one or more antennas 510, wired, or wireless links as described herein. For example, the transceiver 506 can represent a wireless transceiver and can communicate bi-directionally with another wireless transceiver. The transceiver 506 can also include a modem to modulate the packets and to demodulate packets received from one or more antennas 510. The transceiver 506 can include one or more transmitters, one or more receivers, or a combination thereof.

[0142] The transmit chain can be configured to generate and transmit signals (e.g., control information, data, packets). The transmit chain can include at least one modulator to modulate data onto a carrier signal, preparing the signal for transmission over the wireless medium. The at least one modulator can be configured to support one or more techniques such as amplitude modulation (AM), frequency modulation (FM), or a digital modulation scheme like phase-shift keying (PSK) or quadrature amplitude modulation (QAM). The transmit chain can also include at least one power amplifier configured to amplify the modulated signal to the appropriate power level for transmission over the wireless medium. The transmit chain can also include one or more antennas 510 for transmitting the amplified signal into the air or the wireless medium.

[0143] The receive chain can be configured to receive signals (e.g., control information, data, packets) over the wireless medium. For example, the receive chain can include one or more antennas 510 to receive signals over the air or wireless medium. The receive chain can include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receive chain can include at least one demodulator configured to demodulate the received signal and obtain the transmitted data by reversing the modulation techniques applied during signal transmission. The receive chain can include at least one decoder to decode the demodulated signal for receiving the transmitted data.

[0144] FIG. 6 FIG. illustrates an example of a device 600 that supports control resource set transmission in accordance with aspects of the present disclosure. The device 600 can be an example of a second apparatus 220 as described herein. The device 600 can support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The device 600 can include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 602, a memory 604, a transceiver 606, and an optional I / O controller 608. These components can be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses). The processor 602 can include one or more processors, microprocessors, or other logic devices that execute instructions to perform operations. The processor 602 can include one or more application processors and / or one or more baseband processors. The memory 604 can include one or more volatile or non-volatile storage devices, such as RAM, ROM, flash memory, or the like. The memory 604 can store instructions for execution by the processor 602. The transceiver 606 can include one or more transmitters and / or receivers that enable the device 600 to communicate with other devices. The transceiver 606 can be configured to transmit and / or receive signals using various transmission technologies, such as GSM, CDMA, WCDMA, TDSCDMA, FDD-LTE, TDD-LTE, NR, Wi-Fi, or the like. The I / O controller 608 can manage data communication with one or more input / output devices, such as a speaker, microphone, camera, display, or the like.

[0145] The processor 602, the memory 604, the transceiver 606, or various combinations thereof or various components thereof can be examples of means for performing various aspects of the present disclosure as described herein. For example, the processor 602, the memory 604, the transceiver 606, or various combinations or components thereof can support a method for performing one or more of the operations described herein.

[0146] In some implementations, the processor 602, the memory 604, the transceiver 606, or various combinations or components thereof can be implemented in hardware (e.g., in communication management circuitry). The hardware can include a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. In some implementations, a processor 602 and memory 604 coupled with the processor 602 can be configured to perform one or more of the functions described herein (e.g., by the processor 602 executing instructions stored in memory 604).

[0147] For example, the processor 602 can support wireless communication at the device 600, in accordance with examples disclosed herein. The processor 602 can be configured to be operable to support means for transmitting, to a terminal device via a transceiver, a configuration of a first control resource set (CORESET); determining, based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET, a second CORESET; and determining, based on the configuration, a mapping type of a control resource element (CCE) to resource element group (REG) mapping of the second CORESET. The processor 602 can be further configured to be operable to support means for other actions described in the present disclosure. FIG. 2

[0148] The processor 602 can include an intelligent hardware device, (e.g., a general- purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some implementations, the processor 602 can be configured to operate a memory array using a memory controller. In some other implementations, a memory controller can be integrated into the processor 602. The processor 602 can be configured to execute computer-readable instructions stored in a memory (e.g., the memory 604) to cause the device 600 to perform various functions of the present disclosure.

[0149] ​Memory 604 can include random access memory (RAM) and read-only memory (ROM). The memory 604 can store computer-readable, computer-executable software including instructions that, when executed, cause the device 600 to perform various functions described herein. The software can be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the software can not be directly executable by the processor 602 but can cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 604 can include a basic I / O system (BIOS), which can control basic hardware or software operation such as the interaction with peripheral components or devices.

[0150] The I / O controller 608 can manage input and output signals for the device 600. The I / O controller 608 can also manage peripherals not integrated into the device 500. In some implementations, the I / O controller 608 can represent a physical connection or port to the external peripherals. In some implementations, the I / O controller 608 can utilize an operating system such as iOS®, ANDROID®, MS WINDOWS®, OS / 2®, UNIX®, LINUX®, or other known operating systems. In some implementations, the I / O controller 608 can be implemented as part of a processor, such as the processor 602. In some implementations, the user can interact with the device 600 via the I / O controller 608 or via hardware components controlled by the I / O controller 608.

[0151] In some implementations, the device 600 can include a single antenna 610. However, in some other implementations, the device 600 can have more than one antenna 610 (i.e., multiple antennas), including multiple antenna panels or antenna arrays, which are capable of concurrently sending or receiving multiple wireless transmissions. The transceiver 606 can communicate bi-directionally, via the one or more antennas 610, wired, or wireless links as described herein. For example, the transceiver 606 can represent a wireless transceiver and can communicate bi-directionally with another wireless transceiver. The transceiver 606 can also include a modem to modulate the packets and to demodulate packets received from one or more antennas 610. The transceiver 606 can include one or more transmitters, one or more receivers, or a combination thereof.

[0152] The transmit chain can be configured to generate and transmit signals (e.g., control information, data, packets). The transmit chain can include at least one modulator to modulate data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator can be configured to support one or more techniques such as amplitude modulation (AM), frequency modulation (FM), or a digital modulation scheme like phase-shift keying (PSK) or quadrature amplitude modulation (QAM). The transmit chain can also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level for transmission over a wireless medium. The transmit chain can also include one or more antennas 610 for transmitting the amplified signal into the air or wireless medium.

[0153] The receive chain can be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receive chain can include one or more antennas 610 to receive signals over the air or wireless medium. The receive chain can include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receive chain can include at least one demodulator configured to demodulate the received signal and obtain the transmitted data by reversing the modulation techniques applied during signal transmission. The receive chain can include at least one decoder to decode the demodulated signal for receiving the transmitted data.

[0154] FIG. 7 FIGURE 1 illustrates an example of a processor 700 that supports control resource set transmission in accordance with aspects of the present disclosure. The processor 700 can be an example of a processor configured to perform various operations in accordance with examples described herein. The processor 700 can include a controller 702 configured to perform various operations in accordance with examples described herein. The processor 700 can optionally include at least one memory 704. Additionally or alternatively, the processor 700 can optionally include one or more arithmetic logic units (ALUs) 700. One or more of these components can be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces, such as buses.

[0155] The processor 700 can be a processor chipset and include a protocol stack (e.g., software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, sending, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with the examples described herein. The processor chipset can include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 700)) or other memory (e.g., random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc.).

[0156] The controller 702 can be configured to manage and coordinate the various operations (e.g., signaling, receiving, obtaining, retrieving, sending, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 700 to enable the processor 700 to support the various operations in accordance with the examples described herein. For example, the controller 702 can operate as a control unit of the processor 700 to generate control signals for managing the operation of the various components of the processor 700. These control signals include enabling or disabling functional units, selecting data paths, initiating memory accesses, and coordinating operational timing.

[0157] The controller 702 can be configured to retrieve (e.g., obtain, retrieve, receive) instructions from the memory 704 and determine subsequent instruction(s) to be executed to enable the processor 700 to support the various operations in accordance with the examples described herein. The controller 702 can be configured to track memory addresses of instructions associated with the memory 704. The controller 702 can be configured to decode instructions to determine operations to be performed and operands involved. For example, the controller 702 can be configured to interpret instructions and determine control signals to be output to other components of the processor 700 to enable the processor 700 to support the various operations in accordance with the examples described herein. Additionally or alternatively, the controller 702 can be configured to manage data flow within the processor 700. The controller 702 can be configured to control data transfers between registers, arithmetic logic units (ALUs), and other functional units of the processor 700.

[0158] The memory 704 can include one or more caches (e.g., memory or other storage included locally with the processor 700 or otherwise, such as RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash, etc. In some implementations, the memory 704 can reside within or on a processor chipset (e.g., locally with the processor 700). In some other implementations, the memory 704 can reside outside of the processor chipset (e.g., remote from the processor 700).

[0159] The memory 704 can store computer-readable, computer-executable code including instructions that, when executed by the processor 700, cause the processor 700 to perform various functionality described herein. The code can be stored in a non-transitory computer-readable medium, such as a system memory or another type of memory. The controller 702 and / or processor 700 can be configured to execute computer-readable instructions stored in the memory 704 to cause the processor 700 to perform various functionality (e.g., functionality or tasks that support transmit power prioritization). For example, the processor 700 and / or controller 702 can be coupled with or to the memory 704, and the processor 700, controller 702, and memory 704 can be configured to perform the various functionality described herein. In some examples, the processor 700 can include multiple processors, and the memory 704 can include multiple memories. One or more of the multiple processors can be coupled with one or more of the multiple memories, which can be individually or collectively configured to perform the various functionality described herein.

[0160] The one or more ALUs 700 can be configured to support various operations in accordance with examples described herein. In some implementations, the one or more ALUs 700 can reside within or on a processor chipset (e.g., the processor 700). In some other implementations, the one or more ALUs 700 can reside outside of the processor chipset (e.g., the processor 700). The one or more ALUs 700 can perform one or more computations such as addition, subtraction, multiplication, and division. For example, the one or more ALUs 700 can receive input operands and an operation code that determines the operation to be performed. The one or more ALUs 700 are configured with various logic and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate data according to the operation. Additionally or alternatively, the one or more ALUs 700 can support logical operations such as AND, OR, exclusive OR (XOR), NOT OR (NOR), and NOT AND (NAND) such that the one or more ALUs 700 are capable of processing conditional operations, comparisons, and bitwise operations.

[0161] According to examples disclosed herein, the processor 700 can support wireless communication. The processor 700 can be configured as or operable to support means for receiving, via a transceiver, a configuration of a first control resource set (CORESET); determining, based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET, a second CORESET; and determining, based on the configuration, a mapping type of a control resource element (CCE) to resource element group (REG) mapping of the second CORESET. The processor 502 can also be configured as or operable to support FIG. 2 means for other actions described in the detailed description.

[0162] FIG. 8 FIGURE 1 illustrates an example of a processor 800 that supports control resource set transmissions in accordance with aspects of the present disclosure. The processor 800 can be an example of a processor configured to perform various operations in accordance with examples described herein. The processor 800 can include a controller 802 configured to perform various operations in accordance with examples described herein. The processor 800 can optionally include at least one memory 804. Additionally or alternatively, the processor 800 can optionally include one or more arithmetic logic units (ALUs) 806. One or more of these components can be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces, such as buses.

[0163] The processor 800 can be a processor chipset and include a protocol stack (e.g., software stack) executed by the processor chipset to perform various operations (e.g., receive, obtain, retrieve, transmit, output, forward, store, determine, identify, access, write, read) in accordance with examples described herein. The processor chipset can include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., processor 800)) or other memory (e.g., random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc.).

[0164] The controller 802 can be configured to manage and coordinate the various operations (e.g., signaling, receiving, obtaining, retrieving, sending, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 800 to enable the processor 800 to support various operations in accordance with examples described herein. For example, the controller 802 can operate as a control unit of the processor 800 to generate control signals for managing the operations of the various components of the processor 800. These control signals include enabling or disabling functional units, selecting data paths, initiating memory accesses, and coordinating operational timing.

[0165] The controller 802 can be configured to retrieve (e.g., obtain, retrieve, receive) instructions from the memory 804 and determine subsequent instruction(s) to be executed to enable the processor 800 to support various operations in accordance with examples described herein. The controller 802 can be configured to track memory addresses of instructions associated with the memory 804. The controller 802 can be configured to decode instructions to determine operations to be performed and operands involved. For example, the controller 802 can be configured to interpret instructions and determine control signals to be output to other components of the processor 800 to enable the processor 800 to support various operations in accordance with examples described herein. Additionally or alternatively, the controller 802 can be configured to manage data flow within the processor 800. The controller 802 can be configured to control data transfers between registers, arithmetic logic units (ALUs), and other functional units of the processor 800.

[0166] The memory 804 can include one or more caches (e.g., memory or other storage included locally with the processor 800 or other memory, such as RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash, etc.). In some implementations, the memory 804 can reside within or on a processor chipset (e.g., locally with the processor 800). In some other implementations, the memory 804 can reside outside of a processor chipset (e.g., remote from the processor 800).

[0167] The memory 804 can store computer-readable, computer-executable code including instructions that, when executed by the processor 800, cause the processor 800 to perform various functions described herein. The code can be stored in a non-transitory computer-readable medium such as the system memory or another type of memory. The controller 802 and / or the processor 800 can be configured to execute the computer-readable instructions stored in the memory 804 to cause the processor 800 to perform various functions (e.g., functions or tasks that support sending power priorities). For example, the processor 800 and / or the controller 802 can be coupled with or to the memory 804, and the processor 800, the controller 802, and the memory 804 can be configured to perform the various functions described herein. In some examples, the processor 800 can include multiple processors, and the memory 804 can include multiple memories. One or more of the multiple processors can be coupled with one or more of the multiple memories, which can be individually or collectively configured to perform the various functions herein.

[0168] The one or more ALUs 800 can be configured to support various operations in accordance with examples described herein. In some implementations, the one or more ALUs 800 can reside within or on a processor chipset (e.g., the processor 800). In some other implementations, the one or more ALUs 800 can reside outside of a processor chipset (e.g., the processor 800). The one or more ALUs 800 can perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, the one or more ALUs 800 can receive input operands and an operation code that determines the operation to be performed. The one or more ALUs 800 are configured with various logic and arithmetic circuits, including adders, subtractors, shifters, and logic gates to process and manipulate data according to the operation. Additionally or alternatively, the one or more ALUs 800 can support logical operations such as AND, OR, exclusive OR (XOR), NOT OR (NOR), and NOT AND (NAND) such that the one or more ALUs 800 are capable of processing conditional operations, comparisons, and bitwise operations.

[0169] According to examples disclosed herein, the processor 800 can support wireless communications. The processor 800 can be configured or operable to support means for transmitting, to a terminal device via a transceiver, a configuration of a first control resource set (CORESET), determining, based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET, a second CORESET, and determining, based on the configuration, a mapping type of a control resource element (CCE) to resource element group (REG) mapping of the second CORESET. The processor 602 can also be configured or operable to support means for transmitting, to the terminal device via the transceiver, an indication of the mapping type. FIG. 2The components described in this section for other actions.

[0170] FIG. 9 FIGURE 13 illustrates a flowchart of a method 1300 that supports control resource set transmission in accordance with aspects of the present disclosure. The operations of method 1300 can be implemented by a device or its components as described herein. For example, the operations of method 1300 can be performed by the first apparatus 210 as described herein. In some implementations, the device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the device can perform aspects of the described functions using special-purpose hardware.

[0171] At 905, the method includes receiving, via the transceiver, a configuration of a first CORESET. The operations of 905 can be performed according to the methods described herein. In some implementations, aspects of the operations of 905 can be performed by a device as described with reference to FIG. 1A the described devices.

[0172] At 910, the method includes determining a second CORESET based on the configuration and a predefined number of PRBs to puncture from the first CORESET. The operations of 910 can be performed according to the methods described herein. In some implementations, aspects of the operations of 910 can be performed by a device as described with reference to FIG. 1A the described devices.

[0173] At 915, the method includes determining a mapping type of a CCE-to-REG mapping of the second CORESET based on the configuration. The operations of 915 can be performed according to the methods described herein. In some implementations, aspects of the operations of 915 can be performed by a device as described with reference to FIG. 1A the described devices.

[0174] In some embodiments, the configuration can include a PRB offset indicating one of: a first frequency gap between a non-punctured synchronization signal block (SSB) and the first CORESET; or a second frequency gap between a punctured SSB and the first CORESET.

[0175] In some embodiments, the method can further include determining a frequency location of the second CORESET based on the PRB offset, the predefined number of PRBs to puncture from the first CORESET, and a frequency location of the non-punctured SSB.

[0176] In some embodiments, the PRB offset can be selected from a set of candidate PRB offsets, and the set of candidate PRB offsets can be determined based on the predefined number of PRBs to puncture from the first CORESET.

[0177] In some embodiments, the predefined number of PRBs to puncture from the first CORESET in a case where the first CORESET includes 2 symbols can be the same as or different from the predefined number of PRBs to puncture from the first CORESET in a case where the first CORESET includes 3 symbols.

[0178] In some embodiments, determining the second CORESET can include one of: puncturing the lowest 2 CCEs or the lowest 6 PRBs of the first CORESET in a case where the first CORESET includes 2 symbols; or puncturing the lowest 2 CCEs or the lowest 4 PRBs of the first CORESET in a case where the first CORESET includes 3 symbols.

[0179] In some embodiments, determining the mapping type can include determining the mapping type as an interleaved CCE-to-REG mapping or a non-interleaved CCE-to-REG mapping based on the number of symbols of the first CORESET.

[0180] In some embodiments, determining the mapping type based on the number of symbols can include one of: determining the mapping type as the interleaved CCE-to-REG mapping in a case where the number of symbols is 2; or determining the mapping type as the non-interleaved CCE-to-REG mapping in a case where the number of symbols is 3.

[0181] In some embodiments, the method can further include determining a shift value for the CCE-to-REG mapping of the second CORESET based on the configuration.

[0182] In some embodiments, determining the shift value can include determining the shift value based on the mapping type or the number of symbols of the first CORESET.

[0183] In some embodiments, determining the shift value based on the mapping type can include one of: determining the shift value as an identifier (ID) of a cell in which the configuration of the first CORESET is received in a case where the mapping type is the interleaved CCE-to-REG mapping; or determining the shift value as a predetermined value in a case where the mapping type is the non-interleaved CCE-to-REG mapping.

[0184] In some embodiments, determining the shift value based on the number of symbols can include one of: determining the shift value as an ID of a cell in which the configuration of the first CORESET is received in a case where the number of symbols is 2; or determining the shift value as a predetermined value in a case where the number of symbols is 3.

[0185] FIG. 10A flow diagram illustrating a method 1000 that supports control resource set transmission in accordance with aspects of the present disclosure is shown. Operations of the method 1000 can be implemented by a device or its components described herein. For example, the operations of the method 1000 can be performed by the second apparatus 220 described herein. In some implementations, the device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the device can perform aspects of the described functions using special-purpose hardware.

[0186] At 1005, the method includes transmitting, via the transceiver, a configuration of a first CORESET to a terminal device. The operations of 1005 can be performed according to the methods described herein. In some implementations, aspects of the operations of 1005 can be performed by a device as described with reference to FIG. 1A the described devices.

[0187] At 1110, the method includes determining a second CORESET based on the configuration and a predefined number of PRBs to puncture from the first CORESET. The operations of 1110 can be performed according to the methods described herein. In some implementations, aspects of the operations of 1110 can be performed by a device as described with reference to FIG. 1A the described devices.

[0188] At 1115, the method includes determining a mapping type of a CCE-to-REG mapping of the second CORESET based on the configuration. The operations of 1115 can be performed according to the methods described herein. In some implementations, aspects of the operations of 1115 can be performed by a device as described with reference to FIG. 1A the described devices.

[0189] In some embodiments, the configuration can include a PRB offset indicating one of: a first frequency gap between a non-punctured synchronization signal block (SSB) and the first CORESET; or a second frequency gap between a punctured SSB and the first CORESET.

[0190] In some embodiments, the method can further include determining a frequency location of the second CORESET based on the PRB offset, the predefined number of PRBs to puncture from the first CORESET, and a frequency location of the non-punctured SSB.

[0191] Some implementations of the methods and apparatuses described herein can further include determining a set of candidate PRB offsets based on the predefined number of PRBs to puncture from the first CORESET, and selecting the PRB offset from the set of candidate PRB offsets.

[0192] In some embodiments, the predefined number of PRBs to puncture from the first CORESET in a case where the first CORESET includes 2 symbols can be the same as or different from the predefined number of PRBs to puncture from the first CORESET in a case where the first CORESET includes 3 symbols.

[0193] In some embodiments, determining the second CORESET can include one of: determining that the lowest 2 CCEs or the lowest 6 PRBs of the first CORESET are to be punctured in a case where the first CORESET includes 2 symbols; or determining that the lowest 2 CCEs or the lowest 4 PRBs of the first CORESET are to be punctured in a case where the first CORESET includes 3 symbols.

[0194] In some embodiments, determining the mapping type can include determining the mapping type to be an interleaved CCE-to-REG mapping or a non-interleaved CCE-to-REG mapping based on the number of symbols of the first CORESET.

[0195] In some embodiments, determining the mapping type based on the number of symbols can include one of: determining the mapping type to be an interleaved CCE-to-REG mapping in a case where the number of symbols is 2; or determining the mapping type to be a non-interleaved CCE-to-REG mapping in a case where the number of symbols is 3.

[0196] In some embodiments, the method can further include determining a shift value for the CCE-to-REG mapping of the second CORESET based on the configuration.

[0197] In some embodiments, determining the shift value can include determining the shift value based on the mapping type or the number of symbols of the first CORESET.

[0198] In some embodiments, determining the shift value based on the mapping type can include one of: determining the shift value to be an identifier (ID) of a cell in which the first CORESET is transmitted in a case where the mapping type is an interleaved CCE-to-REG mapping; or determining the shift value to be a predetermined value in a case where the mapping type is a non-interleaved CCE-to-REG mapping.

[0199] In some embodiments, determining the shift value based on the number of symbols can include one of: determining the shift value to be an ID of a cell in which the first CORESET is transmitted in a case where the number of symbols is 2; or determining the shift value to be a predetermined value in a case where the number of symbols is 3.

[0200] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Further, aspects from two or more of the methods can be combined.

[0201] The various illustrative blocks and components described herein can be implemented with a general purpose processor, a DSP, an ASIC, a CPU, a FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein and can be implemented or performed with a general purpose processor, a DSP, an ASIC, a CPU, a FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0202] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0203] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable ROM (EEPROM), flash memory, compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

[0204] As used herein, including in the claims, the article "a" preceding a list of items is an open, non-restrictive article, and shall be construed to mean "at least one" or "one or more" of the listed items. The terms "a," "at least one," "one or more" and "at least one of, are interchangeable. As used herein, including in the claims, the term "or" as used in the including in the context of a list of items prefaced by "at least one of" or "one or more of" indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as "based on condition A" can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" shall be construed in the same manner as the phrase "based at least in part on." Moreover, as used herein, including in the claims, "set" shall not be construed as a limitation to items that are the same unless explicitly indicated as such. For example, a set of items can include multiple items of the same type or multiple items of different types.

[0205] The description herein is presented to enable a person of ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

[0206] Embodiments of the present disclosure can be further described using the following sections.

[0207] Section 1. A first apparatus for wireless communication, comprising: a processor; and a transceiver coupled to the processor, wherein the processor is configured to: receive, via the transceiver, a configuration of a first control resource set (CORESET); determine, based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET, a second CORESET; and determine, based on the configuration, a mapping type of a control resource element (CCE) to resource element group (REG) mapping of the second CORESET.

[0208] Section 2. The first apparatus of Section 1, wherein the configuration comprises a PRB offset indicating one of: a first frequency gap between a non-punctured synchronization signal block (SSB) and the first CORESET; or a second frequency gap between a punctured SSB and the first CORESET.

[0209] Section 3. The first apparatus of Section 2, wherein the processor is further configured to determine a frequency location of the second CORESET based on the PRB offset, a predefined number of the PRBs to be punctured from the first CORESET, and a frequency location of the SSB that is not punctured.

[0210] Section 4. The first apparatus of Section 2, wherein the PRB offset is selected from a set of candidate PRB offsets, and the set of candidate PRB offsets is determined based on the predefined number of the PRBs to be punctured from the first CORESET.

[0211] Section 5. The first apparatus of Section 1, wherein the predefined number of the PRBs to be punctured from the first CORESET in a case that the first CORESET comprises 2 symbols is the same as or different from the predefined number of the PRBs to be punctured from the first CORESET in a case that the first CORESET comprises 3 symbols.

[0212] Section 6. The first apparatus of Section 1, wherein determining the second CORESET comprises one of: puncturing a lowest 2 CCEs or a lowest 6 PRBs of the first CORESET in a case that the first CORESET comprises 2 symbols; or puncturing a lowest 2 CCEs or a lowest 4 PRBs of the first CORESET in a case that the first CORESET comprises 3 symbols.

[0213] Section 7. The first apparatus of Section 1, wherein determining the mapping type comprises determining the mapping type as an interleaved CCE-to-REG mapping or a non-interleaved CCE-to-REG mapping based on a number of symbols of the first CORESET.

[0214] Section 8. The first apparatus of Section 7, wherein determining the mapping type based on the number of symbols comprises one of: determining the mapping type as the interleaved CCE-to-REG mapping in a case that the number of symbols is 2; or determining the mapping type as the non-interleaved CCE-to-REG mapping in a case that the number of symbols is 3.

[0215] Section 9. The first apparatus of any of Sections 1 to 8, wherein the processor is further configured to determine a shift value of the CCE-to-REG mapping of the second CORESET based on the configuration.

[0216] Section 10. The first apparatus of Section 9, wherein determining the shift value comprises determining the shift value based on the mapping type or a number of symbols of the first CORESET.

[0217] Section 11. The first apparatus of Section 10, wherein determining the shift value based on the mapping type comprises one of: determining the shift value as an identifier (ID) of a cell in which the first CORESET is received in a case that the mapping type is interleaved CCE-to-REG mapping; or determining the shift value as a predetermined value in a case that the mapping type is non-interleaved CCE-to-REG mapping.

[0218] Section 12. The first apparatus of Section 10, wherein determining the shift value based on the number of symbols comprises one of: determining the shift value as an ID of a cell in which the first CORESET is received in a case that the number of symbols is 2; or determining the shift value as a predetermined value in a case that the number of symbols is 3.

[0219] Section 13. A second apparatus for wireless communication, comprising a processor; and a transceiver coupled to the processor, wherein the processor is configured to: transmit, via the transceiver, a configuration of a first control resource set (CORESET) to a first apparatus; determine a second CORESET based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET; and determine a mapping type of a control resource element (CCE)-to-resource element group (REG) mapping of the second CORESET based on the configuration.

[0220] Section 14. The second apparatus of Section 13, wherein the configuration comprises a PRB offset indicating one of: a first frequency gap between an unpunctured synchronization signal block (SSB) and the first CORESET; or a second frequency gap between a punctured SSB and the first CORESET.

[0221] Section 15. The second apparatus of Section 14, wherein the processor is further configured to determine a frequency location of the second CORESET based on the PRB offset, the predefined number of PRBs to be punctured from the first CORESET, and a frequency location of the unpunctured SSB.

[0222] Section 16. The second apparatus of Section 14, wherein the processor is further configured to determine a set of candidate PRB offsets based on the predefined number of PRBs to be punctured from the first CORESET; and select the PRB offset from the set of candidate PRB offsets.

[0223] Chapter 17. The second apparatus of Chapter 13, wherein a predefined number of PRBs to be punctured from the first CORESET in a case where the first CORESET comprises 2 symbols is the same as or different from a predefined number of PRBs to be punctured from the first CORESET in a case where the first CORESET comprises 3 symbols.

[0224] Chapter 18. The second apparatus of Chapter 13, wherein determining the second CORESET comprises one of: determining that a lowest 2 CCEs or a lowest 6 PRBs of the first CORESET are to be punctured in a case where the first CORESET comprises 2 symbols; or determining that a lowest 2 CCEs or a lowest 4 PRBs of the first CORESET are to be punctured in a case where the first CORESET comprises 3 symbols.

[0225] Chapter 19. The second apparatus of Chapter 13, wherein determining the mapping type comprises determining the mapping type as an interleaved CCE-to-REG mapping or a non-interleaved CCE-to-REG mapping based on a number of symbols of the first CORESET.

[0226] Chapter 20. The second apparatus of Chapter 19, wherein determining the mapping type based on the number of symbols comprises one of: determining the mapping type as the interleaved CCE-to-REG mapping in a case where the number of symbols is 2; or determining the mapping type as the non-interleaved CCE-to-REG mapping in a case where the number of symbols is 3.

[0227] Chapter 21. The second apparatus of any of Chapters 13 to 20, wherein the processor is further configured to determine a shift value of the CCE-to-REG mapping of the second CORESET based on the configuration.

[0228] Chapter 22. The second apparatus of Chapter 21, wherein determining the shift value comprises determining the shift value based on the mapping type or a number of symbols of the first CORESET.

[0229] Chapter 23. The second apparatus of Chapter 22, wherein determining the shift value based on the mapping type comprises one of: determining the shift value as an identifier (ID) of the configured cell in which the first CORESET is transmitted in a case where the mapping type is an interleaved CCE-to-REG mapping; or determining the shift value as a predetermined value in a case where the mapping type is a non-interleaved CCE-to-REG mapping.

[0230] Clause 24. The second apparatus of Clause 22, wherein determining the shift value based on the number of symbols comprises one of: determining the shift value to be an ID of a cell in which the configuration of the first CORESET is transmitted in a case that the number of symbols is 2; or determining the shift value to be a predetermined value in a case that the number of symbols is 3.

[0231] Clause 25. A processor for wireless communication, comprising: at least one memory; and a controller coupled with the at least one memory and configured such that the controller: receives, via the transceiver, a configuration of a first control resource set (CORESET); determines a second CORESET based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET; and determines, based on the configuration, a mapping type of a control resource element (CCE) to resource element group (REG) mapping of the second CORESET.

[0232] Clause 26. A processor for wireless communication, comprising: at least one memory; and a controller coupled with the at least one memory and configured such that the controller: transmits, via the transceiver, a configuration of a first control resource set (CORESET) to a first apparatus; determines a second CORESET based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET; and determines, based on the configuration, a mapping type of a control resource element (CCE) to resource element group (REG) mapping of the second CORESET.

[0233] Clause 27. A method performed by a first apparatus, comprising: receiving, via a transceiver, a configuration of a first control resource set (CORESET); determining a second CORESET based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET; and determining, based on the configuration, a mapping type of a control resource element (CCE) to resource element group (REG) mapping of the second CORESET.

[0234] Clause 28. A method performed by a second apparatus, comprising: transmitting, via a transceiver, a configuration of a first control resource set (CORESET) to a first apparatus; determining a second CORESET based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET; and determining, based on the configuration, a mapping type of a control resource element (CCE) to resource element group (REG) mapping of the second CORESET.

[0235] Clause 29. A computer-readable medium having stored thereon instructions that, when executed by a processor of an apparatus, cause the apparatus to perform at least the method of any of clauses 27 or 28.

Claims

1. A first apparatus for wireless communication, comprising: a processor; and a transceiver coupled to the processor, wherein the processor is configured to: receive, via the transceiver, a configuration of a first control resource set, CORESET; determine, based on the configuration and a predefined number of physical resource blocks, PRBs, to be punctured from the first CORESET, a second CORESET; and determine, based on the configuration, a mapping type of a control resource element, CCE, to resource element group, REG, mapping of the second CORESET.

2. The first apparatus of claim 1, wherein the configuration comprises a PRB offset indicating one of: a first frequency gap between an unpunctured synchronization signal block, SSB, and the first CORESET; or a second frequency gap between a punctured SSB and the first CORESET.

3. The first apparatus of claim 2, wherein the processor is further configured to: determine, based on the PRB offset, the predefined number of PRBs to be punctured from the first CORESET, and a frequency location of the unpunctured SSB, a frequency location of the second CORESET.

4. The first apparatus of claim 2, wherein the PRB offset is selected from a set of candidate PRB offsets, and the set of candidate PRB offsets is determined based on the predefined number of PRBs to be punctured from the first CORESET.

5. The first apparatus of claim 1, wherein the predefined number of PRBs to be punctured from the first CORESET in a case that the first CORESET comprises 2 symbols is the same as or different from the predefined number of PRBs to be punctured from the first CORESET in a case that the first CORESET comprises 3 symbols.

6. The first apparatus of claim 1, wherein determining the second CORESET comprises one of: puncturing a lowest 2 CCEs or a lowest 6 PRBs of the first CORESET in a case that the first CORESET comprises 2 symbols; or puncturing a lowest 2 CCEs or a lowest 4 PRBs of the first CORESET in a case that the first CORESET comprises 3 symbols.

7. The first apparatus of claim 1, wherein determining the mapping type comprises: determining, based on a number of symbols of the first CORESET, the mapping type as an interleaved CCE to REG mapping or a non-interleaved CCE to REG mapping.

8. The first apparatus of claim 7, wherein determining the mapping type based on the number of symbols comprises one of: determining the mapping type as the interleaved CCE to REG mapping in a case that the number of symbols is 2; or determining the mapping type as the non-interleaved CCE to REG mapping in a case that the number of symbols is 3.

9. The first apparatus of any one of claims 1-8, wherein the processor is further configured to: ​ ​ determine, based on the configuration, a shift value for the CCE-to-REG mapping of the second CORESET.

10. The first apparatus of claim 9, wherein determining the shift value comprises: determining the shift value based on the mapping type or a number of symbols of the first CORESET.

11. The first apparatus of claim 10, wherein determining the shift value based on the mapping type comprises one of: in a case that the mapping type is interleaved CCE-to-REG mapping, determining the shift value as an identifier (ID) of a cell in which the configuration of the first CORESET is received; or in a case that the mapping type is non-interleaved CCE-to-REG mapping, determining the shift value as a predetermined value.

12. The first apparatus of claim 10, wherein determining the shift value based on the number of symbols comprises one of: in a case that the number of symbols is 2, determining the shift value as an ID of a cell in which the configuration of the first CORESET is received; or in a case that the number of symbols is 3, determining the shift value as a predetermined value.

13. A second apparatus for wireless communication, comprising: a processor; and a transceiver coupled to the processor, wherein the processor is configured to: send, via the transceiver, a configuration of a first control resource set (CORESET) to a first apparatus; determine a second CORESET based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET; and determine, based on the configuration, a mapping type for a control resource element (CCE)-to-resource element group (REG) mapping of the second CORESET.

14. The second apparatus of claim 13, wherein the predefined number of PRBs to be punctured from the first CORESET in a case that the first CORESET comprises 2 symbols is the same as or different from the predefined number of PRBs to be punctured from the first CORESET in a case that the first CORESET comprises 3 symbols.

15. The second apparatus of claim 13, wherein determining the second CORESET comprises one of: in a case that the first CORESET comprises 2 symbols, determining that a lowest 2 CCEs or a lowest 6 PRBs of the first CORESET are to be punctured; or in a case that the first CORESET comprises 3 symbols, determining that a lowest 2 CCEs or a lowest 4 PRBs of the first CORESET are to be punctured.

16. The second apparatus of claim 13, wherein determining the mapping type comprises: determining the mapping type as interleaved CCE-to-REG mapping or non-interleaved CCE-to-REG mapping based on a number of symbols of the first CORESET.

17. The second apparatus of any one of claims 13 to 16, wherein the processor is further configured to: ​ determining, based on the configuration, a shift value for the CCE-to-REG mapping of the second CORESET.

18. The second apparatus of claim 17, wherein determining the shift value comprises: determining the shift value based on the mapping type or a number of symbols of the first CORESET.

19. A method performed by a first apparatus, comprising: receiving, via a transceiver, a configuration of a first control resource set (CORESET); determining, based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET, a second CORESET; and determining, based on the configuration, a mapping type for a control resource element (CCE)-to-resource element group (REG) mapping of the second CORESET.

20. A method performed by a second apparatus, comprising: transmitting, via a transceiver, to a first apparatus, a configuration of a first control resource set (CORESET); determining, based on the configuration and a predefined number of physical resource blocks (PRBs) to be punctured from the first CORESET, a second CORESET; and determining, based on the configuration, a mapping type for a control resource element (CCE)-to-resource element group (REG) mapping of the second CORESET. ​ ​

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