Clock signal generation method and device, electronic equipment and storage medium

Abstract

The invention discloses a clock signal generation method and device, electronic equipment and a storage medium. The clock signal generation method comprises the following steps: determining an initial cycle ratio of all clocks according to a target frequency of each clock in a clock configuration file; multiplying a value of a proportional item corresponding to each clock in the initial period ratio by a target value to obtain a target period ratio; determining a current error of each clock according to the target cycle ratio; if all the current errors are smaller than or equal to the corresponding preset errors, whether the digit of the binary numerical value corresponding to the value of each proportional term in the target period ratio is smaller than or equal to the preset digit or not is judged, and when the digit of the binary numerical value corresponding to the value of each proportional term in the target period ratio is smaller than or equal to the preset digit, the target period ratio is obtained. Taking the target cycle ratio as a final configuration parameter; and generating a clock signal according to the final configuration parameter. According to the technical scheme, the accuracy of clock signal generation is improved, and the counting amount is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, and in particular to a clock signal generation method and device, electronic equipment and storage medium. BACKGROUND

[0002] In the field of prototype verification and hardware circuit simulation, the logic design of a user needs to be transplanted to a target platform. The logic design of the user usually needs to be provided with multiple clocks of different frequencies, phases and duty cycles from outside. During the transplantation process, the clock information required by the design needs to be restored as accurately as possible.

[0003] However, the existing clock generation method needs to strictly restore the accurate timing relationship of all clock edges, so that the frequency of the generated clock is too low and greatly different from the required frequency, which seriously affects the simulation performance. Moreover, the accurate frequency division requires a complex counter network, which increases the occupation of logic resources, and the period of the low-frequency clock is relatively long, which requires a longer counting time and intensifies the timing path pressure and reduces the highest operating frequency of the system. If the frequency of the clock needs to be modified, a long time of counting is required again, so that the flexibility of the clock generation method is low. Therefore, the existing clock generation method has the problem of excessive counting amount, and the frequency of the generated clock is greatly different from the required frequency, that is, the frequency accuracy of the generated clock is low. SUMMARY

[0004] The present application provides a clock signal generation method, device, electronic equipment and storage medium to solve the problem of excessive counting amount and low accuracy of the clock generation method.

[0005] According to an aspect of the present application, a clock signal generation method is provided, which comprises:

[0006] determining an initial period ratio of all clocks according to the target frequency of each clock in a clock configuration file;

[0007] multiplying the value of the proportional term corresponding to each clock in the initial period ratio by a target value to obtain a target period ratio; wherein the target value is the ratio of the least common multiple of the inverses of the phase offsets of all clocks to the value of the target proportional term; the clock corresponding to the target proportional term is a target clock; the phase offset of the clock is the phase offset of the clock relative to the zero phase;

[0008] determining the current error of each clock according to the target period ratio;

[0009] If all the current errors are less than or equal to the corresponding preset errors, it is determined whether the bit number of the binary value corresponding to the value of each ratio term in the target period ratio is less than or equal to a preset bit number, and when the bit number of the binary value corresponding to the value of each ratio term in the target period ratio is less than or equal to the preset bit number, the target period ratio is taken as the final configuration parameter;

[0010] A clock signal is generated according to the final configuration parameter.

[0011] Optionally, after the current error of each clock is determined according to the target period ratio, the method further comprises:

[0012] If there is a current error of a clock that is greater than the preset error corresponding to the clock, each ratio term in the target period ratio is multiplied by the ratio of the current error to the preset error corresponding to the clock outside the group, and the step of determining the current error of each clock according to the target period ratio is performed again.

[0013] Optionally, after it is determined whether the bit number of the binary value corresponding to the value of each ratio term in the target period ratio is less than or equal to a preset bit number, the method further comprises:

[0014] When there is a ratio term in the target period ratio whose value corresponds to a binary value with a bit number greater than the preset bit number, the target period ratio is adjusted, and the step of determining whether the bit number of the binary value corresponding to the value of each ratio term in the target period ratio is less than or equal to a preset bit number is performed again.

[0015] Optionally, the target period ratio is adjusted by:

[0016] If the target period ratio has been adjusted or the current error is equal to the preset error corresponding to the clock outside the group, the current number of times that there is a ratio term in the target period ratio whose value corresponds to a binary value with a bit number greater than the preset bit number is determined;

[0017] When the current number of times is less than or equal to the number of clocks outside the group, the value of each ratio term in the target period ratio corresponding to the clock outside the group is arranged in descending order, and the value of the nth ratio term is reduced to obtain an adjusted target period ratio; wherein n is the current number of times;

[0018] When the current number of times is greater than the number of clocks outside the group, a prompt message is sent.

[0019] If the target period ratio has not been adjusted and the current error is not equal to the preset error corresponding to the clock outside the group, each ratio term in the target period ratio is multiplied by the ratio of the current error to the preset error corresponding to the clock outside the group, and the step of determining whether the bit number of the binary value corresponding to the value of each ratio term in the target period ratio is less than or equal to a preset bit number is performed again.

[0020] Optionally, the initial cycle ratio of all clocks is determined based on the target frequency of each clock in the clock profile, including:

[0021] Based on the target frequency of each clock in the clock configuration file, determine the cycle ratio of all clocks, and divide each ratio term of all clock cycles by the greatest common factor of all target frequencies to obtain the initial cycle ratio.

[0022] Optionally, determining the current error for each clock cycle based on the target cycle ratio includes:

[0023] The current frequency of the reference clock is determined based on the value of the corresponding proportional term in the target period ratio and the target frequency of the target clock.

[0024] The current error of each clock is determined based on the current frequency.

[0025] Optionally, the preset error corresponding to the clock in the group in the clock configuration file is zero;

[0026] The preset error corresponding to the clock outside the group in the clock configuration file is the input error in the clock configuration file.

[0027] According to another aspect of the present invention, a clock signal generating apparatus is provided, the clock signal generating apparatus comprising:

[0028] The initial cycle ratio determination module is used to determine the initial cycle ratio of all clocks based on the target frequency of each clock in the clock configuration file.

[0029] The target period ratio determination module is used to multiply the value of the proportional term corresponding to each clock in the initial period ratio by a target value to obtain the target period ratio; wherein, the target value is the ratio of the least common multiple of the reciprocals of the phase offsets of all clocks to the value of the target proportional term; the clock corresponding to the target proportional term is the target clock; the phase offset of the clock is the phase offset of the clock relative to the zero phase;

[0030] The current error determination module is used to determine the current error of each clock cycle based on the target cycle ratio.

[0031] The final configuration parameter determination module is used to determine whether the number of bits of the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits if all current errors are less than or equal to the corresponding preset errors. When the number of bits of the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits, the target period ratio is used as the final configuration parameter.

[0032] A clock signal generation module is used to generate a clock signal based on the final configuration parameters.

[0033] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0034] At least one processor; and

[0035] A memory communicatively connected to the at least one processor; wherein,

[0036] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the clock signal generation method according to any embodiment of the present invention.

[0037] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the clock signal generation method according to any embodiment of the present invention.

[0038] The technical solution of this invention determines the initial cycle ratio of all clocks based on the target frequency of each clock in the clock configuration file. The target cycle ratio is obtained by multiplying the value of the proportional term corresponding to each clock in the initial cycle ratio by a target value. The target value is the ratio of the least common multiple of the reciprocals of the phase offsets of all clocks to the value of the target proportional term. The clock corresponding to the target proportional term is the target clock. The current error of each clock is determined based on the target cycle ratio. When all current errors are less than or equal to the corresponding preset errors, and the number of bits in the binary value corresponding to the value of each proportional term in the target cycle ratio is less than or equal to the preset number of bits, the target cycle ratio is used as the final configuration parameter. A clock signal is generated based on the final configuration parameter. By multiplying the value of the proportional term corresponding to each clock in the initial cycle ratio by the target value to obtain the target cycle ratio, the generated clock is guaranteed to reflect the phase offset, and the cycle unit corresponding to each clock is not too large. Furthermore, by dividing by the value of the target proportional term, the cycle unit corresponding to clocks within the group is guaranteed to be an integer, while the cycle unit corresponding to clocks outside the group can be non-integer, thus ensuring the accuracy of clocks within the group. By sacrificing the accuracy of non-critical clocks (clocks outside the group), the value of the proportional term in the target period ratio can be kept from being too large, avoiding excessively long clock periods that would require a longer counting time. This reduces the number of counts and allows the frequency of the generated clock to be close to the target frequency, thus improving the accuracy of the generated clock signal.

[0039] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a flowchart of a clock signal generation method provided in an embodiment of the present invention;

[0042] Figure 2 This is a flowchart of another clock signal generation method provided in an embodiment of the present invention;

[0043] Figure 3 This is a flowchart of another clock signal generation method provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of the structure of a clock signal generation device provided in an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] As mentioned in the background section, existing clock generation methods suffer from high computational complexity and low accuracy. The inventors discovered that this problem arises because related technologies employ least common multiple frequency division. For example, if the required frequency for the first clock is 100MHz with a 20% phase shift, and the required frequency for the second clock is 30MHz, the cycle ratio of the two clocks is 3:10. However, because the first clock has a phase shift, the number of cycles must be multiplied by 20% to be an integer. This results in cycle units of 15 and 50. For instance, if the reference clock frequency is 100MHz, 15 cycles of the reference clock are needed to generate the first clock, and 50 cycles are needed to generate the second clock. This reduces the frequency of the first clock by a factor of 15, leading to low accuracy. Furthermore, the values ​​of 15 and 50 are relatively large, resulting in long clock cycle lengths (the duration of a single cycle), requiring lengthy processing times and causing excessive computational complexity. Therefore, existing clock generation methods suffer from both high computational complexity and low accuracy.

[0049] To address the aforementioned technical problems, embodiments of the present invention provide a clock signal generation method. The clock signal generation method can be executed by a clock signal generation device and can be applied in scenarios requiring clock signals, such as prototype verification platforms, hardware circuit simulation accelerators, or electronic design automation (EDA) software. Figure 1 This is a flowchart of a clock signal generation method provided in an embodiment of the present invention, see reference. Figure 1 Clock signal generation methods include:

[0050] S110. Determine the initial cycle ratio of all clocks based on the target frequency of each clock in the clock configuration file.

[0051] The clock configuration file is a configuration file written by the user during prototype verification or circuit simulation. The clock configuration file includes the clock name (or clock number), the group name to which the clock belongs, the clock parameters (at least frequency, and may also include phase and duty cycle), and accuracy requirements. The accuracy requirement (or input error) is the preset error corresponding to clocks outside the group, while the preset error for clocks within the group is zero. Clocks within the group are those for which the user requires higher accuracy, such as clocks corresponding to the same circuit structure; this is not specifically limited here. For example, the clock configuration file includes clocks CLK0, CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6. Clock CLK0 has a frequency of 100MHz, CLK1 has a frequency of 70MHz and a phase of 90 degrees, CLK2 has a frequency of 50MHz and a duty cycle of 10%, CLK3 has a frequency of 100kHz, CLK4 has a frequency of 33MHz, CLK5 has a frequency of 10MHz and a phase of 180 degrees, and CLK6 has a frequency of 12.5MHz. Clocks CLK4 and CLK5 belong to the first group, and clock CLK6 belongs to the second group. That is, clocks CLK4, CLK5, and CLK6 are clocks within the same group, while clocks CLK0, CLK1, CLK2, and CLK3 are clocks outside the same group. The frequency corresponding to the clock in the clock configuration file is the target frequency of the clock.

[0052] Specifically, based on the target frequency of each clock in the clock configuration file, the initial period ratio of all clocks is determined. The initial period ratio of all clocks can be obtained by taking the ratio of the reciprocals of all target frequencies, or by dividing each proportional term of the ratio of the reciprocals of all target frequencies by the greatest common factor of all target frequencies. No limitation is imposed here.

[0053] S120. Multiply the value of the proportional term corresponding to each clock in the initial cycle ratio by the target value to obtain the target cycle ratio; where the target value is the ratio of the least common multiple of the reciprocals of the phase offsets of all clocks to the value of the target proportional term; the clock corresponding to the target proportional term is the target clock; the phase offset of the clock is the phase offset of the clock relative to the zero phase.

[0054] The phase offset is the phase of the clock, which is the offset relative to the zero phase. For example, the clock signal starts at zero phase when it jumps from high level to low level, or the clock signal starts at zero phase when it jumps from low level to high level. There is no limitation on this.

[0055] For example, the target clock can be any clock in the group within the clock configuration file. The values ​​of the ratio terms in the initial cycle ratio and target cycle ratio represent the cycle units. For example, if there are two clocks in the clock configuration file and the initial cycle ratio is 3:10, it means that one cycle of one clock requires 3 cycles of reference clock to generate, and one cycle of the other clock requires 10 cycles of reference clock to generate.

[0056] Specifically, the target cycle ratio is obtained by multiplying the value of the proportional term corresponding to each clock in the initial cycle ratio by the target value (i.e., multiplying the value of each proportional term in the initial cycle ratio by the least common multiple of the reciprocals of the phase offsets of all clocks), and then dividing by the value of the target proportional term. Multiplying by the least common multiple of the reciprocals of the phase offsets of all clocks ensures that the value of the proportional term corresponding to each clock in the target cycle ratio divided by the corresponding phase offset is an integer, and the ratio of the target cycle ratio to the initial cycle ratio is the same, guaranteeing that the generated clock reflects the phase offset. For example, if the clock configuration file contains two clocks, one with a phase offset of 20% and the other with no phase offset (zero phase), and the initial cycle ratio is 3:10, then multiplying the value of each proportional term by the reciprocal of 20% (5) yields 15:50, ensuring that 15 divided by 20% is an integer, guaranteeing that the generated clock reflects the corresponding phase offset. By dividing by the target ratio term, the value of each ratio term can be prevented from becoming too large. This avoids the ratio term value (period unit) in the target period ratio of the clock being too large, thus preventing the generated clock period from being too long and causing the frequency of the generated clock to differ too much from the target frequency. For example, if the initial period ratio is 3:10 and the target ratio term value is 3, multiplying the value of each ratio term by the reciprocal of 20% (5) and then dividing by 3, we obtain the target period ratio as follows: For example, if the reference clock frequency (here, the actual frequency, i.e., the physical frequency) is 100MHz, and one cycle of the first clock requires 5 cycles of the reference clock, then the frequency of the first clock obtained is 20MHz, only reduced by a factor of 5. This ensures that the period unit of the clock corresponding to the target ratio (the target clock) in the target cycle ratio is an integer, and the target clock is the clock within the group, guaranteeing the accuracy of the clock within the group. The other clock is the clock outside the group, and its period unit does not have to be an integer. Therefore, by sacrificing the accuracy of the non-critical clock (the clock outside the group), the value of the ratio term in the target cycle ratio can be prevented from becoming too large, avoiding excessively long clock cycles that require longer counting times. This reduces the computational load and allows the frequency of the generated clock to be close to the target frequency, improving the accuracy of the generated clock signal.

[0057] S130. Determine the current error of each clock cycle based on the target cycle ratio.

[0058] Specifically, when the proportional term in the target period ratio is an integer, one cycle of the clock is generated by an integer number of reference clock cycles. Therefore, when the proportional term in the target period ratio is an integer, an accurate clock can be generated, meaning the current error of the clock with an integer proportional term in the target period ratio is zero. When the proportional term in the target period ratio is a fraction or decimal, the current error of the corresponding clock is not zero. When the proportional term in the target period ratio is a fraction or decimal, the current error of the corresponding clock is the current cycle length of the reference clock. The current cycle length of the reference clock can be determined based on the target frequency of the target clock determined by the current target period ratio. For example, the current frequency of the reference clock can be determined based on the target frequency and the value of the proportional term of the target clock in the target period ratio, and the current cycle length of the reference clock can be determined based on the current frequency of the reference clock.

[0059] For example, the target period ratio is When generating the first clock, 5 units of reference clock are required, and the current error is zero. When generating the second clock, the units for every three consecutive cycles are 17, 16, and 17 respectively, so each cycle unit is consistent with... The discrepancy means the current error of the clock is not zero. (16 and) If the difference is significant, approximately 1, then the current error corresponding to this clock is the duration of one reference clock cycle. The ratio of the reference clock frequency, the first clock frequency, and the second clock frequency is... If the target frequency of the first clock is 100MHz, then the current frequency of the reference clock is 500MHz, and the current error of the second clock is 2ns. It should be noted that the current frequency of the reference clock here is a relative frequency.

[0060] For example, the target period ratio is When generating the first clock, 10 units of reference clock are required, and the current error is zero. When generating the second clock, the units for every three consecutive cycles are 33, 34, and 33 respectively, so each cycle unit is consistent with... The discrepancy means that the current error of the second clock is not zero. 34 and If the difference is significant, approximately 1, then the current error of that clock is the duration of one reference clock cycle. For example, if the target frequency of the first clock is 100MHz, and 10 reference clock cycles are needed to generate one cycle of the first clock, then the current frequency of the reference clock is 1000MHz, and the current error of the second clock is 1ns.

[0061] S140. If all current errors are less than or equal to the corresponding preset errors, then determine that the number of bits in the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits. When the number of bits in the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits, the target period ratio is used as the final configuration parameter.

[0062] Within a group, the clock is, for example, the clock within the same circuit module. The preset error of the clock within the group can be zero to ensure the accuracy of the clock within the group and to make the circuit simulation effective. The preset error of the clock outside the group is the accuracy requirement (input error) set in the clock configuration file.

[0063] Specifically, if the current error of each clock is less than or equal to the preset error corresponding to that clock, it indicates that the determined target period ratio meets the accuracy requirements. Then, if the number of bits in the binary value corresponding to each proportional term in the target period ratio is less than or equal to the preset number of bits, it indicates that the value has not overflowed, and the target period ratio is then used as the final configuration parameter. This avoids situations where the number of bits is too large, preventing the electronic device from meeting the required configuration and thus failing to generate the desired value. The preset number of bits can be 32 or 64; no limitation is made here.

[0064] If all the values ​​of the proportional terms in the target period ratio are integers, then the values ​​of the proportional terms in the target period ratio are directly converted into binary values. If there is a proportional term in the target period ratio that is a fraction, then the values ​​of all the proportional terms in the target period ratio are multiplied by the least common multiple of the denominators of all the fractions, the values ​​of all the proportional terms are converted into integers, then converted into binary values, and then it is determined whether the value is greater than the preset number of digits.

[0065] S150, Generate a clock signal based on the final configuration parameters.

[0066] Specifically, the value of each ratio item in the final configuration parameters is the final period unit, and a corresponding clock signal can be generated based on the period unit corresponding to each clock. For example, the target period ratio is... When all current errors are less than or equal to the corresponding preset errors, and the number of bits in the binary value corresponding to each proportional item in the target period ratio is less than or equal to the preset number of bits, then the final configuration parameters are: A clock signal can be generated by generating a reference clock with 5 cycles. When generating another clock, the units for every three consecutive cycles are 17, 16, and 17 respectively. That is, another clock signal can be generated by generating a reference clock with 17 cycles, a reference clock with 16 cycles, a reference clock with 17 cycles, and so on. This ensures that the cycle units for clocks within a group are integers, resulting in zero error. Clocks outside the group do not need to be integers. By sacrificing the accuracy of non-critical clocks (clocks outside the group), the value of the proportional term in the target cycle ratio is prevented from becoming too large, avoiding excessively long clock cycles that require longer counting times. Furthermore, the frequency of the generated clock is made close to the target frequency, improving the accuracy of the generated clock signal. Compared to related technologies, to ensure all period units are integers, when the initial period ratio is 3:10, the value of each proportional term is multiplied by the reciprocal of the clock offset of 20%, resulting in a period ratio of 15:50. When the reference clock frequency is 100MHz, the clock corresponding to period unit 15 is used as the reference clock. This reduces the frequency of the clock corresponding to the final generated period unit 15 by a factor of 15. The final configuration parameters in this embodiment are as follows: The actual frequency of the clock corresponding to the final generated period unit 5 is 20MHz, which is reduced by 5 times. This makes the period unit smaller and closer to the target frequency in the clock configuration file, thus improving the accuracy of clock signal generation.

[0067] When generating clock signals, any clock can be used as a standard to calculate the phase of all clocks. That is, the phase of other clocks besides the standard clock is generated according to the phase difference with the standard clock. At the edge of the clock (level transition), if the phase of a certain clock is less than the accuracy requirement of the phase of the standard clock, the edge of that clock can be aligned with the edge of the standard clock so that the edges overlap.

[0068] Optionally, after the clock signal is generated, if the clock configuration file is updated, the execution of step S110 is returned according to the updated clock configuration file. That is, steps S110 to S150 are re-executed according to the updated clock configuration file to realize dynamic modification of the clock signal frequency, that is, to realize dynamic configuration of the clock frequency, which makes it easy to modify the frequency at any time.

[0069] The technical solution of this embodiment determines the initial cycle ratio of all clocks based on the target frequency of each clock in the clock configuration file. The target cycle ratio is obtained by multiplying the value of the proportional term corresponding to each clock in the initial cycle ratio by the target value. The target value is the ratio of the least common multiple of the reciprocals of the phase offsets of all clocks to the value of the target proportional term. The clock corresponding to the target proportional term is the target clock. The current error of each clock is determined based on the target cycle ratio. When all current errors are less than or equal to the corresponding preset errors, and the number of bits in the binary value corresponding to the value of each proportional term in the target cycle ratio is less than or equal to the preset number of bits, the target cycle ratio is used as the final configuration parameter. A clock signal is generated based on the final configuration parameter. By multiplying the value of the proportional term corresponding to each clock in the initial cycle ratio by the target value, the target cycle ratio is obtained. This ensures that the generated clock reflects the phase offset, and that the cycle unit corresponding to each clock is not too large. Furthermore, by dividing by the value of the target proportional term, the cycle unit corresponding to clocks within the group is guaranteed to be an integer, while the cycle unit corresponding to clocks outside the group can be non-integer, thus ensuring the accuracy of the clocks within the group. By sacrificing the accuracy of non-critical clocks (clocks outside the group), the value of the proportional term in the target period ratio can be kept from being too large, avoiding excessively long clock periods that would require a longer counting time. Furthermore, the frequency of the generated clock can be made closer to the target frequency, thus improving the accuracy of the generated clock signal.

[0070] Based on the above technical solutions, Figure 2 This is a flowchart of another clock signal generation method provided by an embodiment of the present invention. Optionally, refer to... Figure 2 Clock signal generation methods include:

[0071] S210. Determine the initial cycle ratio of all clocks based on the target frequency of each clock in the clock configuration file.

[0072] S220. Multiply the value of the proportional term corresponding to each clock in the initial cycle ratio by the target value to obtain the target cycle ratio; where the target value is the ratio of the least common multiple of the reciprocals of the phase offsets of all clocks to the value of the target proportional term; the clock corresponding to the target proportional term is the target clock; the phase offset of the clock is the phase offset of the clock relative to the zero phase.

[0073] S230. Determine the current error of each clock cycle based on the target cycle ratio.

[0074] S240. Determine whether all current errors are less than or equal to the corresponding preset errors. If not, proceed to step S250. If yes, proceed to step S260.

[0075] S250, Multiply each proportional item in the target period ratio by the ratio of the current error to the preset error corresponding to the clock outside the group, and return to the execution step S230.

[0076] The preset error of clocks within a group is zero, while the preset error of clocks outside the group is the accuracy requirement set in the clock configuration file. In other words, all clocks outside the group have the same preset error.

[0077] Specifically, when the current error of a clock is greater than the preset error corresponding to that clock, the ratio of the current error to the preset error corresponding to the clock outside the group is greater than 1. Then, after multiplying each proportional term in the target period ratio by the ratio of the current error to the preset error corresponding to the clock outside the group, the period unit corresponding to each clock increases, the current frequency of the reference clock increases, and the current period duration of the reference clock decreases, thereby reducing the error of the clock corresponding to the non-integer proportional term.

[0078] S260. Determine whether the number of bits in the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits. If not, proceed to step S270; if yes, proceed to step S280.

[0079] S270. Adjust the target cycle ratio and return to step S260.

[0080] Specifically, if the number of bits in the binary value corresponding to the value of a proportional term in the target period ratio is greater than the preset number of bits, it indicates that the value has overflowed and the target period ratio needs to be adjusted and updated. For example, the value of the larger proportional term in the target period ratio can be reduced to decrease the value and thus reduce the overflow.

[0081] S280, Use the target cycle ratio as the final configuration parameter.

[0082] Specifically, the target period ratio corresponding to all current errors less than or equal to the corresponding preset errors, and the number of bits of the binary value corresponding to the value of each ratio item in the target period ratio less than or equal to the preset number of bits, is used as the final configuration parameter, so that the error of the final configuration parameter is small and the value does not overflow.

[0083] S290, Generate a clock signal based on the final configuration parameters.

[0084] Based on the above technical solutions, Figure 3 This is a flowchart of another clock signal generation method provided by an embodiment of the present invention. Optionally, refer to... Figure 3 Clock signal generation methods include:

[0085] S310. Determine the initial cycle ratio of all clocks based on the target frequency of each clock in the clock configuration file.

[0086] S320. Multiply the value of the proportional term corresponding to each clock in the initial cycle ratio by the target value to obtain the target cycle ratio; where the target value is the ratio of the least common multiple of the reciprocals of the phase offsets of all clocks to the value of the target proportional term; the clock corresponding to the target proportional term is the target clock; the phase offset of the clock is the phase offset of the clock relative to the zero phase.

[0087] S330. Determine the current error of each clock cycle based on the target cycle ratio.

[0088] S340. Determine whether all current errors are less than or equal to the corresponding preset errors. If not, proceed to step S350. If yes, proceed to step S360.

[0089] S350, Multiply each proportional item in the target period ratio by the ratio of the current error to the preset error corresponding to the clock outside the group, and return to the execution step S330.

[0090] S360. Determine whether the number of bits in the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits. If not, proceed to step S370. If yes, proceed to step S394.

[0091] S370. Determine whether the target period ratio has been adjusted or whether the current error is equal to the preset error corresponding to the clock outside the group. If not, proceed to step S380; if yes, proceed to step S390.

[0092] Specifically, if the target period ratio determined in the first step makes each clock less than or equal to the corresponding preset error (i.e., the value of the proportional term corresponding to each clock in the initial period ratio is multiplied by the target value, resulting in a target period ratio where each clock is less than or equal to the corresponding preset error), then the target period ratio has not been adjusted before step S370. If the target period ratio obtained by multiplying the value of the proportional term corresponding to each clock in the initial period ratio by the target value has a current error greater than the corresponding preset error, then the target period ratio needs to be adjusted, meaning the target period ratio has been adjusted. If the current error is equal to the preset error corresponding to a clock outside the group, then the ratio of the current error to the preset error corresponding to a clock outside the group is 1. Multiplying by 1 cannot adjust the value of the proportional term, so the target period ratio is adjusted by directly decreasing the value of the nth proportional term.

[0093] S380. Multiply each proportional item in the target period ratio by the ratio of the current error to the preset error corresponding to the clock outside the group, and return to the execution step S360.

[0094] Specifically, when the target period ratio has not been adjusted and the current error is not equal to the preset error corresponding to the clock outside the group, the value of each proportional term in the target period ratio can be multiplied by the ratio of the current error to the preset error corresponding to the clock outside the group. If the current error is less than the preset error corresponding to the clock outside the group, the value of each proportional term in the target period ratio can be reduced, thereby reducing numerical overflow.

[0095] S390. Determine the current number of times that the binary value corresponding to the proportional term in the target period ratio has more bits than the preset number of bits.

[0096] Specifically, after the target cycle ratio is adjusted, and when the current error equals the preset error corresponding to the clock outside the group, the target cycle ratio is determined to have a binary value whose number of bits is greater than the preset number of bits for the current number of times. Based on this current number, the value of the nth proportional term is reduced to obtain the adjusted target cycle ratio. This avoids the problem of excessive computation caused by multiplying the adjusted target cycle ratio by the ratio of the current error to the preset error corresponding to the clock outside the group. It also avoids the problem of the ratio of the current error to the preset error corresponding to the clock outside the group being 1, making adjustment impossible.

[0097] The current count is the number of times the binary value corresponding to the value of the proportional item in the target period ratio has more bits than the preset number of bits. In other words, it is the number of times that after executing S360 and judging whether the binary value corresponding to the value of each proportional item in the target period ratio has more bits than or equal to the preset number of bits, the result is no.

[0098] S391. Determine whether the current count is less than or equal to the number of clocks outside the group. If yes, proceed to step S392; otherwise, proceed to step S393.

[0099] S392. Arrange the values ​​of the proportional terms in the target cycle ratio corresponding to the clocks outside the group in descending order, and reduce the value of the nth proportional term to obtain the adjusted target cycle ratio, and return to execute step S360; where n is the current number of times.

[0100] Specifically, the values ​​of the proportional terms in the current target period ratio corresponding to the clocks outside the group are arranged in descending order, meaning the first proportional term has the largest value and corresponds to the lowest clock frequency. The value of the nth proportional term is decreased to obtain the adjusted target period ratio, where n is the current count. That is, if the number of bits in the binary value corresponding to each proportional term in the target period ratio is greater than a preset number of bits in the first check, the value of the first proportional term is decreased. If the value still overflows after decreasing the first proportional term, the value of the second proportional term is decreased in the second check, and so on, until the adjusted target period ratio does not overflow, or until the values ​​of all the target proportional terms corresponding to the clocks outside the group have been adjusted. This reduces the larger values ​​in the target period ratio, preventing overflow. Furthermore, the target period ratio values ​​corresponding to the clocks within the group remain unchanged, ensuring the accuracy of the clocks within the group.

[0101] Decreasing the value of the nth proportional term can be achieved by reducing the value of the nth proportional term according to the number of decimal places within the precision range. Specifically, it can be done by reducing the value of the nth proportional term according to the number of decimal places *m* of the preset error of the external clock, where *m* is an integer greater than or equal to 0. For example, the value of the nth proportional term can be reduced by removing the value after the *m*th decimal place. For instance, if the preset error of the external clock is 1.2 ns with one decimal place, and the value of the nth proportional term is 33.33, then the value of the nth proportional term will be reduced to 33.3. Alternatively, if the preset error of the external clock is an integer, such as 1 ns, then the value of the nth proportional term will be reduced to 33. For example, if the target period ratio is... If the preset error of the clock outside the group is an integer, then the adjusted target cycle ratio is 10:33.

[0102] S393, Issue a prompt message.

[0103] Specifically, after adjusting the values ​​of the target ratio terms corresponding to the clocks outside the group, if the binary value corresponding to the ratio term in the target period ratio still has a preset number of bits, a prompt message will be issued to report an error, and the user can exit after reporting the error.

[0104] S394. Use the target cycle ratio as the final configuration parameter.

[0105] S395. Generate a clock signal based on the final configuration parameters.

[0106] Based on the above technical solutions, optionally, the initial cycle ratio of all clocks is determined according to the target frequency of each clock in the clock configuration file, including:

[0107] Based on the target frequency of each clock in the clock configuration file, determine the cycle ratio of all clocks, and divide each ratio term of all clock cycles by the greatest common factor of all target frequencies to obtain the initial cycle ratio.

[0108] Specifically, the ratio of the reciprocals of the target frequencies of each clock in the clock configuration file is the period ratio of all clocks. By dividing each proportional term in the period ratio of all clocks by the greatest common factor of all target frequencies, the initial period ratio is obtained. This ensures that the value of each proportional term in the initial period ratio is not too large, meaning the period unit corresponding to each clock is not too large. This avoids generating clock signals with excessively low frequencies, thereby improving the accuracy of clock signal generation. For example, if the first clock is 100MHz, the second clock is 30MHz, the period ratio of all clocks is 30:100, and the greatest common factor is 10, then the initial period ratio is 3:10.

[0109] Based on the above technical solutions, optionally, the current error of each clock cycle can be determined according to the target cycle ratio, including:

[0110] Step a1: Determine the current frequency of the reference clock based on the value of the proportional term corresponding to the target clock in the target period ratio and the target frequency of the target clock.

[0111] Specifically, the value of the proportional term corresponding to the target clock in the target period ratio represents the period unit of the target clock, that is, how many reference clock periods are needed to generate one period of the target clock. The duration of one period of the target clock divided by the value of the proportional term in the target period ratio gives the duration of one period of the reference clock. Therefore, the target frequency of the target clock multiplied by the value of the proportional term in the target period ratio gives the current frequency of the reference clock. For example, if the value of the proportional term in the target period ratio is 5, and the target frequency of the target clock is 100MHz, then the current frequency of the reference clock is 500MHz.

[0112] Step a2: Determine the current error of each clock based on the current frequency.

[0113] Specifically, the current error of the clock within the group is zero. When the target period ratio of the clock outside the group is an integer, an integer number of reference clock periods are needed to generate one clock period. Therefore, the current error of the clock outside the group with an integer target period ratio is also zero. For example, if the current frequency of the reference clock is 500MHz and the period length is 2ns, and the target period ratio of the clock outside the group is not an integer, the corresponding current error is greater than zero, approximately the period length of one reference clock, which is 2ns.

[0114] Based on the above technical solutions, optionally, the preset error corresponding to the clock in the group in the clock configuration file is zero;

[0115] The preset error for clocks outside the group in the clock configuration file is the input error in the clock configuration file.

[0116] Specifically, the preset error for the clock within the group is zero, which guarantees the accuracy of the clock within the group. The preset error for the clock outside the group in the clock configuration file, and the input error (or accuracy requirement) in the clock configuration file, can ensure that the clock outside the group also meets the user's accuracy requirements.

[0117] This invention also provides a clock signal generation device, which is used to execute the clock signal generation method provided in any embodiment of this invention. Figure 4 This is a schematic diagram of a clock signal generation device provided in an embodiment of the present invention, for reference. Figure 4 The clock signal generating device includes:

[0118] The initial cycle ratio determination module 101 is used to determine the initial cycle ratio of all clocks based on the target frequency of each clock in the clock configuration file.

[0119] The target period ratio determination module 102 is used to multiply the value of the proportional term corresponding to each clock in the initial period ratio by the target value to obtain the target period ratio; wherein, the target value is the ratio of the least common multiple of the reciprocals of the phase offsets of all clocks to the value of the target proportional term; the clock corresponding to the target proportional term is the target clock; the phase offset of the clock is the phase offset of the clock relative to the zero phase;

[0120] The current error determination module 103 is used to determine the current error of each clock cycle based on the target cycle ratio;

[0121] The final configuration parameter determination module 104 is used to determine whether the number of bits of the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits if all current errors are less than or equal to the corresponding preset errors. When the number of bits of the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits, the target period ratio is used as the final configuration parameter.

[0122] The clock signal generation module 105 is used to generate a clock signal based on the final configuration parameters.

[0123] The clock signal generation device provided in the embodiments of the present invention can execute the clock signal generation method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0124] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Figure 5A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0125] like Figure 5 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0126] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0127] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as clock signal generation methods.

[0128] In some embodiments, the clock signal generation method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the clock signal generation method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the clock signal generation method by any other suitable means (e.g., by means of firmware).

[0129] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0130] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0131] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0132] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0133] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0134] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0135] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0136] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for generating a clock signal, characterized in that, include: Determine the initial cycle ratio of all clocks based on the target frequency of each clock in the clock configuration file; The target period ratio is obtained by multiplying the value of the proportional term corresponding to each clock in the initial period ratio by the target value; wherein, the target value is the ratio of the least common multiple of the reciprocals of the phase offsets of all clocks to the value of the target proportional term; the clock corresponding to the target proportional term is the target clock; the phase offset of the clock is the phase offset of the clock relative to the zero phase; The current error for each clock cycle is determined based on the target cycle ratio; If all current errors are less than or equal to the corresponding preset errors, then determine whether the number of bits of the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits. If the number of bits of the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits, then use the target period ratio as the final configuration parameter. A clock signal is generated based on the final configuration parameters.

2. The method according to claim 1, characterized in that, After determining the current error of each clock cycle based on the target cycle ratio, the method further includes: If the current error of a clock is greater than the preset error corresponding to the clock, then each ratio term in the target period ratio is multiplied by the ratio of the current error to the preset error corresponding to the clock outside the group, and the process returns to the step of determining the current error of each clock based on the target period ratio.

3. The method according to claim 1, characterized in that, After determining that the number of bits in the binary value corresponding to each proportional term in the target period ratio is less than or equal to a preset number of bits, the method further includes: If the number of bits in the binary value corresponding to the value of a proportional term in the target period ratio is greater than the preset number of bits, the target period ratio is adjusted, and the process returns to the step of determining whether the number of bits in the binary value corresponding to the value of each proportional term in the target period ratio is less than or equal to the preset number of bits.

4. The method according to claim 3, characterized in that, Adjusting the target cycle ratio includes: If the target cycle ratio has been adjusted or the current error is equal to the preset error corresponding to the clock outside the group, then it is determined that there is a current number of times that the binary value corresponding to the value of the proportional term in the target cycle ratio has more bits than the preset number of bits. When the current count is less than or equal to the number of clocks outside the group, the values ​​of the proportional terms in the target period ratio corresponding to the clocks outside the group are arranged in descending order, and the value of the nth proportional term is reduced to obtain the adjusted target period ratio; where n is the current count; When the current count exceeds the number of clocks outside the group, a prompt message is issued; If the target period ratio has not been adjusted and the current error is not equal to the preset error corresponding to the clock outside the group, then each proportional term in the target period ratio is multiplied by the ratio of the current error to the preset error corresponding to the clock outside the group, and the process returns to the step of determining whether the number of bits of the binary value corresponding to the value of each proportional term in the target period ratio is less than or equal to the preset number of bits.

5. The method according to any one of claims 1-4, characterized in that, Based on the target frequency of each clock in the clock profile, determine the initial cycle ratio of all clocks, including: Based on the target frequency of each clock in the clock configuration file, determine the cycle ratio of all clocks, and divide each ratio term of all clock cycles by the greatest common factor of all target frequencies to obtain the initial cycle ratio.

6. The method according to any one of claims 1-4, characterized in that, Determining the current error of each clock cycle based on the target cycle ratio includes: The current frequency of the reference clock is determined based on the value of the corresponding proportional term in the target period ratio and the target frequency of the target clock. The current error of each clock is determined based on the current frequency.

7. The method according to any one of claims 1-4, characterized in that, The preset error for the clock within the group in the clock configuration file is zero. The preset error corresponding to the clock outside the group in the clock configuration file is the input error in the clock configuration file.

8. A clock signal generating device, characterized in that, include: The initial cycle ratio determination module is used to determine the initial cycle ratio of all clocks based on the target frequency of each clock in the clock configuration file. The target period ratio determination module is used to multiply the value of the proportional term corresponding to each clock in the initial period ratio by a target value to obtain the target period ratio; wherein, the target value is the ratio of the least common multiple of the reciprocals of the phase offsets of all clocks to the value of the target proportional term; the clock corresponding to the target proportional term is the target clock; the phase offset of the clock is the phase offset of the clock relative to the zero phase; The current error determination module is used to determine the current error of each clock cycle based on the target cycle ratio. The final configuration parameter determination module is used to determine whether the number of bits of the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits if all current errors are less than or equal to the corresponding preset errors. When the number of bits of the binary value corresponding to the value of each proportional item in the target period ratio is less than or equal to the preset number of bits, the target period ratio is used as the final configuration parameter. A clock signal generation module is used to generate a clock signal based on the final configuration parameters.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the clock signal generation method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the clock signal generation method according to any one of claims 1-7.

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