Three-dimensional simulation control circuit generation method and system and electronic equipment

Abstract

The invention is suitable for the technical field of electric power simulation, and provides a three-dimensional simulation control circuit generation method and system and electronic equipment, and the method comprises the steps: responding to a user topology adjustment operation, starting from a set terminal in a circuit topology, carrying out the recursive traversal of a plurality of topology nodes in the circuit topology, determining a grounding state of a common end in the plurality of topological nodes and a topological connection relationship between non-common ends; under the condition that the grounding state is an effective grounding state, determining at least one target topological branch extending from each non-common end based on the topological connection relationship, and determining branch current and branch voltage of each target topological branch corresponding to each non-common end; generating a legal target wire path based on the branch current of each target topological branch; and generating a three-dimensional simulation control circuit based on the branch current, the branch voltage and the target wire path. According to the scheme, the generation efficiency of the three-dimensional simulation control circuit can be improved, and the real-time interaction requirement of electric power operation training is met.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power simulation, and particularly relates to a three-dimensional simulation control circuit generation method and system and electronic equipment. BACKGROUND

[0002] A three-dimensional power simulation system is constructed by using a three-dimensional power simulation technology. A three-dimensional simulation control circuit exists in the three-dimensional power simulation system, and the three-dimensional simulation control circuit can visually display device layout and electrical connection to provide visual support for power operation training. However, when a user adjusts a circuit topology, the three-dimensional simulation control circuit corresponding to the adjusted circuit topology is generated at a relatively low efficiency, and cannot meet the real-time interaction requirement of power operation training. SUMMARY

[0003] Embodiments of the application provide a three-dimensional simulation control circuit generation method and system and electronic equipment to solve the problem in the prior art that the three-dimensional simulation control circuit is generated at a low efficiency when a user adjusts a circuit topology, and cannot meet the real-time interaction requirement of power operation training.

[0004] A first aspect of embodiments of the application provides a three-dimensional simulation control circuit generation method, including: In response to a user topology adjustment operation, a plurality of topology nodes in a circuit topology are recursively traversed from a set terminal in the circuit topology to determine a grounding state of a common terminal and a topology connection relationship between non-common terminals in the plurality of topology nodes; In a case where the grounding state is a valid grounding state, at least one target topology branch extending from each non-common terminal is determined based on the topology connection relationship, and branch current and branch voltage of each target topology branch corresponding to each non-common terminal are determined; A target conductor path with a legal path is generated based on the branch current of each target topology branch; A three-dimensional simulation control circuit is generated based on the branch current, the branch voltage, and the target conductor path.

[0005] A second aspect of embodiments of the application provides a three-dimensional simulation control circuit generation system, including: A first determination module is configured to, in response to a user topology adjustment operation, recursively traverse a plurality of topology nodes in a circuit topology from a set terminal in the circuit topology to determine a grounding state of a common terminal and a topology connection relationship between non-common terminals in the plurality of topology nodes; A second determination module is configured to, in a case where the grounding state is a valid grounding state, determine at least one target topology branch extending from each non-common terminal based on the topology connection relationship, and determine branch current and branch voltage of each target topology branch corresponding to each non-common terminal. a path generation module configured to generate a path-legal target conductor path based on the branch current of each of the target topology branches; a circuit generation module configured to generate a three-dimensional simulation control circuit based on the branch current, the branch voltage and the target conductor path.

[0006] A third aspect of the embodiments of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the method according to the first aspect when executing the computer program.

[0007] A fourth aspect of the present application provides a computer program product, the computer program product comprising a computer program, the computer program being executed by a processor to implement the steps of the method according to the first aspect.

[0008] A fifth aspect of the embodiments of the present application provides a computer-readable storage medium, the computer-readable storage medium storing a computer program, and the computer program being executed by a processor to implement the steps of the method according to the first aspect.

[0009] As can be seen from the above, in response to a user topology adjustment operation, the present application starts from a set terminal in a circuit topology, recursively traverses a plurality of topology nodes in the circuit topology, determines the state of a common terminal and a non-common terminal in the plurality of topology nodes, determines at least one target topology branch extended by each non-common terminal based on a topology connection relationship when the ground state is valid, and further determines the branch current and the branch voltage of each target topology branch. The conditional design avoids redundant calculation in an invalid state and avoids resource waste of global electrical parameter recalculation. The branch current is used to generate a legal target conductor path, without waiting for global voltage convergence, thereby improving the path generation efficiency. The branch current, the branch voltage and the target conductor path are combined to generate a usable three-dimensional simulation control circuit, the circuit generation efficiency and the generation quality are greatly improved, and the real-time interaction demand of power operation training can be met. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0011] Figure 1 is a flowchart of a three-dimensional simulation control circuit generation method provided by the embodiments of the present application; Figure 2is a branch current monitoring schematic of a topology branch provided by an embodiment of the present application Figure 1 ; Figure 3 is a branch current monitoring schematic of a topology branch provided by an embodiment of the present application Figure 2 ; Figure 4 is a structure diagram of a three-dimensional simulation control circuit generation system provided by an embodiment of the present application; Figure 5 is a structure diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0012] In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular architectures, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, circuits, and

[0013] It is to be understood that the terminology "includes", "has", "holds", "contains" and / or "comprising", "comprised of", "comprising", as used in the specification and in the following claims, indicates the presence of the stated features, integers, steps, operations, elements, and / or components but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0014] It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in this specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0015] It will be further understood that the terms "and", "or", as used herein, and in the following claims are used to mean one and / or the other and / or both in the items linked by these terms. In addition, the terms "comprises", "comprising", "includes", "including", "has", "having" and the like are to be construed in a non-exclusive manner when employed in the description of the embodiments of the present application.

[0016] As used in this specification and the appended claims, the term "if" can be construed to mean "when" or "once" or "in response to a determination" or "in response to the occurrence of" that follows, depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be construed to mean "once it is determined" or "in response to a determination" or "once [the described condition or event] is detected" or "in response to the occurrence of [a described condition or event]," depending on the context.

[0017] In particular implementations, the terminals described in the embodiments of the present application include, but are not limited to, other portable devices such as mobile telephones, laptop computers, or tablet computers with touch-sensitive surfaces (e.g., touch screen displays and / or touch pads). It should also be understood that, in some embodiments, the device is not a portable communication device, but is a desktop computer with a touch-sensitive surface (e.g., a touch screen display and / or a touch pad).

[0018] In the following discussion, a terminal that includes a display and a touch-sensitive surface is described. It should be understood, however, that a terminal can include one or more other physical user-interface devices, such as a physical keyboard, a mouse and / or a joystick.

[0019] The terminal supports a variety of applications, such as one or more of the following: a drawing application, a presentation application, a word processing application, a website creation application, a disk authoring application, a spreadsheet application, a game application, a telephone application, a video conferencing application, an e-mail application, an instant messaging application, a workout support application, a photo management application, a digital camera application, a digital camcorder application, a web browsing application, a digital music player application, and / or a digital video player application.

[0020] The various applications that can be executed on the terminal can use at least one common physical user-interface device, such as a touch-sensitive surface. One or more functions of the touch-sensitive surface, as well as the display of information related to those functions, on the terminal can be adjusted and / or changed by the various applications based on their respective needs. By way of example, the display of information related to a particular application can be adjusted and / or changed by the application based on its needs. In some embodiments, the information displayed related to a particular application can be adjusted and / or changed by the application for which the information is displayed. In some embodiments, the information displayed related to a particular application can be adjusted and / or changed by the application for which the information is displayed.

[0021] It should be understood that the sequence of the steps in the embodiments of the present application does not mean the order of execution, the execution order of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0022] In order to illustrate the technical solutions described in the present application, the following will be described by specific embodiments.

[0023] Referring to Figure 1 , Figure 1 is a flowchart of a three-dimensional simulation control circuit generation method provided by the embodiments of the present application. As Figure 1 shown, a three-dimensional simulation control circuit generation method includes the following steps: At step 101, in response to a user topology adjustment operation, a plurality of topology nodes in the circuit topology are recursively traversed from a set terminal in the circuit topology to determine a grounding state of a common terminal in the plurality of topology nodes and a topology connection relationship between non-common terminals.

[0024] The topology adjustment operation of the user refers to a logical action of modifying an existing circuit topology structure (such as adjusting a grounding state, adding or deleting a node, adding or deleting a branch, or adjusting a connection relationship) or creating a brand-new circuit topology. The topology adjustment operation covers all scenarios from local fine-tuning to global reconstruction.

[0025] The set terminal is a user-specified topology change starting point (such as dragging a wire end point) or a key node determined automatically according to the circuit topology structure (such as a switch terminal, a device input terminal, a power input terminal, or a grounding collection point). The essence is a dynamic entry of recursive traversal. The set terminal is a non-common terminal node. If it is a common terminal, the grounding is directly determined, and the traversal value is lost.

[0026] The topology node is a basic unit of the circuit topology, including a common terminal (a zero potential reference point) and a non-common terminal (such as a load access point or a signal transmission node). The common terminal assumes a safety grounding function, and the non-common terminal is responsible for current distribution and signal transmission.

[0027] The topology connection relationship describes the connection state and structure level between non-common terminals, including an on-off state, impedance characteristics, and dynamic connection rules. This relationship is the basis for current distribution, voltage distribution, and path generation.

[0028] In response to the topology adjustment operation of the user, recursive traversal is initiated from the set terminal in the circuit topology provided by the user. The properties of each topology node connected to the set terminal or other terminals traversed are quickly determined, and the common terminal and the non-common terminal in the circuit topology are identified. The grounding state of the common terminal is determined, and the topology connection relationship between the non-common terminals is determined according to the electrical connection state between the non-common terminals. Real-time and accurate topology states are provided for subsequent current distribution, voltage distribution, path generation, and three-dimensional circuit generation, ensuring generation efficiency and electrical rule safety.

[0029] In some embodiments, an example code for circuit topology construction and common terminal identification is as follows: void InitializeAlgorithms() { / / Create a circuit topology graph CircuitGraph graph = BuildTopologyGraph(); / / Precompute common terminal relationship CachePublicTerminalRelations(); }。

[0030] In some embodiments, the example code for detecting the grounding state of the public terminal is as follows: bool isGrounded = GroundingJudement(startTerminal, groundTerminal).

[0031] In some embodiments, the method for determining the grounding state of the public terminal and the topological connectivity relationship between the non-public terminals from the set terminal in the circuit topology comprises: traversing all the topological nodes connected by each terminal in the circuit topology in a depth-first order from the set terminal; determining whether each topological node is the public terminal during the traversal; if yes, terminating further traversal of the current topological branch and outputting the grounding state of the public terminal; if not, marking the topological node as visited and continuing to traverse the unvisited adjacent topological nodes of the topological node; and generating the topological connectivity relationship between the non-public terminals according to the access marks and connection relationships of all the topological nodes.

[0032] The depth-first search is started from the set terminal to identify the public terminal and the non-public terminal in the plurality of topological nodes.

[0033] In some embodiments, if a topological node forms a direct electrical connection with the ground or the system reference ground through a conductor, the topological node is determined to be a grounded node, i.e., a public terminal, otherwise, it is a non-public terminal.

[0034] In some embodiments, if the grounding resistance value of the public terminal meets the grounding safety threshold, the grounding state of the public terminal is determined to be effective grounding.

[0035] If the topological node is a public terminal, its grounding state is outputted and the traversal of the current topological branch is terminated to avoid redundant access to remote nodes. If the topological node is a non-public terminal, it is marked as visited and its connected unvisited adjacent nodes are recursively accessed.

[0036] In some embodiments, the recursive traversal guarantees the integrity of the topology and avoids the risk of missing nodes. During the recursive traversal, all visited nodes are recorded in the visited list to skip the processed nodes and avoid repeated traversal, reducing the time complexity from exponential to O(V+E), where V is the number of topological nodes and E is the number of topological branches.

[0037] Based on the node access state mark maintained in the recursive traversal process and the physical connection relationship between nodes, a connection relationship network of the non-public end is constructed to generate its topological connectivity relationship. The topological connectivity relationship reflects the connection state of the non-public end after user operation in real time, providing a structured input for subsequent current allocation.

[0038] In step 102, in the case where the grounding state is a valid grounding state, at least one target topological branch extended by each non-public end is determined based on the topological connectivity relationship, and the branch current and the branch voltage of each target topological branch corresponding to each non-public end are determined.

[0039] The valid grounding state refers to a state in which the grounding resistance value of the public end meets the grounding safety threshold, ensuring that the fault current can be effectively discharged to the ground to avoid dangerous voltage on the equipment. This state is a prerequisite for safe allocation of current and voltage, and is determined by real-time detection of the grounding resistance.

[0040] In the transmission direction of the current from the power supply to the load, the target topological branch is the topological branch extended by the non-public end, i.e., the topological branch with the non-public end as the starting node of the branch, which refers to an independent path (such as a wire path from a branch junction to an inductive load) that meets the electrical connectivity condition. Its boundary is defined by the branch starting node (current injection point) and the termination node (load access point).

[0041] The branch current and the branch voltage represent the current of the target topological branch and the potential difference between the two ends of the path, respectively.

[0042] Based on the topological connectivity relationship, the non-public end nodes that are electrically connected are screened to obtain the target topological branch, and then the branch current and the branch voltage of each target topological branch are determined. The allocation of current and voltage depends on the valid grounding state, and the calculation is automatically blocked when the grounding is invalid to avoid waste of redundant resources.

[0043] In some embodiments, the branch voltage is solved by Kirchhoff's voltage law based on the branch starting node.

[0044] In some embodiments, the branch current includes the current-carrying capacity and the phase characteristic, and the determination of the branch current of each target topological branch corresponding to each non-public end includes: according to the number of target topological branches extended by each non-public end, the to-be-allocated current is equally allocated to each target topological branch to obtain the current-carrying capacity of each target topological branch; and according to the load type of each target topological branch, the phase characteristic of the target topological branch is determined.

[0045] The branch current refers to the current flowing through the target topological branch, including the current-carrying capacity and the phase characteristic. The current-carrying capacity is determined by the branch allocation rule, and the phase characteristic is determined depending on the load type.

[0046] The non-public end is taken as a current distribution root node, and the to-be-distributed current at the current distribution root node is distributed according to the number of topology branches extending from the non-public end, and the to-be-distributed current is distributed to each target topology branch according to the distribution principle of I 支路 = I 总 / n in an equal ratio. The current-carrying capacity is independently calculated without impedance scanning of the whole network, and the equal ratio distribution algorithm reduces the calculation complexity from O(n 2 ) of the traditional impedance ratio distribution to constant level O(1), thereby reducing the distribution delay.

[0047] The load types are divided into three types of resistance, inductance or capacitance, and different types of loads correspond to different phase compensation requirements. Therefore, the phase characteristics of the target topology branch need to be determined in combination with the type of the load in the target topology branch.

[0048] In some embodiments, the determination of the phase characteristics of the target topology branch according to the type of the load in each target topology branch comprises: if the type of the load in the target topology branch is an inductive load, a set lag compensation angle is superimposed on the initial phase angle of the target topology branch; if the type of the load in the target topology branch is a capacitive load, a set lead compensation angle is superimposed on the initial phase angle of the target topology branch; and if the type of the load in the target topology branch is a resistive load, the initial phase angle of the target topology branch is determined as a target phase angle.

[0049] The initial phase angle refers to the phase state value of a periodic signal (such as alternating current) at the starting point of timing (t=0).

[0050] The current of the resistive load is in phase with the voltage, that is, the phase difference is 0°, and there is no phase compensation requirement; the current of the inductive load lags behind the voltage by 90°, and a phase compensation angle of +180° is required to suppress eddy current loss; and the current of the capacitive load leads the voltage by 90°, and a phase compensation angle of -90° is required to balance the electric field. The design of maintaining the initial phase angle of the resistive load can avoid redundant operation and improve the efficiency of the circuit generation. The dynamic compensation of the capacitive load and the inductive load can ensure that the system resonance risk approaches zero and improve the quality of the circuit generation.

[0051] The load type of each branch end is identified, the resistive load maintains the initial phase angle, the inductive load superimposes a set lag compensation angle, that is, superimposes a compensation angle of +180°, and the capacitive load superimposes a set lead compensation angle, that is, superimposes a compensation angle of -90°. According to this logic, the phase characteristics of the target topology branch are determined, that is, the phase angle is adaptively adjusted through the load type, the phase accuracy is improved, the current loss is reduced, and the signal fidelity of the three-dimensional simulation control circuit is improved.

[0052] In some embodiments, an example code for determining the branch current is as follows: if (isGrounded), DistributeCurrent(totalCurrent, rootNode).

[0053] At step 103, a path-legal target wire path is generated based on the branch current of each target topology branch.

[0054] The path legality requires that the generated wire path meets the electrical safety rules (such as the minimum line diameter constraint corresponding to the current-carrying capacity, the magnetic field avoidance distance corresponding to the phase characteristic) and the spatial obstacle avoidance requirements (such as the obstacle avoidance distance, the structure conflict detection).

[0055] The target wire path is a simulated geometric entity generated based on the branch current parameter, and its form (such as a straight line, an L-shaped polyline, and a Z-shaped polyline) is determined by the physical constraints of current mapping and the recursive obstacle avoidance algorithm.

[0056] The branch current of the target topology branch is dynamically mapped to the wire geometric constraint, and the physical routing meeting the electrical safety rules and the spatial rules, i.e., the target wire path, is generated.

[0057] The branch current realizes the wire path planning, reduces the path generation delay, and improves the efficiency and accuracy of the wire path generation.

[0058] In some embodiments, the generation of the path-legal target wire path based on the branch current of each target topology branch includes: determining a target electrical safety distance that needs to be met by the target wire path according to the current-carrying capacity in the branch current; in the case that there is a straight line path without obstacles and not less than the target electrical safety distance between two terminals to be connected, determining the straight line path as the wire path between the terminals; in the case that there is no straight line path without obstacles between the two terminals to be connected, recursively generating a polyline path bypassing the obstacle as the wire path with the target electrical safety distance as an initial value; if the polyline path bypassing the obstacle is not generated, increasing the target electrical safety distance by a set step length until the wire path meeting all electrical safety rules and spatial obstacle avoidance requirements is generated; performing path legality verification on the wire path, and determining the wire path that is path-legal as the target wire path.

[0059] The initial coordinates of two terminals to be connected in the target topology branch are obtained, and the initial distance between the terminals is determined.

[0060] In some embodiments, the target electrical safety distance that needs to be met by the current wire path is calculated according to the current-carrying capacity parameter contained in the branch current, and the distance is the minimum geometric distance that guarantees electrical insulation and prevents signal interference.

[0061] In some embodiments, the target electrical safety clearance that the current wire path needs to satisfy is determined by querying a preset load capacity and safety clearance table.

[0062] In some embodiments, the first electrical safety clearance is calculated according to the load capacity of the branch current, for example, when the load capacity is 20A, the first electrical safety clearance is 6.4mm or 40 pixels (pixel). The second electrical safety clearance is calculated according to the phase characteristics of the branch current, for example, when the load type in the target topology branch is an inductive load, the phase characteristics are the initial phase angle plus the lag compensation angle, and the magnetic field avoidance clearance, i.e., the second electrical safety clearance, is equal to the first electrical safety clearance multiplied by 20%. Finally, the target electrical safety clearance is solved based on the first electrical safety clearance and the second electrical safety clearance, for example, the target electrical safety clearance = the first electrical safety clearance + the second electrical safety clearance.

[0063] The safety clearance is solved by the branch current, and the global electromagnetic simulation is skipped to improve the path generation efficiency.

[0064] If there is no obstacle (such as other elements, case walls, etc.) on the straight line path between the two terminals to be connected and the initial clearance is greater than or equal to the target electrical safety clearance, the straight line path is determined as the wire path between the two terminals.

[0065] If there is an obstacle between the two terminals, the target electrical safety clearance calculated is used as the initial value, and a path planning algorithm is called to plan and generate a polyline path (such as an L-shaped or Z-shaped path) that can bypass the obstacle.

[0066] In some embodiments, if an effective polyline path is generated according to the target safety clearance, the polyline path is determined as the wire path.

[0067] In some embodiments, if the planning fails, i.e., a path that avoids all obstacles cannot be found according to the target safety clearance, a step size, for example, 15 pixels, is added to the target electrical safety clearance step by step, and after increasing the clearance, the recursive detection step is returned to try to generate the wire path again. This cycle is iterated until a wire path that satisfies the electrical safety rules (such as clearance requirements) and the space obstacle avoidance requirements is generated.

[0068] The generated wire path is subjected to path legality verification by a preset verification rule to obtain the target wire path.

[0069] In some embodiments, the path legality verification of the wire path and the determination of the wire path as the target wire path comprises: applying a test voltage signal on the wire path and monitoring the transmission direction of the test voltage signal in the wire path; if the terminal point of the transmission direction is the target terminal, determining that the wire path is legal and determining the wire path as the target wire path; if the terminal point of the transmission direction is not the target terminal, determining that the wire path is illegal.

[0070] A specific test voltage signal is applied on the generated wire path, and the transmission direction of the signal in the path is monitored in real time. When the terminal point of the signal direction is monitored to be the target terminal, it is determined that the wire path is legal, and the wire path is determined as the target wire path. If the terminal point of the signal direction is not the target terminal, it is determined that the wire path is illegal.

[0071] The path legality verification adopts a multi-scene dynamic judgment mechanism to cope with different types of electrical connections.

[0072] In some embodiments, the test voltage signal is applied by a tester, and the signal simulates the actual working current.

[0073] When the terminal point of the transmission direction of the test voltage signal is monitored to be the target terminal (including the tester terminal and the common terminal meeting the grounding standard), it is determined that the path is legal.

[0074] In some embodiments, if the terminal point is the tester terminal, a voltage increase operation can be performed to further verify the electrical connectivity by continuously applying the test voltage.

[0075] In some embodiments, if the terminal point is a common ground terminal, a phase angle adjustment is triggered to suppress the phase offset of the ground loop generated by the verification.

[0076] When the terminal point of the transmission direction is monitored to be a non-target terminal (such as other irrelevant devices) or an invalid terminal (open circuit), it is determined that the path is illegal.

[0077] In some embodiments, if the terminal point is a non-target terminal, the signal transmission is immediately blocked, and an alarm is given to prevent signal leakage.

[0078] In some embodiments, if the terminal point is in an open circuit state, it is marked as a high resistance fault.

[0079] The verification mechanism accurately identifies physical connection errors through voltage direction tracking, ensuring the electrical safety and topological accuracy of three-dimensional circuit simulation.

[0080] In some embodiments, an example code of the test voltage verification is as follows: bool isValid = ValidateVoltagePath(sourceDevice, targetTerminal).

[0081] In some embodiments, the example code for wire path generation is as follows: if (isValid), signalPaths = FindValidSignalPaths(sourceDevice)。

[0082] In the wire path generation process, the branch current is converted into intuitive geometric constraints (safety distance), combined with the "straight line first" strategy and the adaptive iterative loop path search algorithm, which avoids the tedious process of relying on engineers to manually test and adjust repeatedly in traditional circuit design. In a short period of time, the optimal layout scheme is automatically found to ensure the electrical safety and physical feasibility of the path, greatly reducing the design rework and cycle delay caused by design violations, realizing the automatic, efficient and reliable generation of wire paths, and improving the automation level of three-dimensional simulation control circuit design.

[0083] In some embodiments, if the legality check result of the wire path is illegal, the branch current of the topology branch associated with the wire path is re-determined.

[0084] If the legality check result of the wire path is illegal, the current redistribution algorithm is triggered, and the branch current of the topology branch associated with the wire path is re-determined based on the current topology connectivity relationship, providing compliance parameters for path regeneration. According to the updated branch current, the corresponding wire path is re-planned. Through local path regeneration, full network reconstruction is avoided, and the path generation efficiency is improved.

[0085] Step 104, generating a three-dimensional simulation control circuit based on the branch current, the branch voltage and the target wire path.

[0086] According to the spatial coordinates and topology connection relationship of the target wire path, multiple topology nodes and load devices are connected, and the branch current and branch voltage are bound for each target wire path, forming a three-dimensional simulation control circuit.

[0087] The abstract circuit parameters are converted into quantifiable and interactive three-dimensional simulation entities, realizing the closed-loop mapping of topology path to executable control circuit. The parameterized generation mechanism skips the manual layout link, reduces the three-dimensional modeling time, improves the circuit generation efficiency and generation quality, and further improves the user interaction experience.

[0088] In some embodiments, the three-dimensional simulation control circuit is a virtual model. According to the three-dimensional simulation control circuit, a corresponding real physical circuit can be constructed in the real world. Measuring equipment can be used to measure electrical parameters in the real physical circuit.

[0089] As Figure 2 shown, Figure 2 is a schematic diagram of branch current monitoring of a topology branch provided by an embodiment of the present application Figure 1 . The monitoring interface shown in Figure 2 shows the real-time branch current of the 01 branch (number 0001). The branch current parameters come from two independent measurement channels AD1 and AD2 and are collected via a current transformer (Chinese circuit symbol TA) with a transformation ratio of 1200:1. The figure clearly shows the current carrying capacity of each phase current, for example, the A-phase current (I a ) is 000.50A, the B-phase current (I b ) is 001.00A, and the C-phase current (I c ) is 000.00A. The figure also synchronously displays the phase angle of each current, for example, the phase angle of I b is ∠239°, and the phase angle of the zero sequence current (3I0) is ∠269°.

[0090] As Figure 3 shown, Figure 3 is a schematic diagram of branch current monitoring of a topology branch provided by an embodiment of the present application Figure 2 . The monitoring interface shown in Figure 3 shows the real-time branch current of the 02 branch (number 0002) which is different from Figure 2 . For example, the B-phase current (I b ) has a current carrying capacity of 003.00A and a phase angle of ∠120°, and the zero sequence current (3I0) has a current carrying capacity of 002.29A and a phase angle of ∠131°.

[0091] The current data of the 01 branch and the 02 branch are significantly different, and this difference intuitively reflects the influence of different load types (such as inductive and capacitive) or different operating states on the current parameters of each topology branch.

[0092] Real measurement shows that the branch current of the three-dimensional simulation control circuit generated by the present application is measurable, reproducible and accurate in the real world, which confirms that the present application from recursive traversal, electrical parameter allocation, path generation to the final three-dimensional simulation control circuit generation is feasible, reliable and efficient. The three-dimensional simulation control circuit generated by the present application is highly consistent with the physical reality, which can provide users with a more realistic and reliable simulation experience and improve the effect of power training.

[0093] In the embodiments of the present application, in response to a user topology adjustment operation, starting from a set terminal in a circuit topology, a plurality of topology nodes in the circuit topology are recursively traversed, the states of common terminals and non-common terminals in the plurality of topology nodes are determined, at least one target topology branch extending from each non-common terminal is determined based on a topology connection relationship when a ground state is valid, and branch currents and branch voltages of each target topology branch are further determined. Conditional design avoids redundant calculation in invalid state and avoids resource waste of global electrical parameter recalculation. A legal target wire path is generated using the branch current, without waiting for global voltage convergence, thereby improving path generation efficiency. Combined with the branch current, the branch voltage and the target wire path, a usable three-dimensional simulation control circuit is generated, and the circuit generation efficiency and generation quality are greatly improved, which can meet the real-time interaction demand of power operation training.

[0094] Referring to Figure 4 , Figure 4 is a structural diagram of a three-dimensional simulation control circuit generation system provided by the embodiments of the present application, and only parts related to the embodiments of the present application are shown for ease of description.

[0095] The three-dimensional simulation control circuit generation system 400 comprises a first determination module 401, a second determination module 402, a path generation module 403 and a circuit generation module 404.

[0096] The first determination module 401 is configured to, in response to a user topology adjustment operation, starting from a set terminal in a circuit topology, recursively traverse a plurality of topology nodes in the circuit topology, and determine a ground state of a common terminal and a topology connection relationship between non-common terminals in the plurality of topology nodes.

[0097] The second determination module 402 is configured to, in the case that the ground state is a valid ground state, determine at least one target topology branch extending from each non-common terminal based on the topology connection relationship, and determine a branch current and a branch voltage of each target topology branch corresponding to each non-common terminal.

[0098] The path generation module 403 is configured to generate a path legal target wire path based on the branch current of each target topology branch.

[0099] The circuit generation module 404 is configured to generate a three-dimensional simulation control circuit based on the branch current, the branch voltage and the target wire path.

[0100] In some embodiments, the first determination module is specifically configured to: starting from the set terminal, traversing all topology nodes connected by each terminal in the circuit topology in a depth-first order; in the traversal process, judging whether each topology node is the common terminal; If yes, terminate further traversal of the current topology branch and output the grounding state of the common end; If no, mark the topology node as visited and continue to traverse unvisited adjacent topology nodes of the topology node; According to the visit marks and connection relationships of all the topology nodes, generate the topology connectivity relationship between the non-common ends.

[0101] In some embodiments, the branch current includes a current-carrying capacity and a phase characteristic, and the second determination module is specifically configured to: According to the number of target topology branches extending from each of the non-common ends, allocate the to-be-allocated current to each of the target topology branches in equal proportions to obtain a current-carrying capacity of each of the target topology branches; According to the load type of each of the target topology branches, determine the phase characteristic of the target topology branch.

[0102] In some embodiments, the second determination module is further configured to: If the load type of the target topology branch is an inductive load, superimpose a set lag compensation angle on an initial phase angle of the target topology branch; If the load type of the target topology branch is a capacitive load, superimpose a set lead compensation angle on the initial phase angle of the target topology branch; If the load type of the target topology branch is a resistive load, determine the initial phase angle of the target topology branch as a target phase angle.

[0103] In some embodiments, the path generation module is specifically configured to: According to the current-carrying capacity in the branch current, determine a target electrical safety distance that needs to be met by the target conductor path; In the case that there is a straight line path between two terminals to be connected without obstacles and not less than the target electrical safety distance, determine the straight line path as the conductor path between the terminals; In the case that there is no straight line path without obstacles between two terminals to be connected, recursively generate a polygonal line path bypassing obstacles as the conductor path with the target electrical safety distance as an initial value; If the polygonal line path bypassing obstacles is not generated, increase the target electrical safety distance by a set step size until the conductor path meeting all electrical safety rules and space obstacle avoidance requirements is generated; Perform path legality verification on the conductor path, and determine the conductor path that is path legal as the target conductor path.

[0104] In some embodiments, the path generation module is specifically configured to: applying a test voltage signal on the wire path, and monitoring a transmission direction of the test voltage signal in the wire path; if the end point of the transmission direction is the target terminal, determining that the wire path is legal, and determining the wire path as the target wire path; if the end point of the transmission direction is not the target terminal, determining that the wire path is illegal.

[0105] In some embodiments, the path generation module is further configured to: if the legal verification result of the wire path is illegal, re-determining the branch current of the topology branch associated with the wire path.

[0106] The three-dimensional simulation control circuit generation system provided by the embodiments of the present application can realize each process of the embodiments of the three-dimensional simulation control circuit generation method and achieve the same technical effects. To avoid repetition, no further description is given here.

[0107] Figure 5 is a structural diagram of an electronic device provided by an embodiment of the present application. As shown in the diagram, the electronic device 5 of the embodiment includes at least one processor 50 (only one is shown in the diagram), a memory 51, and a computer program 52 stored in the memory 51 and executable on the at least one processor 50, wherein the processor 50 implements the steps in any of the method embodiments described above when executing the computer program 52. Figure 5

[0108] The electronic device 5 can be a desktop computer, a notebook computer, a palm computer, a cloud server, and the like. The electronic device 5 can include, but is not limited to, the processor 50 and the memory 51. Those skilled in the art can understand that the electronic device 5 can include more or fewer components, or combine certain components, or include different components, for example, the electronic device can also include an input / output device, a network access device, a bus, and the like. Figure 5 The electronic device 5 is merely an example and does not constitute a limitation on the electronic device 5, and can include more or fewer components than shown in the diagram, or combine certain components, or include different components, for example, the electronic device can also include an input / output device, a network access device, a bus, and the like.

[0109] ​The processor 50 can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0110] The memory 51 can be an internal storage unit of the electronic device 5, such as a hard disk or a memory of the electronic device 5. The memory 51 can also be an external storage device of the electronic device 5, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 5. Further, the memory 51 can also include both the internal storage unit and the external storage device of the electronic device 5. The memory 51 is used to store the computer program and other programs and data required by the electronic device. The memory 51 can also be used to temporarily store data that has been output or will be output.

[0111] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is exemplified, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the system is divided into different functional units or modules to complete all or part of the above described functions. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit, and the integrated unit can be realized in the form of hardware or in the form of software. In addition, the specific names of each functional unit and module are only for easy distinction, and do not limit the protection scope of the present application. The specific working process of the units and modules in the system can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0112] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0113] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0114] In the embodiments provided by the present application, it should be understood that the disclosed system / electronic device and method can be implemented in other ways. For example, the above-described system / electronic device embodiments are merely illustrative. For example, the division of the modules or units is merely a logical function division. There can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling or communication connection between the units can be indirect coupling or communication connection through some interface, system or unit, and can be electrical, mechanical or in other forms.

[0115] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. they can be located in one place, or distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0116] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0117] The integrated module / unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the above-mentioned embodiment methods can also be implemented by a computer program instructing related hardware, and the computer program can be stored in a computer readable storage medium. The computer program can implement the steps of each method embodiment described above when executed by a processor. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate forms. The computer readable medium can include any entity or device, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. that can carry the computer program code. It should be noted that the contents included in the computer readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.

[0118] The above-mentioned embodiment methods can also be implemented by a computer program product, which, when running on an electronic device, causes the electronic device to execute the steps of each method embodiment described above.

[0119] The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A three-dimensional simulation control circuit generation method characterized by comprising: The method comprises: in response to a user topology adjustment operation, recursively traversing a plurality of topology nodes in a circuit topology from a set terminal in the circuit topology, determining a grounding state of a common terminal in the plurality of topology nodes and a topology connectivity relationship between non-common terminals; in a case where the grounding state is a valid grounding state, determining at least one target topology branch extending from each of the non-common terminals based on the topology connectivity relationship, and determining a branch current and a branch voltage of each of the target topology branches corresponding to each of the non-common terminals; generating a target wire path that is path-legal based on the branch currents of each of the target topology branches; generating a three-dimensional simulation control circuit based on the branch currents, the branch voltages and the target wire path.

2. The method of claim 1, wherein, The recursively traversing a plurality of topology nodes in a circuit topology from a set terminal in the circuit topology, determining a grounding state of a common terminal in the plurality of topology nodes and a topology connectivity relationship between non-common terminals comprises: traversing all the topology nodes connected by each terminal in the circuit topology in a depth-first order from the set terminal; in the traversal process, determining whether each of the topology nodes is the common terminal; if yes, terminating further traversal of the current topology branch and outputting the grounding state of the common terminal; if no, marking the topology node as visited, and continuing to traverse unvisited adjacent topology nodes of the topology node; generating the topology connectivity relationship between the non-common terminals according to the access marks and connection relationships of all the topology nodes.

3. The method of claim 1, wherein, The branch current includes a current-carrying capacity and a phase characteristic, and the determining of the branch current of each of the target topology branches corresponding to each of the non-common terminals comprises: according to the number of target topology branches extending from each of the non-common terminals, equally distributing a to-be-distributed current to each of the target topology branches to obtain a current-carrying capacity of each of the target topology branches; determining the phase characteristic of the target topology branch according to a load type of each of the target topology branches.

4. The method of claim 3, wherein, The determining of the phase characteristic of the target topology branch according to a load type of each of the target topology branches comprises: if the load type of the target topology branch is an inductive load, superimposing a set lag compensation angle on an initial phase angle of the target topology branch; if the load type of the target topology branch is a capacitive load, superimposing a set lead compensation angle on the initial phase angle of the target topology branch; if the load type of the target topology branch is a resistive load, determining the initial phase angle of the target topology branch as a target phase angle.

5. The method of claim 1, wherein, The generating of a target wire path that is path-legal based on the branch currents of each of the target topology branches comprises: determining a target electrical safety distance that needs to be met by the target wire path according to the current-carrying capacity in the branch current; in a case where there is a straight line path between two terminals that needs to be connected, the straight line path being unobstructed and not less than the target electrical safety distance, determining the straight line path as a wire path between the terminals; In the case that there is no straight path without obstacles between the two terminals to be connected, taking the target electrical safety distance as an initial value, a broken line path bypassing obstacles is recursively generated as the wire path; If the broken line path bypassing obstacles is not generated, the target electrical safety distance is increased by a set step length until the wire path satisfying all electrical safety rules and spatial obstacle avoidance requirements is generated; The wire path is subjected to path legality verification, and the wire path that is path legal is determined as the target wire path.

6. The method of claim 5, wherein, The wire path is subjected to path legality verification, and the wire path that is path legal is determined as the target wire path, including: A test voltage signal is applied on the wire path, and transmission direction of the test voltage signal in the wire path is monitored; If the end point of the transmission direction is a target terminal, it is determined that the wire path is legal, and the wire path is determined as the target wire path; If the end point of the transmission direction is not the target terminal, it is determined that the wire path is illegal.

7. The method of claim 6, wherein, The method further includes: If the legality verification result of the wire path is illegal, the branch current of the topology branch associated with the wire path is re-determined.

8. A three-dimensional simulation control circuit generation system characterized by comprising: It includes: A first determination module is configured to, in response to a user topology adjustment operation, recursively traverse a plurality of topology nodes in a circuit topology from a set terminal in the circuit topology, determine a grounding state of a common terminal in the plurality of topology nodes and a topology connectivity relationship between non-common terminals, and determine a branch current and a branch voltage of each target topology branch extended by each non-common terminal based on the topology connectivity relationship in the case that the grounding state is a valid grounding state. A path generation module is configured to generate a path legal target wire path based on the branch current of each target topology branch. A circuit generation module is configured to generate a three-dimensional simulation control circuit based on the branch current, the branch voltage and the target wire path. An electronic device including a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to enable the electronic device to implement the method of any one of claims 1 to 7.

9. An electronic device, comprising: A computer program that, when executed, causes the method of any one of claims 1 to 7 to be performed.

10. A computer program product, characterised in that, ​

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