Resolution-oriented 4D millimeter wave radar antenna array and physical layout collaborative optimization method, program, equipment and storage medium

Abstract

The invention discloses a resolution-oriented 4D millimeter wave radar antenna array and physical layout collaborative optimization method, a program, equipment and a storage medium, which are suitable for a radar system with a limited space and a multi-chip structure. The method comprises the steps of firstly collecting system input parameters; then, an antenna design constraint model is constructed, spatial discretization is carried out, and an optimizable matrix model is formed; transmitting and receiving array structures in the azimuth angle direction and the pitch angle direction are jointly designed through a virtual array mapping strategy, so that the requirements of MIMO mapping efficiency maximization and target angle resolution are met. After an antenna structure is determined, an optimization objective function is further constructed based on strong constraint and soft constraint, and an antenna layout scheme which meets the manufacturing requirements and has optimal performance is obtained through a traversal and search method. According to the method, the virtual aperture can be effectively improved, the antenna number redundancy is reduced, the wiring accessibility is optimized, and the resolution and engineering realizability of a 4D radar system are enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radar system design and radar signal processing and electronic engineering, and particularly relates to a resolution-oriented 4D millimeter wave radar antenna array and physical layout collaborative optimization method, program, device and storage medium, which is suitable for high-resolution millimeter wave radar array design under a multi-chip cascading structure. BACKGROUND

[0002] With the rapid development of automatic driving and advanced driving assistance systems (ADAS), the performance requirements of vehicle perception systems are continuously increasing. 4D millimeter wave radars have gradually become one of the key sensors of vehicle environment perception systems due to their all-weather capability, multi-dimensional perception capability and anti-interference capability.

[0003] The angular resolution of traditional 4D millimeter wave radars is usually limited by the size and layout of the antenna array. To improve the resolution, existing solutions often expand the virtual aperture by increasing the number of antennas, using sparse arrays, optimizing waveform design, etc. However, these methods have many engineering constraints, such as limited printed circuit board (PCB) space, complex inter-chip wiring, fixed forbidden area, etc., making it difficult to deploy ideal antenna array designs in practice.

[0004] In addition, most current array design methods focus on electromagnetic performance optimization and are often disconnected from physical implementation, failing to model resolution design and physical layout uniformly, resulting in a large contradiction between antenna performance and engineering feasibility, limiting the mass production application of high-performance 4D radar systems.

[0005] Therefore, there is an urgent need for a resolution-oriented array structure design and layout method that can automatically adapt to multi-chip structures, circuit board space and wiring restrictions while meeting angular resolution requirements, achieving an engineering-landable antenna array solution. SUMMARY

[0006] The present application aims to propose a 4D millimeter wave radar antenna design method that balances radar performance and engineering feasibility, by constructing a constraint model and a collaborative optimization algorithm to unify the antenna array structure design and physical layout process, meeting the system's demand for high-resolution imaging in azimuth and elevation angles.

[0007] The present application proposes a resolution-oriented 4D millimeter wave radar antenna array and physical layout collaborative optimization method, program, device and storage medium, which includes the following technical solutions:

[0008] A resolution-oriented 4D millimeter wave radar antenna array and physical layout collaborative optimization method includes the following steps:

[0009] Step 1: Obtain the chip arrangement coordinates, printed circuit board size, antenna number, antenna size, forbidden step area parameters and target actual resolution, and combine them into a parameter set.

[0010] Step 2: According to the parameter set, a constraint model is constructed, and a design space is constructed according to the constraint model.

[0011] Step 3: Traverse all antenna layout matrices in the design space, and output candidate layout matrices.

[0012] Step 4: According to the candidate layout matrix, the space position is traversed and optimized based on the strong constraint mechanism and the soft constraint mechanism, and the optimal antenna space arrangement matrix is output.

[0013] Further, step 2 specifically includes the following steps:

[0014] Step 2.1: Construct a constraint model based on the parameter set.

[0015] Step 2.1.1: Map the chip coordinate set , and complete the mapping layer conversion by encapsulating the printed circuit board size, antenna size and forbidden step area parameters to obtain the constraint vector .

[0016]

[0017] Wherein, is the receiving antenna width, is the transmitting antenna width, is the printed circuit board width, is the printed circuit board length, is the chip width, is the chip length, is the chip arrangement coordinates.

[0018] Step 2.1.2: According to the constraint vector , the half-wavelength conversion is carried out to obtain the discretization constraint , and a binary antenna layout model is constructed.

[0019]

[0020] Wherein, is the discretization value of the receiving antenna width, is the discretization value of the transmitting antenna width, is the discretization value of the printed circuit board width, is the discretization value of the printed circuit board length, is the discretization value of the chip width, is the discretization value of the chip length, Discretized values ​​for chip layout coordinates;

[0021] The binary antenna layout matrix model for:

[0022]

[0023] in, For receiving antenna matrix, This is the azimuth transmit antenna vector. The elevation angle is the transmit antenna vector.

[0024] Step 2.2: Construct an traversable design space based on the constraint model.

[0025] Furthermore, the half-wavelength conversion in step 2.1.2 satisfies the following conditions: antenna size and forbidden area size are rounded up; printed circuit board size is rounded down; and chip coordinates are rounded to the nearest integer.

[0026] The traversable design space described in step 2.2 for:

[0027]

[0028] In this context, 0 represents an empty space, and 1 represents an antenna station location.

[0029] Furthermore, step 3 specifically includes the following steps:

[0030] Step 3.1: Generate the virtual antenna array corresponding to the current antenna layout matrix through spatial discretization and convolution mapping strategies.

[0031]

[0032]

[0033]

[0034] in, For azimuth virtual array, For pitch virtual array, This is a convolution operation.

[0035] Step 3.2: Calculate the virtual aperture and theoretical resolution based on the virtual antenna array.

[0036] Step 3.3: Determine whether the theoretical resolution is greater than the actual target resolution. If so, adjust the azimuth and elevation transmit antenna vectors of the current antenna layout matrix, update them to the next antenna layout matrix, and return to step 3.1. If so, output the antenna layout matrix corresponding to the current virtual antenna array layout design as the candidate layout matrix, and execute step 4.

[0037] Furthermore, the virtual aperture described in step 3.2 and theoretical resolution The specific calculation methods include:

[0038]

[0039]

[0040]

[0041] in, For azimuth virtual aperture, For pitch to virtual aperture.

[0042]

[0043]

[0044]

[0045] in This is the theoretical azimuth resolution. For theoretical pitch angle resolution, λ is the wavelength.

[0046] Furthermore, the strong constraint mechanism described in step 4 specifically includes:

[0047] The candidate layout matrices are superimposed.

[0048]

[0049]

[0050] in, The result of the superposition operation. For the candidate layout matrix, This is a no-step region matrix, where 1000 represents the no-step region outside the printed circuit board boundary, 100 represents the no-step region around the chip, and 0 represents the freely deployable region.

[0051] If the result value If the value is 101 or 1001, it indicates that the antenna overlaps with the boundary of the restricted area. In this case, the azimuth transmit antenna vector and the elevation transmit antenna vector are adjusted, and the process returns to step 3.

[0052] If the result value If the value is greater than or equal to the threshold, it indicates a violation of the antenna physical spacing rule. In this case, the azimuth transmit antenna vector and the elevation transmit antenna vector are adjusted, and the process returns to step 3.

[0053] If the result value If the value is not 101 or 1001 and is not greater than or equal to the threshold, then the candidate layout matrix satisfies the strong constraint mechanism condition and a soft constraint mechanism is applied to it.

[0054] Furthermore, the soft constraint mechanism described in step 4 specifically includes:

[0055] For all candidate layout matrices that satisfy the strong constraint mechanism, calculate the layout cost function value for each candidate layout matrix, and select the candidate layout matrix with the smallest layout cost function value as the optimal antenna spatial arrangement matrix.

[0056] The layout cost function The calculation methods include:

[0057]

[0058] in, All are weighting coefficients. This is the sum of the standard deviations of the distances between receiving antennas corresponding to the same chip. This is the sum of the standard deviations of the distances between the transmitting antennas corresponding to the same chip. This represents the standard deviation of the distance between the receiving antennas of different chips and the center of the chip. This represents the standard deviation of the distance between the transmitting antennas of different chips and the center of the chip.

[0059] A computer system includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method described above.

[0060] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0061] A computer program product includes computer instructions that, when executed by a processor, implement the steps of the above-described method.

[0062] The beneficial effects of this invention are as follows:

[0063] Compared with existing technologies, this invention effectively improves the integration and practicality of radar systems through joint optimization of antenna structure design and physical layout; with a fixed number of antennas, it can achieve a larger virtual aperture and higher angular resolution; at the same time, it can effectively avoid problems such as antenna conflicts, wiring difficulties and high-frequency phase mismatch, thereby enhancing system consistency; in addition, this design can flexibly adapt to different chip arrangement methods and circuit board limitations, and has broad engineering adaptability and promotional value. Attached Figure Description

[0064] Figure 1 This is a schematic diagram of the process of the present invention.

[0065] Figure 2 This is a diagram showing the matrix transformation structure of the antenna array model of the present invention.

[0066] Figure 3 This is a block diagram of the antenna array design algorithm of the present invention.

[0067] Figure 4 This is a schematic diagram of the antenna array layout algorithm of the present invention.

[0068] Figure 5 This is a comparison diagram of the output array arrangement in an embodiment of the present invention.

[0069] Figure 6 This is a comparison diagram of the output virtual array arrangement in an embodiment of the present invention.

[0070] Figure 7 This is a comparison diagram of the planar layout in an embodiment of the present invention.

[0071] Figure 8 This is a schematic diagram showing the performance analysis output of the antenna array design in an embodiment of the present invention. Detailed Implementation

[0072] The following is in conjunction with the appendix Figure 1 The present invention will be further described below.

[0073] A resolution-oriented method for co-optimizing 4D millimeter-wave radar antenna arrays and physical layout includes the following steps:

[0074] Step 1: Obtain the chip layout coordinates, printed circuit board size, number of antennas, antenna size, no-step region parameters, and actual target resolution, and combine them into a parameter set.

[0075] Step 2: Based on the parameter set, construct a constraint model, and construct a design space based on the constraint model.

[0076] Step 2 specifically includes the following steps:

[0077] Step 2.1: Construct a constraint model based on the parameter set.

[0078] Step 2.1.1: Define the chip coordinate set The mapping layer transformation is completed by encapsulating the printed circuit board size, antenna size, and forbidden region parameters to obtain the constraint vector. :

[0079]

[0080] in, For the receiving antenna width, The width of the transmitting antenna. For the width of the printed circuit board, For the length of the printed circuit board, For chip width, For chip length, The coordinates for chip layout.

[0081] Step 2.1.2: Based on the constraint vector Perform half-wavelength conversion to obtain the discretized constraints. And construct a binary antenna layout model. The half-wavelength conversion satisfies the following rules: antenna size and forbidden zone size are rounded up; printed circuit board size is rounded down; chip coordinates are rounded to the nearest integer.

[0082]

[0083] in, This is a discretized value of the receiving antenna width. This is a discretized value of the transmit antenna width. This represents the discretized value of the printed circuit board width. This represents the discretized value of the printed circuit board length. This is a discretized value of the chip width. This is a discretized value for the chip length. This represents the discretized values ​​of the chip layout coordinates.

[0084] The binary antenna layout matrix model for:

[0085]

[0086] in, For receiving antenna matrix, This is the azimuth transmit antenna vector. The elevation angle is the transmit antenna vector.

[0087] Step 2.2: Construct an traversable design space based on the constraint model. :

[0088]

[0089] In this context, 0 represents an empty space, and 1 represents an antenna station location.

[0090] Step 3: Traverse all antenna layout matrices in the design space and output candidate layout matrices.

[0091] Step 3 specifically includes the following steps:

[0092] Step 3.1: Generate the virtual antenna array corresponding to the current antenna layout matrix through spatial discretization and convolution mapping strategies.

[0093] The method for generating the virtual antenna array specifically includes:

[0094]

[0095]

[0096]

[0097] in, For azimuth virtual array, For pitch virtual array, This is a convolution operation;

[0098] Step 3.2: Calculate the virtual aperture and theoretical resolution based on the virtual antenna array.

[0099] The virtual aperture The specific calculation methods include:

[0100]

[0101]

[0102]

[0103] in, For azimuth virtual aperture, For pitch to virtual aperture.

[0104] The theoretical resolution The specific calculation methods include:

[0105]

[0106]

[0107]

[0108] in This is the theoretical azimuth resolution. For theoretical pitch angle resolution, λ is the wavelength.

[0109] Step 3.3: Determine whether the theoretical resolution is greater than the actual target resolution. If so, adjust the azimuth and elevation transmit antenna vectors of the current antenna layout matrix, update them to the next antenna layout matrix, and return to step 3.1. If so, output the antenna layout matrix corresponding to the current virtual antenna array layout design as the candidate layout matrix, and execute step 4.

[0110] Step 4: Based on the candidate layout matrix, perform spatial location traversal optimization based on strong constraint mechanism and soft constraint mechanism, and output the optimal antenna spatial layout matrix.

[0111] The strong constraint mechanism specifically includes:

[0112] Perform a superposition operation on the candidate layout matrices:

[0113]

[0114]

[0115] in, The result of the superposition operation. For the candidate layout matrix, This is a no-step region matrix, where 1000 represents the no-step region outside the printed circuit board boundary, 100 represents the no-step region around the chip, and 0 represents the freely deployable region.

[0116] If the result value If the value is 101 or 1001, it indicates that the antenna overlaps with the boundary of the restricted area. In this case, the azimuth transmit antenna vector and the elevation transmit antenna vector are adjusted, and the process returns to step 3.

[0117] If the result value If the value is greater than or equal to the threshold, it indicates a violation of the antenna physical spacing rule. In this case, the azimuth transmit antenna vector and the elevation transmit antenna vector are adjusted, and the process returns to step 3.

[0118] If the result value If the value is not 101 or 1001 and is not greater than or equal to the threshold, then the candidate layout matrix satisfies the strong constraint mechanism condition and a soft constraint mechanism is applied to it.

[0119] The soft constraint mechanism specifically includes:

[0120] For all candidate layout matrices that satisfy the strong constraint mechanism, calculate the layout cost function value for each candidate layout matrix, and select the candidate layout matrix with the smallest layout cost function value as the optimal antenna spatial arrangement matrix.

[0121] The layout cost function The calculation methods include:

[0122]

[0123] in, All are weighting coefficients. This is the sum of the standard deviations of the distances between receiving antennas corresponding to the same chip. This is the sum of the standard deviations of the distances between the transmitting antennas corresponding to the same chip. This represents the standard deviation of the distance between the receiving antennas of different chips and the center of the chip. This represents the standard deviation of the distance between the transmitting antennas of different chips and the center of the chip.

[0124] Example

[0125] This embodiment provides a detailed description of a specific implementation plan to demonstrate its complete design logic and engineering feasibility.

[0126] Step 1: Obtain system input parameters, including operating frequency, chip layout, PCB size, antenna quantity limit and no-deployment area, transmit and receive antenna configuration requirements, target horizontal and elevation angle resolution indicators, etc.

[0127] In one embodiment of the present invention, such as Figure 1 As shown, parameter modeling and constraint extraction are performed first to construct a system-level design space. This stage collects and uniformly describes various constraints affecting antenna array design and layout optimization, mainly including:

[0128] The operating parameters of the radar system, such as the center frequency and corresponding wavelength; the total number of chips in the multi-chip structure and their arrangement on the PCB, such as single row, double row, symmetrical distribution, etc.; the number of transmit channels (TX) and receive channels (RX) contained in each chip, used to calculate the total antenna resources of the system.

[0129] At the same time, the physical size parameters of the antenna unit must be input, and the minimum spacing and packaging restrictions of the antenna arrangement must be determined in combination with the actual chip packaging and wiring rules. The overall size and boundary shape of the PCB are also used as basic constraints. In addition, the location and size of the forbidden area must be marked to reflect the unsuitable space caused by factors such as the chip body, wiring layers, and heat dissipation components.

[0130] Ultimately, users can set the target angular resolution in both the azimuth and elevation directions according to the system's functional requirements, which will directly affect the subsequent construction and performance evaluation of the virtual array.

[0131] After the above parameters are input uniformly, the system constructs an overall design model that includes electromagnetic performance targets and physical manufacturing constraints, which serves as the basis for subsequent array structure optimization and planar layout solution.

[0132] Step 2: Construct a design constraint model based on the input parameters to form a design space that includes PCB space, electrical constraints, and target performance indicators;

[0133] In one specific embodiment of the present invention, in order to achieve unified optimization of the antenna array structure and physical layout space, such as Figure 2 As shown, the system maps the actual antenna structure and PCB space to a two-dimensional coordinate system with 0.5λ as the basic unit, establishing a multi-level discretized modeling framework. This modeling method ensures the accuracy of electromagnetic theory while taking into account the wiring precision of actual manufacturing, making the entire design process both engineering feasible and optimizable.

[0134] This modeling process includes the following four levels:

[0135] The first layer is the physical layer, which describes the actual physical structure of the system, including the chip layout on the PCB, the circuit board boundary outline, various no-debugging areas, and the physical dimensional constraints of devices such as chips and antennas. This layer reflects the placement boundaries and non-placeable areas, and is the foundation of the entire modeling process.

[0136] The second layer is the mapping layer. In this layer, the deployment points of each transmit antenna (TX) and receive antenna (RX) are abstracted as coordinate points in two-dimensional space, and a logical array structure is constructed. This structure is used for the subsequent construction of virtual apertures and MIMO convolution mapping process, and the antenna combination relationship is expressed through position encoding.

[0137] The third layer is a half-wavelength discrete layer, which discretizes the physical space into a grid system with units of 0.5λ. All physical structures (including the chip body, cannibalization areas, boundaries, etc.) are mapped to discrete grid coordinates. This precision meets the minimum spacing requirements of the antenna array and accurately reflects the device arrangement constraints, facilitating subsequent deployment decisions.

[0138] Finally, the matrix layer maps antenna deployment status, feasibility assessment, scoring functions, and other parameters into two-dimensional matrix operations. Deployment results are represented by a deployment matrix, no-deployment zones by an obstruction matrix, and the layout optimization objective function is expressed as a scoring matrix. All antenna translations, superpositions, collision detection, and objective optimizations can be efficiently performed in the matrix space.

[0139] Through the above four-layer modeling system, the system realizes a complete mapping from physical space to optimization space, enabling array structure design and layout optimization to be carried out collaboratively under a unified data framework, and providing a mathematical foundation and structural support for subsequent layout search algorithms.

[0140] Step 3: Adopt the MIMO virtual array principle and design a convolutional mapping strategy to jointly arrange the transmitting and receiving antennas to generate a virtual aperture, and design the array structure with the goal of maximizing the virtual aperture;

[0141] In one specific embodiment of the present invention, such as Figure 3 As shown, the system adopts the virtual array principle of MIMO radar. By constructing the two-dimensional arrangement of the transmitting antenna (TX) and receiving antenna (RX) in space, and using a two-dimensional convolutional mapping strategy, it combines and maps them into a virtual aperture array to achieve high-resolution angular domain sensing.

[0142] In this process, firstly, in the aforementioned discrete modeling space, all TX and RX combination schemes that meet resource constraints (i.e., the total number of antenna channels, chip port limitations, etc.) are enumerated. For each combination, the system performs a two-dimensional convolution operation to obtain the corresponding virtual array mapping result.

[0143] After the convolution result is generated, the system evaluates its structural performance, mainly including the following two aspects:

[0144] Firstly, angular resolution satisfaction is assessed. The continuous coverage length of the virtual array generated by convolution in the azimuth and elevation directions is analyzed to determine if it meets the user-defined target angular resolution requirements. If the virtual aperture length does not reach the corresponding threshold, the combination will be discarded.

[0145] Secondly, for virtual array structure optimization, the goal is to prioritize combinations that create larger virtual aperture lengths within a fixed number of antennas, while avoiding structural compaction or overlap. The system records the actual coverage area of ​​the virtual array in two-dimensional space and selects the scheme with the largest total aperture length to enhance resolution redundancy and angular accuracy.

[0146] In addition, the system also evaluates the mapping efficiency of the virtual array. Specifically, for each virtual array point, the number of times it is mapped by different TX-RX path combinations is counted, and a mapping frequency matrix is ​​constructed. A preference is given to combinations with fewer repetitive points and higher mapping uniformity to improve energy distribution efficiency and angular domain response consistency.

[0147] Finally, the system selects the best-performing array structure from all candidate combinations based on a comprehensive scoring function (which may consider virtual length, repetition rate, structural centrality, etc.), which serves as the input basis for the subsequent antenna physical layout stage.

[0148] Step 4: Under the constraints of chip layout, circuit board size, antenna size and no-hide area, adjust the physical layout of the antenna based on an optimization mechanism that combines strong and soft constraints to improve resolution and engineering feasibility.

[0149] In one specific embodiment of the present invention, after completing the virtual array structure design, the selected transmit (TX) and receive (RX) antennas need to be physically deployed in the circuit board (PCB) space, such as... Figure 4 As shown. This step not only needs to meet the design goals in terms of structure, but also needs to meet the manufacturing and wiring requirements in terms of engineering implementation.

[0150] The antenna deployment process of this invention comprehensively considers two types of constraints: strong constraints (hard restrictions) and soft constraints (adjustable optimization objectives).

[0151] Regarding strong constraints, the system ensures that the placement of each antenna element must meet the following conditions:

[0152] First, no two antennas may overlap, and the overall layout must not exceed the boundary area of ​​the PCB.

[0153] Second, the antenna must not cover the no-coverage area formed by the periphery of the chip or other components;

[0154] Third, the antenna elements must maintain a minimum physical distance of at least the preset distance to avoid electromagnetic coupling and to reserve space for subsequent wiring processes.

[0155] Regarding soft constraints, the system establishes a set of optimization objective functions to select the best-performing solution from feasible layout schemes. Specifically, these include:

[0156] (1) The positions of each TX and RX antenna relative to the center of the chip to which they are connected should be as consistent as possible in order to improve signal path consistency and reduce phase offset;

[0157] (2) The antenna layout among multiple chips should be kept as balanced as possible to avoid excessive density in a single area, thereby simplifying the wiring process and improving accessibility;

[0158] (3) The geometric center of the entire antenna array should be close to the center area of ​​the PCB to achieve layout symmetry and structural balance, and improve the electromagnetic stability and actual packaging compatibility of the system.

[0159] The deployment process employs an iterative spatial search algorithm, traversing all possible TX / RX deployment combinations. In each iteration, the system first performs a strong constraint validity check on the deployment scheme; if the scheme is feasible, it further calculates the comprehensive score function value based on soft constraint objectives such as deployment symmetry, balance, and center of gravity shift, and records the current optimal solution.

[0160] The iterative algorithm continuously searches for the highest-scoring layout scheme in the feasible solution space, and finally outputs a set of antenna layout results that perform well in terms of physical manufacturability, electromagnetic performance, system symmetry and trace reachability, as the final design output.

[0161] Step 5: Output the antenna deployment results that meet the performance indicators, constraints, and physical implementation requirements.

[0162] The antenna array design and planar layout design method proposed in this invention was verified on the TI millimeter-wave radar platform. The experiment selected a typical ULA chip layout structure and generated multiple array design schemes based on a fixed number of chips, channel resources, and PCB space.

[0163] like Figure 8 As shown, the system tests the resolution in the azimuth and elevation directions under various virtual array structures, verifying that the proposed structure optimization method can ensure that the system resolution meets the target requirements of 1.36° and 19.1°.

[0164] Furthermore, in Figure 6 By comparing the distribution of virtual array points generated under different combinations, it was found that the array point distribution generated by the present invention is more uniform, the aperture utilization rate is higher, the repetition rate is significantly reduced, and the energy concentration of the virtual array is enhanced.

[0165] Figure 5 The comparison between the traditional dense deployment scheme and the optimized deployment scheme obtained by the method of this invention is shown. In the traditional method, the antennas are concentrated on the periphery of the chip, resulting in serious wiring conflicts and asymmetry; while the structure generated by the method of this invention satisfies all strong deployment constraints and has good symmetry and balance.

[0166] Ultimately, as Figure 7 As shown, the output antenna layout scheme meets the manufacturing rules in the PCB physical space, with good layout centrality and balance, and achieves conflict-free routing, thus possessing engineering practicality.

[0167] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A resolution-oriented method for co-optimizing 4D millimeter-wave radar antenna arrays and physical layout, characterized in that... Includes the following steps: Step 1: Obtain the chip layout coordinates, printed circuit board size, number of antennas, antenna size, no-step region parameters, and actual target resolution, and combine them into a parameter set; Step 2: Based on the parameter set, construct a constraint model, and construct a design space based on the constraint model; Step 3: Traverse all antenna layout matrices in the design space and output the candidate layout matrix; Step 4: Based on the candidate layout matrix, perform spatial location traversal optimization based on strong constraint mechanism and soft constraint mechanism, and output the optimal antenna spatial layout matrix.

2. The resolution-oriented 4D millimeter-wave radar antenna array and physical layout co-optimization method according to claim 1, characterized in that, Step 2 specifically includes the following steps: Step 2.1: Construct a constraint model based on the parameter set; Step 2.1.1: Define the chip coordinate set The mapping layer transformation is completed by encapsulating the printed circuit board size, antenna size, and forbidden region parameters to obtain the constraint vector. ; in, For the receiving antenna width, The width of the transmitting antenna. For the width of the printed circuit board, For the length of the printed circuit board, For chip width, For chip length, For chip layout coordinates; Step 2.1.2: Based on the constraint vector Perform half-wavelength conversion to obtain the discretized constraints. And construct a binary antenna layout model; in, This is a discretized value of the receiving antenna width. This is a discretized value of the transmit antenna width. This represents the discretized value of the printed circuit board width. This represents the discretized value of the printed circuit board length. This is a discretized value of the chip width. This is a discretized value for the chip length. Discretized values ​​for chip layout coordinates; The binary antenna layout matrix model for: in, For receiving antenna matrix, This is the azimuth transmit antenna vector. The elevation angle is the transmit antenna vector; Step 2.2: Construct an traversable design space based on the constraint model.

3. The resolution-oriented 4D millimeter-wave radar antenna array and physical layout co-optimization method according to claim 2, characterized in that: Step 2.1.2 describes a half-wavelength conversion that satisfies the following conditions: antenna size and forbidden zone size are rounded up; printed circuit board size is rounded down; chip coordinates are rounded to the nearest integer. The traversable design space described in step 2.2 for: In this context, 0 represents an empty space, and 1 represents an antenna station location.

4. The resolution-oriented 4D millimeter-wave radar antenna array and physical layout co-optimization method according to claim 3, characterized in that, Step 3 specifically includes the following steps: Step 3.1: Generate the virtual antenna array corresponding to the current antenna layout matrix through spatial discretization and convolution mapping strategies; in, For azimuth virtual array, For pitch virtual array, This is a convolution operation; Step 3.2: Calculate the virtual aperture and theoretical resolution based on the virtual antenna array; Step 3.3: Determine whether the theoretical resolution is greater than the actual target resolution. If so, adjust the azimuth and elevation transmit antenna vectors of the current antenna layout matrix, update them to the next antenna layout matrix, and return to step 3.

1. If so, output the antenna layout matrix corresponding to the current virtual antenna array layout design as the candidate layout matrix, and execute step 4.

5. The resolution-oriented 4D millimeter-wave radar antenna array and physical layout co-optimization method according to claim 4, characterized in that, Step 3.2 Virtual aperture and theoretical resolution The specific calculation methods include: in, For azimuth virtual aperture, For pitch towards the virtual aperture; in This is the theoretical azimuth resolution. For theoretical pitch angle resolution, λ is the wavelength.

6. The resolution-oriented 4D millimeter-wave radar antenna array and physical layout co-optimization method according to claim 5, characterized in that, The strong constraint mechanism described in step 4 specifically includes: Perform an overlay operation on the candidate layout matrices; in, The result of the superposition operation. For the candidate layout matrix, This is a no-step region matrix, where 1000 represents the no-step region outside the printed circuit board boundary, 100 represents the no-step region around the chip, and 0 represents the freely deployable region. If the result value If the value is 101 or 1001, it indicates that the antenna overlaps with the boundary of the no-step area. In this case, the azimuth transmit antenna vector and the elevation transmit antenna vector are adjusted, and the process returns to step 3. If the result value If the value is greater than or equal to the threshold, it indicates that the physical spacing between the antennas is violated. In this case, the azimuth transmit antenna vector and the elevation transmit antenna vector are adjusted, and the process returns to step 3. If the result value If the value is not 101 or 1001 and is not greater than or equal to the threshold, then the candidate layout matrix satisfies the strong constraint mechanism condition and a soft constraint mechanism is applied to it.

7. The resolution-oriented 4D millimeter-wave radar antenna array and physical layout co-optimization method according to claim 6, characterized in that, The soft constraint mechanism described in step 4 specifically includes: For all candidate layout matrices that satisfy the strong constraint mechanism, calculate the layout cost function value of each candidate layout matrix, and select the candidate layout matrix with the smallest layout cost function value as the optimal antenna spatial arrangement matrix. The layout cost function The calculation methods include: in, All are weighting coefficients. This is the sum of the standard deviations of the distances between receiving antennas corresponding to the same chip. This is the sum of the standard deviations of the distances between the transmitting antennas corresponding to the same chip. This represents the standard deviation of the distance between the receiving antennas of different chips and the center of the chip. This represents the standard deviation of the distance between the transmitting antennas of different chips and the center of the chip.

8. A computer system comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method of claim 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the steps of the method of claim 7.

10. A computer program product comprising computer instructions, characterized in that: When the computer instructions are executed by the processor, they implement the steps of the method of claim 7.

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