Systems and methods for reducing TDDB of non-selected transistors in reram devices

Abstract

In a conventional programming process of a resistive random access memory (ReRAM) array, many ReRAM cells are subjected to unnecessary stresses. This overstress results in a lower reliability of time dependent dielectric breakdown (TDDB). According to the embodiment, a negative voltage is applied to a bit line (BL) of a programmed cell, and at the same time, a negative voltage is also applied to word lines (WL) of all unprogrammed cells. In this manner, a lower WL voltage and a source line (SL) voltage than existing solutions may be employed. Therefore, the stress borne by the non-selected unit (especially the transistor of the non-selected unit) is reduced, and the TDDB is reduced.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 674441, filed July 23, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to resistive random access memory (ReRAM) cells, and more specifically to reducing the effects of time delay dielectric breakdown in ReRAM cells. Background Technology

[0004] Time-dependent dielectric breakdown (TDDB), sometimes called time-delayed dielectric breakdown, is a problem affecting semiconductor devices that rely on dielectric materials. Complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) can be affected by TDDB because the insulating properties of the gate oxide in CMOS transistors (typically field-effect transistors (FETs) of ICs) gradually deteriorate over time. Gate oxide breakdown due to TDDB can lead to leakage current and affect transistor operation, potentially causing circuit failure. Similarly, TDDB can affect the performance of power electronics and microelectromechanical systems (MEMS) or cause them to fail.

[0005] An example of non-volatile memory (NVM) is resistive random access memory (ReRAM). ReRAM is known for its potential to provide high-density, fast, and energy-efficient data storage. It works by utilizing the resistive switching properties of certain dielectric materials, which are used as its resistive elements. It also includes a transfer transistor to which the resistive elements are connected and controlled to perform various operations. During programming, the transistor and resistive elements of the programmed cell are subjected to dielectric stress due to the applied voltage. It is beneficial to integrate such NVMs into logic designs and manufacturing techniques that utilize transistors not typically designed to withstand continuous stress.

[0006] Those skilled in the art will therefore readily recognize the need to manage TDDB to ensure the durability, performance, and / or data retention of semiconductor devices. Various strategies exist for mitigating TDDB in ReRAM devices, such as optimizing dielectric material properties, voltage pulse shaping, and implementing error-correcting codes (ECC) to mitigate the impact of potential data errors caused by dielectric breakdown. However, this primarily targets cells that are currently being programmed.

[0007] Figure 1A schematic block diagram 100 of a resistive random access memory (ReRAM) device is shown. The device includes an array 110 of ReRAM cells arranged in rows and columns. Under the control of a control logic unit 140, a bit line (BL) and source line (SL) control unit 120 and a word line (WL) control unit 130 provide SET, RESET, and read signal operations for the ReRAM cells.

[0008] Figure 2 For use with standard operating voltage Figure 1 This is a schematic diagram of the ReRAM array 110 in the ReRAM device 100. Each ReRAM cell includes an access transistor 250 and a resistor 240. In this specific case, such as when WL j 230-j applied a 2V voltage while SL i When a voltage of 1.8V is applied to 220-i, ReRAM cell i,j (i.e., the ReRAM cell containing resistor 240-i,j and access transistor 250-i,j) is selected for programming. In this case, access transistors 250-i,1, 250-i,1 up to access transistor 250-n,j in row i will experience leakage current. For access transistor 250-i,j, even in a small array, this leakage current can become quite significant when a large number of access transistors are leaking.

[0009] The higher operating voltage employed (especially when the ReRAM performs a RESET operation) will stress the access transistors 250-1,j, 250-2,j, and up to access transistor 250-i,m in column j. This necessitates the use of larger transistors in the manufacturing process to withstand this stress. Using smaller core transistors would lead to breakdown, thereby reducing device reliability. Although access transistor 250-i,j withstands V ds The voltage stress is within the limit, but in reality, there are many more, such as the m-1 access transistors 250 shown in the diagram, which are subjected to higher stress. For example, access transistors 250-i,1 in SL i =1.8V 220-i and BL i =0V210-i withstands a voltage drop. Therefore, more storage bits will be affected by stress. Using high-voltage withstand transistors means that the area of ​​this cell will be significantly affected by the size of the access transistors (e.g., 250-i,j).

[0010] Therefore, a favorable solution is needed that can alleviate the stress on the unselected access transistor 250 while avoiding the use of a high-voltage transistor as the process core transistor, thereby overcoming the shortcomings of the current implementation. A more advantageous solution is to directly use the process core transistor instead of a specially designed high-voltage withstand transistor. Certain operational defects of the core transistor when operating at high voltage also need to be addressed. This is particularly important because both the selected and unselected access transistors 250 may be subjected to high voltages at different stages of reading and / or writing ReRAM cells. Summary of the Invention

[0011] The following is a summary description of several exemplary embodiments of this disclosure. This summary is intended to provide the reader with a basic understanding of these embodiments and is not intended to fully define the scope of this disclosure. This summary is not an exhaustive overview of all contemplated embodiments, nor does it attempt to identify key elements of all embodiments, nor is it intended to define the scope of any or all aspects. Its sole purpose is to present certain concepts of one or more embodiments in a simplified form as a prelude to a more detailed description thereafter. For ease of description, the term "certain embodiments" may be used in this document to refer to a single embodiment or multiple embodiments of this disclosure.

[0012] Some embodiments disclosed herein include a resistive random access memory (ReRAM) device with improved time-dependent dielectric breakdown (TDDB) characteristics, the device comprising: an array of ReRAM cells arranged in multiple columns and rows, each cell including a resistive element and a select transistor, the resistive element having a first port and a second port, the select transistor having a gate port, a drain port, and a source port, wherein the second port of the resistive element is electrically connected to the drain port of the select transistor; multiple word lines, each word line being assigned to one column of the multiple columns and electrically connected to each gate of the select transistor of each ReRAM cell in the column; and multiple bit lines, each bit line corresponding to one of the multiple rows. The system comprises: a row and electrically connected to the first port of the resistive element of each ReRAM cell in the row; multiple source lines, each source line being assigned to one row of the multiple rows and electrically connected to the source port of each select transistor of each ReRAM cell in the row; a word line control unit (WLCU) electrically connected to each word line of the multiple word lines; a bit line source line control unit (BLSLCU) electrically connected to each bit line of the multiple bit lines and each source line of the multiple source lines; and a control unit electrically connected to the BLSLCU and configured to provide a first negative voltage to the bit lines in the multiple rows when the first ReRAM cell is RESET programmed, wherein the bit lines in the multiple rows include the first ReRAM cell.

[0013] Some embodiments disclosed herein also include a method for RESET programming a ReRAM device with improved TDDB characteristics, the method comprising: selecting one or more rows of the ReRAM array of the ReRAM device via a bit line source line control unit (BLSLCU), and selecting one or more columns of the ReRAM array of the ReRAM device via a word line control unit (WLCU), wherein the intersection of the selected column and the selected row indicates the ReRAM cell to be RESET operated on; and via the WLCU to select a non-selected row... A first voltage is applied to each word line of the selected column; a first positive voltage is applied to each word line of the selected column via the WLCU; a reference voltage is applied to the bit lines of the unselected row via the BLSLCU; a reference voltage is applied to the source lines of the unselected row via the BLSLCU; a second negative voltage is applied to the bit lines of the selected row via the BLSLCU; and a second positive voltage is applied to the source lines of the selected row via the BLSLCU. These voltages are applied such that the selected ReRAM cell performs a RESET operation while avoiding overstressing the select transistors of the unselected ReRAM cells. Attached Figure Description

[0014] The claims at the end of this specification clearly define the subject matter to be protected herein. The above and other objects, features, and advantages of the disclosed embodiments will become apparent upon reading the following detailed description in conjunction with the accompanying drawings.

[0015] Figure 1 This is a schematic block diagram of a resistive random access memory (ReRAM) device.

[0016] Figure 2 For use with standard operating voltage Figure 1 The diagram shows a ReRAM array of the ReRAM device.

[0017] Figure 3 This is a first schematic diagram of a ReRAM array employing a ReRAM device with an operating voltage according to an embodiment.

[0018] Figure 4 This is a second schematic diagram of a portion of a ReRAM array in a ReRAM device employing the operating voltage principle according to an embodiment.

[0019] Figure 5 This is a third schematic diagram of a portion of a ReRAM array in a ReRAM device employing the operating voltage principle according to an embodiment.

[0020] Figure 6 This is a graph illustrating the time-dependent dielectric breakdown (TDDB) gain according to one embodiment.

[0021] Figure 7 A flowchart illustrating RESET programming of a ReRAM array according to one embodiment.

[0022] Figure 8 A flowchart describing RESET programming of a ReRAM array according to another embodiment. Detailed Implementation

[0023] It should be noted that the embodiments disclosed herein are merely examples of the many advantages of this innovative teaching. Generally, the descriptions in this specification do not necessarily limit the scope of the claims. Furthermore, some descriptions may apply to certain features of the invention but not others. Unless otherwise stated, singular elements may contain plural forms, and vice versa; this principle has universal application. In the accompanying drawings, the same numbers in multiple views refer to the same parts.

[0024] In the conventional programming process of resistive random access memory (ReRAM) arrays, many ReRAM cells (hereinafter simply referred to as cells) are subjected to unnecessary stress. This overstress leads to low reliability due to time-dependent dielectric breakdown (TDDB). According to one embodiment, a negative voltage is applied to the bit line (BL) of the programmed cell, and simultaneously a negative voltage is applied to the word line (WL) of all unprogrammed cells. In this way, lower WL voltages and source line (SL) voltages can be used than in conventional methods. Therefore, the stress on unselected cells (especially the transistors of unselected cells) is reduced, thereby reducing TDDB.

[0025] Figure 3 To use the operating voltage described in the embodiment Figure 1 This is an exemplary first schematic diagram of the first ReRAM array 300 in the shown ReRAM device. From a schematic perspective, this ReRAM device is similar to... Figure 1 Similar to the example shown, but the voltage applied during the RESET operation is different, specifically as follows: Figure 3 As shown. In this example, a RESET operation is performed on ReRAM cells i,j. Except for WL j 230-j is outside 1.5V, WL1 230-1 to WL m Both 230-m values ​​are at 0V. (And...) Figure 2 Compared to the supplied voltage, this voltage is reduced by 0.5V. Except for BL i In addition to 210-i, BL1 210-1 to BL n Both 210-n are subjected to 0V voltage; while BL i 210-i then applies a voltage lower than 0V, that is, a voltage lower than the voltage supplied to BL in the known embodiments. i The 210-i has a lower voltage. In one embodiment, BL iThe 210-i is subjected to a voltage of -250mV (-0.25V). Except for SL i In addition to 220-i, SL1 220-1 to SL n 0V is applied to both 220-n; while SL i 220-i applies a voltage lower than 1.8V, which is lower than the voltage supplied to SL in known embodiments. i The 220-i has a lower voltage. In one embodiment, SL i The 220-i is subjected to a voltage of 1.5V.

[0026] According to the embodiments, for every 1mV decrease in the BL voltage (below 0V), the WL voltage can decrease by approximately 1mV accordingly. For example, if the BL voltage is -200mV, the WL voltage can decrease by 200mV, or in one embodiment by 195mV to 205mV; if the BL voltage is -250mV, the WL voltage can decrease by 250mV, or in one embodiment by 240mV to 260mV.

[0027] As can be seen from the voltage scheme, the voltage applied to the access transistors 250-i,j according to this embodiment is basically the same as that in the existing implementation, the only difference being BL. i Operating at a negative voltage. The main difference lies in the voltage stress experienced by the unselected access transistors 250 (e.g., transistors 250-1,j to 250-nj), except for the access transistors 250-i,j to be performed on the RESET operation. Although the voltage stress experienced by these unselected access transistors 250 in the RESET column is lower, the access transistors 250 in the RESET row (i.e., access transistors 250-i,1 to 250-i,m, excluding the access transistor 250-i,j performing the RESET operation) still maintain low leakage current characteristics. Therefore, those skilled in the art will understand that, to implement the technical solutions described herein, at least the BL / SL controller 120 must be adapted to provide a negative voltage when performing the RESET operation of resistor 240. According to one embodiment, the leakage current of all unselected but active corresponding BL 210 and SL 220 access transistors 250 in the bit lines should not exceed a predetermined percentage of the current of the selected access transistor. For example (but not limitingly), the leakage current of all unselected but active access transistors 250, including BL 210 and SL 220, should not exceed one percent (1%) of the current of the selected access transistor.

[0028] Figure 4This is an exemplary second schematic diagram of a portion of a ReRAM array 400 in a ReRAM device employing an operating voltage principle according to an embodiment. The ReRAM array is arranged in a matrix of '1' rows and 'J' columns of ReRAM cells, where '1' and 'J' are integers greater than '1'. The programmed cells include resistive elements 440. m,n and select transistor 450 m,n The unit. The values ​​of 'm' and 'n' are within the range of 'I' and 'J', that is, 'm' must not be less than 2 or greater than 'I', and 'n' must not be less than 2 or greater than 'J'. In this example, for ease of explanation, WL m-1 The 430-m-1 receives voltages below 0V, i.e., receives negative voltages (typically relative to ground or another common reference potential), while WL m+1 430-m+1 receives 0V voltage. The non-programmed resistor element in line n-1 (i.e., resistor element 440) m-1,n-1 440 m,n-1 and 440 m+1,n-1 Connect BL which is at 0V n-1 410-n-1 and SL at 0V n-1 420-n-1. The resistor element in the nth row (i.e., resistor element 440). m-1,n 440 m,n and 440 m+1,n ) Connect BL to a voltage below 0V (i.e., negative voltage) n-1 410-n-1, and SL connected at a positive voltage below 1.8V. n-1 420-n-1. To program this resistor element, WL m 430-m receives less than 2V but not lower than SL n The positive voltage that exists on 420-n.

[0029] After applying the voltage scheme described above (it should be noted that this scheme is for illustrative purposes only), as those skilled in the art will understand, transistor 450 m-1,n-1 450 m,n-1 and 450 m+1,n-1 No current leakage was observed. Furthermore, transistor 450... m-1,n There is also no current leakage, a point that is also understood by those skilled in the art. However, this example is intended to illustrate that transistor 450 m+1,n Current leakage does exist. Therefore, according to one embodiment, providing a negative bias to the word line of the unselected cell can suppress leakage current in such unselected cells. Therefore, compared to the proposed WL... m+1 The 0V bias applied at 430-m+1 affects WL m-1Applying a negative bias to 430-m-1 is more advantageous. Therefore, according to one embodiment, applying a negative bit-line voltage during RESET operation allows the same RESET voltage to be achieved on the programmed ReRAM cell with a lower word-line voltage. This embodiment also requires reducing the SL 420 voltage of the programmed cell to maintain the same V on the selected transistor. DS .

[0030] Figure 5 This is an exemplary third schematic diagram of a portion of a ReRAM array 500 in a ReRAM device employing the operating voltage principle. The diagram illustrates a programmable resistor element 540. m,n The specific programming voltage provides the benefits of the disclosed embodiments for the ReRAM device. The voltages applied to the unselected cells are: WL m-1 =-0.25V 530-m-1、WL m+1 =-0.25V530-m+1,BL n-1 =0V 510-n-1, and SL n-1 =0V 520-n-1.

[0031] like Figure 4 For transistor 450 m-1,n-1 450 m,n-1 and 450 m+1,n-1 As mentioned above, all transistors 550 on the unselected row n-1 m-1,n-1 550 m,n-1 and 550 m+1,n-1 There is no leakage current. Therefore, BL n-1 510-n-1 and SL n-1 520-n-1 are all biased at 0V. As word lines for the unselected cells in columns m-1 and m+1, WL m-1 530-m-1 and WL m+1 All 530-m+1 are biased at -0.25V. This is for the 540 resistor element. m,n Execute the RESET operation, BL n The 510-n is biased at -0.25V, SL n The 520-n is biased at 1.55V. The gate voltage of the transistor in the unselected cell receives -0.25V from the unselected word line to suppress bit line leakage current in the unselected cell. Therefore, as Figure 4 and Figure 5 As shown, the implementation of applying a negative voltage to the bit line of the selected cell can be carried out without degrading the leakage current performance of the ReRAM array.

[0032] In summary, according to these embodiments, the bit line voltage applied during RESET is negative, which allows the same RESET voltage to be achieved on ReRAM with a lower word line voltage. Therefore, the SL voltage also needs to be reduced to maintain the same VL on the selected transistor of the selected cell. DS Except for the word line containing the selected cell, the word line voltage of the unselected cell is biased negative to suppress leakage current of the unselected cell. The word line voltage of the column containing the programmed cell is reduced from the normal 2V to 1.8V, so that the selected cell reaches the same voltage as the bit line voltage of -250mV during the RESET operation.

[0033] Figure 6 As an example graph 600, it illustrates the growth of time-dependent dielectric breakdown (TDDB) according to one embodiment. The horizontal axis 610 of the graph represents the parts per million (ppm) value, where a lower ppm value should be understood as better. This ppm value measures the component failure caused by TDDB. The vertical axis 620 of the graph represents the maximum word line voltage used for RESET programming. Four curves 630-1, 630-2, 630-3, and 630-4 are shown in the graph. In this case, curves 630-1 to 630-4 are generated for a 1Mb array at 85°C. Curve 630-1 corresponds to 10,000 cycles at 100 ns. Curve 630-2 corresponds to 10,000 cycles at 1 μs. Curve 630-1 corresponds to 10,000 cycles at 100 ns × 1024 / 22. Curve 630-4 corresponds to 100,000 cycles at 1 μs. All curves clearly demonstrate that reducing the word line voltage is beneficial. Observe the ppm effect shown in curve 630-1. Using a 1.8V word line voltage compared to a 2V word line voltage achieves a three-order-of-magnitude improvement. By utilizing TDDB reduction, the number of overstressed cells is significantly reduced, resulting in a substantial improvement in module reliability. For example, in the programmed word line WL... m In 530-m, although all transistors in column m are subjected to a voltage of 1.8V, the stress they experience is lower than the stress when 2V is applied. Figure 600 shows a comparison of the effects under different conditions.

[0034] To implement the teachings herein, the BL / SL controller 120 and WL controller 130 are modified to allow the application of the voltage scheme described herein. Specifically, the modified BL / SL controller 120 can provide a negative BL voltage and a 0V voltage. The BL / SL controller 120 is further modified to provide a reduced SL voltage during programming, for example, using 1.55V instead of the 1.8V of the current embodiment. The WL controller 130 is modified to provide a reduced word line voltage during programming (e.g., reducing the typical value of 2V in the current embodiment to 1.8V), and further modified to provide a negative voltage (e.g., -0.25V instead of 0V). It should be understood that these specific voltage values ​​are given by way of example only and should not limit the scope of the disclosed embodiments. The negative voltage supply scheme shown herein reduces the word line voltage during programming, thereby subjecting unprogrammed transistors to less stress and thus improving TDDB characteristics.

[0035] Figure 7 Example flowchart 700 describes RESET programming of a ReRAM array according to one embodiment. In S710, one or more column cells and one or more row cells to be selected for the RESET operation. Such selection can be, for example, by Figure 1 The control logic 140 shown is executed in conjunction with the modified BL / SL controller 120 and the modified WL controller 130 described herein. Selected rows or columns contain at least one ReRAM cell for which a RESET operation is to be performed. Unselected rows or columns do not contain any ReRAM cells for which a RESET operation is to be performed.

[0036] In S720, a predetermined voltage (e.g., 0V) is applied to all WLs of the unselected column (i.e., the column not selected in S710).

[0037] In S730, a predetermined positive voltage (e.g., 1.8V) is applied to all WLs of the selected column (i.e., the column selected in S710).

[0038] In S740, a 0V reference voltage or ground potential is applied to the bit line of the unselected row.

[0039] In the S750, a 0V reference voltage or ground potential is applied to each SL of the unselected row.

[0040] In S760, a predetermined negative voltage (e.g., -0.25V) is applied to the bit lines of one or more selected rows.

[0041] In S770, a predetermined positive voltage (e.g., 1.55V) is applied to the SL of one or more selected rows.

[0042] Although S720 through S770 are described in sequence, this sequence should not be construed as restrictive, and any other execution order is permissible. This also includes applications in which various voltages are applied simultaneously to all or some of S720 through S770.

[0043] Figure 8 This is an example flowchart 800 describing RESET programming of a ReRAM array according to another embodiment. Specifically, in this embodiment, a negative voltage is also applied to each unselected WL. This method is used when the bias reaches a level where leakage current becomes a problem, thus requiring additional compensation to limit such leakage current to the desired range.

[0044] In S810, one or more column cells and one or more row cells to be selected for the RESET operation. Such selection can be achieved by, for example... Figure 1 The control logic 140 shown is executed in conjunction with the modified BL / SL controller 120 and the modified WL controller 130 described herein. Selected rows or columns contain at least one ReRAM cell for which a RESET operation is to be performed. Unselected rows or columns do not contain any ReRAM cell for which a RESET operation is to be performed.

[0045] In S820, a predetermined voltage (e.g., 0V) is applied to all WLs of the unselected column (i.e., the column not selected in S710).

[0046] In S830, a predetermined positive voltage (e.g., 1.8V) is applied to all WLs of the selected column (i.e., the column selected in S710).

[0047] In S840, a 0V reference voltage or ground potential is applied to the bit line of the unselected row.

[0048] In the S850, a 0V reference voltage or ground potential is applied to each SL of the unselected row.

[0049] In S860, a predetermined negative voltage (e.g., -0.25V) is applied to the bit lines of one or more selected rows.

[0050] In S870, a predetermined positive voltage (e.g., 1.55V) is applied to the SL of one or more selected rows.

[0051] Although S820 through S870 are described sequentially, this order should not be construed as restrictive, and any other execution order is permissible. This also includes applications in which various voltages are applied simultaneously to all or some of S820 through S870.

[0052] While specific example voltages are provided, it should be understood that appropriately adjusted voltage ranges can also be used as long as negative voltages are used for both the WL and BL voltages according to the embodiments described herein. Thus, in one embodiment, the range of the first predetermined positive voltage may be 1.5V to 1.8V. In one embodiment, the range of the second predetermined positive voltage may be 0.85V to 0.95V. The range of the first predetermined negative voltage may be -400mV to -100mV. The range of the second predetermined negative voltage may also be -400mV to -100mV.

[0053] All examples and conditional language listed herein are for illustrative purposes and are intended to help readers understand the principles of the embodiments of this disclosure and the concepts contributed by the inventors to advance the art. They should not be construed as limiting the specific examples and conditions described. Furthermore, all statements in this document that set forth the principles, aspects, and implementation methods of the embodiments of this disclosure, as well as specific examples thereof, are intended to cover their structural and functional equivalents. Such equivalents include both currently implemented equivalents and future-developed equivalents, i.e., any development elements that perform the same function regardless of structural differences.

[0054] It should be understood that the use of terms such as "first," "second," etc., to refer to elements in this document generally does not impose any limitation on the number or order of those elements. Rather, these terms are generally used as a convenient way to distinguish between two or more elements or instances of elements. Therefore, referencing the first and second elements does not imply that only two elements can be used, nor does it imply that the first element must precede the second element in some way. Furthermore, unless otherwise stated, a group of elements contains one or more elements.

[0055] As used herein, the phrase “at least one” followed by a listed item means that any of the listed items may be used alone, or any combination of two or more of the listed items may be used. For example, if a system is described as including “at least one A, B, and C”, then the system may include A alone; include B alone; include C alone; 2 A's; 2 B's; 2 C's; 3 A's; a combination of A and B; a combination of B and C; a combination of A and C; a combination of A, B, and C; a combination of 2 A's and C; a combination of A, 3 B's, and 2 C's; and so on.

Claims

1. A resistive random access memory (ReRAM) device having improved time dependent dielectric breakdown (TDDB) characteristics, the ReRAM device comprising: an array of ReRAM cells arranged in a plurality of columns and a plurality of rows, each cell including a resistive element having a first port and a second port, and a select transistor having a gate port, a drain port, and a source port, wherein the second port of the resistive element is electrically connected to the drain port of the select transistor; a plurality of word lines, each word line assigned to one of the plurality of columns and electrically connected to each gate of the select transistor of each ReRAM cell of the column; a plurality of bit lines, each bit line assigned to one of the plurality of rows and electrically connected to the first port of the resistive element of each ReRAM cell of the row; a plurality of source lines, each source line assigned to one of the plurality of rows and electrically connected to the source port of the select transistor of each ReRAM cell of the row; a word line control unit (WLCU) electrically connected to each of the plurality of word lines; a bit line source line control unit (BLSLCU) electrically connected to each of the plurality of bit lines and each of the plurality of source lines; and a control unit electrically connected to the BLSLCU, the control unit configured to provide a first negative voltage to a bit line of the plurality of rows when programming a first ReRAM cell in RESET, wherein the bit line of the plurality of rows includes the first ReRAM cell.

2. The ReRAM device of claim 1, wherein a word line voltage when the programming in RESET is in a range of 1.5 V to 1.8 V.

3. The ReRAM device of claim 1, wherein the first negative voltage applied by the WLCU is between -400 mV and -100 mV.

4. The ReRAM device of claim 3, wherein the first negative voltage is -250 mV.

5. The ReRAM device of claim 1, wherein the control unit is further electrically connected to the WLCU, and the control unit is configured to provide a second negative voltage to a word line of the plurality of columns when programming a first ReRAM cell in RESET, wherein the word line of the plurality of columns does not include the first ReRAM cell.

6. The ReRAM device of claim 5, wherein the second negative voltage applied by the BLSLCU is between -400 mV and -100 mV.

7. The ReRAM device of claim 6, wherein the second negative voltage is -250 mV.

8. The ReRAM device of claim 1, wherein a select voltage applied by the BLSLCU to each source line of a non-selected row is 0 V.

9. The ReRAM device of claim 1, wherein a select voltage applied by the BLSLCU to each source line of a selected row is between 1.55 V and 1.8 V. ​ 10. The ReRAM device of claim 9, wherein the BLSLCU applies a select voltage to each source line of a selected row of 1.55 V.

11. The ReRAM device of claim 1, wherein a total leakage current of all unselected access transistors on a bit line of the plurality of bit lines is lower than a predetermined proportion of a current of the selected transistor on the bit line.

12. The ReRAM device of claim 11, wherein the predetermined proportion is equal to or lower than 1%.

13. A programming method for performing a RESET programming on a resistive random access memory (ReRAM) device having improved time-dependent dielectric breakdown (TDDB) characteristics, the method comprising: selecting one or more rows by a bit line source line control unit (BLSLCU) of the ReRAM device and selecting one or more columns of a ReRAM array of the ReRAM device by a word line control unit (WLCU) of the ReRAM device, wherein an intersection of a selected column and a selected row indicates a ReRAM cell to perform a RESET operation, and wherein the indicated ReRAM cell is a selected ReRAM cell; applying, by the WLCU, a first voltage to each word line of the ReRAM array of the non-selected columns; applying, by the WLCU, a first positive voltage to each word line of the ReRAM array of the selected columns; applying, by the BLSLCU, a reference voltage to bit lines of non-selected rows; applying, by the BLSLCU, a reference voltage to source lines of non-selected rows; applying, by the BLSLCU, a second negative voltage to bit lines of the selected rows; and applying, by the BLSLCU, a second positive voltage to source lines of the selected rows; wherein the applying of the voltages causes each of the selected ReRAM cells to perform a RESET operation while avoiding overstressing selected transistors of non-selected ReRAM cells.

14. The method of claim 13, wherein a word line voltage is in a range of 1.5 V to 1.8 V when the RESET programming.

15. The method of claim 13, wherein the first voltage applied by the WLCU is a negative voltage.

16. The method of claim 15, wherein the first voltage is between -400 mV and -100 mV. the second negative voltage applied by the BLSLCU is between -400 mV and -100 mV.

17. The method of claim 13, wherein, the reference voltage applied by the BLSLCU to the bit lines and the reference voltage applied by the BLSLCU to the source lines are both 0 V.

18. The method of claim 13, wherein, the second positive voltage applied by the BLSLCU to each source line of a selected row is between 1.55 V and 1.8 V.

19. The method of claim 13, wherein, the voltages applied by the WLCU are applied in parallel, wherein the voltages applied by the WLCU are either: applying the first voltage to each word line of the ReRAM array of the non-selected columns, and applying the first positive voltage to each word line of the ReRAM array of the selected columns.

20. The method of claim 13, wherein, ​ 21. The method of claim 13, wherein, The voltage applied by the BLSLCU is applied in parallel, wherein the voltage applied by the BLSLCU is any one of: applying a reference voltage to bit lines of non-selected rows, applying a reference voltage to source lines of non-selected rows, applying a second negative voltage to bit lines of selected rows, and applying a second positive voltage to source lines of selected rows.

22. The method of claim 13, wherein, A total leakage current of all unselected transistors on a bit line of the ReRAM device is lower than a predetermined proportion of a current of the selected transistor in the bit line.

23. The method of claim 22, wherein, The predetermined proportion is equal to or lower than 1%.

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