Capacitor mismatch calibration method and system with foreground and background calibration fused

Abstract

The invention discloses a foreground and background calibration fused capacitor mismatch calibration method and system, and the method comprises the steps: carrying out foreground digital calibration after a chip is powered on, and comprises the steps: obtaining an error voltage; quantizing the obtained error voltage to generate a corresponding error code word; the weight of foreground calibration is obtained; the method comprises the following steps of: generating a pseudorandom sequence and injecting the pseudorandom sequence into an input signal of an ADC (Analog to Digital Converter) when an ADC (Analog to Digital Converter) enters normal work; carrying out weighted summation on the digital code word quantized and output by the ADC and eliminating the interference of the pseudo-random sequence from the digital code word; and carrying out correlation calculation on the weighted summation result after the interference of the pseudo-random sequence is eliminated and the pseudo-random sequence to obtain a calibration coefficient, and carrying out iterative calculation on the capacitance weight according to the calibration coefficient. The advantages of foreground calibration and background calibration are fully combined, so that a better calibration effect is achieved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuits, and particularly relates to a capacitor mismatch calibration method and system with front and back calibration fusion. BACKGROUND

[0002] In modern high-performance analog-to-digital converter (ADC) design, a capacitor array is widely used in key circuits such as digital-to-analog conversion, sample and hold, and charge redistribution, especially in successive-approximation-register (SAR) analog-to-digital converters, where a unit capacitor array is the core component for building the precision of a digital-to-analog converter (DAC). Ideally, the capacitor array should have strict consistency and matching to ensure that each digital code corresponds to an accurate analog voltage. However, in the actual manufacturing process, due to factors such as process deviation, uneven doping, photolithography error, and temperature gradient, the unit capacitors on the chip will have non-negligible deviations in physical size, dielectric thickness, etc., which is known as capacitor mismatch. Capacitor mismatch is one of the important non-ideal factors affecting ADC precision, especially in high-resolution (10 bits or more) and low-power design. Capacitor mismatch will directly lead to output error of the capacitor array, and further cause deterioration of quantization nonlinearity, including differential nonlinearity (DNL) and integral nonlinearity (INL). Without calibration, capacitor mismatch can cause the effective number of bits (ENOB) of the SAR ADC to decrease by 1-2 bits, or even more.

[0003] To offset the effects of capacitor mismatch, researchers have proposed various calibration methods, which can be mainly divided into two categories: front-end circuit design optimization and back-end digital calibration technology. The former, such as using large-area unit capacitors to reduce relative mismatch error, common-centroid design, guard ring, etc., although helps to reduce mismatch, often increases chip area and power consumption, and is not suitable for miniaturization and high-density integration design requirements. Therefore, in recent years, more attention has been focused on back-end digital calibration algorithms, which can still adjust errors after the chip is completed and has advantages such as reconfigurability and low overhead.

[0004] The commonly used digital calibration methods include background calibration algorithm based on measurement-fitting, mismatch estimation method based on pseudo-random injection, error lookup table calibration based on DNL / INL test, and neural network compensation method combined with artificial intelligence, etc. Different methods have their own advantages and disadvantages, for example, the estimation method is suitable for online real-time estimation, but may interfere with normal work, the lookup table method has high precision but requires additional storage resources. In recent years, there are also studies that combine multiple algorithms to improve the overall calibration accuracy through data fusion, signal reconstruction or error weighting. SUMMARY

[0005] In order to overcome the limitations of the existing capacitor mismatch calibration methods, the present application proposes a front and background calibration fusion capacitor mismatch calibration method and system, which fully combines the advantages of front and background calibration to achieve better calibration results.

[0006] In one aspect, the present application is implemented by the following technical solutions:

[0007] A front and background calibration fusion capacitor mismatch calibration method, comprising:

[0008] After the chip is powered on, the foreground digital calibration is performed, including: obtaining an error voltage; generating a corresponding error code word by quantizing the obtained error voltage; obtaining a real weight as the weight of the foreground calibration according to the error code word and an ideal weight;

[0009] The ADC enters normal work, and the background digital calibration is performed, including: generating a pseudo-random sequence and injecting it into the input signal of the ADC; performing weighted summation on the digital code word quantized and output by the ADC and eliminating the interference of the pseudo-random sequence therefrom; performing correlation calculation on the weighted summation result after eliminating the interference of the pseudo-random sequence and the pseudo-random sequence to obtain a calibration coefficient, and performing iterative calculation on the capacitor weight according to the calibration coefficient.

[0010] In some embodiments, the error voltage is obtained by:

[0011] The number of bits of the capacitor array to be calibrated is determined, the capacitors higher than the number of bits are the capacitors to be calibrated, and the capacitors lower than the number of bits constitute the calibration capacitor array and ignore the influence of the capacitor mismatch, and the capacitor weight of the calibration capacitor array is considered as an ideal weight; the determination of the number of bits needs to ensure that the calibration capacitor array composed of the selected low-bit capacitors maintains linearity at the selected capacitor bit number accuracy;

[0012] By pre-charging the capacitor array, since there is no path for charge leakage, the charge is conserved. The lower plate of the capacitor to be calibrated is first switched to ground, and then switched to the reference voltage. The error voltage can be extracted and stored at the output of the capacitor array to await the next step of quantization. The capacitor array is switched according to this process to obtain the error voltage of each capacitor to be calibrated.

[0013] In some embodiments, quantizing the acquired error voltage to generate corresponding error codewords includes:

[0014] The error voltage of each capacitor to be calibrated is quantized using the calibration capacitor array through a successive approximation method to obtain the corresponding error codeword.

[0015] In some implementations, obtaining the true weights based on the error codewords and the ideal weights as the weights for front-end calibration includes:

[0016] The ideal weight of each capacitor to be calibrated is added to its corresponding error codeword to obtain the true weight of the capacitor to be calibrated; the capacitor weights of the calibration capacitor array are the ideal weights.

[0017] In some implementations, the weighted summation of the digital codewords output by the ADC quantization and the elimination of interference from the pseudo-random sequence includes:

[0018] The input signal injected into the pseudo-random sequence is quantized by an ADC to obtain the corresponding digital codeword;

[0019] The corresponding decimal analog value is obtained by weighted summation of the digital codewords; the capacitor weights used in the weighted summation process are the weights calibrated at the front end.

[0020] The interference of the pseudo-random sequence is eliminated from the decimal analog value.

[0021] In some embodiments, the step of performing correlation calculations between the weighted summation result after eliminating interference from the pseudo-random sequence and the pseudo-random sequence to obtain calibration coefficients, and then iteratively calculating the capacitance weights based on the calibration coefficients, includes:

[0022] The calibration coefficient is obtained by multiplying the interference-free decimal analog value with each pseudo-random code in the pseudo-random sequence and summing the results.

[0023] The capacitor weight is iteratively calculated using a weight iteration calculation formula, which is: the capacitor weight calculated in the current iteration is equal to the capacitor weight calculated in the previous iteration minus the product of the calibration coefficient and the step size, where the initial weight is the weight of the front-end calibration.

[0024] In some embodiments, the background digital calibration further comprises:

[0025] The capacitor weight calculated in each iteration is fused with the foreground calibration weight by Kalman filtering to obtain an optimal capacitor weight.

[0026] In another aspect, the application further provides a capacitor mismatch calibration system with foreground and background calibration fusion, comprising:

[0027] The foreground digital calibration module is configured to perform foreground digital calibration after the chip is powered on, including: obtaining an error voltage; quantizing the obtained error voltage to generate a corresponding error code word; and obtaining a real weight from the error code word and an ideal weight as a foreground calibration weight;

[0028] The background digital calibration module is configured to perform background digital calibration when the ADC is in normal operation, including: generating a pseudo-random sequence and injecting it into the input signal of the ADC; performing weighted summation on the digital code word quantized and output by the ADC and eliminating the interference of the pseudo-random sequence therefrom; performing correlation calculation on the weighted summation result after eliminating the interference of the pseudo-random sequence and the pseudo-random sequence to obtain a calibration coefficient, and performing iterative calculation on the capacitor weight according to the calibration coefficient.

[0029] In some embodiments, the foreground digital calibration module comprises:

[0030] The error voltage obtaining unit is configured to obtain the error voltage by switching the capacitor lower plate switch;

[0031] The quantization unit is configured to quantize the error voltage using the successive approximation method with a determined calibration capacitor array to generate a corresponding error code word;

[0032] The compensation unit is configured to add the corresponding error code word to the ideal weight of the capacitor to obtain a real weight as a foreground calibration weight.

[0033] In some embodiments, the background digital calibration module comprises:

[0034] The pseudo-random sequence generating unit is configured to generate a pseudo-random sequence and inject it into the input signal of the ADC;

[0035] The interference eliminating unit is configured to perform weighted summation on the digital code word quantized and output by the ADC and eliminate the interference of the pseudo-random sequence therefrom;

[0036] The correlation calculation unit is configured to perform correlation calculation on the weighted summation result after eliminating the interference of the pseudo-random sequence and the pseudo-random sequence to obtain a calibration coefficient.

[0037] and an iterative calculation unit configured to iteratively calculate the capacitance weight according to the calibration coefficient;

[0038] Optionally, the background digital calibration module further comprises:

[0039] a fusion unit configured to fuse the capacitance weight obtained by each iteration of the iterative calculation unit and the weight obtained by the foreground digital calibration module by Kalman filtering to obtain an optimal capacitance weight.

[0040] The application provides a capacitive mismatch calibration method based on foreground and background calibration fusion. By combining the advantages of foreground calibration and background calibration, the calibration accuracy, speed and system stability can be effectively improved. The foreground calibration provides initial accurate parameter estimation, and the background calibration adjusts and tracks changes in real time. The two complement each other, improving the overall accuracy and stability. The capacitive mismatch calibration method also provides an initial value through foreground calibration to accelerate the convergence speed of background calibration. Since the initial estimation accuracy is high, the background calibration algorithm can quickly enter a stable working state, thereby greatly shortening the convergence time of the background calibration algorithm and reducing the error in the initial calibration. In addition, the capacitive mismatch calibration method can also improve fault tolerance and reduce system risk. If the background calibration algorithm is estimated to be wrong due to noise, data loss or abnormal operation, the system can still adaptively adjust the fusion strategy according to the confidence of the foreground and background observations, and return to the foreground calibration value as the real weight to ensure the correctness of the basic function.

[0041] Correspondingly, the capacitive mismatch calibration system based on foreground and background calibration fusion provided by the application also has the same technical effects as described above. BRIEF DESCRIPTION OF DRAWINGS

[0042] The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and constitute a part of the application, illustrate embodiments of the application and are used to explain the principle of the application. In the drawings:

[0043] Figure 1 A flowchart of the capacitive mismatch calibration method provided by the embodiments of the application;

[0044] Figure 2 An ADC circuit structure diagram of the embodiments of the application;

[0045] Figure 3 An error convergence curve in the embodiments of the application;

[0046] Figure 4 A principle block diagram of the capacitive mismatch calibration system provided by the embodiments of the application. DETAILED DESCRIPTION

[0047] Hereinafter, the term "include" or "may include" used in various embodiments of the present application indicates existence of the inventive function, operation, or element, and does not limit one or more additional functions, operations, or elements. Also, the terms "include", "have", and their conjugates as used in various embodiments of the present application, are merely intended to denote specific features, numbers, steps, operations, elements, components, or combinations thereof, and are not intended to, in and of themselves, exclude the existence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, unless clearly so defined in the various embodiments of the present application.

[0048] In various embodiments of the present application, the expression "or" or "at least one of A or / and B" includes any combination of the listed terms or all the terms. For example, the expression "A or B" or "at least one of A or / and B" can include A, can include B, or can include both A and B.

[0049] The expressions, such as "first", "second", and the like, used in various embodiments of the present application can modify various components in various embodiments, but can not limit the corresponding components. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are used merely for the purpose of distinguishing a component from other components. For example, a first user device and a second user device indicate different user devices, although both are user devices. For example, a first element can be termed a second element, and likewise, a second element can be termed a first element without departing from the scope of various embodiments of the present application.

[0050] It should be noted that if a description describes one component "connected to" another component, a first component can be directly connected to a second component, and "connected" to the second component via a third component. Conversely, if a description describes one component "directly connected to" another component, it should be understood that there are no third components between the first component and the second component.

[0051] The terms used in various embodiments of the present application are merely used to describe specific embodiments and are not intended to limit various embodiments of the present application. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present application belong. Such terms, as defined in commonly used dictionaries, are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless clearly defined otherwise in various embodiments of the present application.

[0052] In order to make the purpose, technical solutions and advantages of the present application clearer, further detailed description of the present application is made below in combination with embodiments and drawings, the illustrative embodiments of the present application and the description thereof are only used to explain the present application, and do not limit the present application.

[0053] The existing capacitor mismatch calibration technology mainly includes foreground calibration and background calibration. The foreground calibration means that the SAR ADC cannot perform normal quantization when the system is corrected, and generally a known input quantity is needed to excite the system. The background calibration can be calibrated at the same time when the ADC is working, and most of the time, as long as the input signal meets certain conditions, the calibration can be performed without affecting the normal work of the ADC. The advantage of foreground calibration is simple structure and fast convergence, but it cannot track the changes of PVT (Process, Voltage, Temperature) in real time. The advantage of background calibration is that it can track the changes of PVT, but the amount of information required is usually larger, accompanied by complex circuit structure or algorithm, or slower convergence speed. In view of the limitations of the existing capacitor mismatch calibration technology, the embodiment of the present application proposes a capacitor mismatch calibration method combining foreground and background calibration.

[0054] As shown in Figure 1 The capacitor mismatch calibration method proposed by the embodiment of the present application includes the following steps:

[0055] Step 110, after the chip is powered on, foreground digital calibration is performed, including: obtaining an error voltage; quantizing the obtained error voltage to generate a corresponding error code word, and obtaining a weight of foreground calibration;

[0056] Step 120, the ADC enters normal work, and background digital calibration is performed, including: generating a pseudo-random sequence and injecting it into the input signal of the ADC; performing weighted summation on the digital code word output by the ADC quantization and eliminating the interference of the pseudo-random sequence therefrom; performing correlation calculation on the weighted summation result after eliminating the interference of the pseudo-random sequence and the pseudo-random sequence to obtain a calibration coefficient, and iteratively calculating the capacitor weight according to the calibration coefficient.

[0057] Further, in step 110 of the embodiment of the present application, after the chip is powered on, the error voltage is obtained by switching the switch of the lower plate of the capacitor, and the specific process is as follows:

[0058] First, the number of bits P of the calibration capacitor array is determined, the capacitors higher than P bits are the capacitors to be calibrated, the capacitors lower than P bits constitute the calibration capacitor array, and the influence of the capacitor mismatch is ignored, and it is considered that the capacitor weight of the calibration capacitor array is ideal binary (i.e. ideal weight). The principle is that the resolution of the SAR ADC is 14 bits, and the circuit structure is as Figure 2The ideal quantization process is shown in the figure. In the ideal quantization process, each conversion step is of the same size, while the presence of capacitor mismatch causes the actual conversion step to deviate from the ideal value, which causes the generation of DNL. The capacitor matching value obeys a normal distribution with a mean of zero, and for an N-bit unsegmented capacitor array, the total capacitor mean is wherein, is the unit capacitance, and the standard deviation is wherein is the standard deviation of the capacitor mismatch, and the maximum standard deviation of DNL can be calculated as Therefore, as long as the selected low-bit capacitors of the capacitor array remain linear at the selected capacitor bit precision (i.e., the maximum standard deviation of DNL is within ±0.5 LSB), the capacitor mismatch error caused by the capacitors can be ignored for the entire ADC, and thus the capacitors are regarded as ideal standard binary capacitors, i.e., a calibration capacitor array. In the embodiments of the present application, the number of bits P of the calibration capacitor array is preferably 6, i.e., capacitors with more than 6 bits are to be calibrated, and capacitors with less than 6 bits constitute the calibration capacitor array.

[0059] By pre-charging the capacitor array, since there is no path for charge leakage at this time, the charge is conserved, the lower plate of the to-be-calibrated capacitor is first switched to ground, and then switched to the reference voltage, and the error voltage can be extracted and stored at the output end of the capacitor array, waiting for the next step of conversion. Subsequently, the capacitor array switch is controlled to switch, and the error voltage of each to-be-calibrated capacitor can be extracted in the same way. Specifically, the upper plate of the capacitor array is connected to the common-mode voltage, the lower plate of the to-be-calibrated capacitor is connected to ground, the lower plates of the low-bit capacitors below the to-be-calibrated capacitor are all connected to the reference voltage, and the upper plates of the high-bit capacitors above the to-be-calibrated capacitor are all connected to ground. At this time, the amount of charge stored in the entire capacitor array can be calculated as wherein is the to-be-calibrated capacitor, is the low-bit capacitor below the to-be-calibrated capacitor, and subsequently, the capacitor array switch is controlled to switch, and first, the switch connected to the common-mode voltage is turned off, and then the lower plate of the to-be-calibrated capacitor is connected to the reference voltage, and the lower plates of the remaining bit capacitors are connected to ground. At this time, the total charge of the capacitor array is conserved, and after charge redistribution, the upper plate voltage of the capacitor at this time can be calculated as If there is no capacitor mismatch, the error voltage extracted at this time is which is 0, but in reality, due to the presence of capacitor mismatch, the error voltage at this time is not 0. In this way, the error voltages of all subsequent bits can be extracted. It is worth noting that during the extraction process, the lower plates of all capacitors above the to-be-calibrated capacitor need to be connected to ground.

[0060] Further, in step 110 of the embodiment of the application, the quantization error code word of the error voltage is determined using the determined calibration capacitor array by using a successive approximation method, i.e., starting from the highest bit of the calibration capacitor array, setting the highest bit as 1, connecting it to the reference voltage, judging whether the highest bit is kept as 1 by the output of the comparator, if the comparator output is 1, keeping the lower plate of the capacitor connected to the reference voltage, if the comparator output is 0, setting the highest bit as 0, then repeating the operation in the next highest bit, until the value of the last bit is determined, at this time, the corresponding code word of the lower plate of the capacitor array is the error code word.

[0061] Further, in step 110 of the embodiment of the application, after the error code word is obtained, the error caused by the calibration of each bit of the capacitor mismatch can be compensated, i.e., the error code word is added to the ideal weight of each bit of the capacitor, and the real weight obtained is the weight of the foreground calibration, i.e., the weight of the 14-bit capacitor is obtained . It should be noted that the error of the calibration capacitor array in the capacitor array is negligible, the weight of the calibration capacitor array is the ideal weight, and the weight of the capacitor to be calibrated is the real weight (the ideal weight plus the error code word).

[0062] The foreground digital calibration algorithm used in the embodiment of the application can realize the quantization of the error voltage by multiplexing the low-bit capacitor without increasing the additional calibration capacitor array, thereby reducing the power consumption of the circuit.

[0063] Further, in step 120 of the embodiment of the application, the ADC enters normal work, and the calibration algorithm switches to the background digital calibration mode, at this time, the ADC starts normal sampling and quantization, and a pseudo-random sequence is injected. The pseudo-random sequence has certain statistical properties similar to random noise, and can be repeatedly generated. It is a sequence obtained by filtering and other processing of a periodic digital sequence, and the M sequence is the most common sequence in the pseudo-random sequence and is widely used in various digital signal processing. The M sequence is the longest periodic sequence generated by a shift register with linear feedback, and the longest sequence period generated by an n-level feedback shift register is , and as long as the period of the random sequence reaches the maximum value, the ordering rule of the generated sequence will not change with the change of the initial state, and the change of the output sequence is only related to the feedback logic of the linear feedback shift register. By setting shift registers with different bit numbers and initial values with different states, uncorrelated pseudo-random sequences can be generated. And the autocorrelation characteristics of the pseudo-random sequence determine that the probabilities of the elements in the sequence are mutually independent, and this characteristic can ensure that the pseudo-random sequence injected into the ADC for extracting the capacitor mismatch value is correct. In the embodiment of the application, n is preferably 16, i.e., the pseudo-random sequence with a period of 16383.

[0064] Further, in step 120 of the embodiment of the present application, the pseudo-random sequence is added to the input signal VIN and then quantized by the ADC to obtain a corresponding digital code word , and a corresponding decimal analog value is obtained by weighted summation of the digital code word , which is the output after interference by the pseudo-random code, so that the interference of the pseudo-random code is eliminated , and the corresponding input , i.e. , is obtained. It is worth noting that the weight at this time is not an ideal binary weight, but a real weight containing a capacitance mismatch calculated by foreground calibration.

[0065] Further, in step 120 of the embodiment of the present application, the weight after foreground calibration cannot reflect the change of the capacitance weight in real time, and at this time the weight after foreground calibration needs to be iterated by calculating an error. Specifically, a calibration coefficient can be obtained by correlating the result after weighted summation of the digital output with the corresponding pseudo-random code, and the weight is iterated based on the calibration coefficient. The specific process is as follows:

[0066] The calibration coefficient can be obtained by multiplying and summing the result after weighted summation of the digital output with the corresponding pseudo-random code , i.e. , so that the calibration coefficient contains information including a capacitance mismatch and a foreground calibration error, and also reflects the size of the error. If the calibration coefficient is large, it means that the weight of the current state is still far from the real value, and vice versa. At this time, the weight is iterated , where is the weight obtained by the current iteration, is the weight obtained by the previous iteration, is the number of iterations, is the step size for adjusting the weight. The selection of the step size is crucial for the convergence of the algorithm. If the step size is too large, the algorithm may not converge, and if the step size is too small, the iteration time may be too long. The initial weight in the iteration process can be the weight after foreground calibration.

[0067] Further, due to the injection of the pseudo-random sequence, the input signal superimposed with the pseudo-random sequence will inevitably be disturbed more than the pseudo-random sequence itself in practical applications, and such disturbance cannot be completely removed in the quantization cancellation operation. That is, the calibration algorithm based on pseudo-random code injection introduces inherent noise in a certain sense from the beginning, which affects the result of the background calibration. At this time, the weight obtained through the foreground calibration can be used as a correction to assist the background calibration to achieve more accurate calibration results. Specifically, in the weight iteration process, more robust error estimation can be obtained through Kalman filtering. Kalman filtering is a recursive state estimation algorithm suitable for linear systems and can optimally estimate the system state in the presence of noise. The filtering process includes two main steps: prediction and update. The prediction equation is as follows:

[0068]

[0069] where, is the state transition matrix, is the control input matrix, is the state at time k-1, is the predicted value at time k, is the known external input of the system.

[0070] The predicted covariance matrix is calculated as follows, which is used to reflect the uncertainty of state prediction:

[0071]

[0072] where, is the covariance at time k-1, is the process noise covariance matrix, is the estimated covariance at time k.

[0073] The state update equation is as follows:

[0074]

[0075] where, is the observation residual, is the observation value, is the Kalman gain, which is determined by the equation , is the observation matrix, is the observation noise covariance matrix, is the predicted value at time k, is the correction value at time k, which is the result of the joint action of observation and prediction. The Kalman gain determines the weight distribution between prediction and observation.

[0076] Finally, the covariance matrix is updated to reflect the revised estimation uncertainty: Kalman filter fuses the model prediction and measurement information at each time instant through the above-mentioned two steps of prediction and update, and realizes the recursive optimal estimation of the system state.

[0077] The real weight of each bit capacitor is modeled as a state vector that needs to be estimated. The capacitor weight of the foreground calibration is used as the initial value of the state vector, and the background calibration continuously provides updated observations during system operation. Kalman filter uses the confidence of the two types of observations (represented by the observation noise variance) in each sampling round to weight the output of the current optimal capacitor weight estimation. Specifically, the foreground calibration variance is: wherein, is the observation value of the foreground calibration, is the observation matrix of the foreground calibration, is the state vector of the foreground calibration, is the observation noise of the foreground calibration. Since the foreground calibration is completed during the system startup or test phase, the corresponding observation noise is relatively small, and the background calibration variance is: wherein, is the observation value of the background calibration, is the observation matrix of the background calibration, is the state vector of the background calibration, is the observation noise of the background calibration. Since the background calibration calculates the capacitor weight by inserting a pseudo-random code, the observation noise is relatively large, so they can be unified into the same state space model, combined with the above-mentioned Kalman filter, to achieve better calibration effect, as shown in Figure 3 the error convergence curve of the calibration.

[0078] Based on the same technical concept described above, the embodiment of the present application also proposes a capacitor mismatch calibration system that fuses foreground and background calibration, as shown in Figure 4 The capacitor mismatch calibration system proposed in the embodiment of the present application comprises:

[0079] The foreground digital calibration module is configured to perform foreground digital calibration after the chip is powered on, including: acquiring an error voltage; quantizing the acquired error voltage to generate a corresponding error code word, and obtaining a foreground calibration weight.

[0080] And a background digital calibration module configured to: when the ADC is in normal operation, perform background digital calibration, including: generating a pseudo-random sequence and injecting it into the input signal of the ADC; weighted summing the digital code words of the quantized output of the ADC and eliminating the interference of the pseudo-random sequence therefrom; correlating the weighted summing result after eliminating the interference of the pseudo-random sequence with the pseudo-random sequence to obtain a calibration coefficient, and iteratively calculating the capacitance weight according to the calibration coefficient.

[0081] Further, the foreground digital calibration module of the embodiment of the application includes:

[0082] An error voltage acquisition unit configured to: acquire the error voltage by switching the capacitance lower plate switch, and the specific process is as described in the above step 110, which will not be repeated here.

[0083] A quantization unit configured to: quantize the error voltage using the determined calibration capacitance array using the successive approximation method to generate a corresponding error code word, and the specific process is as described in the above step 110, which will not be repeated here.

[0084] And a compensation unit configured to: add the corresponding error code word to the ideal weight of the capacitance to obtain the real weight, which is the weight of the foreground calibration.

[0085] Further, the background digital calibration module of the embodiment of the application includes:

[0086] A pseudo-random sequence generation unit configured to: generate a pseudo-random sequence and inject it into the input signal of the ADC. The pseudo-random sequence generation process is as described in the above step 120, which will not be repeated here.

[0087] An interference elimination unit configured to: weighted sum the digital code words of the quantized output of the ADC and eliminate the interference of the pseudo-random sequence therefrom. The specific process is as described in the above step 120, which will not be repeated here.

[0088] A correlation calculation unit configured to: correlate the weighted summing result after eliminating the interference of the pseudo-random sequence with the pseudo-random sequence to obtain a calibration coefficient. The specific calculation process is as described in the above step 120, which will not be repeated here.

[0089] And an iterative calculation unit configured to: iteratively calculate the capacitance weight according to the calibration coefficient. The specific iterative calculation process is as described in the above step 120, which will not be repeated here.

[0090] Further, the background digital calibration module of the embodiment of the application further includes:

[0091] The fusing unit is configured to fuse the capacitance weight obtained by each iteration calculation of the iteration calculation unit and the real weight obtained by the compensation unit by Kalman filtering to obtain an optimal capacitance weight. The specific process is described in the above step 120, and will not be described here.

[0092] The above detailed description further illustrates the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A capacitance mismatch calibration method integrating front-end and back-end calibration, characterized in that, include: After the chip is powered on, a front-end digital calibration is performed, including: acquiring the error voltage; quantizing the acquired error voltage to generate a corresponding error codeword; and obtaining the actual weight based on the error codeword and the ideal weight as the weight for the front-end calibration. Once the ADC enters normal operation, background digital calibration is performed, including: generating a pseudo-random sequence and injecting it into the input signal of the ADC; performing a weighted summation on the digital codewords quantized by the ADC and eliminating interference from the pseudo-random sequence; performing correlation calculations between the weighted summation result after eliminating interference from the pseudo-random sequence and the pseudo-random sequence to obtain calibration coefficients, and iteratively calculating the capacitor weights based on the calibration coefficients.

2. The capacitance mismatch calibration method with front-end and back-end calibration fusion according to claim 1, characterized in that, The method for obtaining the error voltage includes: The number of bits in the capacitor array to be calibrated is determined. Capacitors with more than the number of bits are the capacitors to be calibrated, and capacitors with fewer than the number of bits constitute the calibration capacitor array, ignoring the effect of capacitor mismatch. The capacitor weights of the calibration capacitor array are considered to be ideal weights. The determination of the number of bits needs to ensure that the calibration capacitor array composed of the selected low-bit capacitors remains linear with the accuracy of the selected number of bits. By pre-charging the capacitor array, since there is no path for charge leakage, the charge is conserved. The lower plate of the capacitor to be calibrated is first switched to ground, and then switched to the reference voltage. The error voltage can be extracted and stored at the output of the capacitor array to await the next step of quantization. The capacitor array is switched according to this process to obtain the error voltage of each capacitor to be calibrated.

3. The capacitance mismatch calibration method integrating front-end and back-end calibration according to claim 2, characterized in that, The step of quantizing the acquired error voltage to generate corresponding error codewords includes: The error voltage of each capacitor to be calibrated is quantized using the calibration capacitor array through a successive approximation method to obtain the corresponding error codeword.

4. The capacitance mismatch calibration method integrating front-end and back-end calibration according to claim 2, characterized in that, The method of obtaining the true weight as the front-end calibration weight based on the error codeword and the ideal weight includes: The ideal weight of each capacitor to be calibrated is added to its corresponding error codeword to obtain the true weight of the capacitor to be calibrated; the capacitor weights of the calibration capacitor array are the ideal weights.

5. A capacitance mismatch calibration method integrating front-end and back-end calibration according to any one of claims 1-4, characterized in that, The weighted summation of the digital codewords output by the ADC quantization, and the elimination of interference from the pseudo-random sequence, includes: The input signal injected into the pseudo-random sequence is quantized by an ADC to obtain the corresponding digital codeword; The corresponding decimal analog value is obtained by weighted summation of the digital codewords; the capacitor weights used in the weighted summation process are the weights calibrated at the front end. The interference of the pseudo-random sequence is eliminated from the decimal analog value.

6. The capacitance mismatch calibration method with front-end and back-end calibration fusion according to claim 5, characterized in that, The step of performing a correlation calculation between the weighted summation result after eliminating interference from the pseudo-random sequence and the pseudo-random sequence to obtain a calibration coefficient, and then iteratively calculating the capacitance weights based on the calibration coefficient, includes: The calibration coefficient is obtained by multiplying the interference-free decimal analog value with each pseudo-random code in the pseudo-random sequence and summing the results. The capacitor weight is iteratively calculated using a weight iteration calculation formula, which is: the capacitor weight calculated in the current iteration is equal to the capacitor weight calculated in the previous iteration minus the product of the calibration coefficient and the step size, where the initial weight is the weight of the front-end calibration.

7. The capacitance mismatch calibration method with front-end and back-end calibration fusion according to claim 6, characterized in that, The aforementioned background digital calibration also includes: The optimal capacitance weights are obtained by weighting and fusing the capacitance weights calculated in each iteration with the weights of the front-end calibration using Kalman filtering.

8. A capacitance mismatch calibration system integrating front-end and back-end calibration, characterized in that, include: The front-end digital calibration module is configured to perform front-end digital calibration after the chip is powered on, including: acquiring an error voltage; quantizing the acquired error voltage to generate a corresponding error codeword; and obtaining a true weight based on the error codeword and an ideal weight as the weight for front-end calibration. Additionally, the background digital calibration module is configured to perform background digital calibration when the ADC enters normal operation, including: generating a pseudo-random sequence and injecting it into the input signal of the ADC; performing a weighted summation on the digital codewords quantized by the ADC and eliminating interference from the pseudo-random sequence; performing correlation calculations between the weighted summation result after eliminating interference from the pseudo-random sequence and the pseudo-random sequence to obtain calibration coefficients, and iteratively calculating the capacitor weights based on the calibration coefficients.

9. A capacitance mismatch calibration system integrating front-end and back-end calibration according to claim 8, characterized in that, The front-end digital calibration module includes: The error voltage acquisition unit is configured to acquire the error voltage by switching the lower plate of the capacitor. The quantization unit is configured to quantize the error voltage using a successive approximation method with a defined calibration capacitor array to generate the corresponding error codeword; Furthermore, the compensation unit is configured to add the corresponding error codeword to the ideal weight of the capacitor to obtain the true weight, which is the weight of the front-end calibration.

10. A capacitance mismatch calibration system integrating front-end and back-end calibration according to claim 8, characterized in that, The background digital calibration module includes: A pseudo-random sequence generation unit is configured to generate a pseudo-random sequence and inject it into the input signal of the ADC; The interference cancellation unit is configured to: perform a weighted summation on the digital codewords quantized by the ADC and eliminate interference from the pseudo-random sequence therefrom; The relevant calculation unit is configured to: perform correlation calculation between the weighted summation result after eliminating the interference of the pseudo-random sequence and the pseudo-random sequence to obtain the calibration coefficient; And, the iterative calculation unit is configured to: perform iterative calculation of the capacitance weights based on the calibration coefficients; Optionally, the background digital calibration module further includes: The fusion unit is configured to use Kalman filtering to perform weighted fusion of the capacitance weights calculated by the iterative calculation unit in each iteration with the weights obtained by the front-end digital calibration module to obtain the optimal capacitance weights.

Images