A multi-stage concatenated sequence enhanced dual-domain signal transmission method, system and medium

Abstract

The application discloses a kind of multi-level connection sequence enhanced double-domain signal transmission method, system and medium, it is related to signal processing technical field.The method thereof includes: obtaining original signal and key initial value to be transmitted;Key initial value is generated two-dimensional chaotic sequence X and two-dimensional chaotic sequence Y by cross chaotic system;Original signal is masked in symbol domain using two-dimensional chaotic sequence X, and symbol domain encrypted signal is obtained;Symbol domain encrypted signal is converted into serial-parallel, PAM4 mapping, and mapping signal is obtained;Mapping signal is input into FIFO register and masked in time domain, and time domain encrypted signal is obtained;Clock delay of FIFO register is controlled by two-dimensional chaotic sequence Y;Time domain encrypted signal is transmitted.The application avoids the problem that key is fixed and difficult to update in traditional scheme, while ensuring nanoscale processing delay, realizes the cooperative optimization of real-time transmission and security.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, in particular to a multi-cascaded sequence enhanced dual-domain signal transmission method, system and medium. BACKGROUND

[0002] With the rapid development of optical communication networks, enhancing the security performance of data transmission becomes more and more important with the continuous growth of computing power, while the explosive growth of data traffic also makes low-latency data transmission a key issue. The current mainstream quantum key distribution and chaotic encryption and other secure communication schemes rely heavily on offline computing platforms, and their multi-level encryption algorithms require high-complexity iterative operations and complex key negotiation mechanisms, which require more time for data processing than signal transmission, resulting in high latency and difficulty in meeting real-time dynamic transmission requirements. Although real-time optical communication systems based on FPGA significantly improve data transmission efficiency, the limitations of hardware will result in loss of computing precision, and the ergodicity, randomness and initial value sensitivity of digital chaotic encryption will be affected. Therefore, building a real-time encryption system deeply integrated with the physical layer of high-speed optical communication has become a key issue.

[0003] There have been some researches in real-time encryption theory, which can achieve bit-by-bit real-time encryption of physical layer data while maintaining nanosecond-level processing delay by mapping simple chaotic encryption algorithms to FPGA hardware pipelines. In order to balance high security and low complexity of algorithms, chaotic enhancement technology has also gradually attracted attention. Among them, cascading and coupling of different chaotic systems is the most common method to enhance chaotic dynamics. Through cascading operation, a new chaotic system with higher initial value sensitivity and larger parameter range can be obtained, but its enhancement effect is single and still affected by hardware limitations. The coordinated optimization of real-time performance and security of signal transmission still faces great challenges.

[0004] Therefore, in high-speed optical communication transmission, how to balance real-time performance and security at the same time has become a problem to be solved. At the same time, the limitation of key update, the insufficient hardware implementation precision of chaotic system and the high delay of traditional encryption method all restrict its application in real-time communication scenarios. SUMMARY

[0005] The purpose of the present application is to overcome the deficiencies in the prior art, provide a dual-cascaded sequence enhanced dual-domain signal transmission method, system and medium, which avoids the problem of fixed key and difficult update in traditional schemes, and realizes the coordinated optimization of real-time transmission and security while ensuring nanosecond-level processing delay.

[0006] To achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0007] In one aspect, the application provides a multi-stage sequence enhanced dual-domain signal transmission method, comprising:

[0008] obtaining an original signal to be transmitted and a key initial value;

[0009] generating a two-dimensional chaotic sequence X and a two-dimensional chaotic sequence Y from the key initial value through a cross chaotic system; and controlling parameters of the cross chaotic system through a closed-loop adjustment mechanism based on Lyapunov index difference;

[0010] performing symbol domain masking on the original signal by using the two-dimensional chaotic sequence X to obtain a symbol domain encrypted signal;

[0011] performing serial-parallel conversion and PAM4 mapping on the symbol domain encrypted signal to obtain a mapped signal;

[0012] inputting the mapped signal into a FIFO register to perform time domain masking to obtain a time domain encrypted signal; and controlling clock delay of the FIFO register by using the two-dimensional chaotic sequence Y;

[0013] performing signal transmission on the time domain encrypted signal.

[0014] Optionally, the cross chaotic system uses Sine mapping and Tent mapping as a basis to obtain the two-dimensional chaotic sequence X and the two-dimensional chaotic sequence Y, and is expressed as:

[0015]

[0016] wherein, , respectively represent data of the two-dimensional chaotic sequence X generated in the i th iteration and data of the two-dimensional chaotic sequence X generated in the j th iteration; respectively represent data of the two-dimensional chaotic sequence Y generated in the i th iteration and data of the two-dimensional chaotic sequence Y generated in the j th iteration; respectively represent Sine chaotic parameters and Tent chaotic parameters of the cross chaotic system. Optionally, the parameters of the cross chaotic system are controlled through the closed-loop adjustment mechanism based on Lyapunov index difference, comprising: obtaining a cross chaotic system of floating point numbers;

[0017] performing hardware fixed-point simulation on the cross chaotic system of floating point numbers through an FPGA hardware platform to obtain a cross chaotic system of fixed-point numbers;

[0018] obtaining a cross chaotic system of floating point numbers;

[0019] performing hardware fixed-point simulation on the cross chaotic system of floating point numbers through an FPGA hardware platform to obtain a cross chaotic system of fixed-point numbers; ​​​​​

[0020] Calculate the floating-point Lyapunov exponent based on the cross-chaotic system of floating-point numbers, and calculate the fixed-point Lyapunov exponent based on the cross-chaotic system of fixed-point numbers.

[0021] The floating-point Lyapunov exponent and the fixed-point Lyapunov exponent are compared using an adaptive rule function, and the parameters of the cross-chaotic system are controlled based on the comparison result.

[0022] Optionally, the parameters of the cross-chaotic system can be controlled based on the comparison results, including:

[0023] If the floating-point Lyapunov exponent is greater than the fixed-point Lyapunov exponent, then the Sine chaos parameter of the cross-chaotic system is increased, as shown in the formula:

[0024] ;

[0025] If the floating-point Lyapunov exponent is less than the fixed-point Lyapunov exponent, then the Sine chaos parameter of the cross-chaotic system is reduced, as shown in the formula:

[0026] ;

[0027] If the floating-point Lyapunov exponent is equal to the fixed-point Lyapunov exponent, then the parameters of the cross-chaotic system remain unchanged.

[0028] in, , They represent the first The next iteration, the... Sine chaotic parameters of a sub-iterative cross-chaotic system; Indicates the adjustment step size; , These represent the maximum and minimum values ​​of the Sine chaotic parameter of the cross-chaotic system, respectively. , These represent taking the maximum and taking the minimum values, respectively.

[0029] Optionally, the original signal is symbolically masked using a two-dimensional chaotic sequence X to obtain a symbolically encrypted signal, including:

[0030] The original signal is divided into bytes to obtain a byte signal sequence. ;in, These represent the first group of byte signals, the second group of byte signals, and the third group of byte signals, respectively. Group byte signal, first Group byte signal;

[0031] Determining the symbol field masking mode based on the two-dimensional chaotic sequence X ;in, representing the low two bits of the binary data obtained by intercepting the last iteration of the two-dimensional chaotic sequence X as a symbol field mask pattern;

[0032] According to the symbol field mask pattern , the original signal is subjected to symbol field masking to obtain a symbol field encrypted signal.

[0033] Optionally, the original signal is subjected to symbol field masking according to the symbol field mask pattern to obtain a symbol field encrypted signal, comprising:

[0034] If , the odd group byte signals in the byte signal sequence are subjected to bitwise inversion respectively to obtain the symbol field encrypted signal;

[0035] If , each group of byte signals in the byte signal sequence is subjected to reverse processing respectively to obtain the symbol field encrypted signal;

[0036] If , the even group byte signals in the byte signal sequence are subjected to bitwise inversion respectively to obtain the symbol field encrypted signal;

[0037] If , a group of byte signals are taken from both ends of the byte signal sequence in turn respectively until all groups of byte signals in the byte signal sequence are transposed, or only the middle group of byte signals in the byte signal sequence remains in the original position, then the symbol field encrypted signal is obtained.

[0038] Optionally, the clock delay of the FIFO register is controlled by a two-dimensional chaotic sequence Y, comprising:

[0039] According to the two-dimensional chaotic sequence Y, the model index of the clock delay is determined and the table index of the clock delay ; wherein, representing the low two bits of the binary data obtained by intercepting the last iteration of the two-dimensional chaotic sequence Y as the model index of the clock delay; representing the high two bits of the binary data obtained by intercepting the last iteration of the two-dimensional chaotic sequence Y as the table index of the clock delay; representing the number of data bits of the binary data obtained by intercepting the last iteration of the two-dimensional chaotic sequence Y;

[0040] According to the model index of the clock delay and the table index of the clock delay , a clock delay table is generated;

[0041] According to the clock delay table, the clock delay of the FIFO register is controlled.

[0042] Optionally, the clock delay of the FIFO register is controlled according to the clock delay table, comprising:

[0043] If and , and , and , or and , the FIFO register is controlled without delay;

[0044] If and , and , and , or and , the FIFO register is controlled to delay the writing of data by 1 clock cycle;

[0045] If and , and , and , or and , the FIFO register is controlled to delay the writing of data by 2 clock cycles;

[0046] If and , and , and , or and , the FIFO register is controlled to delay the writing of data by 3 clock cycles.

[0047] In a second aspect, the application provides a multi-stage sequence enhanced dual-domain signal transmission system, comprising:

[0048] An information acquisition module is configured to acquire an original signal to be transmitted and a key initial value;

[0049] A chaotic sequence generation module is configured to generate a two-dimensional chaotic sequence X and a two-dimensional chaotic sequence Y by a cross chaotic system through the key initial value, and to control parameters of the cross chaotic system through a closed-loop adjustment mechanism based on Lyapunov index difference;

[0050] A symbol domain encryption module is configured to perform symbol domain masking on the original signal by using the two-dimensional chaotic sequence X to obtain a symbol domain encrypted signal;

[0051] The signal mapping module is configured to perform serial-parallel conversion and PAM4 mapping on the symbol domain encrypted signal to obtain a mapped signal.

[0052] The time domain encryption module is configured to input the mapped signal into a FIFO register to perform time domain masking to obtain a time domain encrypted signal, and control clock delay of the FIFO register through a two-dimensional chaotic sequence Y.

[0053] The signal transmission module is configured to perform signal transmission on the time domain encrypted signal.

[0054] In a third aspect, the present application provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the multi-cascaded sequence enhanced dual-domain signal transmission method of the first aspect.

[0055] Compared with the prior art, the present application has the following beneficial effects:

[0056] The present application designs a chaotic enhancement mechanism through Lyapunov exponent, realizes an adaptive dynamic chaotic enhancement cross chaotic system, and introduces symbol domain and time domain perturbation in the transmission process to realize dynamic masking of signal timing, greatly enhances the anti-attack ability and security, and single domain encryption can only provide protection against certain attacks, which has potential vulnerabilities. In addition, in the symbol encryption and timing perturbation process, the state parameters of the cross chaotic system are changing in real time, so that the key can be dynamically updated, avoiding the problem of fixed key and difficult updating in the traditional scheme, ensuring the reliability and continuity of the communication process, while ensuring the processing delay of nanoseconds, realizing the cooperative optimization of real-time performance and security in high-speed optical communication. BRIEF DESCRIPTION OF DRAWINGS

[0057] Figure 1 Fig. 1 shows a flowchart of the multi-cascaded sequence enhanced dual-domain signal transmission method in the embodiment of the present application;

[0058] Figure 2 Fig. 4 shows a bifurcation diagram of Sine mapping in the embodiment of the present application;

[0059] Figure 3 Fig. 5 shows a bifurcation diagram of Tent mapping in the embodiment of the present application;

[0060] Figure 4 Fig. 6 shows a bifurcation diagram of the cross chaotic system in the embodiment of the present application;

[0061] Figure 5 Fig. 7 shows a flowchart of controlling parameters of the cross chaotic system in the embodiment of the present application;

[0062] Figure 6A flow chart of processing of the dual-domain encrypted signal in the embodiment of the application is shown.

[0063] Figure 7 A clock delay table in the embodiment of the application is shown. DETAILED DESCRIPTION

[0064] The technical solutions of the application will be described in detail below with reference to the drawings and specific embodiments. It should be understood that the embodiments of the application and the specific features in the embodiments are detailed descriptions of the technical solutions of the application, rather than limitations of the technical solutions of the application. In the case of no conflict, the technical features in the embodiments of the application and the embodiments can be combined with each other.

[0065] The term "and / or", only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " generally represents that the associated objects before and after it are in an "or" relationship.

[0066] Embodiment 1

[0067] As Figure 1 shown, the embodiment introduces a multi-stage concatenated sequence enhanced dual-domain signal transmission method, including the following steps:

[0068] At the sending end:

[0069] Step 1: Obtain the original signal to be transmitted and the key initial value.

[0070] Step 2: Symbol and time domain encryption, and Quadrilateral Amplitude Modulation (PAM4) mapping, specifically:

[0071] Generate a two-dimensional chaotic sequence X and a two-dimensional chaotic sequence Y from the key initial value through a cross chaotic system; control the parameters of the cross chaotic system through a closed-loop adjustment mechanism based on the difference in Lyapunov exponents;

[0072] Use the two-dimensional chaotic sequence X to perform symbol domain masking on the original signal to obtain a symbol domain encrypted signal;

[0073] Perform serial-parallel conversion and PAM4 mapping on the symbol domain encrypted signal to obtain a mapping signal;

[0074] Input the mapping signal into a First In First Out (FIFO) register to perform time domain masking to obtain a time domain encrypted signal; control the clock delay of the FIFO register through the two-dimensional chaotic sequence Y.

[0075] Step 3: Signal transmission, specifically:

[0076] The time domain encrypted signal is sequentially transmitted through a digital-to-analog converter, an amplifier, a laser, and a modulator.

[0077] At the receiving end:

[0078] Step one: signal receiving, specifically:

[0079] The time domain encrypted signal from the sending end is sequentially received through a detector and an analog-to-digital converter.

[0080] Step two: PAM4 demapping and symbol and time dual-domain decryption, specifically:

[0081] PAM4 demapping and symbol and time dual-domain decryption is the inverse process of the sending end, which will not be described here.

[0082] Step three: obtaining the original signal to be transmitted and the key initial value.

[0083] Step four: bit error rate analysis, specifically:

[0084] The bit error rate of the original signal is analyzed on a personal computer through the international standard test protocol, namely Joint Test Action Group (JTAG).

[0085] The receiving end is the inverse process of the sending end, and legitimate users can recover the original signal through PAM4 demodulation and dual-domain decryption operations. It is worth noting that the state parameters of the chaotic system are updated in real time during each symbol encryption and timing disturbance process, so that the key continuously changes dynamically, and the identity verification is completed synchronously during decryption, further enhancing the security of the system.

[0086] This embodiment introduces symbol domain and time domain disturbance in the transmission process, realizes dynamic masking of signal timing, greatly enhances the anti-attack ability and security; in addition, the state parameters of the chaotic system are changing in real time during symbol encryption and timing disturbance, so that the key can be dynamically updated, avoiding the problem of fixed key and difficult updating in traditional schemes; the legitimate receiving end can realize synchronous identity verification in the process of demodulation and decryption, ensuring the reliability and continuity of the communication process; not only improves the randomness and key space of chaotic encryption, but also realizes the cooperative optimization of real-time and security in high-speed optical communication.

[0087] Embodiment 2

[0088] Based on embodiment 1, this embodiment introduces a multi-level sequence enhanced dual-domain signal transmission method, and details the signal processing process of the sending end, including the following steps:

[0089] Step one: obtain the original signal to be transmitted and the key initial value.

[0090] Step two: symbol and time domain encryption, and PAM4 mapping, specifically:

[0091] Sine mapping is a classic one-dimensional chaotic system:

[0092] ;

[0093] wherein, , respectively represent the data generated in the first iterative one-dimensional Sine mapping chaotic sequence and the data generated in the first iterative one-dimensional Sine mapping chaotic sequence; Sine mapping system parameter; as shown in Figure 2 is the bifurcation diagram of Sine mapping with respect to Sine mapping system parameter .

[0094] Tent mapping is a one-dimensional discrete chaotic mapping system that is widely used at present, which is a piecewise linear one-dimensional mapping, simple in form, uniform in power spectral density, and its mathematical model is:

[0095] ;

[0096] wherein, , respectively represent the data generated in the first iterative one-dimensional Tent mapping chaotic sequence and the data generated in the first iterative one-dimensional Tent mapping chaotic sequence; Tent mapping system parameter, which controls the dynamic characteristics of Tent mapping, and its bifurcation diagram with respect to Tent mapping system parameter is shown in Figure 3 .

[0097] Since one-dimensional chaotic systems have security defects such as chaotic periodic window, uneven output of sequences, poor randomness, etc. when applied to encryption, and in real-time encryption scenarios, these defects will be further magnified due to the calculation precision of hardware systems. Avoiding periodic windows requires the introduction of a complex parameter screening mechanism, and improving statistical properties often requires increasing the number of iterations, which contradicts the requirement of real-time systems for computational efficiency.

[0098] Therefore, the chaotic system in the embodiment adopts a cross chaotic system, which cross obtains a two-dimensional chaotic sequence X and a two-dimensional chaotic sequence Y based on Sine mapping and Tent mapping, and is represented as:

[0099] ;

[0100] in, , They represent the first The data of the two-dimensional chaotic sequence X generated in the nth iteration, the nth Data of the two-dimensional chaotic sequence X generated in the next iteration; , Let Y represent the data of the two-dimensional chaotic sequence Y generated in the nth iteration, and Y represent the data of the two-dimensional chaotic sequence Y generated in the nth iteration, respectively. Data of the two-dimensional chaotic sequence Y generated in the next iteration; , These represent the Sine chaotic parameter and the Tent chaotic parameter of the cross-chaotic system, respectively. , , , The system's complexity is affected by the two sub-mappings, which greatly increases the system's complexity and sequence randomness, while the initial value of the fixed key remains unchanged. , Tent chaotic parameters of cross-chaotic systems Plot the Sine chaotic parameters of the cross-chaotic system. The bifurcation graph, with a step size set to 0.005, yields information about... The bifurcation diagram, such as Figure 4 As shown. It can be clearly observed that the system only... There is a periodic window within the interval. The system is in a chaotic state within the interval, exhibiting extremely high randomness.

[0101] Considering the limitations of cascading operations in hardware implementation, a closed-loop adjustment mechanism based on Lyapunov exponent (LE) differences is proposed to control the parameters of the cross-chaotic system, achieving adaptive optimization of chaotic enhancement to achieve synergistic optimization of safety and real-time performance. Figure 5 As shown:

[0102] First, the floating-point chaotic system is output, and the floating-point Lyapunov exponent LE_float is calculated in real time and input into the adaptive rule function;

[0103] Secondly, the floating-point cross-chaotic system is simulated using a hardware fixed-point simulation on an FPGA platform. In the offline system, the hardware fixed-point simulation is constructed entirely according to the real-time FPGA system, i.e.:

[0104] Based on the FPGA hardware platform, the floating-point iteration process of the chaotic system is transformed into a fixed-point iteration process through equivalent transformation. Specifically, the cross-chaotic system is quantized, and the initial key value is input into the chaotic system in the form of a fixed-point number to generate a chaotic pseudo-random sequence. From the perspective of hardware implementation, a base-2 representation is used during quantization, so that multiplication can be completed through shift operations, thereby reducing computational complexity. Considering the accuracy requirements, the Q16.16 fixed-point number format is adopted, in which the high 16 bits represent the integer part and the low 16 bits represent the fractional part, so as to balance computational accuracy and hardware implementation efficiency.

[0105] Modular design of nonlinear iterative equations in cross-chaotic systems requires multi-level floating-point operations, necessitating adjustments to the computational methods. Trigonometric functions are implemented using the rotation mode of the Coordinate Rotation Digital Computer (CORDIC) algorithm. The core idea of ​​this algorithm is to approximate rotations of arbitrary angles through a series of shift and addition / subtraction operations, thus avoiding the use of multipliers. Specifically, for the input angle... The CORDIC iterative process is defined as follows:

[0106] ;

[0107] in, , , Represents the spatial coordinates of the i-th iteration point to be rotated; , , Indicates the first Spatial coordinates of the next rotation point; Indicates the first The rotation direction of the next iteration; The symbolic function is represented; the total number of iterations is N;

[0108] In each step, multiply by Achieved through shifting, angle constant Pre-stored in the lookup table, since the pseudo-rotation of the CORDIC iteration method will introduce an overall scaling in numerical terms, the scaling factor can be calculated in advance when initializing the input vector settings so that the calculation result is close to the true value. The same applies to the square root operation.

[0109] The inverse trigonometric function adopts a method of lookup table combined with linear interpolation, a lookup table is pre-calculated and the values are stored in a read-only memory (ROM) in fixed-point format, by inputting normalization, the key initial value of the floating-point number is mapped to the index space of the preset lookup table, the upper and lower bounds are taken, the end point values are obtained by looking up the table, then linear interpolation is performed according to the fractional part to obtain the approximate value of the inverse trigonometric function, and finally the cross chaotic system of the fixed-point number is converted for subsequent hardware calculation.

[0110] The fixed-point Lyapunov exponent LE_fixed is calculated, and the adaptive rule function is input.

[0111] Then, the floating-point Lyapunov exponent and the fixed-point Lyapunov exponent are compared through the adaptive rule function, the cross chaotic system of the fixed-point number is defined as an adaptive system, and the Lyapunov exponent LE_adapt of the adaptive system is the fixed-point Lyapunov exponent LE_fixed.

[0112] Finally, according to the comparison result, the Sine chaotic parameter of the cross chaotic system is controlled, and the adaptive adjustment rule is as follows:

[0113] If the adaptive system degenerates (LE_adapt is much larger than LE_float), the Sine chaotic parameter k of the cross chaotic system is increased, and the formula is:

[0114] ;

[0115] If the adaptive system is over chaotic (LE_adapt is much smaller than LE_float), in order to avoid numerical divergence or distortion, the Sine chaotic parameter k of the cross chaotic system is appropriately reduced, and the formula is:

[0116] ;

[0117] If the adaptive system is normal (LE_adapt is equal to LE_float), the Sine chaotic parameter of the cross chaotic system is unchanged.

[0118] Wherein, , respectively represent the Sine chaotic parameter of the cross chaotic system in the first iteration and the second iteration; respectively represent the Sine chaotic parameter of the cross chaotic system in the first iteration and the second iteration; represents the adjustment step; , respectively represent the maximum value and the minimum value of the Sine chaotic parameter of the cross chaotic system; , respectively represent taking the maximum and taking the minimum.

[0119] ​The adaptive rule function is a closed-loop adjustment mechanism based on the Lyapunov exponential difference. By gradually adjusting the Sine chaotic parameter φ of the cross-chaotic system, the chaotic characteristics of the fixed-point system are made as close as possible to those of the floating-point system, thereby achieving the effect of chaos enhancement.

[0120] The initial key value is used to generate two-dimensional chaotic sequences X and Y through a cross-chaotic system.

[0121] In symbol-domain encryption, attacks on modulation format identification and constellation feature analysis can be effectively resisted by randomly perturbing the modulation symbols or constellation mapping. In time-domain encryption, the attacker's correlation analysis and timing reconstruction capabilities can be weakened by dynamic delay or sampling perturbation. Single-domain encryption often only provides protection against a certain type of attack and has potential vulnerabilities.

[0122] Therefore, this embodiment combines symbol field and time field encryption mechanisms through a dual-domain encryption scheme to achieve dual protection for the modulation layer and the transmission layer, thereby significantly improving the security and robustness of the system.

[0123] Using X in a two-dimensional chaotic sequence to perform symbol-domain masking on the original signal, a symbol-domain encrypted signal is obtained, such as... Figure 6 As shown:

[0124] The original signal is divided into bytes to obtain a byte signal sequence. ;in, These represent the first group of byte signals, the second group of byte signals, and the third group of byte signals, respectively. Group byte signal, first Group byte signal;

[0125] Using the two-dimensional chaotic sequence X as a symbolic domain masking factor, the symbolic domain masking mode is determined. ;in, This indicates that the lowest two bits of the binary data obtained from the last iteration of the two-dimensional chaotic sequence X are used as the symbol field masking mode.

[0126] According to symbolic field masking mode The original signal is scrambled with symbols:

[0127] like Then, the odd-numbered byte signals in the byte signal sequence are bitwise inverted to obtain the symbol field encrypted signal;

[0128] like Then, the byte signals in each group of the byte signal sequence are reversed to obtain the symbol field encryption signal;

[0129] like If the byte signal sequence is

[0130] If the byte signal sequence is , then from the two ends of the byte signal sequence, a group of byte signals are taken in turn to be transposed respectively until all groups of byte signals in the byte signal sequence are transposed or only the middle group of byte signals in the byte signal sequence remains in the original position, and then a symbol domain encrypted signal is obtained; that is, the highest sequence number group of byte signals in the byte signal sequence is transposed with the lowest sequence number group of byte signals, the second highest sequence number group of byte signals is transposed with the second lowest sequence number group of byte signals, and so on, to obtain the symbol domain encrypted signal.

[0131] In a specific embodiment, assuming that the original signal has 128 bits, it is divided into 16 groups of 8-bit bytes to obtain a byte signal sequence ; wherein represents the 1st group of byte signals, the 2nd group of byte signals, the 3rd group of byte signals, the 4th group of byte signals, the 13th group of byte signals, the 14th group of byte signals, the 15th group of byte signals, and the 16th group of byte signals; if , then the odd-numbered groups of byte signals in the byte signal sequence are bitwise inverted respectively to obtain a symbol domain encrypted signal; if , then each group of byte signals in the byte signal sequence is processed in reverse order to obtain a symbol domain encrypted signal; if , then the even-numbered groups of byte signals in the byte signal sequence are bitwise inverted respectively to obtain a symbol domain encrypted signal; if , then and are transposed, and are transposed, and are transposed, and so on, and and are transposed to obtain a symbol domain encrypted signal.

[0132] The symbol domain encrypted signal is converted into a serial-parallel signal and PAM4 mapped to obtain a mapped signal.

[0133] The mapped signal is input into a FIFO register for time domain masking to obtain a time domain encrypted signal;

[0134] wherein the clock delay of the FIFO register is controlled by a two-dimensional chaotic sequence Y, as shown in Figure 6

[0135] ​The two-dimensional chaotic sequence Y is used as a time domain masking factor to determine the model index of clock delay and the table index of clock delay ; wherein, represents that the lower two bits of the binary data obtained by the last iteration of the two-dimensional chaotic sequence Y are intercepted as the model index of clock delay; represents that the higher two bits of the binary data obtained by the last iteration of the two-dimensional chaotic sequence Y are intercepted as the table index of clock delay; represents the number of data bits of the binary data obtained by the last iteration of the two-dimensional chaotic sequence Y, and in the embodiment, the two-dimensional chaotic sequence Y is a 16-bit wide binary sequence, and the higher two bits are the 15th bit and the 14th bit;

[0136] According to the model index of clock delay and the table index of clock delay , a clock delay table is generated, as shown in Figure 7 ;

[0137] If and , and , and , or and , the control FIFO register is not delayed;

[0138] If and , and , and , or and , the writing of data of the control FIFO register is delayed by one clock cycle;

[0139] If and , and , and , or and , the writing of data of the control FIFO register is delayed by two clock cycles;

[0140] If and , and , and , or and If the FIFO register data is written, the write is delayed for 3 clock cycles.

[0141] Step three: signal transmission, specifically:

[0142] The time domain encrypted signal is sequentially transmitted through a digital-to-analog converter, an amplifier, a laser, and a modulator.

[0143] In this embodiment, the Sine mapping and the Tent mapping are cascaded, and a closed-loop adjustment mechanism based on Lyapunov index difference is introduced to enhance the initial value sensitivity and parameter range of the chaotic sequence. A two-dimensional chaotic sequence is generated using a cross chaotic system, and the two-dimensional chaotic sequence is used for symbol domain masking and clock delay introduced by the FIFO. The timing of signal transmission is disturbed, and the time domain is masked. The state parameters of the chaotic system change in real time during each symbol encryption and timing disturbance, and the key is dynamically updated.

[0144] Embodiment 3

[0145] This embodiment introduces a multi-cascaded sequence enhanced dual-domain signal transmission system, which includes:

[0146] The information acquisition module is configured to acquire an original signal to be transmitted and a key initial value.

[0147] The chaotic sequence generation module is configured to generate a two-dimensional chaotic sequence X and a two-dimensional chaotic sequence Y from the key initial value through a cross chaotic system, and control the parameters of the cross chaotic system through a closed-loop adjustment mechanism based on Lyapunov index difference.

[0148] The symbol domain encryption module is configured to perform symbol domain masking on the original signal using the two-dimensional chaotic sequence X to obtain a symbol domain encrypted signal.

[0149] The signal mapping module is configured to perform serial-parallel conversion and PAM4 mapping on the symbol domain encrypted signal to obtain a mapped signal.

[0150] The time domain encryption module is configured to input the mapped signal into a FIFO register for time domain masking to obtain a time domain encrypted signal, and control the clock delay of the FIFO register through the two-dimensional chaotic sequence Y.

[0151] The signal transmission module is configured to perform signal transmission on the time domain encrypted signal.

[0152] The specific functions of the above modules are described in the related content in the methods of Embodiments 1 or 2, which will not be repeated here.

[0153] Embodiment 4

[0154] The embodiment introduces a computer readable storage medium, which stores computer programs / instructions, and the computer programs / instructions are executed by a processor to realize the steps of the multi-cascaded sequence enhanced dual-domain signal transmission method in the embodiment 1 or 2.

[0155] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. In addition, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0156] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system), and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce a device implemented in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that performs the functions specified in the flow(s) or block(s).

[0157] These computer program instructions can also be stored in a computer readable memory that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including instruction apparatus, which realizes the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that performs the functions specified in the flow(s) or block(s).

[0158] These computer program instructions can also be loaded into a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide steps for realizing the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that performs the functions specified in the flow(s) or block(s).

[0159] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are merely illustrative, but not restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims, and these all belong to the protection of the present application.

Claims

1. A multi-stage concatenated sequence enhanced dual domain signal transmission method, characterized in that, The method comprises the following steps: obtaining an original signal to be transmitted and a key initial value; generating a two-dimensional chaotic sequence X and a two-dimensional chaotic sequence Y by a cross chaotic system through the key initial value; controlling the parameters of the cross chaotic system through a closed-loop adjustment mechanism based on the difference of Lyapunov exponents; performing symbol domain masking on the original signal by using the two-dimensional chaotic sequence X to obtain a symbol domain encrypted signal; performing serial-parallel conversion and PAM4 mapping on the symbol domain encrypted signal to obtain a mapped signal; inputting the mapped signal into a FIFO register to perform time domain masking to obtain a time domain encrypted signal; and controlling the clock delay of the FIFO register by the two-dimensional chaotic sequence Y; transmitting the time domain encrypted signal; controlling the parameters of the cross chaotic system through a closed-loop adjustment mechanism based on the difference of Lyapunov exponents, which comprises the following steps: obtaining a cross chaotic system of floating-point numbers; performing hardware fixed-point simulation on the cross chaotic system of floating-point numbers through an FPGA hardware platform to obtain a cross chaotic system of fixed-point numbers; calculating a floating-point Lyapunov exponent according to the cross chaotic system of floating-point numbers and a fixed-point Lyapunov exponent according to the cross chaotic system of fixed-point numbers; comparing the floating-point Lyapunov exponent and the fixed-point Lyapunov exponent through an adaptive rule function and controlling the parameters of the cross chaotic system according to the comparison result; controlling the parameters of the cross chaotic system according to the comparison result, which comprises the following steps: if the floating-point Lyapunov exponent is greater than the fixed-point Lyapunov exponent, increasing the Sine chaotic parameter of the cross chaotic system, and the formula is: ； if the floating-point Lyapunov exponent is less than the fixed-point Lyapunov exponent, decreasing the Sine chaotic parameter of the cross chaotic system, and the formula is: ； if the floating-point Lyapunov exponent is equal to the fixed-point Lyapunov exponent, the parameters of the cross chaotic system remain unchanged; wherein, , respectively represent the Sine chaotic parameters of the cross chaotic system in the first respectively represent the Sine chaotic parameters of the cross chaotic system in the first represents the adjustment step size; , respectively represent the maximum value and the minimum value of the Sine chaotic parameters of the cross chaotic system; , respectively represent taking the maximum and taking the minimum.​ 2. The multi-stage sequence enhanced dual domain signal transmission method according to claim 1, characterized in that, the cross chaotic system obtains a two-dimensional chaotic sequence X and a two-dimensional chaotic sequence Y by cross operation based on Sine mapping and Tent mapping, and is expressed as: ； wherein, , respectively represent the data of the two-dimensional chaotic sequence X generated by the first iteration, the data of the two-dimensional chaotic sequence X generated by the second iteration; , respectively represent the data of the two-dimensional chaotic sequence Y generated by the first iteration, the data of the two-dimensional chaotic sequence Y generated by the second iteration; , respectively represent the Sine chaotic parameter and the Tent chaotic parameter of the cross chaotic system.

3. The method of claim 1, wherein, performing symbol domain masking on the original signal by using the two-dimensional chaotic sequence X to obtain a symbol domain encrypted signal, which comprises the following steps: byte-divide the original signal to obtain a byte signal sequence ; wherein, respectively represent the 1st group of byte signals, the 2nd group of byte signals, the 3rd group of byte signals, and the 4th group of byte signals. Determining a sign field mask according to a two-dimensional chaotic sequence X ; wherein represents intercepting the low two bits of the binary data obtained in the last iteration of the two-dimensional chaotic sequence X as the sign field mask Symbol domain masking mode performing symbol domain masking on the original signal to obtain a symbol domain encrypted signal.

4. The method of claim 3, wherein, performing symbol domain masking on the original signal according to the symbol domain masking mode to obtain a symbol domain encrypted signal, which comprises the following steps: If then the odd number bytes in the byte signal sequence are bitwise inverted to obtain the sign field encrypted signal; If then each group of byte signals in the byte signal sequence is processed in reverse order to obtain a symbol domain encrypted signal; If then the even number bytes in the byte signal sequence are bitwise inverted to obtain the sign field encrypted signal; If then, starting from both ends of the byte signal sequence respectively, a group of byte signals are taken in turn respectively to be transposed, until all groups of byte signals in the byte signal sequence are transposed, or only a middle group of byte signals in the byte signal sequence remains in the original position, and then a symbol domain encrypted signal is obtained.

5. The method of claim 1, wherein, controlling the clock delay of the FIFO register by the two-dimensional chaotic sequence Y, which comprises the following steps: According to the two-dimensional chaotic sequence Y, a model index of clock delay is determined and a table index of clock delay ; wherein, indicates that the lower two bits of the binary data obtained by the last iteration in the two-dimensional chaotic sequence Y are intercepted as the model index of clock delay; indicates that the higher two bits of the binary data obtained by the last iteration in the two-dimensional chaotic sequence Y are intercepted as the table index of clock delay; indicates the number of data bits of the binary data obtained by the last iteration in the two-dimensional chaotic sequence Y. Model index according to clock delay and table index of clock delay generating a clock delay table; controlling the clock delay of the FIFO register according to a clock delay table.

6. The method of claim 5, wherein, controlling the clock delay of the FIFO register according to a clock delay table, which comprises the following steps: If and , and , and , or and , then control the FIFO register without delay; if and , and , and , or and , then control the write of the FIFO register data to be delayed by 1 clock cycle; If and , and , and or and , then control the write of the FIFO register data to be delayed by 2 clock cycles. If and , and , and , or and , then control the write of the FIFO register data to be delayed by 3 clock cycles.

7. A multi-stage cascaded sequence enhanced dual-band signal transmission system, characterized in that, The method comprises the following steps: an information acquisition module, configured to obtain an original signal to be transmitted and a key initial value; a chaotic sequence generation module, configured to generate a two-dimensional chaotic sequence X and a two-dimensional chaotic sequence Y by a cross chaotic system through the key initial value and control the parameters of the cross chaotic system through a closed-loop adjustment mechanism based on the difference of Lyapunov exponents; a symbol domain encryption module, configured to perform symbol domain masking on the original signal by using the two-dimensional chaotic sequence X to obtain a symbol domain encrypted signal; a signal mapping module, configured to perform serial-parallel conversion and PAM4 mapping on the symbol domain encrypted signal to obtain a mapped signal; and The time domain encryption module is configured to: input the mapping signal into a FIFO register to perform time domain masking to obtain a time domain encrypted signal; and control clock delay of the FIFO register by a two-dimensional chaotic sequence Y. The signal transmission module is configured to: perform signal transmission on the time domain encrypted signal. The parameter of the cross chaotic system is controlled by a closed-loop adjustment mechanism based on Lyapunov exponent difference, including: The cross chaotic system of floating-point numbers is obtained. The cross chaotic system of floating-point numbers is simulated by hardware fixed-point on an FPGA hardware platform to obtain a cross chaotic system of fixed-point numbers. The floating-point Lyapunov exponent is calculated according to the cross chaotic system of floating-point numbers, and the fixed-point Lyapunov exponent is calculated according to the cross chaotic system of fixed-point numbers. The floating-point Lyapunov exponent and the fixed-point Lyapunov exponent are compared by an adaptive rule function, and the parameter of the cross chaotic system is controlled according to the comparison result. The parameter of the cross chaotic system is controlled according to the comparison result, including: If the floating-point Lyapunov exponent is greater than the fixed-point Lyapunov exponent, the Sine chaotic parameter of the cross chaotic system is increased, and the formula is: ； If the floating-point Lyapunov exponent is less than the fixed-point Lyapunov exponent, the Sine chaotic parameter of the cross chaotic system is decreased, and the formula is: ； If the floating-point Lyapunov exponent is equal to the fixed-point Lyapunov exponent, the parameter of the cross chaotic system is unchanged. wherein, , respectively represent the Sine chaotic parameters of the cross chaotic system of the i-th iteration, the (i+1)-th iteration; respectively represent the Sine chaotic parameters of the cross chaotic system of the i-th iteration, the (i+1)-th iteration; represents the adjustment step; , respectively represent the maximum value, the minimum value of the Sine chaotic parameters of the cross chaotic system; , respectively represent taking the maximum, taking the minimum.​ 8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the multi-cascaded sequence enhanced double-domain signal transmission method of any one of claims 1 to 6.

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