Fault-tolerant method, system and LED driving chip circuit of a cascade system

Abstract

The application discloses a kind of fault-tolerant method, system and LED drive chip circuit of hierarchical system, comprising the following steps: in each node device: A.powers on initialization step: control the bypass switch between the data input port and the data output port of the node device is in the default on state;B.distributed self-checking step: generate internal test signal, and at least one core function module of the node device is self-checked based on internal test signal, and produce self-checking result;C.intelligent judgment step: if self-checking result indicates that all detected core function modules are normal, then generate control signal to control bypass switch to off state;If self-checking result indicates that any detected core function module is abnormal, then keep bypass switch on state;By this means, abnormal node device is automatically bypassed, does not affect the normal communication and work of subsequent node device, significantly improves the reliability and fault-tolerant capability of hierarchical system.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a fault-tolerant method and system for cascaded systems, as well as a breakpoint resume circuit specifically applied to LED driver chips. Background Technology

[0002] In LED application systems, cascading, compared to matrix cascading, drives LEDs through a chip-to-chip series connection. When increasing the number of LEDs, only the number of driver chip stages needs to be increased, without redesigning complex row and column crossover circuits. Matrix cascading, on the other hand, requires adding both row and column driver chips simultaneously, and the number increases quadratically with the number of LEDs, limiting scalability. Furthermore, each chip in a cascaded drive only needs to handle the current and voltage control of its own LED stage, resulting in simple control logic and no need to coordinate the timing of row and column signals. Matrix cascading, however, requires precise synchronization of row and column driver signals to avoid "cross-lighting," leading to more complex circuit designs (such as scanning timing and anti-ghosting circuits), especially with a large number of LEDs. Moreover, when the number of LEDs is large (such as outdoor large screens or long strip lights), cascading requires fewer driver chips and eliminates the need for additional row and column control chips or logic circuits, significantly reducing hardware costs. Matrix cascading has a cost advantage in small-batch LED production (such as small-sized displays), but costs rise rapidly as production scales up.

[0003] In cascaded applications, such as keyboard backlighting, whether for enhancing the immersive experience of gaming keyboards or improving usability in low-light environments for office keyboards, multiple LED driver chips are typically connected in a cascaded manner to achieve multi-key backlight control. However, with current technology, if the internal logic unit or driver unit of one of the driver chips in the keyboard backlight fails due to prolonged high-frequency use, current surges, or other reasons, resulting in functional failure, it often causes the entire backlight of the keyboard following the key controlled by the faulty chip to go out, severely impacting the keyboard's user experience and visual appeal. Furthermore, troubleshooting often requires disassembling the keyboard to inspect the internal functions of each chip individually. For precision mechanical keyboards or ultra-thin keyboards, the repair process is extremely cumbersome, potentially damaging the keyboard structure and increasing maintenance costs.

[0004] In summary, there is an urgent need in the market for a technical solution that can maintain communication stability and ensure the normal operation of subsequent LED driver chips when internal logic units or driver units are damaged or fail during LED driver chip cascading.

[0005] In addition, similar situations exist in other electronic system designs: when the internal logic unit or drive unit of a node device in a cascaded link is damaged due to long-term high-frequency use, current surges, or other reasons, resulting in functional failure, the communication link from the faulty node to the subsequent nodes will often be interrupted, causing all subsequent node devices to malfunction.

[0006] Therefore, there is an urgent need in this field for a fault-tolerant technology solution that can automatically isolate faulty nodes in a cascaded system and ensure that the communication link is not interrupted. Summary of the Invention

[0007] The present invention aims to solve the technical problem that communication of the entire subsequent system is interrupted due to a single point of failure in the cascaded system in the prior art.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] A fault-tolerant method for a cascaded system, the cascaded system including a main controller and multiple cascaded node devices, the method comprising the following steps: Within each node device: A. Power-on initialization step: controlling a bypass switch located between the data input port and data output port of the node device to be in a default on state; B. Distributed self-test step: generating an internal test signal and performing a self-test on at least one core functional module of the node device based on the internal test signal, generating a self-test result; the core functional module includes a data path processing module; C. Intelligent judgment step: if the self-test result indicates that all tested core functional modules are normal, then generating a control signal to control the bypass switch to an off state, allowing data to be transmitted via the internal data processing path of the node device; if the self-test result indicates that any tested core functional module of any node device is abnormal, then maintaining the bypass switch of that node device in the on state, allowing data to bypass the internal data processing path of that node device and be transmitted directly between the data input port and data output port via the bypass switch; thereby, abnormal node devices are automatically bypassed, without affecting the normal communication and operation of subsequent node devices.

[0010] In some embodiments, at least one of the following technical means is also included:

[0011] The internal test signal is a periodic digital square wave signal; the self-test of the data path processing module of this node device based on the internal test signal specifically includes: sampling the internal test signal using a sampling clock signal; if the expected logic level can be successfully sampled in multiple consecutive sampling periods, the data path processing module is determined to be normal.

[0012] The rising edge of the sampling clock signal is set at the midpoint of the effective level duration of the internal test signal.

[0013] The period of the internal test signal (DIN_Check) is a first predetermined value, and the duty cycle is 50%; the period of the sampling clock signal (SAMP_CLK) is the first predetermined value; the first predetermined value is obtained by dividing the system clock.

[0014] The core functional modules also include a clock module and a PWM generation module; the self-test results are characterized by multiple self-test flag signals (Self_Check<0:2>).

[0015] In the intelligent judgment step, "if the self-test result shows that all the tested core functional modules are normal" is specifically implemented through a combinational logic circuit. This combinational logic circuit receives the multiple self-test flag signals and outputs the control signal that enables the self-test when all self-test flag signals are at a high level indicating normality.

[0016] The bypass switch is driven by a pair of complementary control signals (SN, SP).

[0017] The node device is an LED driver chip.

[0018] The present invention also adopts the following technical solutions:

[0019] A fault-tolerant system for a cascaded system is applied to a cascaded system including a main controller and multiple cascaded node devices. Each node device includes: a bypass switch, located between the data input port (DIN) and the data output port (DOUT) of the node device, which is in a default on state during power-on initialization; a self-test data generation module, configured to generate an internal test signal; and a self-test execution and judgment module, configured to perform a self-test on at least one core functional module of the node device based on the internal test signal to generate a self-test result, wherein the core functional module includes a data path processing module. The self-test execution and judgment module is further configured to: if the self-test result indicates that all tested core functional modules are normal, generate a control signal to control the bypass switch to the off state; if the self-test result indicates that any tested core functional module of any node device is abnormal, maintain the bypass switch of that node device in the on state. Thus, abnormal node devices are automatically bypassed, without affecting the normal communication and operation of subsequent node devices.

[0020] Furthermore,

[0021] The self-test execution and judgment module includes: a sampling signal generation unit configured to generate a sampling clock signal (SAMP_CLK); a sampling logic unit containing a D flip-flop, whose data terminal receives the internal test signal and whose clock terminal receives the sampling clock signal; the output level of the D flip-flop is used to determine whether the data path processing module is normal.

[0022] Furthermore,

[0023] The rising edge of the sampling clock signal is set at the midpoint of the effective level duration of the internal test signal.

[0024] Furthermore,

[0025] The core functional module also includes a PWM generation module; the self-test execution and judgment module also includes a PWM detection logic unit, configured to determine whether the PWM generation module is normal by detecting whether it has a valid PWM waveform output, and output a corresponding self-test flag signal (Self_Check). <2> ).

[0026] Furthermore,

[0027] The self-test execution and judgment module includes combinational logic circuits for receiving multiple self-test flag signals that respectively represent the state of different core functional modules, and outputting the control signal when all self-test flag signals are at a high level indicating normal operation.

[0028] Furthermore,

[0029] The node device is an LED driver chip.

[0030] The present invention also adopts the following technical solutions:

[0031] A breakpoint resume circuit for an LED driver chip, integrated within the chip, includes: a controllable bypass switch connected between the chip's data input pin (DIN) and data output pin (DOUT); a self-test data generation circuit driven by the system clock to generate a periodic internal self-test signal (DIN_Check); a sampling signal generation circuit driven by the system clock to generate a sampling clock signal (SAMP_CLK) with the same frequency as the internal self-test signal and its rising edge located at the midpoint of the high level of the internal self-test signal; a sampling circuit comprising a D flip-flop, whose data input receives the internal self-test signal, whose clock input receives the sampling clock signal, and whose output generates a data path self-test flag signal; and a control logic circuit configured to receive the data path self-test flag signal. When the data path self-test flag signal is active, the control logic circuit outputs a control signal to turn off the bypass switch; when the data path self-test flag signal is inactive, the control logic circuit outputs a control signal to keep the bypass switch active.

[0032] Furthermore,

[0033] The self-test data generation circuit includes a frequency divider for dividing the system clock to generate the periodic internal self-test signal (DIN_Check).

[0034] Furthermore,

[0035] The sampling signal generation circuit includes a counter for counting system clock cycles and generating a pulse of the sampling clock signal (SAMP_CLK) when a predetermined value is reached.

[0036] Furthermore,

[0037] The circuit also includes a PWM detection circuit for detecting whether the internal PWM function of the chip is normal and generating a PWM self-check flag signal (Self_Check). <2> The control logic circuit also receives the PWM self-test flag signal, and only outputs a control signal to turn off the bypass switch when both the data path self-test flag signal and the PWM self-test flag signal are at a valid level.

[0038] Furthermore,

[0039] The control logic circuit includes multiple logic gates for performing a logical AND operation on the data path self-test flag signal and the PWM self-test flag signal.

[0040] Furthermore,

[0041] The controllable bypass switch is an analog switch driven by a pair of complementary control signals (SN, SP).

[0042] Compared with existing technologies, the beneficial effects of this invention are as follows: The technical solution provided by this invention can determine the status of node devices through distributed self-testing when they are powered on, and automatically control the data path, bypassing the device when it malfunctions, thereby ensuring the continuity of cascaded communication. By integrating power-on self-testing and intelligent judgment logic into each node device and setting a controlled bypass switch, each node device has the ability to self-diagnose and autonomously isolate itself. When a single node device experiences an internal functional failure, this solution can automatically and quickly bypass the faulty node from the data path, making it only act as a conductor, thereby ensuring the continuity of the cascaded communication link, avoiding systemic interruptions caused by single-point failures, and greatly improving the reliability and fault tolerance of the cascaded system. This top-level beneficial effect is achieved through the synergistic effect of various technical features: distributed self-testing ensures the timeliness and accuracy of fault identification; intelligent judgment based on self-test results automates isolation operations; and bypass switches provide physical path switching guarantees. Therefore, this invention significantly improves the reliability and fault tolerance of the cascaded system.

[0043] Furthermore, by using a periodic square wave as the internal test signal and sampling at its midpoint, a stable and reliable detection mechanism is provided, improving the accuracy of self-testing and its anti-interference capability.

[0044] Furthermore, by adding detection of core functions such as the PWM module and adopting combinational logic for comprehensive judgment, a more comprehensive health status assessment system has been formed, which further reduces the probability of misjudgment and missed judgment and improves the overall reliability of the fault-tolerant system.

[0045] Furthermore, by specifically applying the aforementioned method, system, and circuit to LED driver chips, a highly reliable solution is provided for LED cascade applications, effectively solving the problem of partial light outages caused by driver chip failures in applications such as LED displays and light strips. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the core architecture of the cascaded system and the internal structure of a single-node device in one embodiment of the present invention.

[0047] Figure 2 This is a circuit diagram of a logic circuit for generating self-test data in one embodiment of the present invention.

[0048] Figure 3 This is a circuit diagram of the sampling signal generation logic circuit in one embodiment of the present invention.

[0049] Figure 4This is a timing diagram of the self-test signal and the sampling signal in one embodiment of the present invention.

[0050] Figure 5 This is a global schematic diagram of the sampling logic circuit in one embodiment of the present invention.

[0051] Figure 6 This is a partial detailed circuit diagram of the sampling logic circuit in one embodiment of the present invention.

[0052] Figure 7 This is a timing diagram of the sampling logic output signal in one embodiment of the present invention.

[0053] Figure 8 This is a circuit diagram of a PWM detection logic circuit in one embodiment of the present invention.

[0054] Figure 9 This is a timing diagram of the PWM detection logic output signal in one embodiment of the present invention.

[0055] Figure 10 This is a circuit diagram of the bypass switch control logic in one embodiment of the present invention.

[0056] Figure 11 This is a timing diagram of the bypass switch control signal in one embodiment of the present invention.

[0057] Figure 12 This is a schematic diagram of an application scenario where 200 chips are cascaded in one embodiment of the present invention.

[0058] Figure 13 This is a schematic diagram illustrating the working principle of the system power-on self-test process in one embodiment of the present invention.

[0059] Figure 14 This is a schematic diagram illustrating the working principle of a fault-tolerant isolation fault node in a system according to an embodiment of the present invention.

[0060] Figure 15 This is a schematic diagram of a cascaded structure of multiple LED driver chips (ICs) in one embodiment of the present invention.

[0061] Figure 16 This is a schematic diagram of the internal functional modules of a typical chip in one embodiment of the present invention. Detailed Implementation

[0062] The embodiments of the present invention will be described in detail below. It should be emphasized that the following description is merely exemplary and not intended to limit the scope and application of the present invention.

[0063] It should be noted that when a component is referred to as "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as "connected to" another component, it can be directly connected to or indirectly connected to that other component. Furthermore, a connection can be used for both fixing and circuit / signal connectivity.

[0064] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of the present invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0066] The basic concept of this invention is as follows:

[0067] A cascaded breakpoint resume circuit for LED driver chips features an internal bypass switch that is closed by default upon power-up. Each chip performs a self-test, verifying its various digital functional modules. If the chip's logic function is normal, it controls the bypass switch to open, allowing normal data input and output. If a failure occurs, the bypass switch remains closed, and the current chip acts as a lead in subsequent operations. This effectively prevents the inability of subsequent chips to function due to the failure of a single cascaded chip.

[0068] Example 1:

[0069] A cascaded LED driver chip breakpoint resume circuit,

[0070] like Figure 15 The illustrated chip cascade link shows the cascaded structure of multiple LED driver chips (ICs), illustrating the signal transmission path from front to back. For example... Figure 16The internal structure of a single chip is shown: It depicts the internal functional modules of a typical chip, including: Data input pin (DIN): receives serial data from the preceding chip or controller; Data output pin (DOUT): sends processed data to the following chip; Bypass switch (S): a controllable switch located between DIN and DOUT, closed by default; Self-test and judgment module (A): responsible for self-testing and bypass switch control after the chip is powered on; Internal functional logic: includes digital functional modules such as clock, data processing, and PWM generation; Signal flow labeling: arrows clearly indicate the paths of normal data flow and bypass data flow.

[0071] Key circuit module logic description:

[0072] Self-test data generation logic

[0073] Appendix Figure 2 This is a detailed schematic diagram of the self-test data generation logic circuit in the "A Cascaded Breakpoint Resumption Circuit for LED Driver Chips" of the present invention. The core function of this circuit is to generate a specific, periodic digital test signal (DIN_Check) to verify the integrity of the internal data path during the chip's power-on self-test phase.

[0074] In the diagram, I50, I8, I74, I76, I172, and I71 are all inverters, which realize "input signal level inversion" (high → low, low → high), enhance signal driving capability, and avoid signal attenuation when transmitting in multi-stage circuits.

[0075] I11, I12, I70, I48, and I60 are all D flip-flops, synchronous sequential devices that latch the data at the D terminal to the Q terminal at the CK clock edge (rising / falling edge);

[0076] The diagram shows multiple cascaded DFFs forming a shift register, which is used to delay and sample the OSC_4M clock, providing a timing reference for subsequent device operation.

[0077] I49, I52, I75, and I73 are NAND gates, used for logical operations ("all 1s output 0, any 0 outputs 1").

[0078] Driven by a 4MHz clock, Check_RNB generates a reset every 1.5µs, and then after frequency division, generates a DIN_Check signal with a period of 3µs and a duty cycle of 50%.

[0079] Sampling signal generation logic,

[0080] Appendix Figure 3This is a detailed schematic diagram of the sampling signal generation logic circuit in the "A Cascaded Breakpoint Resumption Circuit for LED Driver Chips" of the present invention. The core function of this circuit is to generate a precise sampling clock signal (SAMP_CLK), whose frequency and phase are carefully matched with the self-test signal (DIN_Check), which is used to reliably sample the DIN_Check signal during the chip's power-on self-test phase to verify the integrity of the data path.

[0081] In the diagram, X35, X34, X91, X90, and X88 are all inverters, which realize "input signal level inversion" (high → low, low → high), enhance signal driving capability, and avoid signal attenuation when transmitting in multi-stage circuits.

[0082] X37, X36, and X39 are all D flip-flops, synchronous sequential devices that latch the data at the D terminal to the Q terminal at the CK clock edge (rising / falling edge);

[0083] The diagram shows multiple cascaded DFFs forming a shift register, which is used to delay and sample the OSC_4M clock, providing a timing reference for subsequent device operation.

[0084] X89 is a NAND gate, used for logical operations ("all 1s output 0, 0s output 1").

[0085] By combining signals such as Self_Check_EN (self-test enable) and Check_RNB (self-test status), the control logic for the self-test function is generated.

[0086] Driven by the 4M clock OSC_4M, SAMP_CLK generates a rising edge every 3µs to sample the DIN_Check signal. The timing sequence of both is as follows: Figure 4 As shown:

[0087] Appendix Figure 4 This is a timing diagram of the self-test and sampling signals, and a waveform timing diagram of the two key signals DIN_Check and SAMP_CLK.

[0088] Waveform DIN_Check: Displayed as a square wave with a period of 3µs (1.5µs high, 1.5µs low). Waveform SAMP_CLK: Displayed as a narrow pulse signal with a period of 3µs, whose rising edge occurs precisely at the midpoint of the period when the DIN_Check signal is high.

[0089] The timing diagram visually illustrates the correct relationship between the sampling time (rising edge of SAMP_CLK) and the data to be sampled (DIN_Check is high level '1'), ensuring that the sampling logic can stably capture the expected '1' code.

[0090] Sampling logic,

[0091] Sampling logic global and local, such as Figure 5 and Figure 6 As shown:

[0092] Figure 5 This is a global schematic diagram of the sampling logic circuit in the "A Cascaded Breakpoint Resumption Circuit for an LED Driver Chip" of the present invention. It shows the overall architecture of the core sampling circuit used to verify whether the data path function is normal during the chip power-on self-test phase.

[0093] Appendix Figure 5 Detailed textual descriptions of each device, input, and output signal: Appendix Figure 5 It is a digital logic circuit diagram, which mainly includes the following core components:

[0094] 1. D flip-flop: As the core component of the sampling circuit, it is responsible for latching data at the clock edge.

[0095] 2. Input signal:

[0096] DIN_Check: Self-test signal, input to the data terminal (D) of the D flip-flop.

[0097] SAMP_CLK: Sampling clock signal, input to the clock terminal (CLK) of the D flip-flop.

[0098] 3. Output signal:

[0099] Net011 (or labeled Q): The output of the D flip-flop, i.e., the sampling result.

[0100] Appendix Figure 6 This is a partial detailed schematic diagram of the sampling logic circuit in the "A Cascaded Breakpoint Resumption Circuit for LED Driver Chips" of the present invention. It is related to the attached... Figure 5 The diagram further details the global sampling logic, specifically demonstrating the internal circuit structure and precise connection method of the D flip-flop used to perform the data sampling function. The core function of this circuit is to capture the level of the self-test signal under precise sampling clock control, providing direct evidence for determining whether the data path is functioning correctly.

[0101] Combination Figure 5 and Figure 6 The core function of the sampling logic here is to use a D flip-flop to capture the known and regular self-test signal (DIN_Check=DIN) under the precise control of the sampling clock (SAMP_CLK), and output the sampling result for use by the subsequent judgment logic.

[0102] The following is an appendix Figure 6Detailed explanation and description of each component, input, and output signal:

[0103] In the diagram, X169~X171 are all inverters, which realize "input signal level inversion" (high → low, low → high), enhance signal driving capability, and avoid signal attenuation when transmitting in multi-stage circuits.

[0104] X270, X271, X304 and Figure 5 The remaining devices are all D flip-flops, synchronous sequential devices, which latch the data at the D terminal to the Q terminal at the CK clock edge (rising edge);

[0105] The working sequence is as follows:

[0106] SAMP_CLK samples the 1 code sent by DIN_Check on the rising edge each time and obtains the corresponding data.

[0107] Appendix Figure 7 This is a schematic diagram of the sampling logic output in the "Cascaded Breakpoint Resumption Circuit of an LED Driver Chip" of the present invention. This diagram visually illustrates the sampling logic circuit (as shown in the attached diagram) during the chip's power-on self-test phase using waveform timing diagrams. Figure 5 and attached Figure 6 (As shown) This represents the ideal state of its output signal under continuous sampling clock conditions. The core purpose of this diagram is to verify that the sampling logic function is normal and can stably capture and output the expected self-test data.

[0108] Detailed interpretation and explanation:

[0109] D(1) is delayed by D(0), representing two bits of data here. This circuit samples data sequentially.

[0110] PWM detection logic,

[0111] Figure 8 This is a PWM detection logic circuit diagram of the present invention. This diagram shows the circuit used to detect whether the core function (PWM output) of the chip is normal.

[0112] PWM path detection:

[0113] The PWM output signal inside the chip passes through an inverter.

[0114] The inverted signal serves as the clock for another D flip-flop (I277).

[0115] The data terminal (D) of the flip-flop is connected to a fixed high level (VDD).

[0116] Reset control is performed in conjunction with POR_DELAY (power-on delay signal used to control the initial state).

[0117] Principle: If the chip logic is normal, a PWM waveform will be generated. The rising edge of the PWM (after inversion) will trigger the I277, which will capture and output the high level of its D terminal, thus proving that "PWM activity is present".

[0118] Self-test completion instruction:

[0119] The Self_Check_Off signal, after passing through an inverter, drives another D flip-flop (I211).

[0120] The output of this trigger ultimately generates the signal Self_Check. <2> .

[0121] Principle: When Self_Check <2> A transition from '0' to '1' indicates that the PWM detection module has confirmed that the chip's logic function is normal. Self_Check <2> It is one of the three key indicators that ultimately determine whether a chip is healthy.

[0122] The PWM signal, after passing through the inverter, serves as the clock for the I277 flip-flop. The D terminal of the I277 is connected to the power supply (usually high level), and together with POR_DELAY (power-on delay signal), it stores and outputs logic.

[0123] The other end-of-detection indicator signal, Self_Check_Off, is inverted and then drives flip-flop I211, ultimately generating Self_Check. <2> When it jumps from 0 to 1, it means there is PWM output, which means the chip's logic function is normal.

[0124] Appendix Figure 9 This is a schematic diagram of the PWM detection logic output in the "A Cascaded Breakpoint Resumption Circuit for an LED Driver Chip" of the present invention. This diagram visually illustrates the PWM detection logic circuit (as shown in the attached diagram) during the chip's power-on self-test phase using waveform timing diagrams. Figure 8 (As shown) After successfully detecting internal PWM activity, its key output signal Self_Check... <2> The state changes. The core purpose of this diagram is to verify that the PWM detection logic function is normal and to clearly mark the moment when the chip's core logic function (PWM generation) passes the self-test.

[0125] The Self_Check_OFF signal in the diagram is the self-test end flag. When the Self_Check_OFF signal is set from 1 to 0, it means that the self-test process has ended.

[0126] Bypass switch,

[0127] The bypass switch adopts an analog switch design with low on-resistance and low parasitic capacitance, and an output buffer is set before the data output port (DOUT) to ensure that the signal can be reshaped and has sufficient driving capability to be transmitted to the next level node in bypass state, avoiding signal attenuation and distortion.

[0128] Appendix Figure 10 This is the core circuit diagram of the bypass switch control logic in the "A Cascaded Breakpoint Resumption Circuit for LED Driver Chips" of this invention. This circuit is responsible for integrating the results of all self-test modules and generating the final control signal to drive the bypass switch (DataSwitch), determining whether the data enters the chip for processing or is directly bypassed.

[0129] Detailed descriptions of each device, input, and output signal in the attached diagram:

[0130] I. Overall Layout and Composition of the Attached Drawings

[0131] Appendix Figure 10 It can be divided into three functional areas:

[0132] 1. Left side: Self-test signal combinational logic processing area

[0133] Receive three self-check flag signals (Self_Check) <0> , <1> , <2> The system uses combinational logic to determine whether all self-test items have passed.

[0134] 2. Middle: Reset and control signal shaping area

[0135] It receives the power-on reset signal (PORB), shapes and latches the combinational logic output, and generates stable control signals (SN / SP).

[0136] 3. Right side: Data switching and output shaping area

[0137] The data path (internal processing data or direct DIN) is selected based on the control signal, and the output is shaped and sent to DOUT.

[0138] II. Detailed Device and Signal Descriptions

[0139] 1. Left side: Combinational logic processing of self-test signals

[0140] Input signal: Self_Check <0> , <1> , <2>

[0141] Function: These three signals represent the self-test results of different functional modules:

[0142] Self_Check <0> This indicates that the self-check has begun.

[0143] Self_Check <1> : Represents the self-test results of the data sampling module (from the appendix) Figure 5 / 6 of Net011).

[0144] Self_Check <2> : Represents the PWM module self-test result (from the appendix) Figure 8 / 9).

[0145] Logical requirement: The chip is considered to be functioning normally only when all three are high ('1').

[0146] Logic gate structure:

[0147] Three two-input NAND gates (NAND2):

[0148] Each NAND2 gate receives two identical Self_Check signals (e.g., Self_Check). <0> (Simultaneously input two NAND2 gates).

[0149] The intermediate output signal is determined by the following logic: NAND2_output = !(Self_Check <x>& Self_Check <x>).

[0150] A three-input NOR3 gate:

[0151] It receives the outputs of three NAND2 gates.

[0152] The final output logic is: NOR3_output = !(NAND2_out0 | NAND2_out1 | NAND2_out2).

[0153] Meaning: Only when all Self_Check signals are '1' will the three NAND2 outputs be '0' and the NOR3 output be '1' (indicating that the self-test has passed).

[0154] 2. Intermediate: Reset and control signal shaping

[0155] Input signal: PORB (Power On Reset Bar)

[0156] Function: A low-level active power-on reset signal to ensure that the system is in a defined state during the initial power-on phase (bypass switch is closed by default).

[0157] Logic devices:

[0158] Inverters (I3, I5, I6, I7, etc.): Invert and buffer signals to adjust their level and timing.

[0159] NAND gates (I1, I2): form a feedback latch structure, which works with PORB to ensure that the control signal (such as net019) is stable and glitch-free.

[0160] Output control signals: SN and SP

[0161] SN (Switch Negative): The negative control signal for the data switch.

[0162] SP (Switch Positive): The positive control signal for the transmission gate.

[0163] Function: SN / SP is a pair of complementary signals used to control the on and off states of the DataSwitch on the right side.

[0164] Key internal node: net019

[0165] Source: Signal from combinational logic (NOR3 output) and after shaping.

[0166] Function: It is the core enable signal for controlling the bypass switch (DataSwitch I0).

[0167] net019 = 1: Bypass switch I0 is on (data is passed through).

[0168] net019 = 0: Bypass switch I0 is turned off, and the internal processing path is turned on.

[0169] 3. Right side: Data switching and output shaping

[0170] DataSwitch Module (Analog Switch / Transmission Gate):

[0171] I0 (Bypass Switch): Closed by default, direct to DIN signal.

[0172] I20 (Internal Processing Path Switch): Open by default, closed after self-test passes.

[0173] Control signal: driven by SN / SP, which determines which switch is turned on.

[0174] Two input signals:

[0175] Straight-through DIN signal: comes from the chip's DIN pin and is transmitted directly through I0 without any processing.

[0176] Internally processed data: signals from the chip's internal data processing logic (such as clock, PWM, etc.) are transmitted via I20.

[0177] Output shaping circuit:

[0178] NAND2 gate (I36): Receives the switched data signal and Self_Check. <0> / <1> (Used for auxiliary level control).

[0179] Inverter (I38): Buffers and shapes the output signal to improve driving capability.

[0180] MOSFETs (mp5 / mn5): form the output stage, assisting in level conversion and noise suppression.

[0181] Final output: DOUT: Sends to the DIN pin of the subsequent chip.

[0182] III. Circuit Working Process

[0183] Initial power-on phase:

[0184] When PORB is low, the intermediate logic is reset, ensuring that net019=1, and SN / SP control I0 is turned on (bypass mode).

[0185] All Self_Check signals are '0', and the combinational logic output is '0' (self-test not completed).

[0186] Self-check in progress:

[0187] The three Self_Check signals change to '1' in sequence (indicating that the clock, data sampling, and PWM functions are normal).

[0188] When all three are '1', the NOR3 output becomes '1', and after shaping, net019 jumps from '1' to '0'.

[0189] After self-check passes:

[0190] net019=0 causes a change in SN / SP, closing I0 (bypass disconnection) and opening I20 (internal path opening).

[0191] Data is processed through internal channels, shaped by I20, I36, I38, etc., and then output to DOUT.

[0192] Self-check failed:

[0193] When any Self_Check signal is '0', NOR3 output is '0', and net019 remains '1'.

[0194] I0 remains on, and data flows directly from DIN to DOUT, with the chip acting as a conductor.

[0195] Combinational logic processing of self-test signals (left side)

[0196] Self_Check <0> Self_Check <1> Self_Check <2> Input the signal into three NAND2 gates respectively, perform NAND operations, and generate an intermediate signal.

[0197] The outputs of the three NAND2 gates then enter the NOR3 gate for NOR operation, further integrating the self-test logic and providing a basis for subsequent control.

[0198] Reset and control signal shaping (intermediate)

[0199] The PORB (Power-On Reset Signal) is inverted and then interacts with the feedback logic consisting of two other NAND2 gates (I1, I2) to adjust the signal timing / level.

[0200] The inverters (I3, I5, I6, etc.) further shape the signal to generate the control signals required by DataSwitch (such as strobe signals SN / SP).

[0201] Data switching and output shaping (right side)

[0202] The DataSwitch module selects the DIN transmission path based on the intermediate control signal (determining which data path is selected for output), such as... Figure 10 As shown in the updated full chip module diagram in the summary section, the two paths are DOUT_D from the digital logic and DIN from the data port DIN.

[0203] The switched signal combined with Self_Check <0> / <1> After being regulated by an inverter and a MOSFET (mp5 / mn5, auxiliary level control), and then shaped by NAND2 (I36) and an inverter (I38), the final output is DOUT.

[0204] In summary, after power-on, DataSwitch (I0) closes. When the self-test is completed and there are no problems, DataSwitch (I0) opens and DataSwitch (I20) closes.

[0205] Figure 11 This is the timing diagram of the bypass switch control of the present invention, and the waveform timing diagram of the key control signal net019.

[0206] The signal net019 is the enable signal for controlling the DataSwitch (I0) (bypass switch).

[0207] Waveform Changes: As shown in the figure, as the self-test progresses, when the three self-test flags Self_Check... <0> , <1> , <2> After all the signals sequentially changed to high level ('1'), the net019 signal underwent a transition from high level ('1') to low level ('0').

[0208] Action result: When net019 is 1: Bypass switch I0 is turned on (closed), and data is passed directly.

[0209] When net019 changes to 0: Bypass switch I0 is turned off (disconnected). At the same time, another switch I20 (connected to the internal data processing path) is turned on.

[0210] This diagram clearly shows how the success or failure of the self-test directly determines the final state of the bypass switch.

[0211] Where net019 is the enable signal for DataSwitch (I0), it can be seen that when Self_Check... <0> Self_Check <1> Self_Check <2> When all values ​​are set to 1, net019 jumps from 1 to 0, and DataSwitch (I20) is turned on.

[0212] 3. Explanation of Working Principle

[0213] Assuming 200 LED control ICs are cascaded for communication, Figure 12 This is a schematic diagram of 200 cascaded chips. Note: This diagram is... Figure 1 The specific application scenarios are expanded, and the content intuitively demonstrates the application scenario of large-scale cascading of 200 LED driver chips (IC1 to IC200), emphasizing that each chip has a built-in self-test circuit and bypass switch (S). This highlights the great value and economy of this patented technology in large-scale, long-link light strip or display applications.

[0214] After power-on, the bypass switch S is closed by default. Each chip performs a self-test, verifying each digital function module. When the chip's logic function is normal, the chip controls the bypass switch S to open, and DIN and DOUT can transmit and receive data normally. If a failure occurs, S remains closed, and the current chip acts as a wire in subsequent operations.

[0215] like Figure 13 As shown, all switches (S) are closed before operation. After power-on, the chip will perform a self-test. If the chip is not faulty, the data judgment module A will disconnect the switches, and the chip test is completed.

[0216] Figure 13 and Figure 14 These two diagrams, which illustrate the working principles of the system under normal operation and fault tolerance, vividly demonstrate the system's workflow in different states through comparison.

[0217] Figure 13 It is the power-on self-test process.

[0218] Initial state: All chips are powered on, and the internal bypass switches S are all closed by default.

[0219] Self-test process: Each chip begins to perform internal self-tests in parallel (checking clock, data path, PWM, etc.).

[0220] Self-test passed: For chips that are functioning normally (as shown in IC1, IC3...ICn in the figure), their data judgment module A (i.e. Figure 10 The control logic generates a signal to disconnect its own bypass switch S.

[0221] Final state: After the self-test is completed, the bypass switch of the normal chip is turned off, and the data is transmitted and processed through its internal logic.

[0222] Figure 14 It is a single-point-of-failure fault-tolerant process.

[0223] Fault exists: Assume that the second chip (IC2) in the cascaded system has failed internally.

[0224] Self-test result: IC2 failed the self-test, therefore its control module A could not generate a disconnect signal.

[0225] Switch status: The bypass switch S of IC2 remains closed.

[0226] Signal flow: After the data is output from the DOUT of the first chip (IC1), it no longer enters the internal logic of the failed chip IC2. Instead, it is directly transmitted to the DOUT of IC2 through its closed bypass switch, and then sent to the DIN of the third chip (IC3).

[0227] Final result: IC2 is transparently bypassed, acting like a "wire," allowing all subsequent chips (IC3 to ICn) to receive complete data signals and function normally. Only the LED controlled by the faulty chip fails to light up, achieving "breakpoint resumption."

[0228] If the chip fails, A cannot disconnect S, and data will be transmitted from DIN to DOUT.

[0229] like Figure 14 As shown, after the test is completed, the second chip fails. Closing switch S does not affect data transmission, and the remaining chips can still send and receive data.

[0230] The implementation of this embodiment achieves the following technical effects:

[0231] This LED driver chip cascade breakpoint resume circuit provides a reliable signal transmission solution. When the internal logic unit or driver unit of a chip in the cascade system is damaged or fails, it can ensure that the signal continues to be transmitted to the subsequent chip, thereby maintaining the normal operation of most LEDs and improving the stability and reliability of the entire keyboard backlight system (excluding the case of physical short circuit between the chip power supply and ground pins or physical disconnection of the IO port input / output port).

[0232] Example 2:

[0233] The basic concept of this embodiment is as follows:

[0234] The core of this invention lies in endowing each node device in a cascaded system with self-testing and self-isolation capabilities. Specifically, when a node device is powered on, its internal bypass switch is turned on by default. Subsequently, the device automatically generates test signals and tests its own core functional modules (such as data paths, PWM modules, etc.). Only when all tested functions are normal will the device control the bypass switch to turn off, allowing data to enter internal processing; if any function is abnormal, the bypass switch remains on, and data directly passes through that node, thereby achieving "breakpoint resume".

[0235] A fault-tolerant method and system for a cascaded system includes a main controller and multiple node devices connected in sequence. Each node device is equipped with a data input port and a data output port.

[0236] After the main controller powers on, it should wait for a sufficient delay (T_delay) for all cascaded nodes to complete their internal self-tests before sending formal data to the cascaded links. The time T_delay is determined by the self-test time of the slowest node in the system and can be calculated during system design.

[0237] Each node device is equipped with a bypass switch. This bypass switch is physically connected between the data input port and the data output port of the node device. During power-on initialization, the bypass switch is controlled to be in a default on state. The bypass switch can be an analog switch (such as a transmission gate), whose on / off state is driven by a pair of complementary control signals (e.g., SN and SP).

[0238] Each node device also includes a self-test data generation module. This module generates an internal test signal. This internal test signal can be any known signal pattern that can be used for testing.

[0239] Each node device also includes a self-test execution and judgment module. This module is configured to perform a self-test on at least one core functional module of the node device based on the internal test signal, generating a self-test result. The core functional module includes at least a data path processing module. This module is further configured to perform intelligent judgment: if the self-test result indicates that all tested core functional modules are normal, a control signal is generated to control the bypass switch, changing it from its default on state to its off state. This action switches the data flow from the bypass path to the internal data processing path of the node device for transmission and processing. Conversely, if the self-test result indicates that any tested core functional module is abnormal, the self-test execution and judgment module maintains its output signal state, keeping the bypass switch in its initial on state. This action allows the data flow to bypass the internal data processing path of the node device and directly transmit between the data input port and the data output port via the bypass switch.

[0240] In this way, if any node device in the system experiences an internal functional malfunction, it can be automatically identified and bypassed before the data from the upper level is transmitted, thus not affecting the normal communication and operation of all subsequent node devices.

[0241] The specific defect addressed by this embodiment is the reliability issue of a cascaded system where communication of the entire subsequent link is interrupted due to the failure of the internal function of a single node device.

[0242] Technical solution details: as described above.

[0243] Component names, connection relationships, or spatial relationships:

[0244] Bypass switch: Electrically connected between the data input port (DIN) and the data output port (DOUT).

[0245] Self-test data generation module: Its output is connected to the input of the self-test execution and judgment module.

[0246] Self-test execution and judgment module: Its output terminal generates a control signal, which is connected to the control terminal of the bypass switch.

[0247] Core functional modules (such as the data path processing module): connected after the data input port (DIN), its output is processed data. Data flows through this module when the bypass switch is off.

[0248] Working principle: After the system powers on, the bypass switches of all node devices are turned on by default. Each node device starts its self-test process in parallel. The self-test data generation module generates a test signal. The self-test execution and judgment module uses this signal to detect internal functions. If the test passes, its own bypass switch is turned off, and data processing is initiated; if the test fails, the bypass remains on, and data is transmitted transparently. Ultimately, all normal nodes in the system participate in the operation, while abnormal nodes are isolated.

[0249] Dimensional parameters (units cannot be omitted): On-resistance <700Ω, Off-resistance >1000MΩ, Self-test completion time <20ms

[0250] Implementation steps (described in chronological order):

[0251] 1. System power-on procedure: Power on the main controller and all cascaded node devices.

[0252] 2. Initialization steps: The reset circuit (such as the POR circuit) inside each node device generates a reset signal to ensure that the bypass switch control logic is initialized and that the bypass switch is in the on state.

[0253] 3. Self-test signal generation steps: The self-test data generation module of each node device starts working and generates internal test signals.

[0254] 4. Functional self-test steps: The self-test execution and judgment module of each node device tests the functions of the data path processing module and other functions based on internal test signals, and generates self-test results.

[0255] 5. Status Judgment and Switch Control Steps: The self-test execution and judgment module of each node makes a judgment based on the self-test results. If normal, it outputs a control signal to turn off the bypass switch; if abnormal, there is no action, and the bypass switch remains on.

[0256] 6. Normal Communication Procedure: After the self-test phase, the main controller begins sending data. Data flows through each level of nodes; normal nodes process the data, while abnormal nodes transparently transmit data.

[0257] Experimental verification: To verify the effectiveness of this embodiment, a cascaded system containing 5 (e.g., 10) node devices was built for testing.

[0258] Test Project Example 2 (This Solution) Comparative Example 1 (Traditional Non-Tolerant Cascading) Improvement Notes When all nodes are functioning normally, the system functions normal normal Indifference System communication continuity after a single random node failure Keep Interruption This plan can maintain After a single random node fails, the functionality of subsequent nodes... normal Failure The subsequent nodes of this plan are normal. Example

[0259] The difference between this embodiment and Embodiment 2 is that the specific implementation of the self-test data generation module and the self-test execution and judgment module has been refined.

[0260] The internal test signal is specifically a periodic digital square wave signal. The self-test data generation module can be a frequency divider used to divide the system clock to generate the square wave signal.

[0261] The self-test of the data path processing module of this node device based on the internal test signal is specifically performed by the sampling logic unit in the self-test execution and judgment module. This unit includes a D flip-flop. The data terminal of the D flip-flop receives the internal test signal, and its clock terminal receives a sampling clock signal. The output level of the D flip-flop is used to determine whether the data path processing module is normal. The logic is as follows: if the output of the D flip-flop can successfully sample the expected logic level (e.g., high level '1') within three consecutive sampling periods, the data path processing module is determined to be normal. This embodiment can effectively filter out occasional timing jitter or noise interference.

[0262] Furthermore, the rising edge of the sampling clock signal is set at the midpoint of the duration of the effective level (e.g., high level) of the internal test signal. This setting minimizes the metastable region of the signal transition edge, improving sampling reliability.

[0263] Furthermore, the period of the internal test signal is a first predetermined value (its period can be a value in the range of 1μs to 10μs, for example, 3μs), and the duty cycle can be a value in the range of 40% to 60%, for example, 50%. The period of the sampling clock signal is also the first predetermined value (its period can be a value in the range of 1μs to 10μs, for example, 3μs). The first predetermined value is obtained by dividing the system clock (e.g., a 4MHz clock OSC_4M).

[0264] Component name and connection relationship:

[0265] Self-test data generation module (frequency divider): Input is connected to the system clock (OSC_4M), and output is the internal test signal (DIN_Check).

[0266] Sampling signal generation unit: The input is connected to the system clock (OSC_4M) or the frequency divider signal, and the output is the sampling clock signal (SAMP_CLK).

[0267] Sampling logic unit (D flip-flop): Data input (D) connected to DIN_Check, clock input (CLK) connected to SAMP_CLK, output (Q) generates a data path self-check flag signal (e.g., Self_Check). <1> ).

[0268] Example 4:

[0269] The difference between this embodiment and embodiments 2 or 3 is that the self-testing range is expanded and the judgment logic is refined.

[0270] The core functional modules also include a clock module and a PWM generation module. The self-test result is characterized by multiple self-test flag signals (e.g., Self_Check<0:2>). <0> This indicates that the clock module is functioning correctly; Self_Check <1> This indicates that the data path is normal (from Example 3), Self_Check <2> This indicates that the PWM generation module is functioning normally.

[0271] The self-test execution and judgment module also includes a PWM detection logic unit. This unit is configured to determine whether the PWM generation module is functioning correctly by detecting whether it outputs a valid PWM waveform, and outputs a corresponding self-test flag signal (Self_Check). <2> For example, a D flip-flop can be used, with its data terminal connected to a high level and its clock terminal connected to a PWM signal (or its inverted signal). PWM activity can be determined by detecting whether the flip-flop is triggered.

[0272] In the intelligent judgment step, the statement "if the self-test result shows that all tested core functional modules are normal" is specifically implemented through a combinational logic circuit. This combinational logic circuit receives the multiple self-test flag signals (Self_Check). <0> , <1> , <2> When all self-test flag signals are at a high level ('1') indicating normal operation, a high level (or low level) is output to enable the control signal. This combinational logic circuit can be a logical AND relationship composed of multiple logic gates (such as NAND gates and NOR gates).

[0273] Component name and connection relationship:

[0274] PWM detection logic unit: Input is connected to the output of the PWM generation module, and output is the PWM self-check flag signal (Self_Check). <2> ).

[0275] Combinational logic circuit: Input connected to Self_Check <0> , <1> , <2> The output is connected to the control signal generation logic.

[0276] Example 5:

[0277] This embodiment applies the methods and systems described in the foregoing embodiments to a specific node device—an LED driver chip. Essentially, it is a concrete implementation of a breakpoint resume circuit for an LED driver chip.

[0278] The node device is an LED driver chip. This chip integrates the breakpoint resume circuit. The controllable bypass switch is connected between the chip's data input pin (DIN) and data output pin (DOUT). The self-test data generation circuit is driven by the system clock (OSC_4M) and is used to generate periodic internal self-test signals (DIN_Check). The sampling signal generation circuit is driven by the system clock and is used to generate a sampling clock signal (SAMP_CLK). The sampling circuit includes a D flip-flop for generating a data path self-test flag signal. The control logic circuit is configured to receive the self-test flag signal and control the bypass switch. Its operating principle is consistent with the aforementioned embodiment.

[0279] Detailed technical solution: In addition to conventional cascaded communication interfaces, data decoding, PWM generation, and constant current driving modules, this LED driver chip also integrates the fault-tolerant circuit described in this invention. After power-on, the chip first performs a self-test. If the self-test passes, the internal bypass is disconnected, and data is normally received, processed, and forwarded to drive the LED; if the self-test fails, the bypass remains open, only forwarding data, and the LED driven by itself does not light up.

[0280] Experimental verification: An LED strip cascade system was constructed for testing.

[0281] Test Scenario This solution uses an LED driver chip. Traditional LED driver chips A chip failed Subsequent LEDs are working normally Subsequent LED failure Repair costs No need to replace immediately Need to be checked and replaced

[0282] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.< / x> < / x>

Claims

1. A fault-tolerant method for a hierarchical system, characterized by, The stage system comprises a main controller and a plurality of cascaded node devices, and the method comprises the following steps: in each node device: A. power-on initialization step: control the bypass switch arranged between the data input port and the data output port of the node device to be in the default on state; B. distributed self-checking step: generate a periodic internal test signal by a self-checking data generation circuit, and perform self-checking on at least one core function module of the node device based on the internal test signal through a sampling circuit to generate a self-checking result; the core function module comprises a data path processing module; step B specifically comprises: sampling the internal test signal by using a sampling clock signal; if the expected logic level can be successfully sampled in a plurality of continuous sampling periods, it is determined that the data path processing module is normal; C. intelligent judgment step: if the self-checking result indicates that all the detected core function modules are normal, a control signal is generated by a control logic circuit to control the bypass switch to be turned off, so that data is transmitted through the internal data processing path of the node device; if the self-checking result indicates that any core function module of the node device is abnormal, the bypass switch of the node device is kept in the on state, so that data bypasses the internal data processing path of the node device and is directly transmitted between the data input port and the data output port through the bypass switch; thereby, the abnormal node device is automatically bypassed, and only acts as a wire role, without affecting the normal communication and work of the subsequent node device.

2. The method of claim 1, wherein, The internal test signal is a periodic digital square wave signal.

3. The method of claim 2, wherein, The rising edge of the sampling clock signal is arranged at the midpoint of the valid level duration of the internal test signal.

4. The method of claim 2 or 3, wherein, The period of the internal test signal (DIN_Check) is a first predetermined value, and the duty cycle is 50%; the period of the sampling clock signal (SAMP_CLK) is the first predetermined value; the first predetermined value is obtained by frequency division of a system clock.

5. The method of claim 1, wherein, The core function module further comprises a clock module and a PWM generation module; and the self-checking result is represented by a plurality of self-checking flag signals (Self_Check<0:2>).

6. The method of claim 5, wherein, In the intelligent judgment step, "if the self-checking result indicates that all the detected core function modules are normal" is specifically realized by a combination logic circuit which receives the plurality of self-checking flag signals and outputs an enable signal of the control signal when all the self-checking flag signals are high level signals representing normality.

7. The method of claim 1, wherein, The bypass switch is driven by a pair of complementary control signals (SN, SP).

8. The method of claim 1, wherein, The node device is an LED driving chip.

9. A fault-tolerant system for a cascading system, applied to a cascading system including a master controller and a plurality of cascaded node devices, characterized by, Each node device comprises: a bypass switch arranged between the data input port (DIN) and the data output port (DOUT) of the node device, which is in the default on state during power-on initialization; a self-checking data generation module configured to generate a periodic internal test signal by a self-checking data generation circuit; The self-check execution and judgment module is configured to perform self-check on at least one core function module of the node device based on the internal test signal through a sampling circuit to generate a self-check result, and the core function module includes a data path processing module; the self-check execution and judgment module is further configured to: if the self-check result indicates that all the detected core function modules are normal, generate a control signal by a control logic circuit to control the bypass switch to turn off; and if the self-check result indicates that any of the detected core function modules of the node device is abnormal, keep the bypass switch of the node device in the on state; and the self-check execution and judgment module includes: a sampling signal generation unit configured to generate a sampling clock signal (SAMP CLK); a sampling logic unit including a D flip-flop, a data terminal of the D flip-flop receiving the internal test signal, and a clock terminal of the D flip-flop receiving the sampling clock signal; and an output terminal of the D flip-flop being used to determine whether the data path processing module is normal, In this way, the abnormal node device is automatically bypassed to only serve as a wire role, without affecting the normal communication and work of the subsequent node device.

10. The system of claim 9, wherein, The rising edge of the sampling clock signal is set at the midpoint of the valid level duration of the internal test signal.

11. The system of claim 9, wherein, The core function module further includes a PWM generation module; and the self-check execution and judgment module further includes a PWM detection logic unit configured to determine whether the PWM generation module is normal by detecting whether the PWM generation module has a valid PWM waveform output, and output a corresponding self-check flag signal (Self Check<2>).

12. The system of claim 9, wherein, The self-check execution and judgment module includes a combination logic circuit configured to receive a plurality of self-check flag signals respectively representing the states of different core function modules, and output the control signal when all the self-check flag signals are high levels representing normal.

13. The system of claim 9, wherein, The node device is an LED driving chip.

14. A break before make circuit for an LED driver chip, integrated within the chip, characterized by, The circuit includes: a controllable bypass switch connected between a data input pin (DIN) and a data output pin (DOUT) of the chip; a self-check data generation circuit driven by a system clock, configured to generate a periodic internal self-check test signal (DIN Check); a sampling signal generation circuit driven by the system clock, configured to generate a sampling clock signal (SAMP CLK) having the same frequency as the internal self-check test signal and a rising edge located at the midpoint of the high level of the internal self-check test signal; a sampling circuit including a D flip-flop, a data input terminal of the D flip-flop receiving the internal self-check test signal, and a clock input terminal of the D flip-flop receiving the sampling clock signal, and an output terminal of the D flip-flop being used to generate a data path self-check flag signal; a control logic circuit configured to receive the data path self-check flag signal; wherein when the data path self-check flag signal is a valid level, the control logic circuit outputs a control signal to turn off the controllable bypass switch; and when the data path self-check flag signal is an invalid level, the control logic circuit outputs a control signal to keep the controllable bypass switch on and only serve as a wire role.

15. The circuit of claim 14, wherein, The self-check data generation circuit includes a frequency divider for dividing the system clock to generate the periodic internal self-check test signal (DIN_Check).

16. The circuit of claim 14, wherein, The sampling signal generation circuit includes a counter for counting the system clock cycles and generating a pulse of the sampling clock signal (SAMP_CLK) when a predetermined value is reached.

17. The circuit of claim 14, wherein, The circuit further includes a PWM detection circuit for detecting whether the internal PWM function of the chip is normal and generating a PWM self-check flag signal (Self_Check<2>); the control logic circuit further receives the PWM self-check flag signal and only outputs a control signal to turn off the controllable bypass switch when both the data path self-check flag signal and the PWM self-check flag signal are at valid levels.

18. The circuit of claim 17, wherein, The control logic circuit includes a plurality of logic gates for performing a logical AND operation on the data path self-check flag signal and the PWM self-check flag signal.

19. The circuit of claim 14, wherein, The controllable bypass switch is an analog switch driven by a pair of complementary control signals (SN, SP).

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