Memory device with vertical transistor and method of forming same

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor. A respective one of the bit lines and a respective memory cell are coupled to opposite ends of each of the memory cells in a first direction. Two adjacent ones of the vertical transistors in the second direction are mirror-symmetric to each other. The memory cell array is coupled to the peripheral circuit through the bonding interface.

Description

DIVISION

[0001] This application is a divisional application of Chinese Patent Application No. 202180003343.1, filed on August 31, 2021, entitled “Memory Device with Vertical Transistors and Methods of Forming the Same,” which claims priority to U.S. Patent Application No. 17 / 987, 1 1, filed on August 31, 2021, entitled “Memory Device with Vertical Transistors and Methods of Forming the Same,” which claims priority to U.S. Provisional Patent Application No. 62 / 974, 1 1 1, filed on February 28, 2020, entitled “Memory Device with Vertical Transistors and Methods of Forming the Same,” the contents of which are incorporated by reference in their entirety. BACKGROUND

[0002] The present disclosure relates to memory devices and methods of manufacturing the same.

[0003] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing technology become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

[0004] Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells. 3D memory architectures include a memory array and a peripheral circuit to facilitate operation of the memory array. SUMMARY

[0005] In one aspect, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a memory cell array and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to a first direction. Each of the memory cells includes a vertical transistor extending in the first direction and a storage cell coupled to the vertical transistor. A respective one of the bit lines and the respective storage cell are coupled to opposite ends of each of the memory cells in the first direction. Two adjacent ones of the vertical transistors in the second direction are mirror-symmetric to each other. The memory cell array is coupled to the peripheral circuit through the bonding interface.

[0006] In another aspect, a memory system includes a memory device configured to store data and a memory controller coupled to the memory device. The memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to a first direction. Each of the memory cells includes a vertical transistor extending in the first direction and a storage cell coupled to the vertical transistor. A respective one of the bit lines and the respective storage cell are coupled to opposite ends of each of the memory cells in the first direction. Two adjacent ones of the vertical transistors in the second direction are mirror-symmetric to each other. The array of memory cells is coupled to the peripheral circuit through the bonding interface. The memory controller is configured to control the array of memory cells through the peripheral circuit and the bit lines.

[0007] In yet another aspect, a method for forming a 3D memory device is disclosed. A first semiconductor structure including a peripheral circuit is formed. A second semiconductor structure is formed. To form the second semiconductor structure, an array of memory cells is formed, and a plurality of bit lines coupled to the memory cells is formed. Each of the memory cells includes a vertical transistor extending in a first direction and a storage cell coupled to the vertical transistor. A respective one of the bit lines and the respective storage cell are coupled to opposite ends of each of the memory cells perpendicularly. Two adjacent ones of the vertical transistors in a second direction are mirror-symmetric to each other. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the array of memory cells is coupled to the peripheral circuit through a bonding interface. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the relevant art to make and use the present disclosure.

[0009] Figure 1A A schematic diagram showing a cross-section of a 3D memory device is shown in accordance with some aspects of the present disclosure.

[0010] Figure 1B A schematic diagram showing a cross-section of another 3D memory device is shown in accordance with some aspects of the present disclosure.

[0011] Figure 2 A schematic diagram of a memory device including a peripheral circuit and an array of memory cells each having a vertical transistor is shown in accordance with some aspects of the present disclosure.

[0012] Figure 3 A schematic circuit diagram of a memory device including peripheral circuitry and a dynamic random access memory (DRAM) cell array is shown in accordance with some aspects of the present disclosure.

[0013] Figure 4 A schematic circuit diagram of a memory device including peripheral circuitry and a phase change memory (PCM) cell array is shown in accordance with some aspects of the present disclosure.

[0014] Figure 5 A plan view of a memory cell array each including a vertical transistor in a memory device is shown in accordance with some aspects of the present disclosure.

[0015] Figure 6A A side view of a cross-section of a 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0016] Figure 6B A side view of a cross-section of another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0017] Figure 6C A side view of a cross-section of yet another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0018] Figure 6D A side view of a cross-section of still another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0019] Figure 6E A side view of a cross-section of still another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0020] Figure 7 A side view of a cross-section of still another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0021] Figure 8 A plan view of another memory cell array each including a vertical transistor in a memory device is shown in accordance with some aspects of the present disclosure.

[0022] Figure 9 A side view of a cross-section of still another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0023] Figures 10A-10M A fabrication process for forming a 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0024] Figures 11A-11I A manufacturing process for forming another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0025] Figures 12A-12H A manufacturing process for forming yet another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0026] Figures 13A-13H A manufacturing process for forming yet another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0027] Figures 14A-14E A manufacturing process for forming yet another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0028] Figures 15A-15D A manufacturing process for forming yet another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0029] Figure 16 A plan view of yet another memory cell array each including vertical transistors in a memory device is shown in accordance with some aspects of the present disclosure.

[0030] Figure 17 A side view of a cross-section of yet another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0031] Figure 18 A perspective view of an array of vertical transistors is shown in accordance with some aspects of the present disclosure.

[0032] Figures 19A-19M A manufacturing process for forming yet another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0033] Figure 20 A plan view of yet another memory cell array each including vertical transistors in a memory device is shown in accordance with some aspects of the present disclosure.

[0034] Figure 21 A side view of a cross-section of yet another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0035] Figures 22A-22M A manufacturing process for forming yet another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0036] Figure 23A flow diagram illustrating a method for forming a 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure.

[0037] Figure 24 A flow diagram illustrating a method for forming an array of memory cells each including a vertical transistor is shown in accordance with some aspects of the present disclosure.

[0038] Figure 25 A flow diagram illustrating a method for forming another array of memory cells each including a vertical transistor is shown in accordance with some aspects of the present disclosure.

[0039] Figure 26 A flow diagram illustrating a method for forming yet another array of memory cells each including a vertical transistor is shown in accordance with some aspects of the present disclosure.

[0040] Figure 27 A block diagram illustrating an exemplary system with a memory device is shown in accordance with some aspects of the present disclosure.

[0041] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0042] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the scope of the present disclosure. Furthermore, the present disclosure can also be used in various other applications. Thus, the features and structures described in this disclosure can be combined, adjusted, and modified in various ways, and can be applied in ways other than those specifically set out in the accompanying drawings, as would be understood by one of ordinary skill in the art. Accordingly, the present disclosure is not intended to be limited to the specific configurations and arrangements described herein, but is to be accorded the reasonably scope consistent with the principles and features described herein.

[0043] Generally, the terminology can be understood at least in part from usage of the terminology in the description throughout this document. For example, the term "one or more," as used herein, can be taken to describe any feature, structure, or characteristic in the singular or can be taken to describe a combination of features, structures or characteristics, in the plural, depending at least in part on the context in which such term is used. Similarly, terms, such as "a," "an," or "the," again, can be taken to convey a singular usage or a plural usage, depending at least in part on the context in which such terms are used. Additionally, the term "based on" can be understood as not necessarily requiring exclusively factual derivations and instead can allow for approximation, based at least in part on the context in which term is used.

[0044] It should be readily understood that the terms "on," "over," and "above" in the present disclosure should be interpreted in the broadest context possible so that "on" means not only "directly on" but also includes the meaning of "on" with intervening features or layers therebetween, and "over" or "above" means not only the meaning of "over" or "above" but also can include the meaning of "over" or "above" with no intervening features or layers therebetween (i.e., directly on).

[0045] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

[0046] As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. Such a substrate can itself be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0047] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have an extent less than the underlying or overlying structure. Further, a layer can be a region of a continuous structure that is homogeneous or non-homogeneous and has a thickness less than the thickness of the continuous structure. For example, a layer can be between any pair of horizontal planes that are between a top surface and a bottom surface of a continuous structure, or at the top and bottom surfaces of the continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect via contacts are formed) and one or more dielectric layers.

[0048] Transistors are used as switching or selection devices in memory cells of some memory devices (e.g., DRAM, PCM, and ferroelectric DRAM (FRAM)). However, the planar transistors commonly used in existing memory cells typically have a horizontal structure with a buried word line in the substrate and a bit line above the substrate. Because the source and drain of the planar transistor are laterally disposed at different locations, this increases the area occupied by the transistor. The design of the planar transistor also complicates the layout of the interconnect structures (e.g., word lines and bit lines) coupled to the memory cells, for example, limiting the pitch of the word lines and / or bit lines, thereby increasing manufacturing complexity and reducing product yield. Furthermore, because the bit line and the storage cell (e.g., a capacitor or PCM element) are disposed on the same side of the planar transistor (above the transistor and substrate), the bit line process margin is limited by the storage cell, and the coupling capacitance between the bit line and the storage cell (e.g., capacitor) is increased. Planar transistors can also suffer from high leakage current as the saturation drain current continues to increase, which is undesirable for the performance of the memory device.

[0049] On the other hand, the memory cell array and the peripheral circuitry for controlling the memory cell array are typically arranged side-by-side in the same plane. As the number of memory cells continues to increase, in order to maintain the same chip size, the size of the components (e.g., transistors, word lines, and / or bit lines) in the memory cell array needs to continue to decrease to avoid significantly reducing the efficiency of the memory cell array.

[0050] To address one or more of the problems described above, the present disclosure introduces a solution in which a vertical transistor replaces the conventional planar transistor as the switching and selection device in the memory cell array of a memory device (e.g., DRAM, PCM, and FRAM). Compared to the planar transistor, the vertically arranged transistor (i.e., the drain and source overlap in the plan view) can reduce the area of the transistor and simplify the layout of the interconnect structures, e.g., the metal routing word lines and bit lines, which can reduce manufacturing complexity and improve yield. For example, the pitch of the word lines and / or bit lines can be reduced for ease of manufacturing. The vertical structure of the transistor also allows the bit line and the storage cell (e.g., a capacitor) to be disposed on opposite sides of the transistor in the vertical direction (e.g., one above the transistor and one below the transistor), such that the process margin of the bit line can be increased and the coupling capacitance between the bit line and the storage cell can be reduced.

[0051] Consistent with the scope of the disclosure, according to some aspects of the disclosure, a memory cell array with vertical transistors and peripheral circuitry of a memory cell array can be formed on different wafers and bonded together in a face-to-face manner. Thus, the thermal budget of fabricating the memory cell array does not impact the fabrication of the peripheral circuitry. The stacked memory cell array and peripheral circuitry can also reduce chip size compared to side-by-side arrangements, thereby increasing array efficiency. In some implementations, more than one memory cell array is stacked on top of each other using bonding techniques to further increase array efficiency. In some implementations, due to the vertically arranged transistors, word lines and bit lines are disposed close to the bonding interface, which can be coupled to the peripheral circuitry through a large number (e.g., millions) of parallel bonding contacts through the bonding interface, direct, short distance (e.g., micron level) electrical connections can be made between the memory cell array and the peripheral circuitry to increase the throughput and input / output (I / O) speed of the memory device.

[0052] In some implementations, the vertically transistors disclosed herein include multi-gate transistors (e.g., gate-all-around (GAA) transistors, tri-gate transistors, or bi-gate transistors), which can have a larger gate control area to achieve better channel control with smaller subthreshold swing. The leakage current of multi-gate transistors can also be significantly reduced during the off state due to the complete depletion of the channel. Thus, using multi-gate transistors instead of planar transistors can achieve much better speed (saturated drain current) / leakage current performance.

[0053] In some implementations, due to the use of trench isolation extending in the word line direction to separate the multi-gate transistors (e.g., bi-gate transistors), the vertically transistors disclosed herein include single-gate transistors (also referred to as single-sided gate transistors) arranged in mirror symmetry with respect to adjacent transistors in the bit line direction. Thus, the memory cell density in the bit line direction can be significantly increased (e.g., doubled) without overcomplicating the fabrication process compared to using processes such as self-aligned double patterning (SADP), etc. In addition, the mirror-symmetric single-gate transistors have a larger process window for word line, bit line, and transistor pitch reduction compared to conventional planar transistors or multi-gate vertical transistors (e.g., with double-sided or gate-all-around).

[0054] Figure 1AA schematic cross-sectional view of a 3D memory device 100 according to some aspects of this disclosure is shown. The 3D memory device 100 represents an example of a bonded chip. Components of the 3D memory device 100 (e.g., memory cell array and peripheral circuitry) may be formed separately on different substrates and then bonded to form a bonded chip. The 3D memory device 100 may include a first semiconductor structure 102 including peripheral circuitry for the memory cell array. The 3D memory device 100 may also include a second semiconductor structure 104 including the memory cell array. The peripheral circuitry (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). According to some embodiments, the peripheral circuitry in the first semiconductor structure 102 utilizes complementary metal-oxide-semiconductor (CMOS) technology, for example, which may be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0055] like Figure 1A As shown, the 3D memory device 100 may further include a first semiconductor structure 104, which includes an array (memory cell array) of memory cells that can use transistors as switching and selection devices. In some embodiments, the memory cell array includes a DRAM cell array. For ease of description, a DRAM cell array may be used as an example for describing the memory cell array in this disclosure. However, it should be understood that the memory cell array is not limited to a DRAM cell array and may include any other suitable type of memory cell array that can use transistors as switching and selection devices, such as a PCM cell array, a static random-access memory (SRAM) cell array, an FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, to name just a few examples, or any combination thereof.

[0056] The second semiconductor structure 104 may be a DRAM device, wherein memory cells are provided in the form of an array of DRAM cells. In some embodiments, each DRAM cell includes a capacitor for storing data bits as positive or negative charge and one or more transistors (also called transfer transistors) for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor-capacitor (ITIC) cell. Since transistors always leak a small amount of charge, capacitors will discharge slowly, causing the information stored therein to be depleted. Thus, according to some embodiments, the DRAM cell must be refreshed, for example, by peripheral circuitry in the first semiconductor structure 102 to retain the data.

[0057] like Figure 1A As shown, the 3D memory device 100 also includes a portion perpendicularly positioned between the first semiconductor structure 102 and the second semiconductor structure 104 (in the vertical direction, for example, Figure 1A The bonding interface 106 (in the z-direction) is used. As described in detail below, the first semiconductor structure 102 and the second semiconductor structure 104 can be manufactured separately (and in some embodiments in parallel), such that the thermal budget for manufacturing one of the semiconductor structures 102 and 104 does not limit the process for manufacturing the other semiconductor structure. Furthermore, a large number of interconnects (e.g., bonding contacts) can be formed through the bonding interface 106 to provide direct, short-distance (e.g., micrometer-scale) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, instead of long-distance (e.g., millimeter- or centimeter-scale) chip-to-chip data buses on a circuit board (e.g., a printed circuit board, PCB), thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array in the second semiconductor structure 104 and the peripheral circuitry in the first semiconductor structure 102 can be performed via interconnects (e.g., bonding contacts) through the bonding interface 106. By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, the chip size can be reduced and the memory cell density can be increased.

[0058] It should be understood that the relative positions of the stacked first semiconductor structure 102 and the second semiconductor structure 104 are not restricted. Figure 1B A schematic cross-sectional view of another exemplary 3D memory device 101 according to some embodiments is shown. Figure 1AIn 3D memory device 100, second semiconductor structure 104 including a memory cell array is above first semiconductor structure 102 including peripheral circuitry. In 3D memory device 100, first semiconductor structure 102 and second semiconductor structure 104 are bonded together through bonding interface 106. In some embodiments, bonding interface 106 is a direct bonding interface (e.g., a direct metal-to-metal bonding interface). In some embodiments, bonding interface 106 is a hybrid bonding interface (e.g., a hybrid metal / dielectric bonding interface). In some embodiments, bonding interface 106 is a direct metal-to-metal bonding interface and a direct dielectric-to-dielectric bonding interface. In some embodiments, bonding interface 106 is a direct metal-to-metal bonding interface and a hybrid metal / dielectric bonding interface. In some embodiments, bonding interface 106 is a hybrid metal / dielectric bonding interface and a direct dielectric-to-dielectric bonding interface. In some embodiments, bonding interface 106 is a hybrid metal / dielectric bonding interface and a hybrid metal / dielectric bonding interface. Figure 1B In 3D memory device 101, first semiconductor structure 102 including peripheral circuitry is above second semiconductor structure 104 including a memory cell array. However, according to some embodiments, a bonding interface 106 is formed vertically between first semiconductor structure 102 and second semiconductor structure 104 in 3D memory device 101, and first semiconductor structure 102 and second semiconductor structure 104 are vertically joined through bonding (e.g., hybrid bonding). Hybrid bonding (also referred to as “metal / dielectric hybrid bonding”) is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) and can achieve both metal-metal (e.g., copper-copper) bonding and dielectric-dielectric (e.g., silicon oxide-silicon oxide) bonding. Data transfer between the memory cell array in second semiconductor structure 104 and the peripheral circuitry in first semiconductor structure 102 can be performed through interconnects (e.g., bonding contacts) through bonding interface 106.

[0059] Note that, Figure 1A and Figure 1B The substrate of a 3D memory device includes two lateral surfaces that extend laterally in the x-y plane: a top surface on the front side of the wafer on which semiconductor devices can be formed, and a bottom surface on the back side of the wafer opposite the front side of the wafer. The z-axis is perpendicular to both the x- and y-axes. As used herein, when a substrate is positioned in the z-direction (a vertical direction perpendicular to the x-y plane, e.g., a thickness direction of the substrate) in the lowest plane of a 3D memory device, one component (e.g., layer or device) of the 3D memory device is determined to be “on,” “above,” or “below” another component (e.g., layer or device) in the z-direction relative to the substrate of the 3D memory device. The same concept is applied throughout this disclosure for describing spatial relationships.

[0060] Figure 2A schematic diagram of a memory device 200, including peripheral circuitry and arrays of memory cells, each having a vertical transistor, according to some aspects of this disclosure, is shown. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. 3D memory devices 100 and 101 may be examples of memory devices 200 in which the memory cell array 201 and peripheral circuitry 202 may be respectively included in a second semiconductor structure 104 and a first semiconductor structure 102. The memory cell array 201 may be any suitable memory cell array, wherein each memory cell 208 includes a vertical transistor 210 and a memory cell 212 coupled to the vertical transistor 210. In some embodiments, the memory cell array 201 is a DRAM cell array, and the memory cell 212 is a capacitor for storing charge as binary information stored by the respective DRAM cell. In some embodiments, the memory cell array 201 is a PCM cell array, and the storage cell 212 is a PCM element (e.g., including chalcogenide alloys) used to store binary information of the corresponding PCM cell based on the different resistivities of the PCM element in the amorphous and crystalline phases. In some embodiments, the memory cell array 201 is an FRAM cell array, and the storage cell 212 is a ferroelectric capacitor used to store binary information of the corresponding FRAM cell based on the switching between two polarization states of the ferroelectric material under an external electric field.

[0061] like Figure 2 As shown, memory cells 208 can be arranged in a two-dimensional (2D) array having rows and columns. Memory device 200 may include word lines 204 coupling peripheral circuitry 202 to the memory cell array 201 for controlling the switching of vertical transistors 210 in the memory cells 208 located in a row, and bit lines 206 coupling peripheral circuitry 202 to the memory cell array 201 for sending data to and / or receiving data from the memory cells 208 located in a column. That is, each word line 204 is coupled to a memory cell 208 in a corresponding row, and each bit line is coupled to a memory cell 208 in a corresponding column.

[0062] Consistent with the scope of this disclosure, a vertical transistor 210, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), can replace a conventional planar transistor as the transfer transistor for memory cell 208 to reduce the area occupied by the transfer transistor, coupling capacitance, and interconnect wiring complexity, as described in detail below. Figure 2As shown, in some embodiments, unlike planar transistors in which an active region is formed in a substrate, vertical transistor 210 includes a semiconductor body 214 that extends vertically (in the z-direction) above a substrate (not shown). That is, semiconductor body 214 can extend above a top surface of the substrate to expose not only a top surface of semiconductor body 214, but also one or more side surfaces of semiconductor body 214. As Figure 2 As shown, for example, semiconductor body 214 can have a cuboid shape to expose four of its sides. It should be appreciated that semiconductor body 214 can have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, a cross-section of semiconductor body 214 in plan view (e.g., in the x-y plane) can have a square shape, a rectangular shape (or trapezoidal shape), a circular shape (or elliptical shape), or any other suitable shape. It should be appreciated that, consistent with the scope of the present disclosure, for a semiconductor body having a circular or elliptical shape in plan view, the semiconductor body can still be considered to have multiple sides such that a gate structure contacts more than one side of the semiconductor body. As described below with respect to the fabrication process, semiconductor body 214 can be formed from the substrate (e.g., by etching or epitaxy) and thus have the same semiconductor material (e.g., silicon crystalline silicon) as the substrate (e.g., a silicon substrate).

[0063] As Figure 2 As shown, vertical transistor 210 can also include a gate structure 216 in contact with one or more side surfaces of semiconductor body 214, i.e., in one or more planes of the side surface(s) of the active region. That is, the active region of vertical transistor 210 (i.e., semiconductor body 214) can be at least partially surrounded by gate structure 216. Gate structure 216 can include a gate dielectric 218 over one or more side surfaces of semiconductor body 214, e.g., as Figure 2The gate structure 216 is shown to contact the four side surfaces of the semiconductor body 214. The gate structure 216 may also include a gate electrode 220 on and in contact with the gate dielectric 218. The gate dielectric 218 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 218 may include silicon oxide, i.e., a gate oxide. The gate electrode 220 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 220 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 220 includes multiple conductive layers, such as a W layer over a TiN layer. It should be understood that in some examples, the gate electrode 220 and the word line 204 may be a continuous conductive structure. That is, the gate electrode 220 can be regarded as part of the word line 204 forming the gate structure 216, or the word line 204 can be regarded as an extension of the gate electrode 220 to couple to the peripheral circuit 202.

[0064] like Figure 2 As shown, the vertical transistor 210 may further include a pair of source and drain electrodes (S / D, doped regions, also referred to as source and drain electrodes) formed respectively at two ends of the semiconductor body 214 in the vertical direction (z-direction). The source and drain electrodes may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and drain electrodes may be separated in the vertical direction (z-direction) by a gate structure 216. That is, the gate structure 216 is formed vertically between the source and drain electrodes. As a result, when the gate voltage applied to the gate electrode 220 of the gate structure 216 is higher than the threshold voltage of the vertical transistor 210, one or more channels (not shown) of the vertical transistor 210 may be formed vertically between the source and drain electrodes in the semiconductor body 214. That is, according to some embodiments, each channel of the vertical transistor 210 is also formed in the vertical direction along which the semiconductor body 214 extends.

[0065] In some implementations, such as Figure 2 As shown, the vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 can be connected to more than one side of the semiconductor body 214 (e.g., Figure 2 The four sides of the semiconductor body 214 are contacted to form more than one gate, allowing more than one channel to be formed between the source and drain during operation. That is, unlike planar transistors that only include a single planar gate (and create a single planar channel), the 3D structure of the semiconductor body 214 and the gate structure 216 surrounding multiple sides of the semiconductor body 214 enable the formation of more than one gate. Figure 2The vertical transistors 210 shown in FIG. 1 can include multiple vertical gates on multiple sides of the semiconductor body 214. As a result, compared to planar transistors, Figure 2 The vertical transistors 210 shown in FIG. 1 can have a larger gate-controlled area to achieve better channel control with smaller subthreshold swing. During the off state, the leakage current (I off ) of the vertical transistors 210 can also be significantly reduced due to the full depletion of the channel. As described in detail below, the multi-gate vertical transistors can include double-gate vertical transistors (e.g., double-sided gate vertical transistors), triple-gate vertical transistors (e.g., triple-sided gate vertical transistors), and GAA vertical transistors.

[0066] It should be appreciated that although the vertical transistors 210 are shown as multi-gate transistors in FIG. 1, Figure 2 it is also possible for the vertical transistors disclosed herein to include single-gate transistors as described in detail below. That is, for example, for the purpose of increasing transistor and memory cell density, the gate structure 216 can be in contact with a single side of the semiconductor body 214. It should also be appreciated that although the gate dielectric 218 is shown as being separate (i.e., a separate structure) from other gate dielectrics of adjacent vertical transistors (not shown), the gate dielectric 218 can be part of a continuous dielectric layer having multiple gate dielectrics of the vertical transistors.

[0067] In planar transistors and some lateral multi-gate transistors (e.g., FinFETs), the active region (e.g., semiconductor body (e.g., fin)) extends laterally (in the x-y plane), and the source and drain are disposed at different locations in the same lateral plane (x-y plane). In contrast, according to some embodiments, in the vertical transistors 210, the semiconductor body 214 extends vertically (in the z-direction), and the source and drain are disposed in different lateral planes. In some embodiments, the source and drain are formed at two ends of the semiconductor body 214, respectively, in the vertical direction (z-direction), thereby overlapping in a plan view. As a result, compared to planar transistors and lateral multi-gate transistors, the area occupied by the vertical transistors 210 (in the x-y plane) can be reduced. Furthermore, the metal wiring coupled to the vertical transistors 210 can also be simplified, as the interconnects can be routed in different planes. For example, the bit line 206 and the storage cell 212 can be formed on opposite sides of the vertical transistors 210. In one example, the bit line 206 can be coupled to the source or drain at the upper end of the semiconductor body 214, while the storage cell 212 can be coupled to the other source or drain at the lower end of the semiconductor body 214.

[0068] As Figure 2As shown, the storage unit 212 can be coupled to the source or drain of the vertical transistor 210. The storage unit 212 can include any device capable of storing binary data (e.g., 0s and Is), including but not limited to a capacitor for a DRAM cell and an FRAM cell and a PCM element for a PCM cell. In some embodiments, the vertical transistor 210 controls selection and / or state switching of the respective storage unit 212 coupled to the vertical transistor 210. In some embodiments as shown in FIG. 2A, each memory cell 208 is a DRAM cell 302 including a transistor 304 (e.g., implemented using the vertical transistor 210 in FIG. 3A) and a capacitor 306 (e.g., an example of the storage unit 212 in FIG. 3B). The gate of the transistor 304 (e.g., corresponding to the gate electrode 220) can be coupled to the word line 204, one of the source and drain of the transistor 304 can be coupled to the bit line 206, the other of the source and drain of the transistor 304 can be coupled to one electrode of the capacitor 306, and the other electrode of the capacitor 306 can be coupled to ground. In some embodiments as shown in FIG. 2B, each memory cell 208 is a PCM cell 402 including a transistor 404 (e.g., implemented using the vertical transistor 210 in FIG. 4A) and a PCM element 406 (e.g., an example of the storage unit 212 in FIG. 4B). The gate of the transistor 404 (e.g., corresponding to the gate electrode 220) can be coupled to the word line 204, one of the source and drain of the transistor 404 can be coupled to ground, the other of the source and drain of the transistor 404 can be coupled to one electrode of the PCM element 406, and the other electrode of the PCM element 406 can be coupled to the bit line 206. Figure 3 Figure 2 Figure 2 Figure 4 Figure 2 Figure 2

[0069] The peripheral circuit 202 can be coupled to the memory cell array 201 through the bit lines 206, the word lines 204, and any other suitable metal wiring. As described above, the peripheral circuit 202 can include any suitable circuitry for facilitating operation of the memory cell array 201 by applying voltage and / or current signals to and sensing voltage and / or current signals from each memory cell 208 via the word lines 204 and the bit lines 206. The peripheral circuit 202 can include various types of peripheral circuitry formed using CMOS technology.

[0070] According to some aspects of the present disclosure, the vertical transistors of memory cells in a memory device (e.g., the memory device 200) are multi-gate transistors, and the gate dielectrics of the vertical transistors in the word line direction are separated. For example, the vertical transistors of the memory cells in the memory device 200 can be multi-gate transistors, and the gate dielectrics of the vertical transistors in the word line direction can be separated. Figure 5 ​​​​​​A plan view of an array of memory cells 502 each including a vertical transistor in a memory device 500 is shown in accordance with some aspects of the present disclosure. As Figure 5 shown in FIG. 1, the memory device 500 can include a plurality of word lines 504 each extending in a first lateral direction (x-direction, referred to as a word line direction). The memory device 500 can also include a plurality of bit lines 506 each extending in a second lateral direction (y-direction, referred to as a bit line direction) perpendicular to the first lateral direction. It will be appreciated that Figure 5 a cross-section of the memory device 500 in the same lateral plane is not shown, and the word lines 504 and bit lines 506 can be formed in different lateral planes to facilitate wiring as described in detail below.

[0071] The memory cells 502 can be formed at intersections of the word lines 504 and bit lines 506. In some embodiments, each memory cell 502 includes a vertical transistor having a semiconductor body 508 and a gate structure 510 (e.g., the vertical transistor 210 in Figure 2 FIG. 1). The semiconductor body 508 can extend in a vertical direction (z-direction, not shown) perpendicular to the first and second lateral directions. The vertical transistor can be a multi-gate transistor in which the gate structure 510 contacts multiple sides of the semiconductor body 508 (e.g., all 4 sides in Figure 5 FIG. 1) in which an active region of a channel is formed. As Figure 5 shown in FIG. 1, the vertical transistor is a GAA transistor in which the gate structure 510 completely circumscribes the semiconductor body 508 in plan view. That is, according to some embodiments, the gate structure 510 circumscribes (e.g., surrounds and contacts) all four sides of the semiconductor body 508 (having a rectangular or square shaped cross-section) in plan view. The gate structure 510 can include a gate dielectric 512 that completely circumscribes the semiconductor body 508 in plan view, and a gate electrode 514 that completely circumscribes the gate dielectric 512. In some embodiments, the gate dielectric 512 laterally between the gate electrode 514 and the semiconductor body 508 in the bit line direction and the word line direction. As noted above, the gate electrode 514 can be part of the word lines 504, and the word lines 504 can be an extension of the gate electrode 514.

[0072] As Figure 5 shown in FIG. 1, the gate electrodes 514 of vertically adjacent vertical transistors are continuous in the word line direction (x-direction), e.g., are part of a continuous conductive layer having the gate electrodes 514 and 504. In contrast, the gate dielectrics 512 of vertically adjacent vertical transistors are separate in the word line direction, e.g., are not part of a continuous dielectric layer having the gate dielectrics 512.

[0073] Figure 6AA side view showing a cross-section of a 3D memory device 600 including vertical transistors is shown in accordance with some aspects of the present disclosure. The 3D memory device 600 can be one example of the memory device 500 including multi-gate vertical transistors with gate structures fully circumscribing the semiconductor body in plan view, such as GAA vertical transistors. It should be appreciated that, Figure 6A are for illustrative purposes only and can not necessarily reflect actual device structures (e.g., interconnects). As described above with respect to the 3D memory device 100, Figure 1A One example of the 3D memory device 100 described above, the 3D memory device 600 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are joined at a bonded interface 106 between them. As shown, Figure 6A The first semiconductor structure 102 can include a substrate 610, which can include silicon (e.g., single-crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0074] The first semiconductor structure 102 can include a peripheral circuit 612 on the substrate 610. In some embodiments, the peripheral circuit 612 includes a plurality of transistors 614 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of the transistors 614) can also be formed on or in the substrate 610.

[0075] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 616 above the peripheral circuitry 612 for transmitting electrical signals to and from the peripheral circuitry 612. The interconnect layer 616 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and vertical interconnect access (VIA) contacts. As used herein, the term “interconnect” can broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer 616 may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) in which interconnects and via contacts can be formed. That is, the interconnect layer 616 may include interconnects and via contacts in multiple ILD layers. In some embodiments, the peripheral circuitry 612 is coupled to each other via interconnects in the interconnect layer 616. The interconnects in interconnect layer 616 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0076] like Figure 6A As shown, the first semiconductor structure 102 may further include a bonding layer 618 at the bonding interface 106 and above the interconnect layer 616 and the peripheral circuitry 612. The bonding layer 618 may include a plurality of bonding contacts 619 and a dielectric material electrically isolating the bonding contacts 619. The bonding contacts 619 may include a conductive material, such as Cu. The remaining region of the bonding layer 618 may be formed of a dielectric material (e.g., silicon oxide). The bonding contacts 619 in the bonding layer 618 and the surrounding dielectric material may be used for hybrid bonding. Similarly, as Figure 6A As shown, the second semiconductor structure 104 may also include a bonding layer 620 at the bonding interface 106 and above the bonding layer 618 of the first semiconductor structure 102. The bonding layer 620 may include a plurality of bonding contacts 621 and a dielectric material electrically isolating the bonding contacts 621. The bonding contacts 621 may include a conductive material, such as Cu. The remaining region of the bonding layer 620 may be formed of a dielectric material (e.g., silicon oxide). The bonding contacts 621 in the bonding layer 620 and the surrounding dielectric material may be used for mixed bonding. According to some embodiments, the bonding contacts 621 contact the bonding contacts 619 at the bonding interface 106.

[0077] The second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, as a result of hybrid bonding (also referred to as “metal / dielectric hybrid bonding”), the bonding interface 106 is disposed between the bonding layers 620 and 618. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is the location where the bonding layers 620 and 618 meet and bond. In practice, the bonding interface 106 can be a layer of a certain thickness, comprising the top surface of the bonding layer 618 of the first semiconductor structure 102 and the bottom surface of the bonding layer 620 of the second semiconductor structure 104.

[0078] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 622, which includes bit lines 623 above the bonding layer 620 for transmitting electrical signals. The interconnect layer 622 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 622 also include local interconnects, such as bit lines 623 (e.g., Figure 5 Examples of bit lines 506, bit line contacts 625 (which may be omitted in some examples), and word line contacts 627 are shown. Interconnect layer 622 may also include one or more ILD layers in which interconnects and via contacts may be formed. Interconnects in interconnect layer 622 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, peripheral circuitry 612 includes a word line driver / line decoder coupled to word line contacts 627 in interconnect layer 622 via bonding contacts 621 and 619 in bonding layers 620 and 618 and interconnect layer 616. In some implementations, peripheral circuitry 612 includes a bit line driver / column decoder that is coupled to bit lines 623 and bit line contacts 625 in interconnect layer 622 via bonding contacts 621 and 619 in bonding layers 620 and 618 and interconnect layer 616.

[0079] In some embodiments, the second semiconductor structure 104 includes a DRAM device, wherein the memory cells are DRAM cells 624 (e.g., Figure 5 An array of memory cells 502 (as in the example) is provided above the interconnect layer 622 and the bonding layer 620. That is, the interconnect layer 622, including bit lines 623, can be disposed between the bonding layer 620 and the array of DRAM cells 624. It should be understood that... Figure 6A A cross-section of the 3D memory device 600 in the y-direction can be taken along a bit line direction (y-direction), and a bit line 623 in the interconnect layer 622 that extends laterally in the y-direction can be coupled to a column of DRAM cells 624.

[0080] Each DRAM cell 624 can include a vertical transistor 626 (e.g., an example of the vertical transistor 210 in Figure 2 Figure 2 DRAM cell 624 can be a 1T1C cell consisting of one transistor and one capacitor. It should be appreciated that the DRAM cell 624 can be of any suitable construction, such as a 2T1C cell, a 3T1C cell, etc.

[0081] The vertical transistor 626 can be a MOSFET for switching the respective DRAM cell 624. In some embodiments, the vertical transistor 626 includes a semiconductor body 630 (i.e., an active region in which multiple channels can be formed) that extends vertically (in the z-direction) and a gate structure 636 that contacts multiple sides of the semiconductor body 630. As noted above, as in a GAA vertical transistor, the semiconductor body 630 can have a cuboid shape or a cylindrical shape, and the gate structure 636 can completely circumscribe the semiconductor body 630 in a plan view, e.g., as shown in Figure 5 According to some embodiments, the gate structure 636 includes a gate electrode 634 and a gate dielectric 632 laterally between the gate electrode 634 and the semiconductor body 630. For example, for a semiconductor body 630 having a cylindrical shape, the semiconductor body 630, the gate dielectric 632, and the gate electrode 634 can be disposed radially from a center of the vertical transistor 626 in that order. In some embodiments, the gate dielectric 632 surrounds and contacts the semiconductor body 630, and the gate electrode 634 surrounds and contacts the gate dielectric 632.

[0082] As noted above, the DRAM cell 624 can include a capacitor 628 (e.g., an example of the storage cell 212 in Figure 6A ​As shown, in some embodiments, the semiconductor body 630 has two ends (an upper end and a lower end) in the vertical direction (z-direction), and the two ends extend beyond the gate structure 636 into the ILD layers in the vertical direction (z-direction), respectively. That is, the semiconductor body 630 can have a larger vertical dimension (e.g., depth) (e.g., in the z-direction) than that of the gate structure 636, and neither the upper end nor the lower end of the semiconductor body 630 is flush with the respective end of the gate structure 636. As a result, short circuits between the bit line 623 and the word line / gate electrode 634 or between the word line / gate electrode 634 and the capacitor 628 can be avoided. In some embodiments, the two ILD layers into which the semiconductor body 630 extends (e.g., the ILD layer vertically between the bit line contact 625 and the word line 634, and the ILD layer vertically between the word line 634 and the capacitor 628) comprise the same dielectric material, e.g., silicon oxide. The vertical transistor 626 can also include a source and a drain (which can be interchangeable in terms of their positions, and thus both are referred to as 638) disposed at the two ends (the upper end and the lower end) of the semiconductor body 630 in the vertical direction (z-direction), respectively. In some embodiments, one of the source and the drain 638 (e.g., at the upper end in Figure 6A ) is coupled to the capacitor 628, and the other of the source and the drain 638 (e.g., at the lower end in Figure 6A ) is coupled to the bit line 623 (e.g., through the bit line contact 625 or directly).

[0083] In some embodiments, the semiconductor body 630 includes a semiconductor material, such as single crystalline silicon, poly crystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 630 can include single crystalline silicon. The source and drain 638 can be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source and drain 638 and the bit line contact 625 or the first electrode 642 to reduce contact resistance. In some embodiments, the gate dielectric 632 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to aluminum oxide (AI2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), titanium oxide (TiO2), or any combination thereof. In some embodiments, the gate electrode 634 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, poly silicon, silicide, or any combination thereof. In some embodiments, the gate electrode 634 includes multiple conductive layers, such as a W layer on top of a TiN layer. In one example, the gate structure 636 can be a “gate oxide / gate poly” gate, where the gate dielectric 632 includes silicon oxide and the gate electrode 634 includes doped poly silicon. In another example, the gate structure 636 can be a high-k metal gate (HKMG), where the gate dielectric 632 includes a high-k dielectric and the gate electrode 634 includes a metal.

[0084] As described above, since the gate electrode 634 can be part of or extend in the word line direction (e.g., the x-direction in Figure 5 Figure 6A Although not directly shown in Figure 5 , the second semiconductor structure 104 of the 3D memory device 600 can also include multiple word lines (e.g., examples of the word lines 504 in , also referred to as 634) each extending in the word line direction (x-direction). Each word line 634 can be coupled to a row of DRAM cells 624. That is, the bit lines 623 and the word lines 634 can extend in two perpendicular lateral directions, and the semiconductor bodies 630 of the vertical transistors 626 can extend in a vertical direction perpendicular to the two lateral directions in which the bit lines 623 and the word lines 634 extend. According to some embodiments, the word lines 634 are in contact with the word line contacts 627. In some embodiments, the word lines 634 include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, poly silicon, silicide, or any combination thereof. In some embodiments, the word lines 634 include multiple conductive layers, such as a W layer on top of a TiN layer.

[0085] As Figure 6A As shown, according to some embodiments, the vertical transistors 626 extend vertically through and contact the word lines 634, and the source or drain 638 of the vertical transistors 626 at their lower end contacts the bit line contact 625 or directly contacts the bit line 623. Thus, due to the vertical arrangement of the vertical transistors 626, the word lines 634 and the bit lines 623 can be disposed in different planes in the vertical direction, which simplifies the routing of the word lines 634 and the bit lines 623. In some embodiments, the bit lines 623 are disposed vertically between the bonding layer 620 and the word lines 634, and the word lines 634 are disposed vertically between the bit lines 623 and the capacitors 628. The word lines 634 can be coupled to the peripheral circuitry 612 in the first semiconductor structure 102 through word line contacts 627 in the interconnect layer 622, bonding contacts 621 and 619 in the bonding layers 620 and 618, and interconnects in the interconnect layer 616. Similarly, the bit lines 623 in the interconnect layer 622 can be coupled to the peripheral circuitry 612 in the first semiconductor structure 102 through bonding contacts 621 and 619 in the bonding layers 620 and 618, and interconnects in the interconnect layer 616.

[0086] In some embodiments, the second semiconductor structure 104 further includes a plurality of air gaps 640 each disposed laterally between adjacent word lines 634. Each air gap 640 can be a trench extending parallel to the word lines 634 in the word line direction (e.g., x-direction) to separate adjacent rows of vertical transistors 626. As described below with respect to the fabrication process, the air gaps 640 can be formed due to the relatively small pitch of the word lines 634 (and rows of DRAM cells 624) in the bit line direction (e.g., y-direction). On the other hand, the relatively large dielectric constant of air (e.g., about 4 times that of silicon oxide) in the air gaps 640 compared to some dielectrics (e.g., silicon oxide) can improve the insulating effect between the word lines 634 (and rows of DRAM cells 624).

[0087] As Figure 6AAs shown, in some embodiments, the capacitor 628 includes a first electrode 642 over and in contact with the source or drain 638 of the vertical transistor 626 (e.g., the upper end of the semiconductor body 630). The capacitor 628 can also include a capacitor dielectric 644 over and in contact with the first electrode 642, and a second electrode 646 over and in contact with the capacitor dielectric 644. That is, the capacitor 628 can be a vertical capacitor, with the electrodes 642 and 646 and the capacitor dielectric 644 stacked vertically (in the z-direction), and the capacitor dielectric 644 can be sandwiched between the electrodes 642 and 646. In some embodiments, each first electrode 642 is coupled to the source or drain 638 of a respective vertical transistor 626 in the same DRAM cell, while all second electrodes 646 are part of a common plate coupled to ground (e.g., a common ground). As Figure 6A As shown, the second semiconductor structure 104 can also include a capacitor contact 647 in contact with the common plate of the second electrodes 646, for coupling the second electrodes 646 of the capacitor 628 to the peripheral circuit 612 or directly to ground. In some embodiments, where the ILD layer forming the capacitor 628 has the same dielectric material as the two ILD layers into which the semiconductor body 630 extends, such as silicon oxide.

[0088] It should be appreciated that the structure and configuration of the capacitor 628 is not limited to the example in Figure 6A and can include any suitable structure and configuration, such as a planar capacitor, a stacked capacitor, a multi-finned capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. In some embodiments, the capacitor dielectric 644 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to AI2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be appreciated that in some examples, the capacitor 628 can be a ferroelectric capacitor used in FRAM cells, and the capacitor dielectric 644 can be replaced by a ferroelectric layer with a ferroelectric material (e.g., lead zirconate titanate (PZT) or strontium bismuth tantalate (SBT)). In some embodiments, the electrodes 642 and 646 include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0089] As Figure 6AAs shown, according to some embodiments, the vertical transistor 626 extends vertically through and contacts the word line 634, the source or drain 638 of the vertical transistor 626 at its lower end contacts the bit line contact 625 or directly contacts the bit line 623, and the source or drain 638 of the vertical transistor 626 at its upper end contacts the electrode 642 of the capacitor 628. That is, the bit line 623 and the capacitor 628 can be disposed in different planes in the vertical direction and are coupled to opposite ends of the vertical transistor 626 of the DRAM cell 624 in the vertical direction due to the vertical arrangement of the vertical transistor 626. In some embodiments, the bit line 623 and the capacitor 628 are disposed on opposite sides of the vertical transistor 626 in the vertical direction, which simplifies the routing of the bit line 623 and reduces the coupling capacitance between the bit line 623 and the capacitor 628 compared to conventional DRAM cells in which the bit line and the capacitor are disposed on the same side of the planar transistor.

[0090] As Figure 6A shown, in some embodiments, the vertical transistor 626 is disposed vertically between the capacitor 628 and the bonding interface 106. That is, the vertical transistor 626 can be arranged closer to the peripheral circuitry 612 of the first semiconductor structure 102 and the bonding interface 106 than the capacitor 628. According to some embodiments, since the bit line 623 and the capacitor 628 are coupled to opposite ends of the vertical transistor 626 as described above, the bit line 623 (as part of the interconnect layer 622) is disposed vertically between the vertical transistor 626 and the bonding interface 106. As a result, the interconnect layer 622 including the bit line 623 can be arranged close to the bonding interface 106 to reduce interconnect routing distance and complexity.

[0091] In some embodiments, the second semiconductor structure 104 further includes a substrate 648 disposed above the DRAM cell 624. As described below with respect to the fabrication process, the substrate 648 can be part of a carrier wafer. It should be appreciated that in some examples, the substrate 648 can not be included in the second semiconductor structure 104.

[0092] As Figure 6AAs shown, the second semiconductor structure 104 can also include a substrate 648 and a pad-out interconnect layer 650 over the DRAM cells 624. The pad-out interconnect layer 650 can include interconnects, such as contact pads 654, in one or more ILD layers. The pad-out interconnect layer 650 and the interconnect layer 622 can be formed on opposite sides of the DRAM cells 624. According to some embodiments, the capacitor 628 is disposed vertically between the vertical transistor 626 and the pad-out interconnect layer 650. In some embodiments, the interconnects in the pad-out interconnect layer 650 can carry electrical signals between the 3D memory device 600 and external circuitry, for example, for pad-out purposes. In some embodiments, the second semiconductor structure 104 also includes one or more contacts 652 that extend through portions of the substrate 648 and the pad-out interconnect layer 650 to couple the pad-out interconnect layer 650 to the DRAM cells 624 and the interconnect layer 622. As a result, the peripheral circuitry 612 can be coupled to the DRAM cells 624 through the interconnect layers 616 and 622 and the bonding layers 620 and 618, and the peripheral circuitry 612 and the DRAM cells 624 can be coupled to external circuitry through the contacts 652 and the pad-out interconnect layer 650. The contact pads 654 and the contacts 652 can include electrically conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contact pads 654 can include Al and the contacts 652 can include W. In some embodiments, the contacts 652 include vias surrounded by a dielectric spacer (e.g., with silicon oxide) to electrically separate the vias from the substrate 648. Depending on the thickness of the substrate 648, the contacts 652 can be interlayer vias (ILVs) with sub-micron (e.g., between 10 nm and 1 pm) depths, or through substrate vias (TSVs) with micron or tens-of-micron (e.g., between 1 pm and 100 pm) depths.

[0093] It should be appreciated that pad-out of the 3D memory device is not limited to the second semiconductor structure 104 with DRAM cells 624 as shown in FIG. 6B, and can be from the first semiconductor structure 102 with peripheral circuitry 612. For example, as shown in FIG. 6A, the contacts 652 can be used to couple the peripheral circuitry 612 to the DRAM cells 624 through the pad-out interconnect layer 650 and the interconnect layer 622. Figure 6A Figure 6B ​As shown, the 3D memory device 601 can include a pad-out interconnect layer 650 in the first semiconductor structure 102. The pad-out interconnect layer 650 can be disposed above and in contact with the substrate 610 of the first semiconductor structure 102 on which the transistors 614 of the peripheral circuit 612 are formed. In some embodiments, the first semiconductor structure 102 also includes one or more contacts 653 that extend vertically through the substrate 610. In some embodiments, the contacts 653 couple interconnects in the interconnect layer 616 in the first semiconductor structure 102 to contact pads 654 in the pad-out interconnect layer 650 for electrical connection through the substrate 610. The contacts 653 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, the contacts 653 can include W. In some embodiments, the contacts 653 include vias surrounded by a dielectric spacer (e.g., with silicon oxide) to electrically separate the vias from the substrate 610. It should be appreciated that in some examples, the contacts 653 can be ILVs with sub-micron (e.g., between 10 nm and 1 pm) depths or TSVs with micron or tens of micron (e.g., between 1 pm and 100 pm) depths compared to the substrate 610 in the 3D memory device 600. Figure 6A Figure 6B The substrate 610 in the 3D memory device 600 can be a thinned substrate. Depending on the thickness of the substrate 610, the contacts 653 can be ILVs with sub-micron (e.g., between 10 nm and 1 pm) depths or TSVs with micron or tens of micron (e.g., between 1 pm and 100 pm) depths. It should be appreciated that details of identical components (e.g., materials, fabrication processes, functions, etc.) in both the 3D memory devices 600 and 601 are not repeated for ease of description. The pad-out from the first semiconductor structure 102 including the peripheral circuit 612 can reduce the interconnect distance between the contact pads 654 and the peripheral circuit 612, thereby reducing parasitic capacitance from the interconnects and improving electrical performance of the 3D memory device 601.

[0094] It should also be appreciated that the relative vertical positions between the semiconductor bodies and the corresponding gate structures and word lines are not limited to Figure 6A the examples shown in which the upper and lower end portions of the semiconductor bodies 630 extend beyond the gate structures 636 (and word lines 634), respectively, depending on various fabrication processes described in detail below. For example, as Figure 6C ​As shown, the 3D memory device 603 may include vertical transistors 626, each having a semiconductor body 630 and a gate structure 636, and one end of the semiconductor body 630 in the vertical direction (z-direction) may be flush with the gate structure 636. In some embodiments, the upper or lower end of the semiconductor body 630 that contacts the first electrode 642 of the capacitor 628 is flush with the corresponding end of the gate structure 636 and the word line 634. That is, according to some embodiments, one of the upper and lower ends of the semiconductor body 630 that contacts the capacitor 628 does not extend beyond the corresponding end of the gate structure 636 and the word line 634. In some embodiments, such as Figure 6C As shown, the other end of the semiconductor body 630 that contacts the bit line contact 625 in the vertical direction still extends beyond the corresponding ends of the gate structure 636 and the word line 634 into the ILD layer, which is perpendicular between the bit line contact 625 and the word line 634. It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in both 3D memory devices 600 and 603 are not repeated.

[0095] It should also be understood that the dielectric material of the ILD layer extending into the semiconductor body is not limited to... Figure 6A The example shown includes an ILD layer comprising silicon oxide, for example, the same material as the ILD layer in which capacitor 628 is formed, depending on various manufacturing processes described in detail below. For example, as... Figure 6D As shown, the 3D memory device 605 may include two ILD layers 660 and 662 extending therein from a semiconductor body 630. According to some embodiments, ILD layer 660 is perpendicularly positioned between a bit line contact 625 and a word line 634, and ILD layer 662 is perpendicularly positioned between the word line 634 and a first electrode 642 of a capacitor 628. ILD layers 660 and 662 may include a dielectric material different from the dielectric material of the ILD layer in which the capacitor 628 is formed. In some embodiments, ILD layers 660 and 662 comprise silicon nitride, while the ILD layer of the capacitor 628 comprises silicon oxide. Figure 6D As shown, in some embodiments, one end of the semiconductor body 630 that contacts the capacitor 628 in the vertical direction (z-direction) is flush with the corresponding end of the ILD layer 662. In some embodiments, the air gap 640 extends vertically through the ILD layer 662 to separate the ILD layer 662, but does not extend further into the ILD layer 660, i.e., it is stopped by the ILD layer 660. It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in both 3D memory devices 600 and 605 are not repeated.

[0096] It should also be appreciated that the air gaps between the word lines can be partially or completely filled with a dielectric. For example, as shown in Figure 6E the memory device 607 can not include air gaps between adjacent word lines 634 (e.g., air gaps 640 in Figure 6A ). Instead, the memory device 607 can include dielectric wall structures 641 that are each formed between adjacent word lines 634 (e.g., filled with a dielectric, such as silicon oxide). It should be appreciated that in some examples (not shown), air gaps 640 can still exist between the word lines 634, but have a smaller vertical dimension (depth) compared to the word lines 634. It should be appreciated that details of identical components in both 3D memory devices 600 and 607 (e.g., materials, fabrication processes, functionality, etc.) are not repeated for ease of description.

[0097] It should also be appreciated that more than one array of DRAM cells can be stacked on top of each other in order to vertically scale up the number of DRAM cells. For example, as shown in Figure 7 the memory device 700 can also include a third semiconductor structure 702 having an array of DRAM cells 624 stacked on top of the second semiconductor structure 104 and the first semiconductor structure 102. According to some embodiments, the third semiconductor structure 702 and the second semiconductor structure 104 are joined at another bonding interface 704 therebetween. The third semiconductor structure 702 and the second semiconductor structure 104 can have the same array of DRAM cells 624 and interconnect layers 622, and thus, details of the DRAM cells 624 and interconnect layers 622 in the third semiconductor structure 702 are not repeated for ease of description.

[0098] According to some embodiments, the third semiconductor structure 702 and the second semiconductor structure 104 can be bonded in a face-to-face manner such that at least some components (e.g., DRAM cells 624) in the third semiconductor structure 702 and the second semiconductor structure 104 can be symmetrical about the bonding interface 704. The bonding interface 704 can be vertically formed between the DRAM cells 624 in the third semiconductor structure 702 and the DRAM cells 624 in the second semiconductor structure 104. As shown in Figure 7As shown, in some embodiments, the capacitor 628 in the second semiconductor structure 104 is disposed vertically between the bonding interface 704 and the vertical transistor 626 in the second semiconductor structure 104, and the capacitor 628 in the third semiconductor structure 702 is disposed vertically between the bonding interface 704 and the vertical transistor 626 in the third semiconductor structure 702. That is, the capacitor 628 in the second semiconductor structure 104 and the capacitor 628 in the third semiconductor structure 702 can be disposed on opposite sides of the bonding interface 704. In some embodiments, the second electrode 646 of the capacitor 628 in the third semiconductor structure 702 is in contact with the second electrode 646 of the capacitor 628 in the second semiconductor structure 104 at the bonding interface 704.

[0099] In some embodiments, the 3D memory device 700 includes additional interconnects that couple the DRAM cells 624 in the third semiconductor structure 702 across the bonding interfaces 704 and 106 to the peripheral circuitry 612, such as coupling the word lines 634 in the third semiconductor structure 702 and the word line contacts 734 of the peripheral circuitry 612 in the first semiconductor structure 102. As Figure 7 As shown, in contrast to the first semiconductor structure 102 or the second semiconductor structure 104, the third semiconductor structure 702 can include a pad-out interconnect layer 650. In some embodiments, the vertical transistor 626 in the third semiconductor structure 702 is disposed vertically between the capacitor 628 in the third semiconductor structure 702 and the pad-out interconnect layer 650. It should be understood that details of identical components (e.g., materials, fabrication processes, functions, etc.) in both the 3D memory device 600 and 700 are not repeated for ease of description.

[0100] It should be understood that Figure 7 The architecture of the multiple memory cell arrays shown in FIGS. 1-3 is not limited to the design of the DRAM cells 624 and can be applied to any suitable memory cell disclosed herein. It should also be understood that the various designs of memory cells disclosed herein can be mixed in the architecture of the multiple memory cell arrays shown in FIGS. 1-3. For example, the second semiconductor structure 104 and the third semiconductor structure 702 can include different designs of memory cells disclosed herein. Figure 7

[0101] It should also be understood that the memory cell arrays are not limited to Figure 5 , Figures 6A-6D and Figure 7 The vertical transistors shown in FIGS. 1-3 are examples of GAA transistors, but can be any other suitable multi-gate vertical transistor. For example, Figure 8 ​A plan view is shown of an array of other memory cells 802, each including a vertical transistor, in a memory device 800 according to some aspects of this disclosure. Figure 8 As shown, the memory device 800 may include multiple word lines 804 extending in a first lateral direction (x-direction, referred to as the word line direction). The memory device 800 may also include multiple bit lines 806 extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. It should be understood that... Figure 8 The memory device 800 is not shown in a cross-section in the same transverse plane, and word lines 804 and bit lines 806 may be formed in different transverse planes to facilitate wiring, as described in detail below.

[0102] Memory cells 802 may be formed at the intersection of word lines 804 and bit lines 806. In some embodiments, each memory cell 802 includes a vertical transistor having a semiconductor body 808 and a gate structure 810 (e.g., Figure 2 (Vertical transistor 210 in the middle). Figure 8 The vertical transistor of the memory cell 802 may be an example of a three-gate vertical transistor (e.g., a three-side gate vertical transistor). The semiconductor body 808 may extend in a vertical direction (z-direction, not shown) perpendicular to the first lateral direction and the second lateral direction. The gate structure 810 may be connected to multiple sides of the semiconductor body 808 (where the active region forming the channel) (e.g., Figure 8 It is in contact with three of the four sides. That is, with Figure 5 Unlike the GAA vertical transistor in memory cell 502, in the plan view, the gate structure 810 of the vertical transistor in memory cell 802 is partially external to the semiconductor body 808. That is, according to some embodiments, in the plan view, the gate structure 810 externalizes (e.g., surrounds and contacts) three of the four sides (with a rectangular or square cross-section) of the semiconductor body 808. According to some embodiments, the gate structure 810 does not surround and contact at least one side of the semiconductor body 808. The gate structure 810 may include a gate dielectric 812 that is partially or completely external to the semiconductor body 808 in the plan view, and a gate electrode 814 that is partially external to the gate dielectric 812. Therefore, a vertical transistor with a gate structure 810 can be considered as a "tri-gate" vertical transistor, wherein the gate structure 810 contacts two opposite sides of the semiconductor body 808 in the word line direction (x direction) and contacts one side of the semiconductor body 808 in the bit line direction (y direction). As described above, the gate electrode 814 can be a portion of the word line 804, and the word line 804 can be an extension of the gate electrode 814. For example, as Figure 8As shown, one edge of each word line 804 can be formed to align with the same side of each semiconductor body 808, such that the gate electrode 814 can not extend to that side of the semiconductor body 808 to form a GAA transistor. By arranging the semiconductor bodies 808 of the memory cells 802 to align with one side of the word lines 804, the pitch of the word lines 804 and / or the memory cell 802 pitch in the bit line direction (y-direction) can be further increased to reduce manufacturing complexity and increase yield.

[0103] Similar to Figure 5 , the memory device 500 in Figure 8 , the gate electrodes 814 of adjacent vertical transistors in the word line direction (x-direction) are continuous, e.g., are part of a continuous conductive layer having the gate electrodes 814 and 804. In contrast, the gate dielectrics 812 of adjacent vertical transistors in the word line direction are separate, e.g., are not part of a continuous dielectric layer having the gate dielectrics 812.

[0104] Figure 9 A side view showing a cross-section of a 3D memory device 900 including vertical transistors is shown, in accordance with some aspects of the present disclosure. The 3D memory device 900 can be one example of the memory device 800 including a multi-gate vertical transistor, where the gate structure partially circumscribes the semiconductor body in plan view. The 3D memory device 900 is similar to the 3D memory device 600 in Figure 6A , except for the different structure of the multi-gate vertical transistor in the DRAM cell 624. It should be understood that details of identical components in both the 3D memory devices 600 and 900 (e.g., materials, fabrication processes, functions, etc.) are not repeated for ease of description. Similar to Figure 6A , Figure 9 , the cross-section of the 3D memory device 900 can be taken along the bit line direction (y-direction).

[0105] The vertical transistor 926 can be a MOSFET for switching the corresponding DRAM cell 624. In some implementations, the vertical transistor 926 includes a semiconductor body 630 (i.e., an active region in which multiple channels can be formed) extending vertically (in the z-direction) and a gate structure 936 in contact with multiple sides of the semiconductor body 630. The semiconductor body 630 can have a cuboid shape or a cylindrical shape, and the gate structure 936 can partially circumscribe the semiconductor body 630 in plan view, e.g., as shown in Figure 8 Figure 9 ​As shown, according to some embodiments, the gate structure 936 does not extend to at least one side of the semiconductor body 630. According to some embodiments, the gate structure 936 includes a gate electrode 934 and a gate dielectric 932 laterally between the gate electrode 934 and the semiconductor body 630. As Figure 9 As shown, according to some embodiments, the gate electrode 934 does not extend to at least one side of the semiconductor body 630. As the pitch of the word lines 934 and / or the pitch of the DRAM cells 624 in the bit line direction (y-direction) increases, the air gap between the word lines 934 can be partially or fully filled with a dielectric.

[0106] It should also be appreciated that the number of gates in a multi-gate transistor can vary, i.e., is not limited to Figure 5 the GAA vertical transistor examples in Figure 8 the three-gate vertical transistor examples in

[0107] It should also be appreciated that although the storage cells are described as capacitors 628 in Figures 6A-6D , Figure 7 and Figure 9 , in some examples, the storage cells can include any other suitable device, e.g., a PCM element, as described above with respect to Figure 4 For example, the capacitor dielectric 644 of the capacitor 628 can be replaced with a phase change material layer (e.g., a chalcogenide alloy) vertically sandwiched between the electrodes 642 and 646 to form a PCM element. Further, instead of coupling the source or drain 638 of the vertical transistor 626 or 926 to the bit line 623, the electrode 642 or 646 of the PCM element can be coupled to the bit line 623, while the source or drain 638 of the vertical transistor 626 or 926 can be coupled to ground, e.g., a common ground plate.

[0108] According to some aspects of the disclosure, the vertical transistor of a memory cell in a memory device (e.g., the memory device 200) is a single-gate transistor, and the gate dielectric of the vertical transistor is continuous in the word line direction. For example, Figure 16 A plan view of an array of yet another memory cell 1602 each including a vertical transistor in a memory device 1600 according to some aspects of the disclosure is shown. As Figure 16As shown, the memory device 1600 may include multiple word lines 1604, each extending in a first lateral direction (x-direction, referred to as the word line direction). The memory device 1600 may also include multiple bit lines 1606, each extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. It should be understood that... Figure 16 The cross-section of the memory device 1600 in the same transverse plane is not shown, and the word line 1604 and bit line 1606 may be formed in different transverse planes to facilitate wiring, as described in detail below.

[0109] Memory cells 1602 may be formed at the intersection of word lines 1604 and bit lines 1606. In some embodiments, each memory cell 1602 includes a vertical transistor having a semiconductor body 1608 and a gate structure 1610 (e.g., Figure 2 The vertical transistor 210 is shown in the figure. The semiconductor body 1608 may extend in the substrate in a vertical direction (z-direction, not shown) perpendicular to both the first and second lateral directions. The vertical transistor may be a single-gate transistor, wherein the gate structure 1610 is adjacent to a single side of the semiconductor body 1608 (where the active region forming the channel is located). Figure 16 (One of the four sides) contacts. For example... Figure 16 As shown, the vertical transistor is a single-gate transistor, wherein the gate structure 1610 is adjacent to one side of the semiconductor body 1608 (having a rectangular or square cross-section) in the bit line direction (y-direction) in a plan view. According to some embodiments, the gate structure 1610 does not surround or contact the other three sides of the semiconductor body 1608. The gate structure 1610 may include a gate dielectric 1612 adjacent to one side of the semiconductor body 1608 in a plan view, and a gate electrode 1614 in contact with the gate dielectric 1612. In some embodiments, the gate dielectric 1612 is laterally positioned between the gate electrode 1614 and the semiconductor body 1608 in the bit line direction (y-direction). As described above, the gate electrode 1614 may be a portion of the word line 1604, and the word line 1604 may be an extension of the gate electrode 1614. That is, the gate electrodes 1614 of adjacent vertical transistors in the word line direction (x-direction) are continuous, for example, a portion of a continuous conductive layer having gate electrodes 1614 and 1604.

[0110] and Figure 5 and Figure 8 The separate gate dielectrics 512 and 812 in the model are different, such as Figure 16As shown, the gate dielectrics 1612 of adjacent vertical transistors in the word line direction are continuous, for example, a portion of a continuous dielectric layer having gate dielectrics 1612 and extending in the word line direction to abut vertical transistors in the same row on the same side. The gate structure 1610 can therefore be considered as a portion of a continuous structure extending in the word line direction, in which the continuous structure abuts vertical transistors in the same row on the same side.

[0111] like Figure 16 As shown, according to some embodiments, two adjacent vertical transistors (e.g., 1602A and 1602B) of a memory cell in the bit line direction (y-direction) are mirror-symmetrical to each other. As described below regarding the manufacturing process, the semiconductor body 1608 of each pair of two adjacent vertical transistors (e.g., 1602A and 1602B) of the memory cell in the bit line direction (y-direction) can be formed by separating the semiconductor pillars into two pieces using a trench isolation 1616 extending in the word line direction (x-direction) and parallel to the word line 1604. The trench isolation 1616 and the word line 1604 can be arranged in an interleaved manner in the bit line direction. In some embodiments, the trench isolation 1616 is formed in the middle of the semiconductor pillars (not shown) such that the resulting pair of semiconductor bodies 1608 are mirror-symmetrical to each other with respect to the trench isolation 1616, and so are the pairs of vertical transistors having the semiconductor bodies 1608 when the corresponding gate structures 1610 are also mirror-symmetrical to each other with respect to the trench isolation 1616.

[0112] It should be understood that in some examples, trench isolation 1616 extending in the word line direction may not be formed, such that two adjacent semiconductor bodies 1608 separated by corresponding trench isolation 1616 can be merged into a single semiconductor body having two opposing sides in the bit line direction that contact the gate structure 1610. That is, without trench isolation 1616, adjacent single-gate vertical transistors can be merged to form a dual-gate vertical transistor with increased gate control area and lower leakage current. The gate structure of the dual-gate vertical transistor may include... Figure 16 The two mirror-symmetric gate structures 1610 in the combined semiconductor body 1608 allow two sides in the bit-line direction to contact the gate structure in the dual-gate vertical transistor. On the other hand, by using trench isolation 1616 to divide the dual-gate vertical transistor into a single-gate vertical transistor, the number (and cell density) of memory cells 1602 in the bit-line direction can be doubled compared to the dual-gate vertical transistor without unduly complicating the manufacturing process (e.g., compared to using SADP process).

[0113] Figure 17A cross-sectional side view of yet another 3D memory device 1700 including vertical transistors is shown in accordance with some aspects of the present disclosure. The 3D memory device 1700 can be one example of the memory device 1600 including single-gate vertical transistors, where the gate structure abuts a single side of the semiconductor body in plan view. It should be appreciated that, Figure 17 are for illustrative purposes only and can not necessarily reflect actual device structures (e.g., interconnects). As above with respect to Figure 1A One example of the 3D memory device 100 described above, the 3D memory device 1700 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are joined at a bonded interface 106 between them. As Figure 17 indicated, the first semiconductor structure 102 can include a substrate 1710, which can include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0114] The first semiconductor structure 102 can include a peripheral circuit 1712 on the substrate 1710. In some embodiments, the peripheral circuit 1712 includes a plurality of transistors 1714 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of the transistors 1714) can also be formed on or in the substrate 1710.

[0115] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 1716 above the peripheral circuit 1712 to convey electrical signals to and from the peripheral circuit 1712. The interconnect layer 1716 can include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnect lines and VIA contacts. The interconnect layer 1716 can also include one or more ILD layers in which the interconnect lines and via contacts can be formed. That is, the interconnect layer 1716 can include interconnect lines and via contacts in a plurality of ILD layers. In some embodiments, the peripheral circuit 1712 is coupled to one another by interconnects in the interconnect layer 1716. The interconnects in the interconnect layer 1716 can include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0116] As Figure 17As shown, the first semiconductor structure 102 may further include a bonding layer 1718 at the bonding interface 106 and above the interconnect layer 1716 and the peripheral circuitry 1712. The bonding layer 1718 may include a plurality of bonding contacts 1719 and a dielectric material electrically isolating the bonding contacts 1719. The bonding contacts 1719 may include a conductive material, such as Cu. The remaining region of the bonding layer 1718 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 1719 in the bonding layer 1718 and the surrounding dielectric material may be used for hybrid bonding. Similarly, as... Figure 17 As shown, the second semiconductor structure 104 may also include a bonding layer 1720 at the bonding interface 106 and above the bonding layer 1718 of the first semiconductor structure 102. The bonding layer 1720 may include a plurality of bonding contacts 1721 and a dielectric material electrically isolating the bonding contacts 1721. The bonding contacts 1721 may include a conductive material, such as Cu. The remaining region of the bonding layer 1720 may be formed of a dielectric material (e.g., silicon oxide). The bonding contacts 1721 in the bonding layer 1720 and the surrounding dielectric material may be used for mixed bonding. According to some embodiments, the bonding contacts 1721 contact the bonding contacts 1719 at the bonding interface 106.

[0117] The second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), the bonding interface 106 is disposed between bonding layers 1720 and 1718. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is the location where bonding layers 1720 and 1718 meet and bond. In practice, the bonding interface 106 can be a layer of a certain thickness, comprising the top surface of the bonding layer 1718 of the first semiconductor structure 102 and the bottom surface of the bonding layer 1720 of the second semiconductor structure 104.

[0118] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 1722, which includes bit lines 1723 above the bonding layer 1720 for transmitting electrical signals. The interconnect layer 1722 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 1722 also include local interconnects, such as bit lines 1723 (e.g., Figure 16The interconnect layer 1722 can also include one or more ILD layers in which interconnect lines and via contacts can be formed. Interconnects in the interconnect layer 1722 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers can be formed of dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the peripheral circuitry 1712 includes word line drivers / row decoders coupled to word line contacts in the interconnect layer 1722 through the bond contacts 1721 and 1719 in the bond layers 1720 and 1718 and the interconnect layer 1716. In some embodiments, the peripheral circuitry 1712 includes bit line drivers / column decoders coupled to bit lines 1723 and bit line contacts (if any) in the interconnect layer 1722 through the bond contacts 1721 and 1719 in the bond layers 1720 and 1718 and the interconnect layer 1716.

[0119] In some embodiments, the second semiconductor structure 104 includes a DRAM device in which memory cells are provided in the form of an array of DRAM cells 1724 (e.g., Figure 16 The interconnect layer 1722 including the bit lines 1723 can be disposed between the bond layer 1720 and the array of DRAM cells 1724. It will be appreciated that the array of DRAM cells 1724 can be formed in the bond layer 1720 and the interconnect layer 1722 can be formed over the array of DRAM cells 1724. Figure 17 A cross-section of the 3D memory device 1700 in FIG. 17A can be taken along the bit line direction (y-direction) and a bit line 1723 in the interconnect layer 1722 extending laterally in the y-direction can be coupled to a column of DRAM cells 1724.

[0120] Each DRAM cell 1724 can include a vertical transistor 1726 (e.g., Figure 2 The vertical transistor 1726 can be an example of the vertical transistor 210 in FIG. 2. Each DRAM cell 1724 can also include a capacitor 1728 (e.g., Figure 2 The capacitor 1728 can be an example of the storage cell 212 in FIG. 2. The DRAM cell 1724 can be a 1T1C cell consisting of one transistor and one capacitor. It will be appreciated that the DRAM cell 1724 can be of any suitable construction, such as a 2T1C cell, a 3T1C cell, etc. To better illustrate the vertical transistor 1726, Figure 18 A perspective view of an array of vertical transistors 1726 is shown in accordance with some aspects of the present disclosure. When describing the vertical transistor 1726, the Figure 17 and Figure 18 .

[0121] The vertical transistor 1726 may be a MOSFET for switching a corresponding DRAM cell 1724. In some embodiments, the vertical transistor 1726 includes a vertically (in the z-direction) extending semiconductor body 1730 (i.e., an active region in which a channel may be formed) and a gate structure 1736 contacting one side of the semiconductor body 1730 in the bit line direction (y-direction). As described above, such as in a single-gate vertical transistor, the semiconductor body 1730 may have a cubic or cylindrical shape, and the gate structure 1736 may be adjacent to a single side of the semiconductor body 1730 in a planar view, for example, as... Figure 17 and Figure 18 As shown. According to some embodiments, the gate structure 1736 includes a gate electrode 1734 and a gate dielectric 1732 laterally positioned between the gate electrode 1734 and the semiconductor body 1730 in the bit line direction. In some embodiments, the gate dielectric 1732 is adjacent to one side of the semiconductor body 1730, and the gate electrode 1734 is adjacent to the gate dielectric 1732.

[0122] like Figure 17 and Figure 18 As shown, in some embodiments, the semiconductor body 1730 has two ends (an upper end and a lower end) in the vertical direction (z direction), and at least one end (e.g., Figure 17 and Figure 18 The lower end of the semiconductor body 1730 extends in the vertical direction (z-direction) beyond the gate dielectric 1732 into the ILD layer. In some embodiments, one end of the semiconductor body 1730 (e.g., Figure 17 and Figure 18 The upper end of the gate dielectric 1732 (e.g., the corresponding end of the gate dielectric 1732) and the corresponding end of the gate dielectric 1732 (e.g., Figure 17 and Figure 18 The upper end of the semiconductor body 1730 is flush with the gate electrode 1734. In some embodiments, the two ends (upper end and lower end) of the semiconductor body 1730 extend in the vertical direction (z direction) beyond the gate electrode 1734 into the ILD layer. That is, the semiconductor body 1730 may have a larger vertical dimension (e.g., depth) (e.g., in the z direction) than the gate electrode 1734, and neither the upper end nor the lower end of the semiconductor body 1730 is flush with the corresponding end of the gate electrode 1734. Therefore, short circuits between the bit line 1723 and the word line / gate electrode 1734 or between the word line / gate electrode 1734 and the capacitor 1728 can be avoided. The vertical transistor 1726 may also include a source and a drain (both referred to as 1738 since their positions can be interchanged) respectively disposed in the vertical direction (z direction) at the two ends (upper end and lower end) of the semiconductor body 1730. In some embodiments, one of the source and drain 1738 (e.g., in the z direction) is flush with the gate electrode 1734. Figure 17 and Figure 18 At the upper end of the middle) it is coupled to capacitor 1728, and another of the source and drain 1738 (e.g., in the upper end of the middle) ... Figure 17 and Figure 18 (At the lower end of the middle) Coupled to line 1723.

[0123] In some embodiments, the semiconductor body 1730 comprises a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 1730 may comprise monocrystalline silicon. The source and drain 1738 may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source and drain 1738 and the bit line 1723 or the first electrode 1742 to reduce contact resistance. In some embodiments, the gate dielectric 1732 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 1734 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some embodiments, the gate electrode 1734 includes multiple conductive layers, such as a W layer above a TiN layer, as shown below. Figure 17 and Figure 18 As shown in the diagram. In one example, the gate structure 1736 may be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric 1732 comprises silicon oxide and the gate electrode 1734 comprises doped polysilicon. In another example, the gate structure 1736 may be an HKMG, wherein the gate dielectric 1732 comprises a high-k dielectric and the gate electrode 1734 comprises metal.

[0124] As described above, since the gate electrode 1734 can be a portion of the word line or as part of the word line in the word line direction (e.g., Figure 18 Extending in the x-direction (as in the example), Figure 18 As shown, the second semiconductor structure 104 of the 3D memory device 1700 may also include multiple word lines, each extending in the word line direction (x direction) (e.g., Figure 16An example of word line 1604 (also referred to as 1734). Each word line 1734 can be coupled to a row of DRAM cells 1724. That is, bit line 1723 and word line 1734 can extend in two perpendicular lateral directions, and the semiconductor body 1730 of the vertical transistor 1726 can extend in a vertical direction perpendicular to the two lateral directions along which the bit line 1723 and word line 1734 extend. According to some embodiments, word line 1734 is in contact with word line contacts (not shown). In some embodiments, word line 1734 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, word line 1734 includes multiple conductive layers, such as a W layer above a TiN layer, as... Figure 17 As shown in the image.

[0125] like Figure 17 and Figure 18 As shown, according to some embodiments, the vertical transistor 1726 extends vertically through and contacts the word line 1734, and the source or drain 1738 of the vertical transistor 1726 at its lower end contacts the bit line 1723 (or contacts the bit line contact, if any). Therefore, due to the vertical arrangement of the vertical transistor 1726, the word line 1734 and the bit line 1723 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 1734 and the bit line 1723. In some embodiments, the bit line 1723 is vertically disposed between the bonding layer 1720 and the word line 1734, and the word line 1734 is vertically disposed between the bit line 1723 and the capacitor 1728. Word line 1734 can be coupled to peripheral circuitry 1712 in the first semiconductor structure 102 via word line contacts (not shown) in interconnect layer 1722, bonding contacts 1721 and 1719 in bonding layers 1720 and 1718, and interconnections in interconnect layer 1716. Similarly, bit line 1723 in interconnect layer 1722 can be coupled to peripheral circuitry 1712 in the first semiconductor structure 102 via bonding contacts 1721 and 1719 in bonding layers 1720 and 1718, and interconnections in interconnect layer 1716.

[0126] As mentioned above Figure 16 The vertical transistors 1726 can be arranged in a mirror-symmetric manner to increase the density of DRAM cells 1724 in the bit line direction (y-direction). For example... Figure 17 As shown, according to some embodiments, two adjacent vertical transistors 1726 in the bit line direction are isolated relative to the trench 1760 (e.g., corresponding to...). Figure 16The trench isolations 1616 in the second semiconductor structure 104 are mirror-symmetric to each other. That is, the second semiconductor structure 104 may include a plurality of trench isolations 1760, each trench isolation 1760 extending parallel to word line 1734 in the word line direction (x-direction) and disposed between semiconductor bodies 1730 of adjacent rows of vertical transistors 1726. In some embodiments, the rows of vertical transistors 1726 separated by the trench isolations 1760 are mirror-symmetric to each other with respect to the trench isolations 1760. The trench isolations 1760 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. It should be understood that the trench isolations 1760 may include air gaps, each laterally disposed between adjacent semiconductor bodies 1730. As described below regarding the manufacturing process, air gaps can be formed because the spacing of the vertical transistors 1726 in the bit line direction (e.g., the y-direction) is relatively small. On the other hand, the relatively large dielectric constant of air in the air gap (e.g., about 4 times that of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the isolation effect between the vertical transistors 1726 (and the rows of DRAM cells 1724). Similarly, in some embodiments, air gaps are also formed laterally between the word lines / gate electrodes 1734 in the bit line direction, depending on the spacing of the word line / gate electrodes 1734 in the bit line direction.

[0127] like Figure 17 As shown, in some embodiments, capacitor 1728 includes a first electrode 1742 above and in contact with the source or drain 1738 of vertical transistor 1726 (e.g., the upper end of semiconductor body 1730). Capacitor 1728 may also include a capacitor dielectric 1744 above and in contact with the first electrode 1742, and a second electrode 1746 above and in contact with the capacitor dielectric 1744. That is, capacitor 1728 may be a vertical capacitor, wherein electrodes 1742 and 1746 and capacitor dielectric 1744 are stacked vertically (in the z-direction), and capacitor dielectric 1744 may be sandwiched between electrodes 1742 and 1746. In some embodiments, each first electrode 1742 is coupled to the source or drain 1738 of a corresponding vertical transistor 1726 in the same DRAM cell, while all second electrodes 1746 are portions of a common plate (e.g., common ground) coupled to ground. Figure 17As shown, the second semiconductor structure 104 may further include capacitor contacts 1747 that contact a common plate of the second electrode 1746 for coupling the second electrode 1746 of the capacitor 1728 to a peripheral circuit 1712 or directly to ground. In some embodiments, the ILD layer forming the capacitor 1728 has the same dielectric material, such as silicon oxide, as the two ILD layers into which the semiconductor body 1730 extends.

[0128] It should be understood that the structure and construction of capacitor 1728 are not limited to... Figure 17 Examples are provided, and any suitable structure and construction may be included, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-planar capacitors. In some embodiments, capacitor dielectric 1744 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 1728 may be a ferroelectric capacitor used in FRAM cells, and capacitor dielectric 1744 may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, electrodes 1742 and 1746 comprise conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0129] like Figure 17 As shown, according to some embodiments, the vertical transistor 1726 extends vertically through and contacts the word line 1734. The source or drain 1738 of the vertical transistor 1726 at its lower end contacts the bit line 1723, and the source or drain 1738 of the vertical transistor 1726 at its upper end contacts the electrode 1742 of the capacitor 1728. That is, due to the vertical arrangement of the vertical transistor 1726, the bit line 1723 and the capacitor 1728 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 1726 of the DRAM cell 1724. In some embodiments, the bit line 1723 and the capacitor 1728 are arranged on opposite sides of the vertical transistor 1726 in the vertical direction. Compared to conventional DRAM cells where the bit line and capacitor are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 1723 and reduces the coupling capacitance between the bit line 1723 and the capacitor 1728.

[0130] like Figure 17As shown, in some embodiments, the vertical transistor 1726 is disposed vertically between the capacitor 1728 and the bonding interface 106. That is, the vertical transistor 1726 can be arranged closer to the peripheral circuitry 1712 of the first semiconductor structure 102 and the bonding interface 106 than the capacitor 1728. As the bit line 1723 and the capacitor 1728 are coupled to opposite ends of the vertical transistor 1726, as described above, according to some embodiments, the bit line 1723 (as part of the interconnect layer 1722) is disposed vertically between the vertical transistor 1726 and the bonding interface 106. As a result, the interconnect layer 1722 including the bit line 1723 can be arranged proximate to the bonding interface 106 to reduce interconnect routing distance and complexity.

[0131] In some embodiments, the second semiconductor structure 104 further includes a substrate 1748 disposed above the DRAM cell 1724. As described below with respect to the fabrication process, the substrate 1748 can be part of a carrier wafer. It should be appreciated that in some examples, the substrate 1748 can not be included in the second semiconductor structure 104.

[0132] As Figure 17The second semiconductor structure 104 can also include a substrate 1748 and a pad-out interconnect layer 1750 over the DRAM cells 1724, as shown. The pad-out interconnect layer 1750 can include interconnects in one or more ILD layers, such as contact pads 1754. The pad-out interconnect layer 1750 and the interconnect layer 1722 can be formed on opposite sides of the DRAM cells 1724. According to some embodiments, a capacitor 1728 is disposed vertically between the vertical transistor 1726 and the pad-out interconnect layer 1750. In some embodiments, the interconnects in the pad-out interconnect layer 1750 can carry electrical signals between the 3D memory device 1700 and external circuitry, such as for pad-out purposes. In some embodiments, the second semiconductor structure 104 also includes one or more contacts 1752 that extend through portions of the pad-out interconnect layer 1750 and the substrate 1748 to couple the pad-out interconnect layer 1750 to the DRAM cells 1724 and the interconnect layer 1722. As a result, the peripheral circuitry 1712 can be coupled to the DRAM cells 1724 through the interconnect layers 1716 and 1722 and the bonding layers 1720 and 1718, and the peripheral circuitry 1712 and the DRAM cells 1724 can be coupled to external circuitry through the contacts 1752 and the pad-out interconnect layer 1750. The contact pads 1754 and the contacts 1752 can include electrically conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contact pads 1754 can include Al and the contacts 1752 can include W. In some embodiments, the contacts 1752 include vias surrounded by a dielectric spacer (e.g., with silicon oxide) to electrically separate the vias from the substrate 1748. Depending on the thickness of the substrate 1748, the contacts 1752 can be ILVs with sub-micron (e.g., between 10 nm and 1 pm) depths, or TSVs with micron or tens-of-micron (e.g., between 1 pm and 100 pm) depths.

[0133] Although not shown, it should be appreciated that pad-out of the 3D memory device is not limited to from the Figure 17 second semiconductor structure 104 shown with the DRAM cells 1724, and can be from the first semiconductor structure 102 with the peripheral circuitry 1712 in a similar manner as described above with respect to Figure 6B Although not shown, it should also be appreciated that the air gaps between the word lines 1734 and / or between the semiconductor bodies 1730 can be partially or completely filled with a dielectric in a similar manner as described above with respect to Figure 6E Although not shown, it should also be appreciated that more than one array of DRAM cells 1724 can be stacked on top of each other to vertically scale the number of DRAM cells 1724 in a similar manner as described above with respect to Figure 7 ​

[0134] As described above, in some examples, trenches isolation 1616 extending in the word line direction in Figure 16 may be formed such that two adjacent semiconductor bodies 1608 separated by respective trench isolation 1616 can be merged into a single semiconductor body having two opposite sides in the bit line direction that are in contact with gate structures 1610. That is, in the absence of trench isolation 1616, adjacent single-gate vertical transistors can be merged to form a double-gate vertical transistor (e.g., a double-sided gate vertical transistor) having increased gate control area and lower leakage current. For example, Figure 20 A plan view of an array of yet another memory cell 2002 each including a vertical transistor in a memory device 2000 according to some aspects of the present disclosure is shown. As Figure 20 indicated, memory device 2000 can include a plurality of word lines 2004 each extending in a first lateral direction (x-direction, referred to as a word line direction). Memory device 2000 can also include a plurality of bit lines 2006 each extending in a second lateral direction (y-direction, referred to as a bit line direction) perpendicular to the first lateral direction. It will be appreciated that Figure 20 a cross-section of memory device 2000 in the same lateral plane is not shown, and word lines 2004 and bit lines 2006 can be formed in different lateral planes to facilitate wiring, as described in detail below.

[0135] Memory cells 2002 can be formed at intersections of word lines 2004 and bit lines 2006. In some implementations, each memory cell 2002 includes a vertical transistor (e.g., vertical transistor 210 in Figure 2 ) having a semiconductor body 2008 and a gate structure 2010. Semiconductor body 2008 can extend in a substrate in a vertical direction (z-direction, not shown) perpendicular to the first and second lateral directions. The vertical transistor can be a double-gate transistor in which gate structure 2010 is in contact with two sides (e.g., two of the four sides in Figure 20 ) of semiconductor body 2008 (in which an active region forming a channel is formed). As Figure 20As shown, the vertical transistor is a dual gate transistor in which the gate structure 2010 abuts two opposite sides (having a rectangular or square shape in cross-section) of the semiconductor body 1608 in the bit line direction (y direction) in plan view. According to some embodiments, the gate structure 2010 does not surround and contact the other two sides of the semiconductor body 2008 in the word line direction (x direction). That is, the gate structure 2010 can partially circumscribe the semiconductor body 2008 in plan view. The gate structure 2010 can include a gate dielectric 2012 that abuts two opposite sides of the semiconductor body 2008 in plan view, and a gate electrode 2014 in contact with the gate dielectric 2012. In some embodiments, the gate dielectric 2012 laterally between the gate electrode 2014 and the semiconductor body 2008 in the bit line direction (y direction). As noted above, the gate electrode 2014 can be part of the word line 2004, and the word line 2004 can be an extension of the gate electrode 2014. That is, the gate electrodes 1614 of vertically transistors adjacent in the word line direction (x direction) are continuous, e.g., are part of a continuous conductive layer having the gate electrodes 1614 and 1604.

[0136] Unlike the separate gate dielectrics 512 and 812 in Figure 5 and Figure 8 , as shown in Figure 20 , the gate dielectrics 2012 of vertically transistors adjacent in the word line direction are continuous, e.g., are part of a continuous dielectric layer having the gate dielectrics 2012 and extending in the word line direction. The gate structure 2010 can thus be viewed as part of a continuous structure extending in the word line direction in which the continuous structure intersects vertically transistors in the same row.

[0137] Figure 21 A side view showing a cross-section of yet another 3D memory device 2100 including vertical transistors is shown, according to some aspects of the present disclosure. The 3D memory device 2100 can be one example of the memory device 2000 including dual gate vertical transistors in which the gate structure abuts two sides of the semiconductor body in plan view. It should be understood that Figure 21 is for illustrative purposes only, and can not necessarily reflect actual device structures (e.g., interconnects). As one example of the 3D memory device 100 described above with respect to Figure 1A , the 3D memory device 2100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are joined at a bonding interface 106 between them. As Figure 21As shown, the first semiconductor structure 102 may include a substrate 2110, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0138] The first semiconductor structure 102 may include peripheral circuitry 2112 on substrate 2110. In some embodiments, peripheral circuitry 2112 includes a plurality of transistors 2114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors 2114) may also be formed on or in substrate 2110.

[0139] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 2116 above the peripheral circuitry 2112 for transmitting electrical signals to and from the peripheral circuitry 2112. The interconnect layer 2116 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and VIA contacts. The interconnect layer 1716 may also include one or more ILD layers, in which interconnects and via contacts may be formed. That is, the interconnect layer 2116 may include interconnects and via contacts in multiple ILD layers. In some embodiments, the peripheral circuitry 2112 is coupled to each other via interconnects in the interconnect layer 2116. The interconnects in the interconnect layer 2116 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0140] like Figure 21 As shown, the first semiconductor structure 102 may further include a bonding layer 2118 at the bonding interface 106 and above the interconnect layer 2116 and the peripheral circuitry 2112. The bonding layer 2118 may include a plurality of bonding contacts 2119 and a dielectric material electrically isolating the bonding contacts 2119. The bonding contacts 2119 may include a conductive material, such as Cu. The remaining region of the bonding layer 2118 may be formed of a dielectric material (e.g., silicon oxide). The bonding contacts 2119 in the bonding layer 2118 and the surrounding dielectric material may be used for hybrid bonding. Similarly, as... Figure 21As shown, the second semiconductor structure 104 can also include a bonding layer 2120 at the bonding interface 106 and over the bonding layer 2118 of the first semiconductor structure 102. The bonding layer 2120 can include a plurality of bonding contacts 2121 and a dielectric that electrically isolates the bonding contacts 2121. The bonding contacts 2121 can include a conductive material, such as Cu. The remaining areas of the bonding layer 2120 can be formed of a dielectric material, such as silicon oxide. The bonding contacts 2121 and surrounding dielectric in the bonding layer 2120 can be used for hybrid bonding. According to some embodiments, the bonding contacts 2121 contact the bonding contacts 2119 at the bonding interface 106.

[0141] The second semiconductor structure 104 can be bonded on top of the first semiconductor structure 102 in a face-to-face manner at the bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 2120 and 2118 as a result of hybrid bonding, also referred to as "metal / dielectric hybrid bonding," which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer, such as solder or adhesive) and can achieve both metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, the bonding interface 106 is where the bonding layers 2120 and 2118 meet and bond. In effect, the bonding interface 106 can be a layer with a thickness that includes a top surface of the bonding layer 2118 of the first semiconductor structure 102 and a bottom surface of the bonding layer 2120 of the second semiconductor structure 104.

[0142] In some embodiments, the second semiconductor structure 104 also includes an interconnect layer 2122 that includes bit lines 2123 over the bonding layer 2120 to convey electrical signals. The interconnect layer 2122 can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 2122 also include local interconnects, such as the bit lines 2123 (e.g., Figure 20The interconnect layer 2122 can also include one or more ILD layers in which interconnect lines and via contacts can be formed. Interconnects in the interconnect layer 2122 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers can be formed of dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the peripheral circuitry 2112 includes word line drivers / row decoders coupled to word line contacts in the interconnect layer 2122 through the bond contacts 2121 and 2119 in the bond layers 2120 and 2118 and the interconnect layer 2116. In some embodiments, the peripheral circuitry 2112 includes bit line drivers / column decoders coupled to bit lines 2123 and bit line contacts (if any) in the interconnect layer 2122 through the bond contacts 2121 and 2119 in the bond layers 2120 and 2118 and the interconnect layer 2116.

[0143] In some embodiments, the second semiconductor structure 104 includes a DRAM device in which memory cells are provided in the form of an array of DRAM cells 2124 (e.g., examples of memory cells 2002 in Figure 20 The interconnect layer 2122 including the bit lines 2123 can be disposed between the bond layer 2120 and the array of DRAM cells 2124. It will be appreciated that the array of DRAM cells 2124 can be disposed on the bond layer 2120 and the interconnect layer 2122 can be disposed on the array of DRAM cells 2124. Figure 21 A cross-section of the 3D memory device 2100 in the x-direction can be taken along the bit line direction (y-direction) and a bit line 2123 in the interconnect layer 2122 extending laterally in the y-direction can be coupled to a column of DRAM cells 2124.

[0144] Each DRAM cell 2124 can include a vertical transistor 2126 (e.g., examples of vertical transistors 210 in Figure 2 a capacitor 2128 (e.g., examples of memory cells 212 in Figure 2 The DRAM cells 2124 can be 1T1C cells consisting of one transistor and one capacitor. It will be appreciated that the DRAM cells 2124 can be of any suitable construction, such as 2T1C cells, 3T1C cells, etc.

[0145] The vertical transistors 2126 can be MOSFETs for switching the respective DRAM cells 2124. In some embodiments, the vertical transistors 2126 include a semiconductor body 2130 (i.e., an active region in which a channel can be formed) extending vertically (in the z-direction) and a gate structure 2136 in contact with two opposite sides of the semiconductor body 2130 in the bit line direction (y-direction). As described above, as in a dual-gate vertical transistor, the semiconductor body 2130 can have a cuboid shape or a cylindrical shape, and the gate structure 2136 can abut two sides of the semiconductor body 2130 in a plan view, e.g., as shown in FIG. 21A. According to some embodiments, the gate structure 2136 includes a gate electrode 2134 and a gate dielectric 2132 laterally between the gate electrode 2134 and the semiconductor body 2130 in the bit line direction. In some embodiments, the gate dielectric 2132 abuts the two sides of the semiconductor body 2130, and the gate electrode 2134 abuts the gate dielectric 2132. Figure 21 As shown in FIG. 21B, according to some embodiments, the gate dielectric 2132 does not abut the two sides of the semiconductor body 2130, and the gate electrode 2134 abuts the gate dielectric 2132. In some embodiments, the gate dielectric 2132 does not abut the two sides of the semiconductor body 2130, and the gate electrode 2134 does not abut the gate dielectric 2132.

[0146] As shown in FIG. 21C, according to some embodiments, the gate dielectric 2132 does not abut the two sides of the semiconductor body 2130, and the gate electrode 2134 does not abut the gate dielectric 2132. Figure 21 As shown in FIG. 21C, according to some embodiments, the gate dielectric 2132 does not abut the two sides of the semiconductor body 2130, and the gate electrode 2134 does not abut the gate dielectric 2132. Figure 21 In some embodiments, the semiconductor body 2130 has two ends (an upper end and a lower end) in the vertical direction (z-direction), and at least one end (e.g., the lower end in Figure 21 In some embodiments, one end of the semiconductor body 2130 (e.g., the upper end in Figure 21 In some embodiments, both ends of the semiconductor body 2130 (the upper end and the lower end) extend beyond the gate electrode 2134 into the ILD layer in the vertical direction (z-direction), respectively. That is, the semiconductor body 2130 can have a larger vertical dimension (e.g., depth) (e.g., in the z-direction) than that of the gate electrode 2134, and neither the upper end nor the lower end of the semiconductor body 2130 is flush with the respective end of the gate electrode 2134. Thus, short circuits between the bit line 2123 and the word line / gate electrode 2134 or between the word line / gate electrode 2134 and the capacitor 2128 can be avoided. The vertical transistor 2126 can also include a source and a drain (which can be interchangeable in terms of their positions and thus both referred to as 2138) disposed at the two ends (the upper end and the lower end) of the semiconductor body 2130 in the vertical direction (z-direction), respectively. In some embodiments, one of the source and the drain 2138 (e.g., at the upper end in Figure 21 In some embodiments, one of the source and the drain 2138 (e.g., at the upper end in Figure 21 In some embodiments, the other of the source and the drain 2138 (e.g., at the lower end in

[0147] In some embodiments, the semiconductor body 2130 includes a semiconductor material, such as single crystalline silicon, poly crystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 2130 can include single crystalline silicon. The source and drain 2138 can be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source and drain 2138 and the bit line 2123 or the first electrode 2142 to reduce contact resistance. In some embodiments, the gate dielectric 2132 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to AI2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 2134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, poly silicon, silicide, or any combination thereof. In some embodiments, the gate electrode 2134 includes multiple conductive layers, such as a W layer on top of a TiN layer. In one example, the gate structure 2136 can be a "gate oxide / gate poly" gate, where the gate dielectric 2132 includes silicon oxide and the gate electrode 2134 includes doped poly silicon. In another example, the gate structure 2136 can be HKMG, where the gate dielectric 2132 includes a high-k dielectric and the gate electrode 2134 includes a metal.

[0148] As described above, since the gate electrode 2134 can be part of or extend in the word line direction as a word line, the second semiconductor structure 104 of the 3D memory device 2100 can also include a plurality of word lines (e.g., 2004 in FIG. 2) each extending in the word line direction, also referred to as 2134. Each word line 2134 can be coupled to a row of DRAM cells 2124. That is, the bit lines 2123 and the word lines 2134 can extend in two perpendicular lateral directions, and the semiconductor body 2130 of the vertical transistor 2126 can extend in a vertical direction perpendicular to the two lateral directions along which the bit lines 2123 and the word lines 2134 extend. According to some embodiments, the word lines 2134 are in contact with word line contacts (not shown). In some embodiments, the word lines 2134 include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, poly silicon, silicide, or any combination thereof. In some embodiments, the word lines 2134 include multiple conductive layers, such as a W layer on top of a TiN layer. Figure 20 As described above, since the gate electrode 2134 can be part of or extend in the word line direction as a word line, the second semiconductor structure 104 of the 3D memory device 2100 can also include a plurality of word lines (e.g., 2004 in FIG. 2) each extending in the word line direction, also referred to as 2134. Each word line 2134 can be coupled to a row of DRAM cells 2124. That is, the bit lines 2123 and the word lines 2134 can extend in two perpendicular lateral directions, and the semiconductor body 2130 of the vertical transistor 2126 can extend in a vertical direction perpendicular to the two lateral directions along which the bit lines 2123 and the word lines 2134 extend. According to some embodiments, the word lines 2134 are in contact with word line contacts (not shown). In some embodiments, the word lines 2134 include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, poly silicon, silicide, or any combination thereof. In some embodiments, the word lines 2134 include multiple conductive layers, such as a W layer on top of a TiN layer.

[0149] Figure 21 ​As shown, according to some embodiments, the vertical transistors 2126 vertically extend through and contact the word lines 2134, and the source or drain 2138 of the vertical transistors 2126 at their lower end contacts the bit line 2123 (or bit line contact, if any). Thus, due to the vertical arrangement of the vertical transistors 2126, the word lines 2134 and the bit lines 2123 can be disposed in different planes in the vertical direction, which simplifies the routing of the word lines 2134 and the bit lines 2123. In some embodiments, the bit lines 2123 are disposed vertically between the bonding layer 2120 and the word lines 2134, and the word lines 2134 are disposed vertically between the bit lines 2123 and the capacitors 2128. The word lines 2134 can be coupled to the peripheral circuitry 2112 in the first semiconductor structure 102 through word line contacts in the interconnect layer 2122, bonding contacts 2121 and 2119 in the bonding layers 2120 and 2118, and interconnects in the interconnect layer 2116. Similarly, the bit lines 2123 in the interconnect layer 2122 can be coupled to the peripheral circuitry 2112 in the first semiconductor structure 102 through bonding contacts 2121 and 2119 in the bonding layers 2120 and 2118, and interconnects in the interconnect layer 2116.

[0150] In some embodiments, the second semiconductor structure 104 further includes a plurality of air gaps 2140 each disposed laterally between adjacent word lines 2134. Each air gap 2140 can be a trench extending in parallel with the word lines 2134 in the word line direction (e.g., x-direction) to separate adjacent rows of vertical transistors 2126. As described below with respect to the fabrication process, the air gaps 2140 can be formed due to the relatively small pitch of the word lines 2134 (and rows of DRAM cells 2124) in the bit line direction (e.g., y-direction). On the other hand, the relatively large dielectric constant of air (e.g., about 4 times that of silicon oxide) in the air gaps 2140 compared to some dielectrics (e.g., silicon oxide) can improve the insulating effect between the word lines 2134 (and rows of DRAM cells 2124).

[0151] As Figure 21As shown, in some embodiments, the capacitor 2128 includes a first electrode 2142 over and in contact with a source or drain 2138 of a vertical transistor 2126 (e.g., an upper end of a semiconductor body 2130). The capacitor 2128 can also include a capacitor dielectric 2144 over and in contact with the first electrode 2142, and a second electrode 2146 over and in contact with the capacitor dielectric 2144. That is, the capacitor 2128 can be a vertical capacitor, with the electrodes 2142 and 2146 and the capacitor dielectric 2144 stacked vertically (in the z-direction), and the capacitor dielectric 2144 can be sandwiched between the electrodes 2142 and 2146. In some embodiments, each first electrode 2142 is coupled to a source or drain 2138 of a respective vertical transistor 2126 in the same DRAM cell, while all second electrodes 2146 are part of a common plate (e.g., a common ground) coupled to ground. As Figure 21 As shown, the second semiconductor structure 104 can also include a capacitor contact 2147 in contact with the common plate of the second electrodes 2146, for coupling the second electrodes 2146 of the capacitor 2128 to the peripheral circuit 2112 or directly to ground. In some embodiments, where the ILD layer forming the capacitor 2128 has the same dielectric material as the two ILD layers into which the semiconductor body 2130 extends, e.g., silicon oxide.

[0152] It will be appreciated that the structure and configuration of the capacitor 2128 is not limited to the example in Figure 21 and can include any suitable structure and configuration, such as a planar capacitor, a stacked capacitor, a multi-finned capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. In some embodiments, the capacitor dielectric 2144 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to AI2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It will be appreciated that in some examples, the capacitor 2128 can be a ferroelectric capacitor used in FRAM cells, and the capacitor dielectric 2144 can be replaced by a ferroelectric layer with a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrodes 2142 and 2146 include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0153] As Figure 21As shown, according to some embodiments, the vertical transistor 2126 extends vertically through and contacts the word line 2134, the source or drain 2138 of the vertical transistor 2126 at its lower end directly or through a bit line contact contacts the bit line 2123, and the source or drain 2138 of the vertical transistor 2126 at its upper end contacts the electrode 2142 of the capacitor 2128. That is, due to the vertical arrangement of the vertical transistor 2126, the bit line 2123 and the capacitor 2128 can be disposed in different planes in the vertical direction and coupled to opposite ends of the vertical transistor 2126 of the DRAM cell 2124 in the vertical direction. In some embodiments, the bit line 2123 and the capacitor 2128 are disposed on opposite sides of the vertical transistor 2126 in the vertical direction, which simplifies the routing of the bit line 2123 and reduces the coupling capacitance between the bit line 2123 and the capacitor 2128 compared to conventional DRAM cells in which the bit line and the capacitor are disposed on the same side of the planar transistor.

[0154] As Figure 21 shown, in some embodiments, the vertical transistor 2126 is disposed vertically between the capacitor 2128 and the bonding interface 106. That is, the vertical transistor 2126 can be arranged closer to the bonding interface 106 and the peripheral circuitry 2112 of the first semiconductor structure 102 than the capacitor 2128. As described above, according to some embodiments, due to the bit line 2123 and the capacitor 2128 being coupled to opposite ends of the vertical transistor 2126, the bit line 2123 (as part of the interconnect layer 2122) is disposed vertically between the vertical transistor 2126 and the bonding interface 106. As a result, the interconnect layer 2122 including the bit line 2123 can be arranged close to the bonding interface 106 to reduce interconnect routing distance and complexity.

[0155] In some embodiments, the second semiconductor structure 104 further includes a substrate 2148 disposed above the DRAM cell 2124. As described below with respect to the fabrication process, the substrate 2148 can be part of a carrier wafer. It should be appreciated that in some examples, the substrate 2148 can not be included in the second semiconductor structure 104.

[0156] As Figure 21As shown, the second semiconductor structure 104 can also include a substrate 2148 and a pad-out interconnect layer 2150 over the DRAM cells 2124. The pad-out interconnect layer 2150 can include interconnects in one or more ILD layers, e.g., contact pads 2154. The pad-out interconnect layer 2150 and the interconnect layer 2122 can be formed on opposite sides of the DRAM cells 2124. According to some embodiments, the capacitors 2128 are disposed vertically between the vertical transistors 2126 and the pad-out interconnect layer 2150. In some embodiments, the interconnects in the pad-out interconnect layer 2150 can carry electrical signals between the 3D memory device 2100 and external circuitry, e.g., for pad-out purposes. In some embodiments, the second semiconductor structure 104 also includes one or more contacts 2152 that extend through the substrate 2148 and portions of the pad-out interconnect layer 2150 to couple the pad-out interconnect layer 2150 to the DRAM cells 2124 and the interconnect layer 2122. As a result, the peripheral circuitry 2112 can be coupled to the DRAM cells 2124 through the interconnect layers 2116 and 2122 and the bonding layers 2120 and 2118, and the peripheral circuitry 2112 and the DRAM cells 2124 can be coupled to external circuitry through the contacts 2152 and the pad-out interconnect layer 2150. The contact pads 2154 and the contacts 2152 can include electrically conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contact pads 2154 can include Al and the contacts 2152 can include W. In some embodiments, the contacts 2152 include vias surrounded by a dielectric spacer, e.g., with silicon oxide, to electrically separate the vias from the substrate 2148. Depending on the thickness of the substrate 2148, the contacts 2152 can be ILVs with sub-micron, e.g., between 10 nm and 1 pm, depths, or TSVs with micron or tens-of-micron, e.g., between 1 pm and 100 pm, depths.

[0157] Although not shown, it should be appreciated that pad-out of a 3D memory device is not limited to as Figure 21 shown from the second semiconductor structure 104 with DRAM cells 2124, and can be from the first semiconductor structure 102 with peripheral circuitry 2112 in a similar manner as described above with respect to Figure 6B Although not shown, it should be appreciated that the air gaps between the word lines 2134 can be partially or completely filled with a dielectric in a similar manner as described above with respect to Figure 6E Although not shown, it should be appreciated that more than one array of DRAM cells 2124 can be stacked on top of each other to vertically scale the number of DRAM cells 2124 in a similar manner as described above with respect to Figure 7 ​

[0158] Figure 27 A block diagram illustrating a system 2700 having a memory device in accordance with some aspects of the present disclosure is shown. The system 2700 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic device having a storage. As Figure 27 shown, the system 2700 can include a host 2708 and a memory system 2702 having one or more memory devices 2704 and a memory controller 2706. The host 2708 can be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 2708 can be configured to send data to or receive data from the memory device 2704.

[0159] The memory device 2704 can be any memory device disclosed herein, such as the 3D memory devices 100 and 101, the memory devices 200, 500, 800, 1600, and 2000, and the 3D memory devices 600, 601, 603, 605, 607, 700, 900, 1700, and 2100. In some implementations, the memory device 2704 includes an array of memory cells, each memory cell including a vertical transistor, as described in detail above.

[0160] According to some embodiments, a memory controller 2706 is coupled to the memory device 2704 and the host 2708 and is configured to control the memory device 2704. The memory controller 2706 can manage data stored in the memory device 2704 and communicate with the host 2708. The memory controller 2706 can be configured to control operations of the memory device 2704, such as read, write, and refresh operations. The memory controller 2706 can also be configured to manage various functions related to data stored or to be stored in the memory device 2704, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the memory controller 2706 is also configured to determine the maximum memory capacity, the number of memory banks, the memory type and speed, the memory grain data depth and data width, and other important parameters that the computer system can use. Any other suitable functions can also be performed by the memory controller 2706. The memory controller 2706 can communicate with external devices (e.g., the host 2708) according to a particular communication protocol. For example, the memory controller 2706 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, and the like.

[0161] Figures 10A-10M A manufacturing process for forming a 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure. Figures 11A-11I A manufacturing process for forming another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure. Figures 12A-12H A manufacturing process for forming yet another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure. Figures 13A-13H A manufacturing process for forming still another 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure. Figures 14A-14EA flowchart of a method 2300 for forming a 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure. Figures 15A-15D A flowchart of a method 2300 for forming a 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure. Figures 19A-19M A flowchart of a method 2300 for forming a 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure. Figures 22A-22M A flowchart of a method 2300 for forming a 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure. Figure 23 A flowchart of a method 2300 for forming a 3D memory device including vertical transistors is shown in accordance with some aspects of the present disclosure. Figures 10A-10M An example of a 3D memory device depicted in FIG. 1 includes Figure 6A and Figure 6B A 3D memory device 600 and 601 depicted in FIG. 6. Figures 11A-11I An example of a 3D memory device depicted in FIG. 1 includes Figure 9 A 3D memory device 900 depicted in FIG. 9. Figures 12A-12H An example of a 3D memory device depicted in FIG. 1 includes Figure 6C A 3D memory device 603 depicted in FIG. 6. Figures 13A-13H An example of a 3D memory device depicted in FIG. 1 includes Figure 6D A 3D memory device 605 depicted in FIG. 6. Figures 14A-14E and 15A- Figure 15D An example of a 3D memory device depicted in FIG. 1 includes Figure 7 A 3D memory device 700 depicted in FIG. 7. Figures 19A-19M An example of a 3D memory device depicted in FIG. 1 includes Figure 17 A 3D memory device 1700 depicted in FIG. 17. Figure 22A-22M An example of a 3D memory device depicted in FIG. 1 includes Figure 21 A 3D memory device 2100 depicted in FIG. 21. Together Figures 10A-10M , Figures 11A-11I , Figures 12A-12H , Figures 13A-13H , Figures 14A-14E , Figures 15A-15D , Figures 19A-19M , Figures 22A-22M and Figure 23 It should be understood that the operations shown in the method 2300 are not exhaustive and that other operations can be performed before, after, or in between any of the shown operations. Moreover, some operations can be performed concurrently, or in a different order than shown. Figure 23

[0162] In some embodiments, a first semiconductor structure including a peripheral circuit is formed. As Figure 10L ​or Figure 19L As depicted, a first semiconductor structure is formed that includes a peripheral circuit. In some embodiments, a second semiconductor structure is formed that includes a first array of memory cells and a plurality of bit lines coupled to the memory cells. Each of the memory cells can include a vertical transistor and a storage cell coupled to the vertical transistor. A respective one of the bit lines and the respective storage cell are coupled perpendicularly to opposite ends of each of the memory cells. As Figure 10L 、 Figure 11I 、 Figure 12H 、 Figure 13H 、 Figure 19L or Figure 22L As depicted, a second semiconductor structure is formed that includes an array of DRAM cells, each of the DRAM cells including a vertical transistor and a capacitor coupled to the vertical transistor. The second semiconductor structure also includes a plurality of bit lines coupled to the memory cells, and a respective one of the bit lines and a respective storage cell are coupled perpendicularly to opposite ends in each of the memory cells. In some embodiments, the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face fashion such that the first array of memory cells is coupled to the peripheral circuit through a bonding interface. As Figure 10L and Figure 10M 、 Figure 19L or Figure 22L As depicted, the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face fashion such that the array of DRAM cells is coupled to the peripheral circuit through a bonding interface.

[0163] Referring to Figure 23 , the method 2300 begins at operation 2302, where a peripheral circuit is formed on a first substrate. The first substrate can include a silicon substrate. In some embodiments, an interconnect layer is formed over the peripheral circuit. The interconnect layer can include a plurality of interconnects in one or more ILD layers.

[0164] As shown in Figure 10L , a plurality of transistors 1042 are formed on a silicon substrate 1038. The transistors 1042 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1038 by ion implantation and / or thermal diffusion, for example, to serve as the source and drain of the transistors 1042. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1038 by wet / dry etching and thin film deposition. The transistors 1042 can form a peripheral circuit 1040 on the silicon substrate 1038.

[0165] As Figure 10L illustrated, an interconnect layer 1044 can be formed over the peripheral circuit 1040 with transistors 1042. The interconnect layer 1044 can include MEOL interconnects and / or BEOL interconnects in multiple ILD layers to electrically connect with the peripheral circuit 1040. In some embodiments, the interconnect layer 1044 includes multiple ILD layers and interconnects formed therein with multiple processes. For example, the interconnects in the interconnect layer 1044 can include conductive material deposited by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. The fabrication processes to form the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers can include dielectric material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Figure 10L The ILD layers and interconnects illustrated in FIG. 10B can be collectively referred to as the interconnect layer 1044.

[0166] The method 2300 proceeds to operation 2304, as Figure 23 illustrated, where a first bonding layer is formed over the peripheral circuit (and interconnect layer). The first bonding layer can include first bonding contacts. As Figure 10L illustrated, a bonding layer 1046 is formed over the interconnect layer 1044 and the peripheral circuit 1040. The bonding layer 1046 can include a plurality of bonding contacts 1047 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on a top surface of the interconnect layer 1044 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Then, by first patterning a contact hole through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer), the bonding contacts 1047 can be formed through the dielectric layer and to the interconnects in the interconnect layer 1044. The contact hole can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact hole includes depositing a barrier layer, an adhesion layer, and / or a seed layer prior to depositing the conductor.

[0167] The method 2300 proceeds to operation 2306, as Figure 23As shown, an array of memory cells is formed on a second substrate, each memory cell including a vertical transistor and a storage cell. The second substrate can include a carrier substrate. The storage cell can include a capacitor or a PCM element. In some embodiments, the capacitor is formed to be coupled to the vertical transistor in the corresponding memory cell.

[0168] For example, Figure 24 A flow diagram of a method 2400 for forming an array of memory cells each including a vertical transistor is shown in accordance with some aspects of the present disclosure. In Figure 24 At operation 2402 in, a stack of dielectric layers is formed on a substrate. In some embodiments, to form the stack of dielectric layers, three layers of a first dielectric, a second dielectric, and a first dielectric are subsequently deposited on the substrate. The first dielectric can include silicon oxide, and the second dielectric can include silicon nitride. The layer with the second dielectric can be used as a sacrificial layer that is vertically sandwiched between two layers with the first dielectric. The sacrificial layer can be removed by selective etching with respect to the two layers with the first dielectric, and replaced with a conductive layer in a subsequent process.

[0169] As shown in Figure 10A A stack of a silicon oxide layer 1004, a silicon nitride layer 1006, and a silicon oxide layer 1008 is formed on a silicon substrate 1002. To form the dielectric stack, silicon oxide, silicon nitride, and silicon oxide are subsequently deposited onto the silicon substrate 1002 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments, the silicon oxide layer 1004 is formed by oxidizing a top portion of the silicon substrate 1002 using dry oxidation and / or wet oxidation (e.g., in-situ steam generation (ISSG) oxidation process). In some embodiments, the thickness of the silicon oxide layer 1004 (e.g., ISSG silicon oxide) is less than the thickness of the silicon oxide layer 1008 (e.g., CVD silicon oxide). Figure 10A A side view (in Figure 10A a top portion of ) and a plan view (in Figure 10A a bottom portion of ). The same layout of drawings is also arranged in Figures 10B-10G

[0170] In Figure 24 ​At operation 2404, a semiconductor body is formed from a stack extending vertically through the dielectric layer from the substrate. In some embodiments, to form the semiconductor body, an opening extending through the dielectric layer of the stack is etched to expose a portion of the substrate, and the semiconductor body is epitaxially grown from the exposed portion of the substrate in the opening.

[0171] like Figure 10B As shown, an array of openings 1010 is formed, each opening extending perpendicularly (in the z-direction) through the stack of silicon oxide layer 1008, silicon nitride layer 1006, and silicon oxide layer 1004 to reach silicon substrate 1002. As a result, portions of silicon substrate 1002 can be exposed from the openings 1010. In some embodiments, for example based on word line and bit line designs, a photolithography process is performed to pattern the array of openings 1010 using an etch mask (e.g., a photoresist mask), and one or more dry etching and / or wet etching processes (e.g., reactive ion etching (RIE)) are performed to etch the openings 1010 through silicon oxide layer 1008, silicon nitride layer 1006, and silicon oxide layer 1004 until stopped by silicon substrate 1002.

[0172] like Figure 10C As shown, an array of semiconductor bodies 1012 is formed in the opening 1010. The semiconductor bodies 1012 can be epitaxially grown from the corresponding exposed portions of the silicon substrate 1002 in the respective openings 1010. The fabrication process for epitaxially growing the semiconductor bodies 1012 can include, but is not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combination thereof. Epitaxy can proceed upwards (towards the positive z-direction) from the exposed portions of the silicon substrate 1002 in the openings 1010. The semiconductor bodies 1012 can therefore have the same material as the silicon substrate 1002, i.e., single-crystal silicon. Depending on the shape of the opening 1010, the semiconductor bodies 1012 can have the same shape as the opening 1010, such as a cubic or cylindrical shape. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess portions of the semiconductor bodies 1012 that extend beyond the top surface of the silicon oxide layer 1008. As a result, according to some embodiments, an array of semiconductor bodies 1012 (e.g., single-crystal silicon bodies) is thus formed, extending vertically (in the z-direction) from the silicon substrate 1002 through a stack of silicon oxide layers 1008, silicon nitride layers 1006 and silicon oxide layers 1004.

[0173] exist Figure 24At operation 2406, a dielectric layer in the stack of dielectric layers is removed to expose a portion of the semiconductor body. In some embodiments, to remove a dielectric layer in the stack of dielectric layers, a trench is etched through at least a portion of the stack of dielectric layers to expose a layer having a second dielectric, and the layer having the second dielectric (e.g., a sacrificial layer) is etched away via the trench. In some embodiments, trenches are etched between adjacent rows of semiconductor bodies without contacting any sidewalls of the semiconductor bodies.

[0174] like Figure 10D As shown, a plurality of trenches 1014 (slot openings) are formed to expose a silicon nitride layer 1006. Each trench 1014 extends laterally along the word line direction (x-direction) and vertically through at least a silicon oxide layer 1008 and a silicon nitride layer 1006. As a result, portions of the silicon nitride layer 1006 can be exposed from the trenches 1014. In some embodiments, such as based on the word line (word line trench) design, a photolithography process is performed to pattern the trenches 1014 using an etch mask (e.g., a photoresist mask). Figure 10D As shown, trench 1014 is patterned to form between adjacent rows of semiconductor bodies 1012 without contacting any side of the semiconductor bodies 1012, such that the semiconductor bodies 1012 are not exposed from any of their sides. In one example, trench 1014 is patterned to form in the middle between adjacent rows of semiconductor bodies 1012, i.e., two adjacent rows of semiconductor bodies 1012 with the same distance. In some embodiments, one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch trench 1014 through silicon oxide layer 1008, silicon nitride layer 1006, and silicon oxide layer 1004 until it is stopped by silicon substrate 1002. It should be understood that in some examples, etching of trench 1014 may not continue to the silicon substrate 1002, but may stop at silicon oxide layer 1004, as long as silicon nitride layer 1006 is exposed from trench 1014.

[0175] like Figure 10E As shown, the silicon nitride layer 1006 (as shown) is removed. Figure 10DAs shown in the diagram, this exposes a portion of the adjacent silicon nitride layer 1006 of the semiconductor body 1012. In some embodiments, the silicon nitride layer 1006 is etched away via trench 1014. For example, a wet etchant comprising phosphoric acid can be applied through trench 1014 to selectively wet etch the silicon nitride layer 1006 without etching the silicon oxide layers 1004 and 1008, as well as the semiconductor body 1012 and the silicon substrate 1002. As a result, a lateral groove 1016 can be formed vertically between the silicon oxide layers 1004 and 1008, thereby exposing a portion of the semiconductor body 1012. As shown in the plan view, all sides of each semiconductor body 1012 can be exposed from the lateral groove 1016.

[0176] exist Figure 24 At operation 2408, a gate structure is formed that contacts multiple sides of the exposed portion of the semiconductor body. In some embodiments, to form the gate structure, a gate dielectric is formed on the exposed portion of the semiconductor body, a conductive layer is deposited on the gate dielectric, and the conductive layer is patterned to form a gate electrode on the gate dielectric.

[0177] like Figure 10F As shown, a gate dielectric 1018 is formed over the exposed portion of each semiconductor body 1012, i.e., surrounding and contacting all sides of the exposed portion of the semiconductor body 1012. As shown in the plan view, the gate dielectric 1018 may be completely external to the respective semiconductor body 1012. In some embodiments, wet oxidation and / or dry oxidation processes (e.g., ISSG) are performed to form a native oxide (e.g., silicon oxide) on the semiconductor body 1012 (e.g., single-crystal silicon) as the gate dielectric 1018. In some embodiments, the gate dielectric 1018 is formed by depositing a dielectric layer (e.g., silicon oxide) over the exposed portion of the semiconductor body 1012 through trenches 1014 and lateral recesses 1016 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) without filling the lateral recesses 1016 and trenches 1014.

[0178] like Figure 10G As shown, through the groove 1014 in the transverse groove 1016 ( Figure 10FA conductive layer 1020 is formed over the gate dielectric 1018 (as shown). In some embodiments, the conductive layer 1020 is formed by depositing a conductive material (e.g., a metal or a metal compound (e.g., TiN)) over the gate dielectric 1018 through the trenches 1014 to fill the lateral recesses 1016 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In one example, the deposition of the conductive layer 1020 is controlled to not fill the trenches 1014. It should be appreciated that in some examples, the deposition of the conductive layer 1020 can also fill the trenches 1014. Accordingly, a planarization process (e.g., CMP) can be performed to remove excess conductive layer 1020 on the top surface of the silicon oxide layer 1008, and the conductive layer 1020 can be patterned to form gate electrodes over the respective gate dielectrics. For example, the trenches 1014 filled with the conductive layer 1020 can also be patterned and etched to separate the conductive layer 1020 between the semiconductor bodies 1012 and the gate dielectrics 1018 of adjacent rows. As described above, a lithography process can be performed to pattern the trenches 1014 also using an etch mask (e.g., a photoresist mask), for example, based on the design of the word lines (word line trenches).

[0179] As a result, the patterned conductive layer 1020 can become word lines, each extending in the word line direction (x-direction) and separated by adjacent trenches 1014, and the portions of the patterned conductive layer 1020 over the gate dielectrics 1018 (e.g., fully circumscribing the respective gate dielectrics 1018 in plan view) can become gate electrodes. Thereby, gate structures can be formed, each including a respective gate dielectric 1018 over an exposed portion of a semiconductor body 1012 and a respective gate electrode (i.e., a portion of the conductive layer 1020) over the gate dielectric 1018. As Figure 10G As shown, according to some embodiments, since the conductive layer 1020 remains on all sides of the semiconductor bodies 1012 (and the gate dielectrics 1018 thereon) when the conductive layer 1020 is patterned (the trenches 1014 are etched), the gate structures are in contact with all sides of the semiconductor bodies 1012. As shown in plan view, the gate structures (with the gate dielectrics 1018 and the gate electrodes) can fully circumscribe the respective semiconductor bodies 1012, and all sides of each semiconductor body 1012 can be surrounded by and in contact with the respective gate structure. It is noted that Figure 10G In comparison, according to some embodiments, Figure 10A the silicon nitride layer 1006 (sacrificial layer) in Figure 10A is ultimately replaced by Figure 10G the conductive layer 1020 in

[0180] In Figure 24At operation 2410, the first end of the semiconductor body, far from the substrate, is doped. For example... Figure 10G As shown, the exposed upper end of each semiconductor body 1012 (i.e., one of the two ends of the semiconductor body 1012 that is away from the silicon substrate 1002 in the vertical direction (z-direction)) is doped to form a source / drain 1021. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1012 to form the source / drain 1021. In some embodiments, a silicide layer is formed on the source / drain 1021 by performing a silicide process at the exposed upper end of the semiconductor body 1012.

[0181] exist Figure 24 At operation 2412, a memory cell is formed in contact with a semiconductor substrate (e.g., its doped first end). The memory cell may include a capacitor or a PCM element. In some embodiments, to form a memory cell that is a capacitor, a first electrode is formed on the doped first end of the semiconductor substrate, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric.

[0182] like Figure 10H As shown, for example, one or more ILD layers are formed on the top surface of the silicon oxide layer 1008 by depositing a dielectric using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). It should be understood that in some examples where the ILD layer comprises silicon oxide (the same material as the silicon oxide layer 1008), the boundary and interface between the ILD layer and the silicon oxide layer 1008 may become indistinguishable after deposition. This depends on the lateral dimensions of the trench 1014 (e.g., ...). Figure 10G As shown, when the ILD layer is formed, trench 1014 may not be completely filled by a dielectric (e.g., silicon oxide), and thus become an air gap 1022 between adjacent word lines (patterned conductive layer 1020). It should be understood that in some examples, when the lateral dimension of trench 1014 is large enough, the dielectric can completely fill trench 1014 during ILD layer formation, thereby eliminating air gap 1022.

[0183] like Figure 10HAs shown, a first electrode 1024, a capacitor dielectric 1026, and a second electrode 1028 are subsequently formed in the ILD layer to form a capacitor in contact with the semiconductor body 1012. In some embodiments, each first electrode 1024 is formed on the corresponding source / drain 1021 (i.e., the doped upper end of the corresponding semiconductor body 1012) by patterning and etching electrode holes aligned with the corresponding source / drain 1021 using photolithography and etching processes, and by depositing conductive material to fill the electrode holes using a thin-film deposition process. Similarly, in some embodiments, the second electrode 1028 is formed on the capacitor dielectric 1026 by patterning and etching electrode holes aligned with the corresponding capacitor dielectric 1026 using photolithography and etching processes, and by depositing conductive material to fill the electrode holes using a thin-film deposition process.

[0184] exist Figure 24 At operation 2414, the substrate is removed to expose the second end of the semiconductor body opposite the first end. For example... Figure 10I As shown, a carrier substrate 1030 (also known as a processing substrate) is bonded to the front side of a silicon substrate 1002, and a device is formed on the front side of the silicon substrate 1002 using any suitable bonding process (e.g., anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the silicon substrate 1002 is above the carrier substrate 1030.

[0185] like Figure 10J As shown, the silicon substrate 1002 is removed ( Figure 10I (As shown) to expose the undoped upper end of the semiconductor body 1012 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1002 until the upper end of the silicon oxide layer 1004 and the semiconductor body 1012 are removed.

[0186] exist Figure 24 At operation 2416, the exposed second end of the doped semiconductor body. For example... Figure 10J As shown, the exposed upper end of each semiconductor body 1012 (i.e., one of the two ends of the semiconductor body 1012 that is away from the carrier substrate 1030 in the vertical direction (z-direction)) is doped to form another source / drain 1023. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1012 to form the source / drain 1023. In some embodiments, a silicide layer is formed on the source / drain 1023 by performing a silicide process at the exposed upper end of the semiconductor body 1012. As a result, as Figure 10JAs shown, according to some embodiments, a vertical transistor having the semiconductor body 1012, the source / drain 1021 and 1023, the gate dielectric 1018, and the gate electrode (a portion of the conductive layer 1020) is thereby formed. As noted above, as Figure 10J As shown, according to some embodiments, a capacitor having the first and second electrodes 1024 and 1028 and the capacitor dielectric 1026 is also thereby formed, and a DRAM cell 1080 having the multi-gate vertical transistor and the capacitor coupled to the multi-gate vertical transistor is thereby formed.

[0187] Referring back to Figure 23 , the method 2300 proceeds to operation 2308, as Figure 23 shown, where an interconnect layer including bit lines is formed over the array of memory cells. As Figure 10K shown, the interconnect layer 1032 can be formed over the DRAM cell 1080. The interconnect layer 1032 can include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers to make electrical connections with the DRAM cell 1080. In some embodiments, the interconnect layer 1032 includes a plurality of ILD layers and interconnects formed therein in a plurality of processes. For example, the interconnects in the interconnect layer 1032 can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes to form the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof on the silicon oxide layer 1004. Figure 10K The ILD layers and interconnects shown in FIG. 11 can be collectively referred to as the interconnect layer 1032.

[0188] As Figure 24 shown, at operation 2418, to form the interconnect layer, a bit line is formed on the doped second end portion. As Figure 10K shown, the bit line 1034 can be formed on the source / drain 1023 by patterning and etching a trench aligned with the respective source / drain 1023 using photolithography and etching processes, and depositing a conductive material to fill the trench using a thin film deposition process. As a result, the bit line 1034 and the capacitor having the electrodes 1024 and 1028 and the capacitor dielectric 1026 can be formed on opposite sides of the semiconductor body 1012 and coupled to opposite end portions of the semiconductor body 1012. It will be appreciated that additional local interconnects, such as word line contacts 1039, capacitor contacts 1083, and bit line contacts 1041 can also be similarly formed.

[0189] The method 2300 proceeds to operation 2310, as Figure 23As shown, a second bonding layer is formed above the memory cell array and the interconnect layer. The second bonding layer may include second bonding contacts. Figure 10K As shown, a bonding layer 1036 is formed over the interconnect layer 1032 and the DRAM cell 1080. The bonding layer 1036 may include a plurality of bonding contacts 1037 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of the interconnect layer 1032 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be first patterned using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts 1037 that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1032. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0190] Method 2300 proceeds to operation 2312, such as Figure 23 As shown, a first semiconductor structure and a second semiconductor structure are bonded face-to-face, such that a first memory cell array is coupled to peripheral circuitry via the bonding interface. Bonding may include hybrid bonding. In some embodiments, after bonding, the first bonding contacts and the second bonding contacts make contact at the bonding interface. In some embodiments, the second semiconductor structure is positioned above the first semiconductor structure after bonding. In some embodiments, the first semiconductor structure is positioned above the second semiconductor structure after bonding.

[0191] like Figure 10L As shown, the carrier substrate 1030 and the components formed thereon (e.g., DRAM cell 1080) are flipped upside down. Figure 10M As shown, the downward-facing bonding layer 1036 is bonded to the upward-facing bonding layer 1046 (i.e., face-to-face), thereby forming a bonding interface 1050. In some embodiments, a processing technique, such as plasma treatment, wet processing, and / or heat treatment, is applied to the bonding surfaces prior to bonding. Although Figure 10L and Figure 10MThe silicon substrate 1038 and components formed thereon (e.g., the peripheral circuitry 1040) can be flipped upside down, and the downward-facing bonding layer 1046 can be bonded with the upward-facing bonding layer 1036 (i.e., in a face-to-face manner) to form a bonding interface 1050 therefrom. After bonding, the bonding contacts 1037 in the bonding layer 1036 and the bonding contacts 1047 in the bonding layer 1046 are aligned and in contact with one another, such that the DRAM cells 1080 can be electrically connected to the peripheral circuitry 1040 via the bonding interface 1050. It can be appreciated that in the bonded chip, the DRAM cells 1080 can be above or below the peripheral circuitry 1040. However, after bonding, the bonding interface 1050 can be formed vertically between the peripheral circuitry 1040 and the DRAM cells 1080.

[0192] The method 2300 proceeds to operation 2314, where a pad-out interconnect layer is formed on a backside of the first semiconductor structure or the second semiconductor structure. As shown in Figure 23 Figure 10M The pad-out interconnect layer 1052 can include interconnects formed in one or more ILD layers, such as pad contacts 1054. The pad contacts 1054 can include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, after bonding, contacts 1056 are formed that extend vertically through the carrier substrate 1030, such as by a wet / dry etching process, followed by deposition of a conductive material. The contacts 1056 can be in contact with the interconnects in the pad-out interconnect layer 1052. It should be appreciated that in some examples, the carrier substrate 1030 can be thinned or removed after bonding and before forming the pad-out interconnect layer 1052 and the contacts 1056, such as using a planarization process and / or an etching process.

[0193] Although not shown, it should be appreciated that in some examples, the pad-out interconnect layer 1052 can be formed on a backside of the silicon substrate 1038, and the contacts 1056 can be formed to extend vertically through the silicon substrate 1038. The silicon substrate 1038 can be thinned before forming the pad-out interconnect layer 1052 and the contacts 1056, such as using a planarization process and / or an etching process.

[0194] As described above, Figures 10A-10M A fabrication process is shown to form a DRAM array with vertical transistors, where the gate structure is in contact with all sides of the semiconductor body, i.e., a GAA transistor. As shown in Figures 11A-11I ​In some of the embodiments shown, a DRAM array with vertical transistors is formed with a relatively large word line pitch and reduced manufacturing complexity by changing the layout of the word line trenches, wherein the gate structure contacts some sides (e.g., three of the four sides) of the semiconductor body.

[0195] like Figure 11A As shown, a stack of silicon oxide layer 1104, silicon nitride layer 1106, and silicon oxide layer 1108 is formed on silicon substrate 1102. To form the dielectric stack, silicon oxide, silicon nitride, and silicon oxide are subsequently deposited onto silicon substrate 1102 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). In some embodiments, silicon oxide layer 1104 is formed by oxidizing the top portion of silicon substrate 1102 using dry oxidation and / or wet oxidation (e.g., ISSG oxidation process). In some embodiments, the thickness of silicon oxide layer 1104 (e.g., ISSG silicon oxide) is less than the thickness of silicon oxide layer 1108 (e.g., CVD silicon oxide). Besides... Figure 11A Outside the side view of the cross-section along the y-direction (e.g., the bit line direction) shown in the top portion, Figure 11A The bottom portion also shows a plan view of the cross-section in the xy plane passing through the silicon nitride layer 1106. Figures 11B-11E The same drawing layout was also used in the middle.

[0196] like Figure 11B As shown, an array of semiconductor bodies 1112 is formed, each semiconductor body 1112 extending vertically through a stack of silicon oxide layer 1108, silicon nitride layer 1106, and silicon oxide layer 1104. The semiconductor bodies 1112 can be epitaxially grown from corresponding exposed portions of a silicon substrate 1102 in corresponding openings (not shown). The fabrication process for epitaxially growing the semiconductor bodies 1112 can include, but is not limited to, VPE, LPE, MPE, or any combination thereof. Epitaxy can proceed upwards (towards the positive z-direction) from the exposed portions of the silicon substrate 1102 in the openings. The semiconductor bodies 1112 can therefore have the same material as the silicon substrate 1102, i.e., monocrystalline silicon. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess portions of the semiconductor bodies 1112 extending beyond the top surface of the silicon oxide layer 1108. As a result, according to some embodiments, an array of semiconductor bodies 1112 (e.g., single-crystal silicon bodies) is thus formed, extending vertically (in the z-direction) from the silicon substrate 1102 through a stack of silicon oxide layers 1108, silicon nitride layers 1106 and silicon oxide layers 1104.

[0197] In some implementations, in Figure 24At operation 2406, a portion of a dielectric layer in the stack of dielectric layers is removed to expose a portion of the semiconductor body. In some embodiments, to remove a dielectric layer in the stack of dielectric layers, a trench is etched through at least a portion of the stack of dielectric layers to expose a layer having a second dielectric, and the layer having the second dielectric (e.g., a sacrificial layer) is etched away via the trench. In some embodiments, the trench is etched to align with a side of the semiconductor body to expose the semiconductor body from that side.

[0198] like Figure 11C As shown, a plurality of trenches 1114 (slot openings) are formed to expose the silicon nitride layer 1106. Each trench 1114 extends laterally along the word line direction (x-direction) and vertically through at least the silicon oxide layer 1108 and the silicon nitride layer 1106. As a result, portions of the silicon nitride layer 1106 can be exposed from the trenches 1114. In some embodiments, for example, based on the design of the word lines (word line trenches), a photolithography process is performed to pattern the trenches 1114 using an etch mask (e.g., a photoresist mask). Figure 11C As shown, according to some embodiments, trench 1114 is patterned to form between adjacent rows of semiconductor bodies 1112 and aligned with one side of the semiconductor body 1112 to expose the semiconductor body 1112 from that side. That is, trench 1114 may be patterned to contact one side of the semiconductor body 1112, such that the semiconductor body 1112 is exposed from that side. In some embodiments, one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch trench 1114 through silicon oxide layer 1108, silicon nitride layer 1106, and silicon oxide layer 1104 until it is stopped by silicon substrate 1102. It should be understood that in some examples, etching of trench 1114 may not continue to the silicon substrate 1102, but may stop at silicon oxide layer 1104, as long as silicon nitride layer 1106 is exposed from trench 1114.

[0199] like Figure 11D As shown, the silicon nitride layer 1106 is removed. Figure 11C (As shown) to expose a portion of the adjacent silicon nitride layer 1106 of the semiconductor body 1112. In some embodiments, the silicon nitride layer 1106 is etched away via trench 1114. For example, the silicon nitride layer 1106 can be selectively wet-etched by applying a wet etchant including phosphoric acid through trench 1114, without etching the silicon oxide layers 1104 and 1108, as well as the semiconductor body 1112 and the silicon substrate 1102. As a result, a lateral groove 1116 can be formed vertically between the silicon oxide layers 1104 and 1108, thereby exposing a portion of the semiconductor body 1112.

[0200] like Figure 11DAs shown, the gate dielectric 1118 is formed over the exposed portions of each semiconductor body 1112, i.e., surrounding and contacting all sides of the exposed portions of the semiconductor body 1112. As shown in plan view, the gate dielectric 1118 can completely circumscribe the corresponding semiconductor body 1112. In some embodiments, a wet oxidation and / or dry oxidation process (e.g., ISSG) is performed to form a native oxide (e.g., silicon oxide) over the semiconductor body 1112 (e.g., single crystalline silicon) as the gate dielectric 1118. In some embodiments, the gate dielectric 1118 is formed by depositing a dielectric layer (e.g., silicon oxide) over the exposed portions of the semiconductor body 1112 through the trenches 1114 and lateral recesses 1116 without filling the lateral recesses 1116 and trenches 1114 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0201] In contrast, Figure 10F In contrast, Figure 10F In contrast, Figure 11D In contrast, Figure 11D In contrast,

[0202] As shown, the conductive layer 1120 is formed over the lateral recesses 1116 through the trenches 1114, as shown in cross-sectional view in FIG. 11B and in plan view in FIG. 11C. In some embodiments, the conductive layer 1120 is formed by depositing a conductive layer (e.g., tungsten) over the exposed portions of the semiconductor body 1112 through the trenches 1114 and lateral recesses 1116 without filling the lateral recesses 1116 and trenches 1114 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Figure 11E Figure 11D ​over the gate dielectric 1118, but not over the elongated gate dielectric portions 1119. In some embodiments, the conductive layer 1120 is formed by depositing a conductive material (e.g., a metal or a metal compound (e.g., TiN)) over the gate dielectric 1118 through the trenches 1114 to fill the lateral recesses 1116 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In one example, the deposition of the conductive layer 1120 is controlled so as not to fill the trenches 1114 (and not over the elongated gate dielectric portions 1119). It should be appreciated that in some examples, the deposition of the conductive layer 1120 can also fill the trenches 1114. Accordingly, a planarization process (e.g., CMP) can be performed to remove excess conductive layer 1120 over the top surface of the silicon oxide layer 1108, and the conductive layer 1120 can be patterned to form gate electrodes only over the gate dielectric 1118 and not over the elongated gate dielectric portions 1119. For example, the trenches 1114 filled with the conductive layer 1120 can also be patterned and etched to separate the conductive layer 1120 between adjacent rows of semiconductor bodies 1112 and the gate dielectric 1118. As described above, for example, based on the design of the word lines (word line trenches), a photolithography process can be performed to pattern the trenches 1114 also using an etch mask (e.g., a photoresist mask).

[0203] As a result, the patterned conductive layer 1120 can become word lines, each extending in the word line direction (x-direction) and separated by adjacent trenches 1114, and the portions of the patterned conductive layer 1120 over the gate dielectric 1118 and not over the elongated gate dielectric portions 1119 can become gate electrodes. Thereby, gate structures can be formed, each including a respective gate dielectric 1118 over an exposed portion of the semiconductor body 1112 and a respective gate electrode (i.e., a portion of the conductive layer 1120) over the gate dielectric 1118. As Figure 11E As shown, according to some embodiments, since the conductive layer 1120 is only left on some sides of the semiconductor body 1012 (and the gate dielectric 1018 thereover) when the conductive layer 1120 is patterned (the trenches 1114 are etched), the gate structures are in contact with some sides, but not all sides, of the semiconductor body 1012. As shown in the plan view, the gate structures (with the gate dielectric 1118 and the gate electrode) can partially circumscribe the respective semiconductor body 1112, and not all sides of each semiconductor body 1112 can be surrounded and in contact by the respective gate structure. In contrast, as shown in the plan view of the example of FIG. 1, the gate structures (with the gate dielectric 1018 and the gate electrode) can circumscribe the respective semiconductor body 1012, and all sides of each semiconductor body 1012 can be surrounded and in contact by the respective gate structure. Figure 10G In contrast to the pitch of the word lines 1020 in the example of FIG. 1, Figure 11E The pitch of the word lines 1120 can be increased to reduce manufacturing complexity.

[0204] As Figure 11E As shown, the exposed upper end of each semiconductor body 1112 (i.e., one of the two ends of the semiconductor body 1112 that is away from the silicon substrate 1102 in the vertical direction (z-direction)) is doped to form a source / drain 1121. In some embodiments, an implantation process and / or a thermal diffusion process are performed to dope a P-type dopant or an N-type dopant onto the exposed upper end of the semiconductor body 1112 to form a source / drain 1021.

[0205] like Figure 11F As shown, for example, a dielectric is deposited on the top surface of the silicon oxide layer 1108 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) to form one or more ILD layers. It should be understood that in some examples where the ILD layer comprises silicon oxide (the same material as the silicon oxide layer 1108), the boundary and interface between the ILD layer and the silicon oxide layer 1108 may become indistinguishable after deposition. This is because trench 1114 (compared to trench 1014) Figure 11E The relatively large lateral dimensions (as a result of the larger spacing of word lines 1120) of the trench 1114, when the ILD layer is formed, allow the trench 1114 to be completely or at least partially filled with a dielectric (e.g., silicon oxide), and thus eliminate or at least reduce the air gap 1022 between adjacent word lines (patterned conductive layer 1120).

[0206] like Figure 11F As shown, a first electrode 1124, a capacitor dielectric 1126, and a second electrode 1128 are subsequently formed in the ILD layer to form a capacitor in contact with the semiconductor body 1112. In some embodiments, each first electrode 1124 is formed on the corresponding source / drain 1121 (i.e., the doped upper end of the corresponding semiconductor body 1112) by patterning and etching electrode holes aligned with the corresponding source / drain 1121 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process. Similarly, in some embodiments, the second electrode 1128 is formed on the capacitor dielectric 1126 by patterning and etching electrode holes aligned with the corresponding capacitor dielectric 1126 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process.

[0207] like Figure 11G As shown, a carrier substrate 1130 (also known as a processing substrate) is bonded to the front side of a silicon substrate 1102, and a device is formed on the front side of the silicon substrate 1102 using any suitable bonding process (e.g., anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the silicon substrate 1102 is above the carrier substrate 1130.

[0208] like Figure 11H As shown, the silicon substrate 1102 is removed ( Figure 11G As shown), to expose the undoped upper end of the semiconductor body 1112 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1102 until the upper end of the semiconductor body 1112 is covered by the silicon oxide layer 1104 and the silicon body 1112.

[0209] like Figure 11H As shown, the exposed upper end of each semiconductor body 1112 (i.e., one of the two ends of the semiconductor body 1112 that is away from the carrier substrate 1130 in the vertical direction (z-direction)) is doped to form another source / drain 1123. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1112 to form the source / drain 1123. As a result, as Figure 11H As shown, according to some embodiments, a multi-gate vertical transistor is thus formed having a semiconductor body 1112, source / drain electrodes 1121 and 1123, a gate dielectric 1118 (excluding the extended gate dielectric portion 1119), and a gate electrode (a portion of the conductive layer 1120). As described above, as... Figure 11H As shown, according to some embodiments, capacitors each having a first electrode 1124 and a second electrode 1128 and a capacitor dielectric 1126 are thus formed, and DRAM cells 1180 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are thus formed.

[0210] like Figure 11I As shown, an interconnect layer 1132 can be formed above the DRAM cell 1180. The interconnect layer 1132 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers to form an electrical connection with the DRAM cell 1180. In some embodiments, the interconnect layer 1132 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1132 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1104 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 11I The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1132. For example... Figure 11IAs shown, trenches aligned with the corresponding source / drain 1123 can be patterned and etched using photolithography and etching processes, and conductive material can be deposited using thin film deposition processes to fill the trenches, forming bit lines 1134 on the source / drain 1123.

[0211] like Figure 11I As shown, a bonding layer 1136 is formed over interconnect layer 1132 and DRAM cell 1180. Bonding layer 1136 may include a plurality of bonding contacts 1137 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of interconnect layer 1132 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be first patterned using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts 1137 that penetrate the dielectric layer and contact the interconnects in interconnect layer 1132. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0212] As mentioned above, Figures 10A-10M A fabrication process for forming a DRAM cell array from a three-layer dielectric stack is illustrated, the three-layer dielectric stack having a sacrificial layer (e.g., silicon nitride layer 1006) sandwiched between two dielectric layers (e.g., silicon oxide layers 1004 and 1008). It should be understood that in other examples, the construction of the dielectric stack forming the DRAM cell array can be varied, resulting in DRAM cells with different structures, for example in... Figure 6C and Figure 6D In the 3D memory devices 603 and 605. In such Figures 12A-12H In some of the embodiments shown, the DRAM cell array is formed by a two-layer dielectric stack having a sacrificial layer on the dielectric layer.

[0213] exist Figure 24 At operation 2402, a stack of dielectric layers is formed on the substrate. In some embodiments, to form the stack of dielectric layers, two layers having a first dielectric and a second dielectric, respectively, are subsequently deposited on the substrate. The first dielectric may include silicon oxide, and the second dielectric may include silicon nitride. The layer having the second dielectric can be used as a sacrificial layer on the layer having the first dielectric. The sacrificial layer can be removed by selective etching relative to the other layer having the first dielectric, and the sacrificial layer can be replaced with a conductive layer in subsequent processes.

[0214] like Figure 12AAs shown, a stack of silicon oxide layer 1204 and silicon nitride layer 1206 is formed on silicon substrate 1202. To form the dielectric stack, silicon oxide and silicon nitride are subsequently deposited onto silicon substrate 1202 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). In some embodiments, the top portion of silicon substrate 1202 is oxidized using dry oxidation and / or wet oxidation (e.g., in-situ vapor generation (ISSG) oxidation process) to form silicon oxide layer 1204.

[0215] like Figure 12B As shown, an array of semiconductor bodies 1212 is formed, each semiconductor body 1212 extending vertically through a stack of silicon nitride layers 1206 and silicon oxide layers 1204. The semiconductor bodies 1212 can be epitaxially grown from corresponding exposed portions of a silicon substrate 1202 in corresponding openings (not shown). The fabrication process for epitaxially growing the semiconductor bodies 1212 can include, but is not limited to, VPE, LPE, MPE, or any combination thereof. Epitaxy can proceed upwards (towards the positive z-direction) from the exposed portions of the silicon substrate 1202 in the openings. The semiconductor bodies 1212 can therefore have the same material as the silicon substrate 1202, i.e., monocrystalline silicon. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess portions of the semiconductor bodies 1212 extending beyond the top surface of the silicon nitride layer 1206. As a result, according to some embodiments, an array of semiconductor bodies 1212 (e.g., monocrystalline silicon bodies) extending vertically (in the z-direction) through a stack of silicon nitride layers 1206 and silicon oxide layers 1204 from the silicon substrate 1202 is thus formed.

[0216] like Figure 12C As shown, a plurality of trenches 1214 (slot openings) are formed to expose a silicon nitride layer 1206. Each trench 1214 extends laterally along the word line direction (x-direction) and vertically through at least the silicon nitride layer 1206. As a result, portions of the silicon nitride layer 1206 can be exposed from the trenches 1214. In some embodiments, for example based on a word line (word line trench) design, a photolithography process is performed to pattern the trenches 1214 using an etching mask (e.g., a photoresist mask). In some embodiments, one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch the trenches 1214 through the silicon nitride layer 1206 and the silicon oxide layer 1204 until stopped by the silicon substrate 1202. It should be understood that in some examples, the etching of the trenches 1214 may not reach the silicon substrate 1202 and may stop at the silicon oxide layer 1204, as long as the silicon nitride layer 1206 is exposed from the trenches 1214.

[0217] like Figure 12D As shown, the silicon nitride layer 1206 is removed. Figure 12CAs shown), to expose a portion of the adjacent silicon nitride layer 1206 of the semiconductor body 1212. In some embodiments, the silicon nitride layer 1206 is etched away via trench 1214. For example, a wet etchant comprising phosphoric acid can be applied through trench 1214 to selectively wet etch the silicon nitride layer 1206 without etching the silicon oxide layer 1204, the semiconductor body 1212, and the silicon substrate 1202. As a result, a lateral groove 1216 is formed to expose a portion of the semiconductor body 1212. It should be understood that in some examples, the top surface of the silicon nitride layer 1206 can be exposed, so that trench 1214 is not required to remove the silicon nitride layer 1206. Dry etching and / or wet etching processes can be applied directly to the silicon nitride layer 1206 to remove the silicon nitride layer 1206 (i.e., from...). Figure 12B Directly to Figure 12D Without going through Figure 12C ).

[0218] like Figure 12D As shown, the gate dielectric 1218 is formed over the exposed portion of each semiconductor body 1212, i.e., surrounding and contacting all sides of the exposed portion of the semiconductor body 1212. In some embodiments, wet oxidation and / or dry oxidation processes (e.g., ISSG) are performed to form a native oxide (e.g., silicon oxide) on the semiconductor body 1212 (e.g., single-crystal silicon) as the gate dielectric 1218. In some embodiments, the gate dielectric 1218 is formed by depositing a dielectric layer (e.g., silicon oxide) over the exposed portion of the semiconductor body 1212 through trenches 1214 and lateral recesses 1216 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) without filling the lateral recesses 1216 and trenches 1214. Since the silicon oxide layer 1008 is omitted, the upper end of the gate dielectric 1218 can be flush with the upper end of the semiconductor body 1212, as shown. Figure 12D As shown, while Figure 10F The upper end of the middle gate dielectric 1018 is below the upper end of the semiconductor body 1012.

[0219] like Figure 12E As shown, through the groove 1214 in the transverse groove 1216 ( Figure 12DA conductive layer 1220 is formed over the gate dielectric 1218 (as shown). In some embodiments, the conductive layer 1220 is formed by depositing a conductive material (e.g., a metal or a metal compound (e.g., TiN)) over the gate dielectric 1218 through the trenches 1214 to fill the lateral recesses 1216 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In one example, the deposition of the conductive layer 1220 is controlled to not fill the trenches 1214. It should be appreciated that in some examples, the deposition of the conductive layer 1220 can also fill the trenches 1214. Accordingly, a planarization process (e.g., CMP) can be performed to remove excess conductive layer 1220 to expose the upper end portions of the semiconductor bodies 1212, and the conductive layer 1220 can be patterned to form gate electrodes over the respective gate dielectrics. For example, the trenches 1214 filled with the conductive layer 1220 can also be patterned and etched to separate the conductive layer 1220 between adjacent rows of semiconductor bodies 1212 and gate dielectrics 1218. As described above, a photolithography process can be performed to pattern the trenches 1214 also using an etch mask (e.g., a photoresist mask), for example, based on the design of the word lines (word line trenches). As a result of omitting the silicon oxide layer 1008, the top surfaces of the conductive layer 1220 (including the gate electrodes and the word lines) can be flush with the upper end portions of the semiconductor bodies 1212, as shown, while the top surfaces of the word lines 1020 are below the upper end portions of the semiconductor bodies 1012 in Figure 12E Figure 10G

[0220] As a result, the patterned conductive layer 1220 can become word lines, each extending in the word line direction (x-direction) and separated by adjacent trenches 1214, and the portions of the patterned conductive layer 1220 over the gate dielectrics 1218 (e.g., fully circumscribing the respective gate dielectrics 1218 in plan view) can become gate electrodes. Thereby, gate structures can be formed, each including a respective gate dielectric 1218 over an exposed portion of the semiconductor bodies 1212 and a respective gate electrode (i.e., a portion of the conductive layer 1220) over the gate dielectric 1218. In comparison with Figure 12E Figure 12A Figure 12A Figure 12E

[0221] As a result, the patterned conductive layer 1220 can become word lines, each extending in the word line direction (x-direction) and separated by adjacent trenches 1214, and the portions of the patterned conductive layer 1220 over the gate dielectrics 1218 (e.g., fully circumscribing the respective gate dielectrics 1218 in plan view) can become gate electrodes. Thereby, gate structures can be formed, each including a respective gate dielectric 1218 over an exposed portion of the semiconductor bodies 1212 and a respective gate electrode (i.e., a portion of the conductive layer 1220) over the gate dielectric 1218. In comparison with Figure 12E ​​​​​​As shown, the exposed upper portion of each semiconductor body 1212 (i.e., one of the two ends of the semiconductor body 1212 that is away from the silicon substrate 1202 in the vertical direction (z-direction)) is doped to form a source / drain 1221. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper portion of the semiconductor body 1212 to form the source / drain 1221.

[0222] like Figure 12F As shown, for example, a dielectric is deposited on the top surface of the conductive layer 1220 by means of one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) to form one or more ILD layers. Depending on the lateral dimensions of the trench 1214 (e.g., ...), Figure 12E As shown, when the ILD layer is formed, trench 1214 may not be completely filled with a dielectric (e.g., silicon oxide), and thus become an air gap 1222 between adjacent word lines (patterned conductive layer 1220). It should be understood that in some examples, when the lateral dimension of trench 1214 is large enough, the dielectric can completely fill trench 1214 during ILD layer formation, thereby eliminating air gap 1222.

[0223] like Figure 12F As shown, a first electrode 1224, a capacitor dielectric 1226, and a second electrode 1228 are subsequently formed in the ILD layer to form a capacitor in contact with the semiconductor body 1212. In some embodiments, each first electrode 1224 is formed on the corresponding source / drain 1221 (i.e., the doped upper end of the corresponding semiconductor body 1212) by patterning and etching electrode holes aligned with the corresponding source / drain 1221 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process. Similarly, in some embodiments, the second electrode 1228 is formed on the capacitor dielectric 1226 by patterning and etching electrode holes aligned with the corresponding capacitor dielectric 1226 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process.

[0224] like Figure 12G As shown, a carrier substrate (also known as a processing substrate) 1230 is bonded to the front side of a silicon substrate 1202, and a device is formed on the front side of the silicon substrate 1202 using any suitable bonding process (e.g., anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the silicon substrate 1202 is above the carrier substrate 1230.

[0225] like Figure 12G As shown, the silicon substrate 1202 is removed ( Figure 12F(As shown) to expose the undoped upper end of the semiconductor body 1212 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1202 until the upper end of the silicon oxide layer 1204 and the semiconductor body 1212 are removed.

[0226] like Figure 12G As shown, the exposed upper end of each semiconductor body 1212 (i.e., one of the two ends of the semiconductor body 1212 away from the carrier substrate 1230 in the vertical direction (z-direction)) is doped to form another source / drain 1223. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1212 to form the source / drain 1223. As a result, as Figure 12G As shown, according to some embodiments, a multi-gate vertical transistor is thus formed having a semiconductor body 1212, source / drain electrodes 1221 and 1223, a gate dielectric 1218, and a gate electrode (a portion of the conductive layer 1220). As described above, as... Figure 12G As shown, according to some embodiments, capacitors each having a first electrode 1224 and a second electrode 1228 and a capacitor dielectric 1226 are thus formed, and DRAM cells 1280 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are thus formed.

[0227] like Figure 12H As shown, an interconnect layer 1232 can be formed above the DRAM cell 1280. The interconnect layer 1232 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1280. In some embodiments, the interconnect layer 1232 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1232 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1204 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 12H The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1232. For example... Figure 12H As shown, trenches aligned with the corresponding source / drain 1223 can be patterned and etched using photolithography and etching processes, and conductive material can be deposited using thin film deposition processes to fill the trenches, forming bit lines 1234 on the source / drain 1223.

[0228] As shown in Figure 12H The bonding layer 1236 is formed over the interconnect layer 1232 and the DRAM cell 1280. The bonding layer 1236 can include a plurality of bonding contacts 1237 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on a top surface of the interconnect layer 1232 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The bonding contacts 1237 can then be formed through the dielectric layer and to the interconnect contacts in the interconnect layer 1232 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and / or a seed layer prior to depositing the conductor.

[0229] In some embodiments, as shown in Figures 13A-13H The DRAM cell array is formed from a four-layer dielectric stack with a sacrificial layer sandwiched between two dielectric layers (e.g., silicon nitride layers) on a pad layer (e.g., a silicon oxide layer).

[0230] At operation 2402 in Figure 24 A stack of dielectric layers is formed on a substrate. In some embodiments, to form the stack of dielectric layers, four layers with a first dielectric, a second dielectric, a third dielectric, and a second dielectric, respectively, are subsequently deposited on the substrate. The second dielectric can include silicon nitride, and the third dielectric can include silicon oxide. The layer with the third dielectric can be used as a sacrificial layer that is vertically sandwiched between two layers with the second dielectric. The sacrificial layer can be removed by selective etching with respect to the other layer with the second dielectric, and replaced with a conductive layer in a subsequent process.

[0231] As shown in Figure 13A A stack of silicon oxide layer 1304, silicon nitride layer 1306, silicon oxide layer 1308, and silicon nitride layer 1309 is formed on a silicon substrate 1302. To form the dielectric stack, silicon oxide and silicon nitride are subsequently and alternately deposited onto the silicon substrate 1202 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments, the silicon oxide layer 1304 (pad layer) is formed by oxidizing a top portion of the silicon substrate 1302 using dry oxidation and / or wet oxidation (e.g., an ISSG oxidation process). In some embodiments, the thickness of the silicon oxide layer 1304 (e.g., ISSG silicon oxide) is less than the thickness of the silicon oxide layer 1308 (e.g., CVD silicon oxide).

[0232] As shown in Figure 13B , an array of semiconductor bodies 1312 is formed, each semiconductor body 1312 extending vertically through the stack of silicon oxide layer 1304, silicon nitride layer 1306, silicon oxide layer 1308, and silicon nitride layer 1309. The semiconductor bodies 1312 can be epitaxially grown from respective exposed portions of the silicon substrate 1302 in respective openings (not shown). The fabrication process for epitaxially growing the semiconductor bodies 1312 can include, but is not limited to, VPE, LPE, MPE, or any combination thereof. The epitaxy can be performed upward (towards the positive z-direction) from the exposed portions of the silicon substrate 1302 in the openings. The semiconductor bodies 1312 can thus be of the same material as the silicon substrate 1302, i.e., single crystalline silicon. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess portions of the semiconductor bodies 1312 beyond the top surface of the silicon nitride layer 1309. As a result, according to some embodiments, an array of semiconductor bodies 1312 (e.g., single crystalline silicon bodies) is thus formed extending vertically (in the z-direction) from the silicon substrate 1302 through the stack of silicon oxide layer 1304, silicon nitride layer 1306, silicon oxide layer 1308, and silicon nitride layer 1309.

[0233] At operation 2406 in Figure 24 , one of the stack of dielectric layers is removed to expose portions of the semiconductor bodies. In some embodiments, to remove one of the stack of dielectric layers, a trench is etched through at least a portion of the stack of dielectric layers to expose the layer having the third dielectric, and the layer having the third dielectric (e.g., the sacrificial layer) is etched away via the trench.

[0234] As shown in Figure 13C , a plurality of trenches 1314 (slit openings) are formed to expose the silicon oxide layer 1308, each trench 1314 extending laterally along the word line direction (x-direction) and vertically through at least the silicon nitride layer 1309 and the silicon oxide layer 1308. As a result, portions of the silicon oxide layer 1308 can be exposed from the trenches 1314. In some embodiments, a lithography process is performed to pattern the trenches 1314 using an etch mask (e.g., a photoresist mask), e.g., based on a design of the word lines (word line trenches). In some embodiments, one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch the trenches 1314 through the silicon nitride layer 1309 and the silicon oxide layer 1308, up to the silicon nitride layer 1306. It should be appreciated that in some examples, the etching of the trenches 1314 can further into the silicon nitride layer 1306, but not into the silicon oxide layer 1304.

[0235] As shown in Figure 13D , the silicon oxide layer 1308 is removed Figure 13C(As shown), to expose a portion of the adjacent silicon oxide layer 1308 of the semiconductor body 1312. In some embodiments, the silicon oxide layer 1308 is etched away via trench 1314. For example, a wet etchant comprising hydrofluoric acid can be applied through trench 1314 to selectively wet etch the silicon oxide layer 1308 without etching the silicon nitride layers 1309 and 1306 and the semiconductor body 1312. As a result, a lateral groove 1316 can be formed to expose a portion of the semiconductor body 1312.

[0236] like Figure 13E As shown, the gate dielectric 1318 is formed over the exposed portion of each semiconductor body 1312, i.e., surrounding and contacting all sides of the exposed portion of the semiconductor body 1312. In some embodiments, wet oxidation and / or dry oxidation processes (e.g., ISSG) are performed to form a native oxide (e.g., silicon oxide) as the gate dielectric 1318 on the semiconductor body 1312 (e.g., single-crystal silicon). In some embodiments, the gate dielectric 1318 is formed by depositing a dielectric layer (e.g., silicon oxide) over the exposed portion of the semiconductor body 1312 through trenches 1314 and lateral recesses 1316 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) without filling the lateral recesses 1316 and trenches 1314. Due to the presence of the silicon nitride layer 1309, in Figure 13E The upper end of the gate dielectric 1318 may be below the upper end of the semiconductor body 1312.

[0237] like Figure 13F As shown, through the groove 1314 in the transverse groove 1316 (as shown) Figure 13EA conductive layer 1320 is formed over the gate dielectric 1318 (in the illustrated example). In some embodiments, the conductive layer 1320 is formed by depositing a conductive material (e.g., a metal or a metal compound (e.g., TiN)) over the gate dielectric 1318 through the trenches 1314 to fill the lateral recesses 1316 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In one example, the deposition of the conductive layer 1320 is controlled to not fill the trenches 1314. It will be appreciated that in some examples, the deposition of the conductive layer 1320 can also fill the trenches 1314. Accordingly, a planarization process (e.g., CMP) can be performed to remove excess conductive layer 1320 to expose the upper end portions of the semiconductor bodies 1312, and the conductive layer 1320 can be patterned to form gate electrodes over the respective gate dielectrics. For example, the trenches 1314 filled with the conductive layer 1320 can also be patterned and etched to separate the conductive layer 1320 between adjacent rows of semiconductor bodies 1312 and gate dielectrics 1318. As described above, a lithography process can be performed to pattern the trenches 1314 using an etch mask (e.g., a photoresist mask) as well, for example, based on the design of the word lines (word line trenches). Due to the presence of the silicon nitride layer 1309, the top surface of the conductive layer 1320 (including the gate electrodes and the word lines) can be below the upper end portions of the semiconductor bodies 1312. Figure 13F

[0238] As a result, the patterned conductive layer 1320 can become word lines, each extending in the word line direction (x-direction) and separated by adjacent trenches 1314, and the portions of the patterned conductive layer 1320 over the gate dielectrics 1318 (e.g., fully circumscribing the respective gate dielectrics 1318 in plan view) can become gate electrodes. From this, gate structures can be formed, each including a respective gate dielectric 1318 over an exposed portion of the semiconductor body 1312 and a respective gate electrode (i.e., a portion of the conductive layer 1320) over the gate dielectric 1318. It will be appreciated that the gate structures can be formed in a similar manner as described above with respect to the gate structures 1310. Figure 13F In comparison to the example of FIG. 13A, according to some embodiments, Figure 13A In comparison to the example of FIG. 13A, according to some embodiments, Figure 13A The silicon oxide layer 1308 (sacrificial layer) in FIG. 13A is ultimately replaced by the conductive layer 1320 in FIG. 13B. Figure 13F The silicon oxide layer 1308 (sacrificial layer) in FIG. 13A is ultimately replaced by the conductive layer 1320 in FIG. 13B.

[0239] As described above with respect to FIG. 13A, the gate dielectric 1318 can be formed by depositing a dielectric material (e.g., silicon oxide) over the exposed portions of the semiconductor bodies 1312 and the silicon nitride layer 1309 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In one example, the deposition of the gate dielectric 1318 is controlled to not fill the trenches 1314. It will be appreciated that in some examples, the deposition of the gate dielectric 1318 can also fill the trenches 1314. Accordingly, a planarization process (e.g., CMP) can be performed to remove excess gate dielectric 1318 to expose the upper end portions of the semiconductor bodies 1312, and the gate dielectric 1318 can be patterned to form gate dielectrics over the respective semiconductor bodies 1312. For example, the trenches 1314 filled with the gate dielectric 1318 can also be patterned and etched to separate the gate dielectrics 1318 between adjacent rows of semiconductor bodies 1312. As described above, a lithography process can be performed to pattern the trenches 1314 using an etch mask (e.g., a photoresist mask) as well, for example, based on the design of the word lines (word line trenches). Due to the presence of the silicon nitride layer 1309, the top surface of the gate dielectric 1318 can be below the upper end portions of the semiconductor bodies 1312. Figure 13F ​As shown, the exposed upper portion of each semiconductor body 1312 (i.e., one of the two ends of the semiconductor body 1312 away from the silicon substrate 1302 in the vertical direction (z-direction)) is doped to form a source / drain 1321. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper portion of the semiconductor body 1312 to form the source / drain 1321.

[0240] like Figure 13G As shown, for example, one or more ILD layers are formed on the top surface of the silicon nitride layer 1309 by depositing a dielectric using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Depending on the lateral dimensions of the trench 1314 (e.g., ...), Figure 13F As shown, when the ILD layer is formed, trench 1314 may not be completely filled by a dielectric (e.g., silicon oxide), and thus become an air gap 1322 between adjacent word lines (patterned conductive layer 1320). It should be understood that in some examples, when the lateral dimension of trench 1314 is large enough, the dielectric can completely fill trench 1314 during the formation of the ILD layer, thereby eliminating air gap 1322.

[0241] like Figure 13G As shown, a first electrode 1324, a capacitor dielectric 1326, and a second electrode 1328 are subsequently formed in the ILD layer to form a capacitor in contact with the semiconductor body 1312. In some embodiments, each first electrode 1324 is formed on the corresponding source / drain 1321 (i.e., the doped upper end of the corresponding semiconductor body 1312) by patterning and etching electrode holes aligned with the corresponding source / drain 1321 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process. Similarly, in some embodiments, the second electrode 1328 is formed on the capacitor dielectric 1326 by patterning and etching electrode holes aligned with the corresponding capacitor dielectric 1326 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process.

[0242] like Figure 13H As shown, a carrier substrate 1330 (also known as a processing substrate) is bonded to the front side of a silicon substrate 1302, and a device is formed on the front side of the silicon substrate 1302 using any suitable bonding process (e.g., anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the silicon substrate 1302 is above the carrier substrate 1330.

[0243] like Figure 13H As shown, the silicon substrate 1302 is removed ( Figure 13G(As shown) to expose the undoped upper end of the semiconductor body 1312 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1302 until the upper end of the silicon oxide layer 1304 and the semiconductor body 1312 are removed.

[0244] like Figure 13H As shown, the exposed upper end of each semiconductor body 1312 (i.e., one of the two ends of the semiconductor body 1312 away from the carrier substrate 1330 in the vertical direction (z-direction)) is doped to form another source / drain 1323. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1312 to form the source / drain 1323. As a result, as Figure 13H As shown, according to some embodiments, a vertical transistor is thus formed having a semiconductor body 1312, source / drain electrodes 1321 and 1323, a gate dielectric 1318, and a gate electrode (a portion of the conductive layer 1320). Figure 13H As shown, according to some embodiments, as described above, capacitors each having a first electrode 1324 and a second electrode 1328 and a capacitor dielectric 1326 are also formed therefrom, and DRAM cells 1380 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are formed therefrom.

[0245] like Figure 13H As shown, an interconnect layer 1332 can be formed above the DRAM cell 1380. The interconnect layer 1332 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1380. In some embodiments, the interconnect layer 1332 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1332 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1304 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 13H The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1332. For example... Figure 13H As shown, trenches aligned with the corresponding source / drain 1323 can be patterned and etched using photolithography and etching processes, and conductive material can be deposited using thin film deposition processes to fill the trenches, forming bit lines 1334 on the source / drain 1323.

[0246] As shown in Figure 13H bonding layer 1336 can include a plurality of bonding contacts 1337 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on a top surface of the interconnect layer 1332 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The bonding contacts 1337 can then be formed through the dielectric layer and to the interconnect contacts in the interconnect layer 1332 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and / or a seed layer prior to depositing the conductor.

[0247] A third semiconductor structure including a second array of memory cells can be formed. Each memory cell can also include a vertical transistor and a storage cell coupled to the vertical transistor. The second semiconductor structure and the third semiconductor structure can be bonded in a face-to-face manner. In some embodiments, the second semiconductor structure and the third semiconductor structure are bonded prior to bonding the first semiconductor structure and the second semiconductor structure. For example, as shown in Figure 23 the second semiconductor structure and the third semiconductor structure can be bonded prior to operation 2312 (e.g., between operation 2306 and operation 2308).

[0248] As shown in Figure 14A two semiconductor structures 1000 and 1400 are formed separately (e.g., in parallel) using any suitable fabrication process disclosed herein (e.g., in Figures 10A-10H ). For ease of description, the fabrication process of forming the semiconductor structure 1400 is not repeated and is the same as the fabrication process of forming the semiconductor structure 1000. Thus, the two semiconductor structures 1000 and 1400 can have the same devices therein.

[0249] As shown in Figure 14A the semiconductor structure 1400 is flipped upside down. As shown in Figure 14BAs shown, a bonding interface 1402 is formed by bonding the downward-facing semiconductor structure 1400 to the upward-facing semiconductor structure 1000 (i.e., face-to-face bonding) using any suitable substrate / wafer bonding process, including, for example, hybrid bonding (as described in detail above), anodic bonding, and fusion (direct) bonding. In one example, fusion bonding can be performed between silicon and silicon, silicon and silicon oxide, or silicon oxide and silicon oxide layers using pressure and heat. In another example, anodic bonding can be performed between silicon oxide (in ionomer glass) and silicon layers using voltage, pressure, and heat. It should be understood that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) can be formed on one or both sides of the bonding interface 1402. For example, a silicon oxide layer can be formed on the top surfaces of semiconductor structures 1000 and 1400 to allow for fusion-bonded SiO2-SiO2 bonding. In some embodiments, the second electrode 1028 of semiconductor structure 1400 is in contact with the second electrode 1028 of semiconductor structure 1000 at bonding interface 1402, and can therefore be regarded as a common electrode (e.g., a common ground plane) for both semiconductor structures 1000 and 1400.

[0250] like Figure 14B As shown, the silicon substrate 1002 (on top of the semiconductor structure 1000 after bonding) has the semiconductor structure 1400 removed. Figure 14A As shown), to expose the undoped upper end of the semiconductor body 1012 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1002 of the semiconductor structure 1400 until the upper end of the semiconductor body 1012 of the semiconductor structure 1400 is removed by the silicon oxide layer 1004.

[0251] like Figure 14B As shown, the exposed upper end of each semiconductor body 1012 of the doped semiconductor structure 1400 (i.e., one of the two ends of the semiconductor body 1012 that is away from the semiconductor structure 1000 in the vertical direction (z-direction)) forms another source / drain 1023. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1012 of the semiconductor structure 1400 to form the source / drain 1023. As a result, as Figure 14B As shown, according to some embodiments, a multi-gate vertical transistor having a semiconductor body 1012, source / drain electrodes 1021 and 1023, a gate dielectric 1018, and a gate electrode (a portion of the conductive layer 1020) is thus formed in the semiconductor structure 1400. As described above, Figure 14BAs shown, according to some embodiments, capacitors each having a first electrode 1024 and a second electrode 1028 and a capacitor dielectric 1026 are also formed, and DRAM cells 1080 of semiconductor structure 1400 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are formed.

[0252] like Figure 14C As shown, an interconnect layer 1032 can be formed above the DRAM cell 1080. The interconnect layer 1032 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1080. In some embodiments, the interconnect layer 1032 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1032 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1004 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 14C The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1032.

[0253] like Figure 14D As shown, a carrier substrate 1030 (also referred to as a processing substrate) is bonded to the front side of the semiconductor structure 1400, and a device is formed on the front side of the semiconductor structure 1400 using any suitable bonding process (e.g., anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the semiconductor structure 1000 is positioned above the carrier substrate 1030. Figure 14D (Not shown in the image).

[0254] like Figure 14D As shown, the silicon substrate 1002 of the semiconductor structure 1000 is removed. Figure 14C As shown), to expose the undoped upper end of the semiconductor body 1012 of the semiconductor structure 1000 (used as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1002 of the semiconductor structure 1000 until the silicon oxide layer 1004 and the upper end of the semiconductor body 1012 of the semiconductor structure 1000 are removed.

[0255] like Figure 14DAs shown, the exposed upper end of each semiconductor body 1012 of the doped semiconductor structure 1000 (i.e., one of the two ends of the semiconductor body 1012 that is away from the semiconductor structure 1400 in the vertical direction (z-direction)) forms another source / drain 1023. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1012 of the semiconductor structure 1000 to form the source / drain 1023. As a result, as Figure 14D As shown, according to some embodiments, a vertical transistor having a semiconductor body 1012, source / drain electrodes 1021 and 1023, a gate dielectric 1018, and a gate electrode (a portion of the conductive layer 1020) is thus formed in the semiconductor structure 1000. As described above, as... Figure 14D As shown, according to some embodiments, capacitors each having a first electrode 1024 and a second electrode 1028 and a capacitor dielectric 1026 are also formed, and DRAM cells 1080 of semiconductor structure 1000 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are formed.

[0256] like Figure 14E As shown, an interconnect layer 1032 can be formed over the DRAM cell 1080 in the semiconductor structure 1000. The interconnect layer 1032 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1080 in the semiconductor structure 1000. In some embodiments, the interconnect layer 1032 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1032 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1004 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 14E The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1032.

[0257] like Figure 14EAs shown, a bonding layer 1036 is formed over the interconnect layer 1032 and the DRAM cell 1080 in the semiconductor structure 1000. The bonding layer 1036 may include a plurality of bonding contacts 1037 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of the interconnect layer 1032 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be first patterned using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts 1037 that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1032. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer before depositing the conductor.

[0258] Then, Figure 14E The bonding structure shown can be bonded to a semiconductor structure, including peripheral circuitry, in a face-to-face manner, as described above regarding... Figure 23 Operation 2312 and Figure 10L and Figure 10M As described in detail.

[0259] In some implementations, the second and third semiconductor structures are bonded after the first and second semiconductor structures are bonded. For example, as... Figure 23 As shown, the second semiconductor structure and the third semiconductor structure can be bonded after operation 2312 (e.g., between operation 2312 and operation 2314).

[0260] like Figure 15A As shown, in Figure 10L Following the manufacturing process shown, the bonded semiconductor structure 1500 is formed by removing the carrier substrate 1030. Any suitable manufacturing process disclosed herein (e.g., in...) can be used. Figures 10A-10H Semiconductor structure 1000 is formed individually (e.g., in parallel). For ease of description, the manufacturing processes for forming semiconductor structures 1000 and 1500 will not be repeated.

[0261] like Figure 15A As shown, the semiconductor structure 1000 is flipped vertically. (As...) Figure 15BAs shown, the downward-facing semiconductor structure 1000 is bonded to the upward-facing semiconductor structure 1500 (i.e., bonded face-to-face) using any suitable substrate / wafer bonding process, including, for example, hybrid bonding (as described in detail above), anodic bonding, and fusion (direct) bonding, thereby forming a bonding interface 1502. In one example, fusion bonding can be performed between silicon and silicon, silicon and silicon oxide, or silicon oxide and silicon oxide layers using pressure and heat. In another example, anodic bonding can be performed between silicon oxide (in ionomer glass) and silicon layers using voltage, pressure, and heat. It should be understood that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) can be formed on one or both sides of the bonding interface 1502. For example, a silicon oxide layer can be formed on the top surfaces of semiconductor structures 1000 and 1500 to allow for fusion-bonded SiO2-SiO2 bonding. In some embodiments, the second electrode 1028 of the semiconductor structure 1000 is in contact with the second electrode 1028 of the semiconductor structure 1500 at the bonding interface 1502, and can therefore be regarded as a common electrode (e.g., a common ground plane) for both semiconductor structures 1000 and 1500.

[0262] like Figure 15C As shown, the silicon substrate 1002 (on top of semiconductor structure 1500 after bonding) with semiconductor structure 1000 removed Figure 15B As shown), to expose the undoped upper end of the semiconductor body 1012 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1002 of the semiconductor structure 1000 until the silicon oxide layer 1004 and the upper end of the semiconductor body 1012 of the semiconductor structure 1000 are removed.

[0263] like Figure 15C As shown, the exposed upper end of each semiconductor body 1012 of the doped semiconductor structure 1000 (i.e., one of the two ends of the semiconductor body 1012 that is away from the semiconductor structure 1500 in the vertical direction (z-direction)) forms another source / drain 1023. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1012 of the semiconductor structure 1000 to form the source / drain 1023. As a result, as Figure 15C As shown, according to some embodiments, a multi-gate vertical transistor having a semiconductor body 1012, source / drain electrodes 1021 and 1023, a gate dielectric 1018, and a gate electrode (a portion of the conductive layer 1020) is thus formed in the semiconductor structure 1000. As described above, as... Figure 15CAs shown, according to some embodiments, capacitors each having a first electrode 1024 and a second electrode 1028 and a capacitor dielectric 1026 are also formed, and DRAM cells 1080 of semiconductor structure 1400 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are formed.

[0264] like Figure 15D As shown, an interconnect layer 1032 can be formed over the DRAM cell 1080 in the semiconductor structure 1000. The interconnect layer 1032 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1080. In some embodiments, the interconnect layer 1032 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1032 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1004 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 15D The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1032.

[0265] Then, as mentioned above... Figure 23 Operation 2314 and Figure 10M A detailed description is available at [website / location]. Figure 15D The bonding structure shown in the figure has pads forming an interconnect layer.

[0266] Method 2300 can also be used through Figures 19A-19M The manufacturing process described in Figure 22 is implemented to form Figure 17 The 3D memory device 1700 depicted here has a single-gate vertical transistor instead of a multi-gate vertical transistor. (Reference) Figure 23 Method 2300 begins at operation 2302, wherein a peripheral circuit is formed on a first substrate. The first substrate may include a silicon substrate. In some embodiments, an interconnect layer is formed over the peripheral circuit. The interconnect layer may include multiple interconnects in one or more ILD layers.

[0267] like Figure 19LAs shown, a plurality of transistors 1948 are formed on a silicon substrate 1944. The transistors 1948 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1944 by ion implantation and / or thermal diffusion, which are used as, for example, the source and drain of the transistors 1948. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1944 by wet / dry etching and thin film deposition. The transistors 1948 can form a peripheral circuit 1946 on the silicon substrate 1944.

[0268] As shown, a plurality of transistors 1948 are formed on a silicon substrate 1944. The transistors 1948 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1944 by ion implantation and / or thermal diffusion, which are used as, for example, the source and drain of the transistors 1948. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1944 by wet / dry etching and thin film deposition. The transistors 1948 can form a peripheral circuit 1946 on the silicon substrate 1944. Figure 19L As shown, a plurality of transistors 1948 are formed on a silicon substrate 1944. The transistors 1948 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1944 by ion implantation and / or thermal diffusion, which are used as, for example, the source and drain of the transistors 1948. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1944 by wet / dry etching and thin film deposition. The transistors 1948 can form a peripheral circuit 1946 on the silicon substrate 1944. Figure 19L The ILD layers and interconnects shown in FIG. 19B can be collectively referred to as an interconnect layer 1950.

[0269] The method 2300 proceeds to operation 2304, as shown, where a first bonding layer is formed over the peripheral circuit (and interconnect layer). The first bonding layer can include first bonding contacts. As shown, a bonding layer 1952 is formed over the interconnect layer 1950 and the peripheral circuit 1946. The bonding layer 1952 can include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on a top surface of the interconnect layer 1950 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Then, bonding contacts can be formed through the dielectric layer and to interconnect contacts in the interconnect layer 1950 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and / or a seed layer prior to depositing the conductor. Figure 23 Figure 19L

[0270] ​​Method 2300 proceeds to operation 2306, such as... Figure 23 As shown, an array of memory cells, each comprising a vertical transistor and a memory cell, is formed on a second substrate. The second substrate may include a carrier substrate. The memory cell may include a capacitor or a PCM element. In some embodiments, the capacitor is formed as a vertical transistor coupled to the respective memory cell.

[0271] For example, Figure 25 A flowchart illustrating a method 2500 for forming another array of memory cells, each comprising a vertical transistor, according to some aspects of this disclosure is shown. Figure 25 At operation 2502, a semiconductor pillar extending vertically in the substrate is formed. The substrate may be a silicon substrate. In some embodiments, to form the semiconductor pillar, the substrate is etched in a first lateral direction to form a plurality of first trenches, a dielectric is deposited to fill the first trenches to form second trench isolation, and the substrate and second trench isolation are etched in a second lateral direction to form a plurality of second trenches and a semiconductor pillar surrounded by the second trenches and second trench isolation. In some embodiments, a dielectric is deposited to partially fill the second trenches.

[0272] like Figure 19A As shown, a plurality of parallel trenches 1904 are formed in the y-direction (e.g., the bit line direction) to form a plurality of parallel semiconductor walls 1905 in the y-direction. In some embodiments, such as based on the bit line design, a photolithography process is performed to pattern the trenches 1904 and semiconductor walls 1905 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch the trenches 1904 in the silicon substrate 1902. Thus, semiconductor walls 1905 extending vertically in the silicon substrate 1902 can be formed. The bottom of the semiconductor walls 1905 may be below the top surface of the silicon substrate 1902. Since the semiconductor walls 1905 are formed by etching the silicon substrate 1902, the semiconductor walls 1905 can have the same material as the silicon substrate 1902, such as single-crystal silicon. Figure 19A A side view of a cross section along the x-direction (word line direction, e.g., in the BB plane) is shown. Figure 19A Plan view of the cross-section in the top part) and in the xy plane (e.g., in the AA plane passing through semiconductor wall 1905). Figure 19A (In the bottom part). Figure 19B The same drawing layout was also used in the middle.

[0273] like Figure 19BAs shown, trench isolation 1908 (e.g., STI) is formed in trench 1904. In some embodiments, a dielectric (e.g., silicon oxide) is deposited using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to completely fill trench 1904. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess dielectric deposited beyond the top surface of the silicon substrate 1902. As a result, parallel semiconductor walls 1905 can be separated by trench isolation 1908.

[0274] like Figure 19C As shown, a plurality of parallel trenches 1910 are formed in the x-direction (e.g., word line direction) to form an array of semiconductor pillars 1906, each extending vertically in the silicon substrate 1902. In some embodiments, such as based on word line design, a photolithography process is performed to pattern the trenches 1910 perpendicular to the trench isolation 1908 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) are performed on the silicon substrate 1902 and the trench isolation 1908 to etch the trenches 1910 in the silicon substrate 1902. As a result, semiconductor walls 1905 ( Figure 19B The semiconductor pillars (as shown) can be cut by trench 1910 to form an array of semiconductor pillars 1906, each extending vertically in the silicon substrate 1902. The bottom of the semiconductor pillars 1906 may be below the top surface of the silicon substrate 1902. Since the semiconductor pillars 1906 are formed by etching the silicon substrate 1902, the semiconductor pillars 1906 may have the same material as the silicon substrate 1902, such as single-crystal silicon. Figure 19C A side view of a cross-section along the y-direction (bitline direction, e.g., in the CC plane) is shown. Figure 19C Plan view of the cross-section in the top part) and in the xy plane (e.g., in the AA plane passing through semiconductor pillar 1906). Figure 19C (In the bottom part). Figures 19C-19G The same drawing layout was also used in the middle.

[0275] like Figure 19CAs shown, a dielectric layer 1912 is formed at the bottom of trench 1910, for example, by depositing a dielectric (e.g., silicon oxide) to partially fill trench 1910 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Deposition conditions (e.g., deposition rate and / or time) can be controlled to control the thickness of the dielectric layer 1912 and avoid completely filling trench 1910. As a result, the bottom surface of trench 1910 can be raised above the bottom surface of semiconductor pillar 1906. As shown in the plan view, two opposite sides of semiconductor pillar 1906 in the y-direction are exposed through trench 1910, and another two opposite sides of semiconductor pillar 1906 in the x-direction are in contact with trench isolation 1908. That is, semiconductor pillar 1906 is surrounded by trench 1910 and trench isolation 1908.

[0276] exist Figure 25 At operation 2504, a gate structure is formed that contacts the opposite side of the semiconductor pillar. In some embodiments, to form the gate structure, a gate dielectric is formed on the opposite side of the semiconductor pillar, and a gate electrode is formed on the gate dielectric. In some embodiments, to form the gate electrode, a conductive layer is deposited on the gate dielectric, and the conductive layer is etched back.

[0277] like Figure 19D As shown, a gate dielectric 1914 is formed over two opposite sides of the semiconductor pillar 1906 exposed from the trench 1910 in the bit line direction (y-direction). As shown in the plan view, the gate dielectric 1914 may be a portion of a continuous dielectric layer formed over the sidewalls of each row of semiconductor pillars 1906 and trench isolation 1908. In some embodiments, the gate dielectric 1914 is formed by depositing a dielectric layer (e.g., silicon oxide) over the sidewalls of the trench 1910 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) without completely filling the trench 1910. It should be understood that in some examples, the gate dielectric 1914 may not be a portion of a continuous dielectric layer. For example, wet oxidation and / or dry oxidation processes (e.g., in-situ vapor generation (ISSG) oxidation) are performed to form a native oxide (e.g., silicon oxide) on the semiconductor pillar 1906 (e.g., single-crystal silicon) as the gate dielectric 1914.

[0278] like Figure 19DAs shown, a conductive layer 1916 is formed over a gate dielectric 1914 in trench 1910. In some embodiments, the conductive layer 1916 is formed by depositing one or more conductive materials (e.g., metals and / or metal compounds (e.g., W and TiN)) over the gate dielectric 1914 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to partially fill trench 1910. For example, a TiN layer and a W layer may be deposited sequentially to form the conductive layer 1916. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of the silicon substrate 1902.

[0279] like Figure 19E As shown, in some embodiments, the conductive layer 1916 is etched back using, for example, dry etching and / or wet etching (e.g., RIE) to form a recess, such that the upper end of the conductive layer 1916 is below the top surface of the semiconductor pillar 1906. In some embodiments, since the gate dielectric 1914 is not etched back, the upper end of the conductive layer 1916 is also below the upper end of the gate dielectric 1914, which is flush with the top surface of the semiconductor pillar 1906. As a result, the etched-back conductive layer 1916 can become word lines extending in the word line direction (x direction), and the portion of the etched-back conductive layer 1916 facing the semiconductor pillar 1906 can become a gate electrode. This allows the formation of gate structures, each including a corresponding gate dielectric 1914 on the exposed side of the semiconductor pillar 1906 and a corresponding gate electrode (i.e., a portion of the conductive layer 1916) on the gate dielectric 1914. In some embodiments, as... Figure 19E As shown, a dielectric layer 1918 is formed in the remaining space of trench 1910 and in the recess (not shown) created by etching back conductive layer 1916, for example, by depositing a dielectric (e.g., silicon oxide) using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). It should be understood that air gaps may be formed in dielectric layer 1918 depending on the word line spacing (i.e., the size of trench 1910).

[0280] exist Figure 25 At operation 2506, a first trench isolation extending vertically through the semiconductor pillar is formed to separate the semiconductor pillar into semiconductor bodies, each semiconductor body contacting a corresponding gate structure in the gate structure. In some embodiments, to form the first trench, the semiconductor pillar is etched in a second lateral direction to form a third trench, and a dielectric is deposited to fill the third trench.

[0281] like Figure 19FAs shown, a plurality of parallel trenches 1922 are formed in the x-direction (e.g., word line direction) to form an array of semiconductor bodies 1920, each extending vertically in the silicon substrate 1902. In some embodiments, a photolithography process is performed to pattern the trenches 1922 on the semiconductor pillars 1906 using an etching mask (e.g., a photoresist mask and / or a hard mask). Figure 19E As shown in the plan view, one or more dry etching and / or wet etching processes (e.g., RIE) are performed on the semiconductor pillars 1906 and trench isolation 1908 to etch the trenches 1922. The etching can be controlled such that the bottom of the trench 1922 is flush with or below the bottom surface of the semiconductor pillars 1906. As a result, each semiconductor pillar 1906 can be separated into two semiconductor bodies 1920 in the y-direction by a corresponding trench 1922. Since the semiconductor bodies 1920 are formed by etching the silicon substrate 1902, the semiconductor bodies 1920 can have the same material as the silicon substrate 1902, such as monocrystalline silicon. As shown in the plan view, each semiconductor body 1920 can contact a gate structure having a gate dielectric 1914 and a gate electrode 1916 on one side of the semiconductor body 1920 in the y-direction. The opposite sides of the semiconductor bodies 1920 can be exposed through the trench 1922. In some implementations, the two semiconductor bodies 1920 and their two gate structures are arranged in a mirror symmetry by forming a trench 1922 across the middle of the respective semiconductor pillars 1906.

[0282] like Figure 19G As shown, for example, a dielectric (e.g., silicon oxide) is deposited to fill trench 1922 by using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof), in trench 1922 ( Figure 19F Trench isolation 1926 is formed in the (shown) layer. A planarization process can be performed to remove excess dielectric above the top surface of the silicon substrate 1902. It should be understood that air gaps can be formed in the trench isolation 1926 depending on the spacing of the semiconductor bodies 1920 (i.e., the size of the trench 1922). As shown in the plan view, parallel trench isolations 1926, each extending in the x-direction, can form an array of semiconductor bodies 1920, wherein a single side contactes a gate structure having a gate dielectric 1914 and a gate electrode 1916.

[0283] exist Figure 25 At operation 2508, the first end of the doped semiconductor substrate is located away from the substrate. For example... Figure 19GAs shown, the exposed upper portion of each semiconductor body 1920 (i.e., one of the two ends of the semiconductor body 1920 away from the silicon substrate 1902 in the vertical direction (z-direction)) is doped to form a source / drain 1924. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper portion of the semiconductor body 1920 to form the source / drain 1924. In some embodiments, a silicide layer is formed on the source / drain 1924 by performing a silicide process at the exposed upper portion of the semiconductor body 1920.

[0284] exist Figure 25 At operation 2510, a memory cell is formed in contact with a semiconductor substrate (e.g., its doped first end). The memory cell may include a capacitor or a PCM element. In some embodiments, to form a memory cell that is a capacitor, a first electrode is formed on the doped first end of the semiconductor substrate, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric.

[0285] like Figure 19H As shown, for example, one or more ILD layers are formed on the top surface of a silicon substrate 1902 by depositing a dielectric material using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). A first electrode 1928, a capacitor dielectric 1930, and a second electrode 1932 are then formed in the ILD layers to form a capacitor in contact with the semiconductor body 1920. In some embodiments, each first electrode 1928 is formed on the respective source / drain 1924 (i.e., the doped upper end of the respective semiconductor body 1920) by patterning and etching electrode holes aligned with the respective source / drain 1924 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin-film deposition process. Similarly, in some embodiments, the second electrode 1932 is formed on the capacitor dielectric 1930 by patterning and etching electrode holes aligned with the respective capacitor dielectric 1930 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin-film deposition process.

[0286] exist Figure 25 At operation 2512, the substrate is thinned to expose the second end of the semiconductor body opposite the first end. For example... Figure 19I As shown, a carrier substrate 1934 (also known as a processing substrate) is bonded to the front side of a silicon substrate 1902, and a device is formed on the front side of the silicon substrate 1902 using any suitable bonding process (e.g., anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the silicon substrate 1902 is above the carrier substrate 1934.

[0287] As shown in Figure 19J , the silicon substrate 1902 (shown in Figure 19I ) is thinned to expose an undoped upper end portion of the semiconductor body 1920 (which served as a lower end portion prior to flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process is performed on the thin silicon substrate 1902 until stopped by the dielectric layer 1918 and the upper end portion of the semiconductor body 1920.

[0288] At operation 2514 in Figure 25 , the exposed second end portion of the semiconductor body is doped. As shown in Figure 19J , the exposed upper end portion of each semiconductor body 1920 (i.e., the two end portions of the semiconductor body 1920 in the vertical direction (z-direction) away from the carrier substrate 1934) is doped to form another source / drain 1936. In some embodiments, an implantation process and / or a thermal diffusion process is performed to dope P-type dopants or N-type dopants to the exposed upper end portion of the semiconductor body 1920 to form the source / drain 1936. In some embodiments, a silicidation process is performed at the exposed upper end portion of the semiconductor body 1920 to form a silicide layer on the source / drain 1936. As a result, as shown in FIG. 19J , a vertical transistor having the semiconductor body 1920, the source / drain 1924 and 1936, the gate dielectric 1914, and the gate electrode (a portion of the conductive layer 1916) is thereby formed according to some embodiments. As noted above, as shown in FIG. 19J , capacitors each having the first electrode 1928 and the second electrode 1932 and the capacitor dielectric 1930 are also thereby formed according to some embodiments, and DRAM cells 1980 each having a single-gate vertical transistor and a capacitor coupled to the single-gate vertical transistor are thereby formed according to some embodiments.

[0289] Referring back to FIG. 23 , the method 2300 proceeds to operation 2308, where an interconnect layer including bit lines is formed over the array of memory cells, as shown in FIG. 23 . As shown in FIG. 19KAs shown, an interconnect layer 1940 can be formed above the DRAM cell 1980. The interconnect layer 1940 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1980. In some embodiments, the interconnect layer 1940 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1940 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). FIG. 19K The ILD layer and interconnect shown can be collectively referred to as Interconnect Layer 1940.

[0290] like FIG. 25 As shown, at operation 2516, bit lines are formed on the doped second end in order to form an interconnect layer. FIG. 19K As shown, trenches aligned with the corresponding source / drain 1936 can be patterned and etched using photolithography and etching processes, and conductive material can be deposited using thin-film deposition processes to fill the trenches, forming bit lines 1938 on the source / drain 1936. As a result, bit lines 1938 and capacitors having electrodes 1928 and 1932 and a capacitor dielectric 1930 can be formed on opposite sides of the semiconductor body 1920 and coupled to opposite ends of the semiconductor body 1920. It should be understood that additional local interconnects, such as word line contacts, capacitor contacts, and bit line contacts, can also be formed similarly.

[0291] Method 2300 proceeds to operation 2310, such as... FIG. 23 As shown, a second bonding layer is formed above the memory cell array and the interconnect layer. The second bonding layer may include second bonding contacts. FIG. 19KAs shown, a bonding layer 1942 is formed over the interconnect layer 1940 and the DRAM unit 1980. The bonding layer 1942 can include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on a top surface of the interconnect layer 1940 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Then, bonding contacts through the dielectric layer and to interconnect contacts in the interconnect layer 1940 can be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and / or a seed layer prior to depositing the conductor.

[0292] The method 2300 proceeds to operation 2312, as FIG. 23 shown, where the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the first array of memory cells is coupled to the peripheral circuitry through the bonding interface. The bonding can include hybrid bonding. In some embodiments, after bonding, the first bonding contacts are in contact with the second bonding contacts at the bonding interface. In some embodiments, the second semiconductor structure is over the first semiconductor structure after bonding. In some embodiments, the first semiconductor structure is over the second semiconductor structure after bonding.

[0293] As FIG. 19L shown, the carrier substrate 1934 and the components (e.g., DRAM units 1980) formed thereon are flipped upside down. As FIG. 19L shown, the downward-facing bonding layer 1942 is bonded (i.e., in a face-to-face manner) to the upward-facing bonding layer 1952, thereby forming a bonding interface 1954. In some embodiments, prior to bonding, a processing FIG. 19L technique, such as a plasma treatment, a wet treatment, and / or a thermal treatment, is applied to the bonding surfaces. Although not shown in FIG. 19B, the silicon substrate 1944 and the components (e.g., the peripheral circuitry 1946) formed thereon can be flipped upside down, and the downward-facing bonding layer 1952 can be bonded (i.e., in a face-to-face manner) to the upward-facing bonding layer 1942, thereby forming the bonding interface 1954. After bonding, the bonding contacts in the bonding layer 1942 and the bonding contacts in the bonding layer 1952 are aligned with and in contact with each other, such that the DRAM units 1980 can be electrically connected to the peripheral circuitry 1946 through the bonding interface 1954. It should be appreciated that in the bonded chip, the DRAM units 1980 can be above or below the peripheral circuitry 1946. However, after bonding, the bonding interface 1954 can be formed vertically between the peripheral circuitry 1946 and the DRAM units 1980.

[0294] Method 2300 proceeds to operation 2314, such as... FIG. 23 As shown, an interconnect layer is formed on the back side of the first semiconductor structure or the second semiconductor structure, with pads leading out. FIG. 19M As shown, a pad-out interconnect layer 1956 is formed on the back side of a carrier substrate 1934. The pad-out interconnect layer 1956 may include interconnects formed in one or more ILD layers, such as pad contacts 1958. The pad contacts 1958 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding, conductive material is subsequently deposited, for example by a wet / dry etching process, to form contacts 1960 extending vertically through the carrier substrate 1934. Contacts 1960 may contact the interconnects in the pad-out interconnect layer 1956. It should be understood that in some examples, the carrier substrate 1934 may be thinned or removed, for example using planarization processes and / or etching processes, after bonding and before the formation of the pad-out interconnect layer 1956 and contacts 1960.

[0295] Although not shown, it should be understood that in some examples, a pad-out interconnect layer 1956 may be formed on the back side of the silicon substrate 1944, and contacts 1960 may be formed to extend vertically through the silicon substrate 1944. Before forming the pad-out interconnect layer 1956 and contacts 1960, the silicon substrate 1944 may be thinned, for example, using planarization and / or etching processes. Although not shown, it should also be understood that in some examples, [further details regarding...] FIG. 14A-14E and FIG. 15A-15D The described manufacturing process is for bonding to components including those mentioned above. FIG. 19A-19M An array of another DRAM cell 1980 is formed in another semiconductor structure of the semiconductor structure of the described DRAM cell 1980.

[0296] Method 2300 can also be used through FIG. 22A-22M and FIG. 26 The manufacturing process described herein is implemented to form FIG. 21 The 3D memory device 2100 depicted here has dual-gate vertical transistors instead of a single-gate vertical transistor. (Reference) FIG. 23 Method 2300 begins at operation 2302, wherein a peripheral circuit is formed on a first substrate. The first substrate may include a silicon substrate. In some embodiments, an interconnect layer is formed over the peripheral circuit. The interconnect layer may include multiple interconnects in one or more ILD layers.

[0297] like FIG. 22LAs shown, a plurality of transistors 2248 are formed on a silicon substrate 2244. The transistors 2248 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 2244 by ion implantation and / or thermal diffusion, for example, to function as source and drain electrodes of the transistors 2248. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2244 by wet / dry etching and thin film deposition. The transistors 2248 can form a peripheral circuit 2246 on the silicon substrate 2244.

[0298] As shown, a plurality of transistors 2248 are formed on a silicon substrate 2244. The transistors 2248 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 2244 by ion implantation and / or thermal diffusion, for example, to function as source and drain electrodes of the transistors 2248. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2244 by wet / dry etching and thin film deposition. The transistors 2248 can form a peripheral circuit 2246 on the silicon substrate 2244. FIG. 22L As shown, a plurality of transistors 2248 are formed on a silicon substrate 2244. The transistors 2248 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 2244 by ion implantation and / or thermal diffusion, for example, to function as source and drain electrodes of the transistors 2248. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2244 by wet / dry etching and thin film deposition. The transistors 2248 can form a peripheral circuit 2246 on the silicon substrate 2244. FIG. 22L The ILD layers and interconnects shown in FIG. 26 can be collectively referred to as the interconnect layer 2250.

[0299] The method 2300 proceeds to operation 2304, as shown, where a first bonding layer is formed over the peripheral circuit (and interconnect layer). The first bonding layer can include first bonding contacts. As shown in FIG. 25, a bonding layer 2252 is formed over the interconnect layer 2250 and the peripheral circuit 2246. The bonding layer 2252 can include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on a top surface of the interconnect layer 2250 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Then, bonding contacts can be formed through the dielectric layer and to interconnect contacts in the interconnect layer 2250 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and / or a seed layer prior to depositing the conductor. FIG. 23 FIG. 22L

[0300] ​​Method 2300 proceeds to operation 2306, as shown, where an array of memory cells each including a vertical transistor and a storage cell is formed on a second substrate. The second substrate can include a carrier substrate. The storage cell can include a capacitor or a PCM element. In some embodiments, the capacitor is formed to be coupled to the vertical transistor in the corresponding memory cell. FIG. 23

[0301] For example, FIG. 26 A flowchart illustrating a method 2600 for forming yet another array of memory cells each including a vertical transistor, in accordance with some aspects of the present disclosure, is shown. At operation 2602 in FIG. 26 In some embodiments, to form the semiconductor body, the handle layer is etched in a first lateral direction to form a first trench, and the handle layer is etched in a second lateral direction to form a second trench, such that two opposite sides of the semiconductor body are exposed by the second trench. In some embodiments, a dielectric is deposited to partially fill the second trench.

[0302] As shown in FIG. 22A In some embodiments, such as a bit line based design, a lithography process is performed to pattern the trenches 2204 and the semiconductor walls 2205 using an etch mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch the trenches 1904 in the SOI substrate 2201. Thus, the semiconductor walls 1905 can be formed to vertically extend in the SOI substrate 2201. As shown in FIG. 22A In some embodiments, to form the trenches 2204, the device layer 2209 is etched using RIE, stopping at the buried oxide layer 2203. That is, the buried oxide layer 2203 can be used as an etch stop layer. It should be appreciated that in some examples, the device layer 2209 can not be part of the SOI substrate, but is transferred from another silicon substrate (not shown, e.g., a SOI substrate) and bonded onto the buried oxide layer 2203. It should also be appreciated that in some examples, the SOI substrate 2201 can be replaced with a silicon substrate, such as FIG. 19A ​In the silicon substrate 1902; the etching of the trench 2204 can be stopped without being stopped by the buried oxide layer 2203, but by controlling the etching rate and / or duration, for example, as FIG. 19A As shown

[0303] However, the bottom of the semiconductor wall 2205 may be below the top surface of the SOI substrate 2201. Since the semiconductor wall 2205 is formed by etching the device layer 2209 of the SOI substrate 2201, the semiconductor wall 2205 may have the same material as the device layer 2209 of the SOI substrate 2201, such as single-crystal silicon. FIG. 22A A side view of a cross section along the x-direction (word line direction, e.g., in the BB plane) is shown. FIG. 22A Plan view of the cross-section in the top part) and in the xy plane (e.g., in the AA plane passing through semiconductor wall 2205). FIG. 22A (in the bottom part).

[0304] like FIG. 22B As shown, a plurality of parallel trenches 2210 are formed in the x-direction (e.g., word line direction) to form an array of semiconductor bodies 2206 that each extends vertically in the SOI substrate 2201. In some embodiments, such as based on word line design, a photolithography process is performed to pattern the trenches 2210 perpendicular to the trenches 2204 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch the trenches 2210 in the device layer 2209 of the SOI substrate 2201. As a result, semiconductor walls 2205 (such as...) FIG. 22A (As shown) can be cut by trench 2210 to form an array of semiconductor bodies 2206, each extending vertically in the SOI substrate 2201. The bottom of the semiconductor bodies 2206 may be below the top surface of the SOI substrate 2201. Since the semiconductor bodies 2206 are formed by etching the device layer 2209 of the SOI substrate 2201, the semiconductor bodies 2206 may have the same material as the device layer 2209 of the SOI substrate 2201, such as single-crystal silicon. FIG. 22B A side view of a cross-section along the y-direction (bitline direction, e.g., in the CC plane) is shown. FIG. 22B Plan view of the cross-section in the top portion of the semiconductor body 2206 (e.g., in the AA plane passing through the semiconductor body 2206) and in the xy plane (e.g., in the AA plane passing through the semiconductor body 2206). FIG. 22B (In the bottom part). FIG. 22C-22G The same drawing layout was also used in the middle.

[0305] It should be appreciated that, in some examples, trenches 2204 and 2210 can be formed in the same process, as opposed to two successive processes. For example, the same photolithography process can be used to pattern trenches 2204 and 2210, followed by the same etching process. It should also be appreciated that, in some examples, trench 2210 can be formed in the word line direction before trench 2204 is formed in the bit line direction. However, after trenches 2204 and 2210 are formed, semiconductor body 2206 can be formed, and all four sides of semiconductor body 2206 can be exposed by trenches 2204 and 2210. In some implementations, two opposite sides of semiconductor body 2206 in the word line direction are exposed by trench 2204, and two opposite sides of semiconductor body 2206 in the bit line direction are exposed by trench 2210, as shown in plan view. That is, semiconductor body 2206 can be surrounded by trenches 2204 and 2210.

[0306] As shown in FIG. 22C For example, by depositing a dielectric (e.g., silicon oxide) to partially fill trench 2210 using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof), a dielectric layer 2212 is formed at the bottom of trench 2210 (and, in some examples, trench 2204). The deposition conditions (e.g., deposition rate and / or time) can be controlled to control the thickness of dielectric layer 2212 and avoid completely filling trench 2210. As a result, the bottom surface of trench 2210 can be elevated above the bottom surface of semiconductor body 2206.

[0307] At operation 2604 in FIG. 26 a gate structure is formed in contact with opposite sides of the semiconductor body. In some implementations, to form the gate structure, a gate dielectric is formed over the opposite sides of the semiconductor body, and a gate electrode is formed over the gate dielectric. In some implementations, to form the gate electrode, a conductive layer is deposited over the gate dielectric, and the conductive layer is etched back.

[0308] As shown in FIG. 22DAs shown, a gate dielectric 2214 is formed over two opposite sides of the semiconductor body 2206 exposed from trench 2210 in the bit line direction (y-direction). As shown in the plan view, the gate dielectric 2214 may be a portion of a continuous dielectric layer formed over the sidewalls of each row of semiconductor bodies 2206. In some embodiments, the gate dielectric 2214 is formed by depositing a dielectric layer (e.g., silicon oxide) over the sidewalls and top surface of the semiconductor body 2206 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) without completely filling the trench 2210. It should be understood that in some examples, the gate dielectric 2214 may not be a portion of a continuous dielectric layer. For example, wet oxidation and / or dry oxidation processes (e.g., ISSG oxidation) are performed to form a native oxide (e.g., silicon oxide) on the semiconductor body 2206 (e.g., single-crystal silicon) as the gate dielectric 2214.

[0309] like FIG. 22D As shown, a conductive layer 2216 is formed over the gate dielectric 2214. In some embodiments, the conductive layer 2216 is formed by depositing one or more conductive materials (e.g., metals and / or metal compounds (e.g., W and TiN)) over the gate dielectric 2214 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to partially fill the trench 2210. For example, layers of TiN and W may be deposited sequentially to form the conductive layer 2216. As shown in the side view, the conductive layer 2216 may be a continuous layer in the bit line direction, as the conductive material may be deposited over the top surface of the semiconductor body 2206 and the bottom surface of the trench 2210.

[0310] like FIG. 22E As shown, in some embodiments, a portion of the conductive layer 2216 at the bottom surface of trench 2210 is removed to separate the continuous conductive layer 2216 into discrete wafers in the bit line direction, for example, by using dry etching and / or dry etching (e.g., RIE) to form a notch 2211 on the bottom surface of trench 2210. In some embodiments, a portion of the conductive layer 2216 at the top surface of semiconductor body 2206 is also removed by the same etching process to expose the gate dielectric 2214 at the top surface of semiconductor body 2206.

[0311] like FIG. 22F As shown, in some embodiments, a dielectric (e.g., silicon oxide) is deposited to fill trench 2210, for example, by using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) to form trench isolation 2218 (e.g.) in trench 2210. FIG. 22EAs shown in the planar view. Planarization processes (e.g., CMP and / or etching processes) can be performed to remove excess dielectric above the top surface of the semiconductor body 2206. In some embodiments, the planarization process also removes a portion of the gate dielectric 2214 above the top surface of the semiconductor body 2206 to expose the top surface of the semiconductor body 2206. It should be understood that, depending on the spacing of the semiconductor bodies 2206 (i.e., the size of the trench 2210), an air gap can be formed in the trench isolation 2218. As shown in the planar view, dielectric deposition can also fill the remaining space in the trench 2204 ( FIG. 22E As shown in the diagram, isolation 2219 is formed between adjacent semiconductor bodies 2206 in the word line direction (e.g., in the same row).

[0312] like FIG. 22G As shown, in some embodiments, the conductive layer 2216 is etched back using, for example, dry etching and / or wet etching (e.g., RIE) to form a recess such that the upper end of the conductive layer 2216 is below the top surface of the semiconductor body 2206. In some embodiments, since the gate dielectric 2214 is not etched back, the upper end of the conductive layer 2216 is also below the upper end of the gate dielectric 2214, which is flush with the top surface of the semiconductor body 2206. As a result, the etched-back conductive layer 2216 can become word lines extending in the word line direction (x direction), and the portion of the etched-back conductive layer 2216 facing the semiconductor body 2206 can become the gate electrode. This allows the formation of gate structures, each including a corresponding gate dielectric 2214 on two exposed opposing sides (in the bit line direction) of the semiconductor body 2206 and a corresponding gate electrode (i.e., a portion of the conductive layer 2216) on the gate dielectric 2214.

[0313] exist FIG. 26 At operation 2606, the first end of the doped semiconductor substrate is located away from the substrate. For example... FIG. 22G As shown, the exposed upper end (top surface) of each semiconductor body 2206 (i.e., one of the two ends of the semiconductor body 2206 away from the processing layer 2202 of the SOI substrate 2201 in the vertical direction (z-direction)) is doped to form a source / drain 2224. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 2206 to form the source / drain 2224. In some embodiments, a silicide layer is formed on the source / drain 2224 by performing a silicide process at the exposed upper end of the semiconductor body 2206.

[0314] exist FIG. 26At operation 2608, a memory cell is formed in contact with a semiconductor substrate (e.g., its doped first end). The memory cell may include a capacitor or a PCM element. In some embodiments, to form a memory cell that is a capacitor, a first electrode is formed on the doped first end of the semiconductor substrate, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric.

[0315] like FIG. 22H As shown, one or more ILD layers are formed on the top surface of a semiconductor body 2206, for example, by depositing a dielectric material using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). A first electrode 2228, a capacitor dielectric 2230, and a second electrode 2232 are then formed in the ILD layers to form a capacitor in contact with the semiconductor body 2206. In some embodiments, each first electrode 2228 is formed on the corresponding source / drain 2224 (i.e., the doped upper end of the corresponding semiconductor body 2206) by patterning and etching electrode holes aligned with the corresponding source / drain 2224 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin-film deposition process. Similarly, in some embodiments, the second electrode 2232 is formed on the capacitor dielectric 2230 by patterning and etching electrode holes aligned with the corresponding capacitor dielectric 2230 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin-film deposition process.

[0316] exist FIG. 26 At operation 2610, the substrate is thinned to expose the second end of the semiconductor body opposite the first end. As shown in FIG22, a carrier substrate 2234 (also referred to as a processing substrate) is bonded to the front side of the SOI substrate 2201, and a device is formed on the front side of the SOI substrate 2201 using any suitable bonding process (e.g., anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped over so that the processing layer 2202 of the SOI substrate 2201 is above the carrier substrate 2234.

[0317] like FIG. 22J As shown, the SOI substrate 2201 is thinned to expose the undoped upper portion of the semiconductor body 2206 (which serves as the lower portion before flipping). In some embodiments, planarization processes (e.g., CMP) and / or e...

Claims

1. A memory device, comprising: Comprising: a bit line extending along a first direction; a first transistor comprising a first semiconductor body extending along a second direction and a first gate structure located at one side of the first semiconductor body along the first direction, the first semiconductor body coupled with the bit line, the first direction intersecting the second direction; a second transistor comprising a second semiconductor body extending along the second direction and a second gate structure located at one side of the second semiconductor body along the first direction, the second semiconductor body coupled with the bit line; and a first isolation structure located between the first semiconductor body and the second semiconductor body along the first direction; wherein the first semiconductor body contacts the first isolation structure and the second semiconductor body contacts the first isolation structure.

2. The memory device of claim 1, wherein, the first semiconductor body is located between the first isolation structure and the first gate structure along the first direction; the second semiconductor body is located between the first isolation structure and the second gate structure along the first direction.

3. The memory device of claim 1, wherein, the first gate structure comprises a first gate electrode and a first gate dielectric layer located between the first gate electrode and the first semiconductor body; the second gate structure comprises a second gate electrode and a second gate dielectric layer located between the second gate electrode and the second semiconductor body.

4. The memory device of claim 3, wherein, the first gate dielectric layer contacts the first semiconductor body, the first semiconductor body being located between the first isolation structure and the first gate dielectric layer along the first direction; the second gate dielectric layer contacts the second semiconductor body, the second semiconductor body being located between the first isolation structure and the second gate dielectric layer along the first direction.

5. The memory device of claim 1, wherein, the first isolation structure comprises a first air gap structure located between the first semiconductor body and the second semiconductor body along the first direction.

6. The memory device of claim 1, wherein, Further comprising: a third transistor comprising a third semiconductor body extending along the second direction, the third semiconductor body coupled with the bit line; a second isolation structure located between the second semiconductor body and the third semiconductor body along the first direction.

7. The memory device of claim 6, wherein, the third transistor comprises a third gate structure located at one side of the third semiconductor body along the first direction; the second gate structure is located between the second semiconductor body and the second isolation structure; the third gate structure is located between the third semiconductor body and the second isolation structure.

8. The memory device of claim 7, wherein, the third gate structure comprises a third gate electrode and a third gate dielectric layer, the third gate dielectric layer located between the third gate electrode and the third semiconductor body; the third gate electrode contacts the second isolation structure.

9. The memory device of claim 7, wherein, the second isolation structure comprises a second air gap structure located between the second gate structure and the third gate structure along the first direction.

10. The memory device of claim 1, wherein, the first gate structure and the second gate structure extend along a third direction, the third direction intersecting both the first direction and the second direction.

11. The memory device of claim 1, wherein, Also included are a first memory cell and a second memory cell, the first memory cell and the bit line being coupled to opposite ends of the first semiconductor body along the second direction, the second memory cell and the bit line being coupled to opposite ends of the second semiconductor body along the second direction.

12. A memory device, comprising: including a first semiconductor structure; the first semiconductor structure includes: a bit line extending along a first direction; and a memory cell array including a plurality of memory cells coupled to the bit line, the memory cells including a transistor extending along a second direction and a memory cell coupled to the transistor, the second direction intersecting the first direction; wherein a respective bit line and a respective memory cell are coupled to opposite ends of the transistor along the second direction; a first one of two transistors adjacent along the first direction includes a first semiconductor body, a second one of the two transistors adjacent along the first direction includes a second semiconductor body, and an air gap structure is between the first semiconductor body and the second semiconductor body.

13. The memory device of claim 12, wherein, the first semiconductor structure further includes an isolation structure between the first semiconductor body and the second semiconductor body along the first direction, the air gap structure being in the isolation structure.

14. The memory device of claim 12, wherein, the first one of the two transistors adjacent along the first direction further includes a first gate structure on a side of the first semiconductor body along the first direction; the second one of the two transistors adjacent along the first direction further includes a second gate structure on a side of the second semiconductor body along the first direction.

15. The memory device of claim 14, wherein, the first semiconductor body is between the air gap structure and the first gate structure along the first direction; the second semiconductor body is between the air gap structure and the second gate structure along the first direction.

16. The memory device of claim 14, wherein, the first gate structure is between the air gap structure and the first semiconductor body along the first direction; the second gate structure is between the air gap structure and the second semiconductor body along the first direction.

17. The memory device of claim 12, wherein, Also included is a second semiconductor structure including a peripheral circuit, wherein the second semiconductor structure is bonded to the first semiconductor structure, and the memory cell array is coupled to the peripheral circuit.

18. A method for forming a memory device, comprising: including: forming a bit line extending along a first direction; forming a first transistor including a first semiconductor body extending along a second direction and a first gate structure on a side of the first semiconductor body along the first direction, the first semiconductor body being coupled to the bit line, the first direction intersecting the second direction; forming a second transistor including a second semiconductor body extending along the second direction and a second gate structure on a side of the second semiconductor body along the first direction, the second semiconductor body being coupled to the bit line; and forming a first isolation structure between the first semiconductor body and the second semiconductor body along the first direction; The first semiconductor body is in contact with the first isolation structure, and the second semiconductor body is in contact with the first isolation structure.

19. The method of claim 18, wherein, The forming of the first isolation structure comprises: forming a semiconductor column extending along the second direction on the substrate; forming a trench passing through the semiconductor column along the second direction, the trench dividing the semiconductor column into a plurality of semiconductor bodies.

20. The method of claim 19, wherein, The forming of the first isolation structure further comprises: filling a dielectric layer in the trench, the dielectric layer being in contact with both the first semiconductor body and the second semiconductor body.

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