Memory and forming method thereof
By using a multilayer dielectric structure of hafnium zirconium oxide and aluminum oxide in DRAM, the problems of insufficient capacitance and excessive leakage current in DRAM capacitors during the miniaturization process are solved, thereby achieving increased capacitance and suppressed leakage current.
Patent Information
- Application Number
- CN202511583171.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-06-18
- Filing Date
- 2025-10-31
- Publication Date
- 2026-01-23
AI Technical Summary
As DRAM feature sizes shrink, insufficient capacitance and excessive leakage current become challenges that are difficult to overcome due to the limitations of existing material miniaturization.
Hafnium zirconium oxide (HfZrO) is used as the dielectric material, and a multilayer dielectric structure is formed by atomic layer deposition (ALD) process, including a silicon-doped first dielectric layer and an undoped second dielectric layer, combined with a barrier layer of aluminum oxide to improve the dielectric constant and suppress leakage current.
The capacitance value was increased, and the leakage current was reduced to meet the requirements of DRAM miniaturization.
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Figure CN121398006A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to memory and methods of forming the same. BACKGROUND
[0002] As dynamic random access memory (DRAM) feature sizes continue to shrink, the shrinking storage capacitor faces critical challenges: insufficient capacitance and excessive leakage current. In addition, while performing a post-deposition anneal process can improve capacitance by obtaining a high-k phase, leakage current at the grain boundaries after annealing increases. In the miniaturization of DRAM capacitors, much effort has been devoted to finding new material stacks to overcome the miniaturization limitations of existing materials. SUMMARY
[0003] Some embodiments of the present disclosure provide a memory comprising a substrate and a capacitor structure over the substrate. The capacitor structure comprises a bottom electrode, a dielectric structure over the bottom electrode, and a top electrode over the dielectric structure. The dielectric structure comprises a first dielectric layer made of hafnium-zirconium oxide (HZO) over the bottom electrode, a blocking layer made of aluminum oxide over the first dielectric layer, and a second dielectric layer made of hafnium-zirconium oxide over the blocking layer, wherein one of the first dielectric layer and the second dielectric layer comprises a first portion adjacent to the blocking layer and a second portion, and wherein the first portion is doped with silicon.
[0004] In some embodiments, the dielectric structure has an aluminum concentration in a range from about 1% to about 10%.
[0005] In some embodiments, the dielectric structure has a silicon concentration in a range from about 1% to about 10%.
[0006] In some embodiments, the second portion of one of the first dielectric layer and the second dielectric layer is free of silicon.
[0007] In some embodiments, the dielectric structure has a thickness in a range from about 30A to about 90A.
[0008] In some embodiments, the dielectric structure has a dielectric constant (k) of about 42.
[0009] In some embodiments, the first dielectric layer is free of silicon.
[0010] In some embodiments, the second dielectric layer is free of silicon.
[0011] In some embodiments, both the first dielectric layer and the second dielectric layer comprise the first portion.
[0012] In some embodiments, the memory further includes: a word line structure over the substrate; and a bit line structure over the substrate and electrically connected to a doped region of the substrate on a first side of the word line structure, wherein the capacitor structure is electrically connected to another doped region of the substrate on a second side of the word line structure.
[0013] Some embodiments of the present disclosure provide a method of forming a memory, comprising: forming a capacitor structure over a substrate. Forming the capacitor structure comprises: forming a bottom electrode; forming a dielectric structure over the bottom electrode; and forming a top electrode over the dielectric structure. Forming the dielectric structure comprises: forming a first dielectric layer made of hafnium-zirconium oxide (HZO); forming a barrier layer over the first dielectric layer and made of aluminum oxide; and forming a second dielectric layer over the barrier layer and made of hafnium-zirconium oxide, wherein one of the first dielectric layer and the second dielectric layer includes a first portion adjacent to the barrier layer and a second portion, and wherein the first portion is doped with silicon.
[0014] In some embodiments, the dielectric structure has an aluminum concentration in a range from about 1% to about 10%.
[0015] In some embodiments, the dielectric structure has a silicon concentration in a range from about 1% to about 10%.
[0016] In some embodiments, the second portion of one of the first dielectric layer and the second dielectric layer is free of silicon.
[0017] In some embodiments, the first portion of one of the first dielectric layer and the second dielectric layer is formed by a plurality of deposition cycles, wherein each of the deposition cycles comprises: depositing a hafnium oxide layer; depositing a silicon oxide layer; and depositing a zirconium oxide layer.
[0018] In some embodiments, the first portion of one of the first dielectric layer and the second dielectric layer is formed by a plurality of deposition cycles, wherein the deposition cycles comprise one or more first sub-cycles and one or more second sub-cycles, wherein the first sub-cycles comprise depositing a hafnium oxide layer and depositing a zirconium oxide layer, and the second sub-cycles comprise depositing a hafnium oxide layer, a silicon oxide layer, and a zirconium oxide layer.
[0019] In some embodiments, the deposition cycles comprise performing X first sub-cycles and performing Y second sub-cycles, wherein X and Y are positive integers.
[0020] In some embodiments, X and Y are different positive integers.
[0021] In some embodiments, X is equal to Y.
[0022] In some embodiments, the dielectric structure has a thickness in a range from about 30Å to about 90Å. BRIEF DESCRIPTION OF DRAWINGS
[0023] The nature of the application will be more fully understood by the following detailed description, taken in conjunction with the accompanying drawings, in which:
[0024] Figure 1 A schematic of a capacitor structure is shown in accordance with some embodiments of the application.
[0025] Figure 2 A schematic of a capacitor structure is shown in accordance with some embodiments of the application.
[0026] Figure 3 A schematic of a capacitor structure is shown in accordance with some embodiments of the application.
[0027] Figure 4 A circuit diagram of a memory cell of a memory is shown in accordance with some embodiments of the application.
[0028] Figure 5 A cross-sectional view of a memory is shown in accordance with some embodiments of the application.
[0029] Figures 6 to 14 Cross-sectional views of different stages of forming a memory are shown in accordance with some embodiments of the application. DETAILED DESCRIPTION
[0030] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described herein to facilitate discussion of the present application. Such examples are provided by way of explanation of the subject matter and are not meant as a limitation of the application. For example, formation of a first feature over or on a second feature in the description that follows can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features can not be in direct contact. In addition, the present application can be repeated with reference to a singe block across various examples and / or configurations. Such repetition is for the purpose of simplicity and clarity and does not itself convey a relationship between the various embodiments and / or configurations discussed.
[0031] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0032] Figure 1 A schematic diagram of a capacitor structure is shown in accordance with some embodiments of the present application. Please refer to FIG. 1A. Figure 1 The capacitor structure 100A includes a bottom electrode 110, a dielectric structure 120 over the bottom electrode 110, and a top electrode 130 over the dielectric structure 120. The dielectric structure 120 can be a multi-layer structure in which multiple dielectric layers are stacked on top of each other. In some embodiments, the dielectric structure 120 in the capacitor structure 100A includes a first dielectric layer 122, a barrier layer 124 over the first dielectric layer 122, and a second dielectric layer 126 over the barrier layer 124. In some embodiments, the second dielectric layer 126 includes a first portion 126A over the barrier layer 124 and a second portion 126B over the first portion 126A. In some embodiments, the bottom electrode 110 and the top electrode 130 can be formed of, for example, TiN, Ti, W, WN, Pt, Ir, Ru, and other suitable conductive materials.
[0033] In some embodiments, the barrier layer 124 can include a dielectric material, such as aluminum oxide (AlO x ). In some embodiments, the first dielectric layer 122 and the second dielectric layer 126 can include the same high-k dielectric material, such as hafnium-zirconium oxide (HfZrO). In some embodiments, the first portion 126A of the second dielectric layer 126 can be further doped with silicon (Si), such as silicon-doped hafnium-zirconium oxide (HfZrO:Si). In some embodiments, the first dielectric layer 122, the barrier layer 124, and the second portion 126B of the second dielectric layer 126 can be free of silicon. That is, the silicon concentration of the first dielectric layer 122, the barrier layer 124, and the second portion 126B of the second dielectric layer 126 can be lower than the silicon concentration of the first portion 126A of the second dielectric layer 126.
[0034] Further, the aluminum (Al) concentration and the silicon (Si) concentration in the dielectric structure 120 can be analyzed by energy dispersive X-ray (EDX) or X-ray photoelectron spectroscopy (XPS) of a transmission electron microscope (TEM). In some embodiments, the aluminum concentration of the dielectric structure 120 is in a range from about 1% to about 10%. In some embodiments, the silicon concentration of the dielectric structure 120 is in a range from about 1% to about 10%. In some embodiments, the silicon concentration within the dielectric structure 120 gradually decreases in both directions away from the first portion 126A of the second dielectric layer 126.
[0035] Further, the thickness of the dielectric structure 120 of the capacitor structure 100A can be analyzed by XPS or TEM. In some embodiments, the thickness of the dielectric structure 120 can be in a range from about 30 A to about 90 A. In some embodiments, the thickness of the second dielectric layer 126 is greater than the thickness of the first dielectric layer 122 in the capacitor structure 100A.
[0036] As shown in FIG. 1, in some embodiments, the bottom electrode 110, the first dielectric layer 122, the barrier layer 124, the second dielectric layer 126, and the top electrode 130 can be sequentially deposited by a suitable deposition process, such as an atomic layer deposition (ALD) process. Figure 1
[0037] In some embodiments, the first portion 126A of the second dielectric layer 126 includes silicon-doped hafnium-zirconium oxide (HfZrO:Si) formed by an ALD process. The ALD process includes repeatedly performing a plurality of deposition cycles until the first portion 126A of the second dielectric layer 126 reaches a desired thickness. Each cycle includes the following three steps: (i) depositing a layer of hafnium oxide (HfOx); (ii) depositing a layer of silicon oxide (SiOx); and (iii) depositing a layer of zirconium oxide (ZrOx). In some embodiments, steps (i) and (iii) can be interchanged.
[0038] In other embodiments, the ALD process for forming the first portion 126A of the second dielectric layer 126 includes repeatedly performing a plurality of deposition cycles until the first portion 126A of the second dielectric layer 126 reaches a desired thickness, where each deposition cycle can include one or more first sub-cycles and one or more second sub-cycles. In some embodiments, the first sub-cycle includes sequentially depositing a layer of hafnium oxide (HfO x ), followed by depositing a layer of zirconium oxide (ZrO x ). On the other hand, the second sub-cycle includes sequentially depositing a layer of hafnium oxide (HfO x ), a layer of silicon oxide (SiO x ), and a layer of zirconium oxide (ZrO x ). That is, no silicon oxide (SiOx The frequency and ratio of the two sub-cycles can be adjusted to precisely control the silicon doping concentration and overall composition of the dielectric structure 120.
[0039] As mentioned above, each deposition cycle can include one or more first sub-cycles and one or more second sub-cycles. In some embodiments, a deposition cycle can include performing X first sub-cycles and performing Y second sub-cycles, where X and Y are positive integers. In some embodiments, X and Y are different positive integers. In other embodiments, X can be equal to Y.
[0040] Based on the above architecture, the blocking layer 124 (e.g., AIO x ) in the capacitor structure 100A can suppress leakage current. In addition, the first portion 126A of the second dielectric layer 126, after being silicon-doped, can increase the tetragonal phase, thereby increasing the dielectric constant (k) to about 42, thereby increasing the capacitance value. In addition, silicon doping can also deepen the depth of the defect energy level in the dielectric layer, thereby suppressing the leakage current of the capacitor structure 100A.
[0041] Although Figure 1 only planar capacitors are shown in FIG. 1, the spirit of the present disclosure can also be applied to capacitors with different designs, such as cylindrical capacitors or pedestal capacitors.
[0042] Figure 2 FIG. 1 is a schematic diagram of a capacitor structure according to some embodiments of the present disclosure. Referring to FIG. 1, the capacitor structure 100A includes a bottom electrode 110, a dielectric structure 120 located above the bottom electrode 110, and a top electrode 130 located above the dielectric structure 120. Figure 2 The capacitor structure 100B shown in FIG. 2 is similar to the capacitor structure 100A shown in FIG. 1. The same or similar elements are assigned with the same reference numbers, and thus the detailed description thereof is omitted. Figure 2 The capacitor structure 100B shown in FIG. 2 is similar to the capacitor structure 100A shown in FIG. 1. The same or similar elements are assigned with the same reference numbers, and thus the detailed description thereof is omitted. Figure 1 Figure 1 The dielectric structure 120 can be a multi-layer structure in which a plurality of dielectric layers are stacked on each other. In some embodiments, the dielectric structure 120 in the capacitor structure 100B includes a first dielectric layer 122, a blocking layer 124 located above the first dielectric layer 122, and a second dielectric layer 126 located above the blocking layer 124. In some embodiments, the first dielectric layer 122 includes a second portion 122B located above the bottom electrode 110 and a first portion 122A located above the second portion 122B. In some embodiments, the bottom electrode 110 and the top electrode 130 can be formed of, for example, titanium nitride (TiN), titanium (Ti), tungsten (W), tungsten nitride (WN), platinum (Pt), iridium (Ir), ruthenium (Ru), and other suitable conductive materials.
[0043] The dielectric structure 120 can be a multi-layer structure in which a plurality of dielectric layers are stacked on each other. In some embodiments, the dielectric structure 120 in the capacitor structure 100B includes a first dielectric layer 122, a blocking layer 124 located above the first dielectric layer 122, and a second dielectric layer 126 located above the blocking layer 124. In some embodiments, the first dielectric layer 122 includes a second portion 122B located above the bottom electrode 110 and a first portion 122A located above the second portion 122B. In some embodiments, the bottom electrode 110 and the top electrode 130 can be formed of, for example, titanium nitride (TiN), titanium (Ti), tungsten (W), tungsten nitride (WN), platinum (Pt), iridium (Ir), ruthenium (Ru), and other suitable conductive materials.
[0044] In some embodiments, the barrier layer 124 can include a dielectric material, such as aluminum oxide (AlO x ). In some embodiments, the first dielectric layer 122 and the second dielectric layer 126 can include the same high-k dielectric material, such as hafnium-zirconium oxide (HfZrO). In some embodiments, the first portion 122A of the first dielectric layer 122 can be further doped with silicon (Si), such as silicon-doped hafnium-zirconium oxide (HfZrO:Si). In some embodiments, the second portion 122B of the first dielectric layer 122, the barrier layer 124, and the second dielectric layer 126 can be free of silicon. That is, the silicon concentration of the second portion 122B of the first dielectric layer 122, the barrier layer 124, and the second dielectric layer 126 can be lower than the silicon concentration of the first portion 122A of the first dielectric layer 122.
[0045] Further, the aluminum (Al) concentration and the silicon (Si) concentration of the dielectric structure 120 in the capacitor structure 100B can be analyzed by TEM or EDX of XPS. In some embodiments, the aluminum concentration of the dielectric structure 120 is in a range from about 1% to about 10%. In some embodiments, the silicon concentration of the dielectric structure 120 is in a range from about 1% to about 10%. In some embodiments, the silicon concentration within the dielectric structure 120 gradually decreases in both directions away from the first portion 122A of the first dielectric layer 122.
[0046] Further, the thickness of the dielectric structure 120 of the capacitor structure 100B can be analyzed by XPS or TEM. In some embodiments, the thickness of the dielectric structure 120 can be in a range from about 30Å to about 90Å. In some embodiments, the thickness of the first dielectric layer 122 is greater than the thickness of the second dielectric layer 126 in the capacitor structure 100B.
[0047] As shown in FIG. 1A, in some embodiments, the bottom electrode 110, the first dielectric layer 122, the barrier layer 124, the second dielectric layer 126, and the top electrode 130 can be sequentially deposited by a suitable deposition process, such as an atomic layer deposition (ALD) process. Figure 2
[0048] In some embodiments, the first portion 122A of the first dielectric layer 122 includes silicon-doped hafnium-zirconium oxide (HfZrO:Si) formed by an atomic layer deposition (ALD) process. The ALD process includes repeatedly performing a plurality of deposition cycles until the first portion 122A of the first dielectric layer 122 reaches a desired thickness. Each cycle includes the following three steps: (i) depositing a layer of hafnium oxide (HfO x ); (ii) depositing a layer of silicon oxide (SiO x ); and (iii) depositing a layer of zirconium oxide (ZrO x ). In some embodiments, step (i) and step (iii) can be interchanged.
[0049] In other embodiments, the ALD process for forming the first portion 122A of the first dielectric layer 122 includes repeatedly performing a plurality of deposition cycles until the first portion 122A of the first dielectric layer 122 reaches a desired thickness, wherein each deposition cycle can include one or more first sub-cycles and one or more second sub-cycles. In some embodiments, the first sub-cycle includes sequentially depositing a layer of hafnium oxide (HfO x ), followed by depositing a layer of zirconium oxide (ZrO x ). On the other hand, the second sub-cycle includes sequentially depositing a layer of hafnium oxide (HfO x ), a layer of silicon oxide (SiO x ), and a layer of zirconium oxide (ZrO x ). That is, no layer of silicon oxide (SiO x ) is deposited during the first sub-cycle. By adjusting the frequency and ratio of the two sub-cycles, the silicon doping concentration and overall composition of the dielectric structure 120 can be precisely controlled.
[0050] As mentioned above, each deposition cycle can include one or more first sub-cycles and one or more second sub-cycles. In some embodiments, a deposition cycle can include performing a first sub-cycle X times and performing a second sub-cycle Y times, where X and Y are positive integers. In some embodiments, X and Y are different positive integers. In other embodiments, X can be equal to Y.
[0051] Based on the above architecture, the blocking layer 124 (e.g., AlO x ) in the capacitor structure 100B can suppress leakage current. Furthermore, the first portion 122A of the first dielectric layer 122, which is silicon-doped, can increase the tetragonal phase, thereby increasing the dielectric constant (k) to about 42, which in turn increases the capacitance value. Moreover, the silicon doping can also deepen the depth of the defect energy level in the dielectric layer, thereby suppressing the leakage current of the capacitor structure 100B.
[0052] Although Figure 2 only shows a planar capacitor, the spirit of the present disclosure can also be applied to capacitors with different designs, such as cylindrical capacitors or pedestal capacitors.
[0053] Figure 3 A schematic diagram of a capacitor structure according to some embodiments of the present disclosure. Referring to Figure 3 , the capacitor structure 100C includes a bottom electrode 110, a dielectric structure 120 located above the bottom electrode 110, and a top electrode 130 located above the dielectric structure 120. Figure 3 The capacitor structure 100C shown is similar to Figure 1 and Figure 2Capacitor structure 100A and capacitor structure 100B are similar. As such, the detailed description of capacitor structure 100A is omitted. Figure 1 As such, the detailed description of capacitor structure 100A is omitted. Figure 2 The same or similar elements are denoted by the same reference numbers, and thus the detailed description thereof is omitted.
[0054] Dielectric structure 120 can be a multi-layer structure in which multiple dielectric layers are stacked on top of each other. In some embodiments, dielectric structure 120 in capacitor structure 100C includes a first dielectric layer 122, a barrier layer 124 located above first dielectric layer 122, and a second dielectric layer 126 located above barrier layer 124. In some embodiments, first dielectric layer 122 includes a second portion 122B located above bottom electrode 110 and a first portion 122A located above second portion 122B. Second dielectric layer 126 includes a first portion 126A located above barrier layer 124 and a second portion 126B located above first portion 126A. In some embodiments, bottom electrode 110 and top electrode 130 can be formed of, for example, titanium nitride (TiN), titanium (Ti), tungsten (W), tungsten nitride (WN), platinum (Pt), iridium (Ir), ruthenium (Ru), and other suitable conductive materials.
[0055] In some embodiments, barrier layer 124 can include a dielectric material, such as aluminum oxide (AlO x In some embodiments, first dielectric layer 122 and second dielectric layer 126 can include the same high-k dielectric material, such as hafnium-zirconium oxide (HfZrO). In some embodiments, first portion 122A of first dielectric layer 122 and first portion 126A of second dielectric layer 126 can also be doped with silicon (Si), such as silicon-doped hafnium-zirconium oxide (HfZrO:Si). In some embodiments, second portion 122B of first dielectric layer 122, barrier layer 124, and second portion 126B of second dielectric layer 126 can be free of silicon. That is, the silicon concentration in second portion 122B of first dielectric layer 122, barrier layer 124, and second portion 126B of second dielectric layer 126 can be lower than the silicon concentration in first portion 122A of first dielectric layer 122 and first portion 126A of second dielectric layer 126.
[0056] In addition, the aluminum (Al) concentration and silicon (Si) concentration of dielectric structure 120 in capacitor structure 100C can be analyzed by TEM or XPS EDX. In some embodiments, the aluminum concentration of dielectric structure 120 is in a range from about 1% to about 10%. In some embodiments, the silicon concentration of dielectric structure 120 is in a range from about 1% to about 10%. In some embodiments, the silicon concentration within dielectric structure 120 gradually decreases in both directions away from first portion 122A of first dielectric layer 122 and first portion 126A of second dielectric layer 126.
[0057] Further, the thickness of the dielectric structure 120 of the capacitor structure 100C can be analyzed using XPS or TEM. In some embodiments, the thickness of the dielectric structure 120 can be in a range from about 30 A to about 90 A.
[0058] As shown in FIG. 1C, in some embodiments, the bottom electrode 110, the first dielectric layer 122, the barrier layer 124, the second dielectric layer 126, and the top electrode 130 can be sequentially deposited by a suitable deposition process, such as an atomic layer deposition (ALD) process. Figure 3
[0059] In some embodiments, the first portion 122A of the first dielectric layer 122 and the first portion 126A of the second dielectric layer 126 include silicon-doped hafnium-zirconium oxide (HfZrO:Si) formed by an ALD process. The ALD process includes repeatedly performing a plurality of deposition cycles until the first portion 122A of the first dielectric layer 122 reaches a desired thickness, where each cycle includes the following three steps: (i) depositing a layer of hafnium oxide (HfO x ); (ii) depositing a layer of silicon oxide (SiO x ); and (iii) depositing a layer of zirconium oxide (ZrO x ). In some embodiments, steps (i) and (iii) can be interchanged. In some embodiments, the first portion 126A of the second dielectric layer 126 can be formed using the same or similar ALD process as the first portion 122A of the first dielectric layer 122.
[0060] In other embodiments, the ALD process for forming the first portion 122A of the first dielectric layer 122 and the first portion 126A of the second dielectric layer 126 includes repeatedly performing a plurality of deposition cycles until the first portion 122A of the first dielectric layer 122 and the first portion 126A of the second dielectric layer 126 reach a desired thickness, where each deposition cycle can include one or more first sub-cycles. In some embodiments, a first sub-cycle includes sequentially depositing a layer of hafnium oxide (HfO x ), followed by a layer of zirconium oxide (ZrO x ). On the other hand, a second sub-cycle includes sequentially depositing a layer of hafnium oxide (HfO x ), a layer of silicon oxide (SiO x ), and a layer of zirconium oxide (ZrO x ). That is, no layer of silicon oxide (SiO x ) is deposited during the first sub-cycle. By adjusting the frequency and proportion of the two sub-cycles, the silicon doping concentration and overall composition of the dielectric structure 120 can be precisely controlled.
[0061] As discussed above, each deposition cycle can include one or more first sub-cycles and one or more second sub-cycles. In some embodiments, a deposition cycle can include performing X number of first sub-cycles and performing Y number of second sub-cycles, where X and Y are positive integers. In some embodiments, X and Y are different positive integers. In other embodiments, X can be equal to Y.
[0062] Based on the above architecture, the blocking layer 124 (e.g., AIO x ) in the capacitor structure 100C can suppress leakage current. In addition, the silicon-doped first portion 122A of the first dielectric layer 122 and the silicon-doped first portion 126A of the second dielectric layer 126 can increase the tetragonal phase, thereby increasing the dielectric constant (k) to about 42, and in turn, increasing the capacitance value. In addition, the silicon-doping can also deepen the depth of the defect energy level in the dielectric layer, thereby suppressing the leakage current of the capacitor structure 100C.
[0063] Although Figure 3 only planar capacitors are shown in FIGS. 1-3, the spirit of the present application can also be applied to capacitors having different designs, such as cylindrical capacitors or pedestal capacitors.
[0064] Figure 4 is a circuit diagram of a memory cell of a memory according to some embodiments of the present application. Referring to Figure 4 , the memory 200 is composed of a plurality of memory cells 202 arranged in a rectangular matrix structure. In some embodiments, the memory 200 is a dynamic random access memory (DRAM) device. The memory cell 202 of the memory 200 is composed of a transistor 200T and a capacitor 200C electrically connected to the transistor 200T as the main structure. One side of the capacitor 200C is coupled to the drain region of the transistor 200T, while the other side of the capacitor 200C is coupled to ground. The memory 200 also includes a word line 200W coupled to the gate region of the transistor 200T, and a bit line 200B coupled to the source of the transistor 200T.
[0065] Figure 5 is a cross-sectional view of a memory according to some embodiments of the present application. The memory 400 is shown. In some embodiments, the cross-sectional view of the memory 400 can be an example of the memory 200 as discussed in Figure 4 .
[0066] Memory 400 includes a substrate 301. In some embodiments, substrate 301 can be a suitable semiconductor material, such as silicon, silicon carbide, gallium arsenide, gallium phosphide, germanium, indium antimonide, indium phosphide, indium arsenide, etc. Substrate 301 can also be doped with a suitable dopant. For example, substrate 301 can be doped with a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), etc. In other embodiments, substrate 301 can be doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), etc.
[0067] Isolation structures 302 are disposed within substrate 301. Isolation structures 302 can be suitable isolation structures, such as shallow trench isolation (STI) structures. In the cross-sectional view of FIG. 4A, two isolation structures 302 are shown, which define an active region 301 A over which at least one transistor is formed. In some embodiments, isolation structures 302 can be made of a suitable dielectric material, such as silicon oxide, silicon nitride, etc. Figure 5
[0068] Memory 400 also includes a plurality of wordline structures 316A and wordline structures 316B. In more detail, in the cross-sectional view of FIG. 4B, wordline structures 316A are embedded in active region 301 A of substrate 301, while wordline structures 316B are embedded in isolation structures 302. Figure 5
[0069] Memory 400 also includes a dielectric layer 306A over corresponding wordline structures 316A, and a dielectric liner 303A that lines corresponding wordline structures 316A and corresponding dielectric layer 306A. In some embodiments, dielectric layer 306A can include a suitable dielectric material, such as silicon oxide, silicon nitride, etc. In some embodiments, dielectric liner 303A can include a suitable dielectric material, such as silicon oxide, silicon nitride, etc.
[0070] Similarly, memory 400 also includes a dielectric layer 306B over corresponding wordline structures 316B, and a dielectric liner 303B that lines corresponding wordline structures 316B and corresponding dielectric layer 306B. The materials of dielectric layer 306B and dielectric liner 303B can be similar to the materials described with respect to dielectric layer 306A and dielectric liner 303A, and therefore, for brevity, relevant details will not be repeated.
[0071] In some embodiments, each word line structure 316A includes a bottom conductive material 304A and a top conductive material 305A over the bottom conductive material 304A. In some embodiments, the bottom conductive material 304A and the top conductive material 305A are made of different materials. In some embodiments, the bottom conductive material 304A can include a suitable conductive material such as cobalt, nickel, titanium, titanium nitride, tungsten, tungsten nitride, etc., or a combination thereof. For example, in some embodiments, a combination of titanium nitride and tungsten is used as the bottom conductive material 304A. In some embodiments, the top conductive material 305A can be a suitable material that reduces band bending between the active region 301 A and the dielectric liner 303A. The top conductive material 305A can be a semiconductor material or a conductive material. In some embodiments, polysilicon is used for the top conductive material 305A. In some other embodiments, doped polysilicon is used for the top conductive material 305A. Although the top conductive material 305A is depicted as having a rectangular cross-section, the present disclosure is not limited thereto. In other embodiments, the top conductive material 305A can also have a semi-circular, triangular, trapezoidal, inverted trapezoidal, irregular shape, etc.
[0072] For the word line structure 316B, each word line structure 316B includes a bottom conductive material 304B and a top conductive material 305B over the bottom conductive material 304B. The materials of the bottom conductive material 304B and the top conductive material 305B can be similar to those described for the bottom conductive material 304A and the top conductive material 305A, and thus the relevant details will not be repeated for brevity.
[0073] The memory 400 also includes a plurality of doped regions 301D within the active region 301A of the substrate 301, where a pair of doped regions 301D is disposed on opposite sides of the word line structure 316A. In some embodiments, the doped regions 301D can include a conductive type opposite that of the substrate 301. For example, when the substrate 301 is a p-type substrate, the doped regions 301D can be n-type doped regions. Similarly, when the substrate 301 is an n-type substrate, the doped regions 301D can be p-type doped regions.
[0074] Here, the word line structure 316A, the dielectric liner 303A, the pair of doped regions 301D on opposite sides of the word line structure 316A, and the active region 301A of the substrate 301 can collectively function as a transistor (e.g., a transistor 200T) of the memory 400. In more detail, the word line structure 316A can function as a gate electrode of the transistor, the dielectric liner 303A can function as a gate dielectric of the transistor, the active region 301A of the substrate 301 can function as a channel region of the transistor, and the doped regions 301D can function as source / drain regions of the transistor. Figure 4 Here, the word line structure 316A, the dielectric liner 303A, the pair of doped regions 301D on opposite sides of the word line structure 316A, and the active region 301A of the substrate 301 can collectively function as a transistor (e.g., a transistor 200T) of the memory 400. In more detail, the word line structure 316A can function as a gate electrode of the transistor, the dielectric liner 303A can function as a gate dielectric of the transistor, the active region 301A of the substrate 301 can function as a channel region of the transistor, and the doped regions 301D can function as source / drain regions of the transistor.
[0075] The memory 400 also includes a bit line structure 317 over the substrate 301 and electrically coupled to one of the plurality of doped regions 301D. In some embodiments, the bit line structure 317 can include a shield contact 312A and a bit line 311A over the shield contact 312A. In some embodiments, the shield contact 312A has a portion embedded in the substrate 301 and a portion protruding from the substrate 301. In some embodiments, the material of the shield contact 312A can be doped silicon or polysilicon. In some embodiments, the material of the bit line 311A can be a suitable conductive material such as tungsten, tungsten nitride, titanium nitride, etc. or a combination thereof.
[0076] The memory 400 also includes a capacitor contact structure 318 over the substrate 301 and electrically coupled to the doped region 301D. In some embodiments, each capacitor contact structure 318 can include a shield contact 312B and a metal contact 311B over the shield contact 312B. In some embodiments, the shield contact 312B has a portion embedded in the substrate 301 and a portion protruding from the substrate 301. In some embodiments, the materials of the shield contact 312B and the metal contact 311B can be similar to the materials described with respect to the shield contact 312A and the bit line 311A, and thus, for brevity, the relevant details will not be repeated.
[0077] The memory 400 also includes a capacitor structure 100 over the corresponding capacitor contact structure 318. In some embodiments, each capacitor structure 100 includes a bottom electrode 110, a first dielectric layer 122, a barrier layer 124, a second dielectric layer 126, and a top electrode 130, where the second dielectric layer 126 includes a first portion 126A and a second portion 126B. In some embodiments, the cross-section of the bottom electrode 110, the first dielectric layer 122, the barrier layer 124, the second dielectric layer 126, and the top electrode 130 can be U-shaped.
[0078] Figure 5 The capacitor structure 100 in the memory 400 is similar to the capacitor structure 100A, the capacitor structure 100B, and the capacitor structure 100C discussed in Figures 1 to 3 In more detail, the bottom electrode 110, the first dielectric layer 122, the barrier layer 124, the first portion 126A and the second portion 126B of the second dielectric layer 126, and the top electrode 130 of the capacitor structure 100 can employ similar materials and formation methods as the bottom electrode 110, the first dielectric layer 122, the barrier layer 124, the first portion 126A and the second portion 126B of the second dielectric layer 126, and the top electrode 130 of the capacitor structure 100A, the capacitor structure 100B, and the capacitor structure 100C, respectively. Similar to the capacitor structure 100A, the capacitor structure 100B, and the capacitor structure 100C, Figures 1 to 3Like or similar elements in the various figures are designated by like reference numerals. Accordingly, for the sake of clarity, the relevant details of like or similar elements will not be repeated in the following description.
[0079] The memory 400 also includes a dielectric layer 307 over the substrate 301 and laterally surrounding the bit line structure 317, the capacitor contact structure 318, and the capacitor structure 100. In some embodiments, the dielectric layer 307 can be formed of, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, or the like, or combinations thereof.
[0080] Figures 6 to 14 are cross-sectional views of various stages of forming a memory according to some embodiments of the present disclosure. In more detail, Figures 6 to 14 illustrates a method for forming a memory as Figure 5 discussed. Accordingly, like elements are labeled with like reference numerals, and the relevant details will not be repeated for the sake of brevity.
[0081] Referring to Figure 6 , a substrate 301 is provided. An isolation structure 302 is formed in the substrate 301 to define an active region 301 A. For example, a series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) over the substrate 301. A photolithography process can be performed to define the location of the isolation structure 302. After the photolithography process, an etching process such as an anisotropic dry etching process can be performed to form a trench that penetrates the pad oxide layer, the pad nitride layer, and the substrate 301. In some embodiments, a cleaning process can be performed by a suitable cleaning method, such as a wet cleaning. An insulating material can be deposited into the trench, and a planarization process such as chemical mechanical polishing can be subsequently performed to remove the excess fill material until the substrate 301 is exposed. After the formation of the isolation structure 302, a doped region 301D can be formed within the active region 301A of the substrate 301 by an implantation process.
[0082] Referring to Figure 7In some embodiments, a patterned mask (e.g., a photoresist layer) can be formed over the substrate 301, where the patterned mask can include openings that define the locations of the trench 501 A and the trench 501B. Subsequently, an etching process can be performed from the openings of the patterned mask to remove portions of the substrate 301 and the isolation structure 302 to form the trench 501 A and the trench 501B. In some embodiments, the etching process can be a suitable etching process, such as a wet etching or a dry etching. In some embodiments, an anisotropic etching process, such as a Reactive-Ion Etching (RIE) process, a Deep Reactive-Ion Etching (DRIE) process, or the like, can be performed. In some embodiments, the aspect ratio of the trench 501 A can be different from (or the same as) the aspect ratio of the trench 501B.
[0083] Referring to Figure 8 The dielectric liner 303 A and the wordline structure 316A are formed in the trench 501 A, and the dielectric liner 303B and the wordline structure 316B are formed in the trench 501B, respectively. The wordline structure 316A includes the bottom conductive material 304A and the top conductive material 305A over the bottom conductive material 304A. The wordline structure 316B includes the bottom conductive material 304B and the top conductive material 305B over the bottom conductive material 304B.
[0084] In some embodiments, a first deposition process can be performed to form the material of the dielectric liner 303 A and the dielectric liner 303B over the substrate 301 and on the liner sidewalls of the trench 501 A and the trench 501B. In some embodiments, the first deposition process can be a suitable deposition method, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), ultrahigh vacuum CVD (UHVCVD), atomic layer deposition (ALD), or the like.
[0085] Subsequently, a second deposition process can be performed to form the material of the bottom conductive material 304A and the bottom conductive material 304B over the substrate 301 and to overfill the trench 501 A and the trench 501B. Then, an etch-back process can be performed to lower the top surface of the material of the bottom conductive material 304A and the bottom conductive material 304B.
[0086] Subsequently, a third deposition process can be performed to form the material of the top conductive material 305A and the top conductive material 305B and to overfill the trench 501 A and the trench 501B.
[0087] After the deposition process, a planarization process such as CMP can be performed on the material of the top conductive material 305A and the top conductive material 305B until the substrate 301 is exposed. As a result, the top surface of the substrate 301, the top surface of the top conductive material 305A, the top surface of the top conductive material 305B, and the top surface of the isolation structure 302 are substantially coplanar. In some embodiments, a cleaning process can be performed after the planarization process.
[0088] Referring to Figure 9 An etch-back process can be performed to lower the top surfaces of the top conductive material 305A and the top conductive material 305B to form recesses 701A and 701B over the word line structure 316A and the word line structure 316B, respectively.
[0089] Referring to Figure 10 The dielectric layer 306A and the dielectric layer 306B are formed over the word line structure 316A and the word line structure 316B, respectively. In some embodiments, a deposition process can be performed to form a dielectric material over the substrate 301 and cover the word line structure 316A and the word line structure 316B. Then, a planarization process can be performed to remove the excess dielectric material until the substrate 301 is exposed. In some embodiments, the planarization process can be performed to make the top surface of the dielectric layer 306A and the top surface of the dielectric layer 306B coplanar with the surface of the substrate 301.
[0090] Referring to Figure 11 The recesses 911A and 911B are formed in the doped region 301D of the substrate 301. In some embodiments, the bottoms of the recesses 911A and 911B can be higher than the top surface of the top conductive material 305A. In some embodiments, a patterned mask (not shown) is formed over the substrate 301, and an etching process is performed to remove the portions of the substrate 301 exposed by the patterned mask to form the recesses 911A and 911B. In some embodiments, a cleaning process can be performed after the etching process. In some embodiments, the recess 911A can be formed between adjacent dielectric layers 306A. In some embodiments, the recess 911B can be formed between adjacent dielectric layers 306A and 306B.
[0091] Referring to Figure 12 The first conductive layer 921 is formed over the substrate 301, and the second conductive layer 923 is formed over the first conductive layer 921. In some embodiments, the first conductive layer 921 can fill the recesses 911A and 911B, and can be in contact with the doped region 301D. In some embodiments, the first conductive layer 921 and the second conductive layer 923 can be formed using appropriate deposition processes.
[0092] Referring to Figure 13The first and second conductive layers 921 and 923 are patterned to form bit line structures 317 and capacitor contact structures 318. In some embodiments, the bit line structures 317 include a shield contact 212A and a bit line 211A above the shield contact 212A, where the shield contact 212A is a remaining portion of the first conductive layer 921 and the bit line 211A is a remaining portion of the second conductive layer 923. On the other hand, the capacitor contact structures 318 include a shield contact 212B and a metal contact 211B above the shield contact 212B, where the shield contact 212B is a remaining portion of the first conductive layer 921 and the metal contact 211B is a remaining portion of the second conductive layer 923.
[0093] Reference is made to Figure 14 A dielectric layer 307 is formed over the substrate 301 and covers the bit line structures 317 and the capacitor contact structures 318. Then, a capacitor structure 100 is formed in the dielectric layer 307 and in contact with a corresponding capacitor contact structure 318. In some embodiments, the dielectric layer 307 can be formed using a suitable deposition process. In some embodiments, the capacitor structure 100 can be formed by, for example, patterning the dielectric layer 307 to form an opening exposing the capacitor contact structure 318, depositing the bottom electrode 110, the first dielectric layer 122, the barrier layer 124, the second dielectric layer 126, and the top electrode 130 in the opening, and then performing a planarization process until the dielectric layer 307 is exposed. The second dielectric layer 126 includes a first portion 126A and a second portion 126B.
[0094] In some embodiments, additional processes and steps can be performed to complete the fabrication process of the memory. In some embodiments, additional back end of line (BEOL) processes can be performed on the memory 400.
[0095] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the present application. Those skilled in the art should appreciate that they can readily use the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present application, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present application.
[0096] NOTATION 100: capacitor structure 100A: capacitor structure 100B: capacitor structure 100C: capacitor structure 110: bottom electrode 120: dielectric structure 122: first dielectric layer 122A: first portion 122B: second portion 124: barrier layer 126: second dielectric layer 126A: first portion 126B: second portion 130: top electrode 200: memory 200B: bit line 200C: capacitor 200T: transistor 200W: word line 202: memory cell 211A: bit line 211B: metal contact 212A: mask contact 212B: mask contact 301: substrate 301A: active region 301D: doped region 302: isolation structure 303A: dielectric liner 303B: dielectric liner 304A: bottom conductive material 304B: bottom conductive material 305A: top conductive material 305B: top conductive material 306A: dielectric layer 306B: dielectric layer 307: dielectric layer 311A: bit line 311B: metal contact 312A: mask contact 312B: mask contact 316A: word line structure 316B: word line structure 317: bit line structure 318: capacitor contact structure 400: memory 501A: trench 501B: trench 701A: recess 701B: recess 911A: recess 911B: recess 921: first conductive layer 923: second conductive layer
Claims
1. A memory, comprising: Comprising: 。 2. The memory of claim 1, wherein an aluminum concentration of the dielectric structure is in a range of 1% to 10%.
3. The memory of claim 1, wherein a silicon concentration of the dielectric structure is in a range of 1% to 10%.
4. The memory of claim 1, wherein the second portion of the one of the first and second dielectric layers is free of silicon.
5. The memory of claim 1, wherein a thickness of the dielectric structure is in a range of 30A to 90A.
6. The memory of claim 1, wherein a dielectric constant of the dielectric structure is 42.
7. The memory of claim 1, wherein the first dielectric layer is free of silicon.
8. The memory of claim 1, wherein the second dielectric layer is free of silicon.
9. The memory of claim 1, wherein both the first and second dielectric layers include the first portion.
10. The memory of claim 1, wherein, Further comprising: a word line structure over the substrate; and a bit line structure over the substrate and electrically connected to a doped region of the substrate on a first side of the word line structure, wherein the capacitor structure is electrically connected to another doped region of the substrate on a second side of the word line structure.
11. A method of forming a memory, comprising: Comprising: 。 12. The method of claim 11, wherein an aluminum concentration of the dielectric structure is in a range of 1% to 10%.
13. The method of claim 11, wherein a silicon concentration of the dielectric structure is in a range of 1% to 10%.
14. The method of claim 11, wherein the second portion of the one of the first and second dielectric layers is free of silicon.
15. The method of claim 11, wherein the first portion of the one of the first and second dielectric layers is formed by a plurality of deposition cycles, wherein each of the plurality of deposition cycles comprises: depositing a hafnium oxide layer; depositing a silicon oxide layer; and depositing a zirconium oxide layer.
16. The method of claim 11, wherein the first portion of the one of the first and second dielectric layers is formed by a plurality of deposition cycles, wherein the plurality of deposition cycles comprises one or more first sub-cycles and one or more second sub-cycles, wherein the first sub-cycles comprise depositing a hafnium oxide layer and a zirconium oxide layer, and the second sub-cycles comprise depositing a hafnium oxide layer, a silicon oxide layer, and a zirconium oxide layer.
17. The method of claim 16, wherein the plurality of deposition cycles comprises performing the first sub-cycle X times and performing the second sub-cycle Y times, wherein X and Y are positive integers.
18. The method of claim 17, wherein X and Y are different positive integers.
19. The method of claim 17, wherein X is equal to Y.
20. The method of claim 17, wherein a thickness of the dielectric structure is in a range of 30A to 90A.