Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device comprises a substrate, a first capacitor structure, a second capacitor structure and a conductive column assembly. The first capacitor structure and the second capacitor structure are arranged on the two faces of the substrate respectively, and the first capacitor structure and the second capacitor structure are at least partially embedded in the substrate. The conductive column assembly penetrates through the substrate, and two ends are electrically connected with the first capacitor structure and the second capacitor structure respectively, so that the first capacitor structure and the second capacitor structure are connected in parallel. The performance of the semiconductor device can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and in particular, relates to a semiconductor device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of semiconductor devices is increasingly reduced, and the types and quantities of semiconductor devices contained in a single chip are also increased, so that any slight difference in the process production can affect the performance of the semiconductor devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many semiconductor devices as possible on a substrate with limited area. Since the advent of Moore's Law, various structural designs and process optimizations of semiconductor devices have been proposed in the industry to meet people's current needs for products. SUMMARY

[0004] The present application aims at the shortcomings of the prior art and provides a semiconductor device, a manufacturing method thereof, and an electronic device, which can effectively improve the performance of the semiconductor device.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: a substrate, a first capacitor structure, a second capacitor structure, and a conductive pillar assembly.

[0006] The first capacitor structure and the second capacitor structure are respectively arranged on two sides of the substrate, and the first capacitor structure and the second capacitor structure are at least partially embedded in the substrate.

[0007] The conductive pillar assembly penetrates the substrate and is electrically connected to the first capacitor structure and the second capacitor structure at both ends, so that the first capacitor structure and the second capacitor structure are connected in parallel.

[0008] In some possible embodiments, the first capacitor structure and the second capacitor structure on the two sides of the substrate are symmetric about the geometric center of the substrate.

[0009] In some possible embodiments, the first capacitor structure and the second capacitor structure each comprise: a first electrode, a dielectric layer, and a second electrode stacked away from the substrate in sequence.

[0010] The conductive pillar assembly comprises a first conductive pillar and a second conductive pillar.

[0011] The two ends of the first conductive pillar are respectively electrically connected to the second electrode of the first capacitor structure and the first electrode of the second capacitor structure, and the two ends of the second conductive pillar are respectively electrically connected to the first electrode of the first capacitor structure and the second electrode of the second capacitor structure.

[0012] In some possible embodiments, one side of the substrate is provided with an array of grooves. The first capacitor structure is at least partially filled in the grooves to form a first deep trench capacitor.

[0013] In some possible embodiments, the other side of the substrate is provided with an array of grooves, and the second capacitor structure is at least partially filled in the grooves to form a second deep trench capacitor.

[0014] In some possible embodiments, the semiconductor device further includes: a first metal layer and a second metal layer arranged in the same layer, and a third metal layer and a fourth metal layer arranged in the same layer. The first metal layer and the fourth metal layer are arranged in a direction away from the substrate, and the second metal layer and the third metal layer are arranged in the direction away from the substrate.

[0015] The second electrode of the first capacitor structure, the second metal layer, the first conductive column, the third metal layer, and the first electrode of the second capacitor structure are sequentially electrically connected.

[0016] The first electrode of the first capacitor structure, the first metal layer, the second conductive column, the fourth metal layer, and the second electrode of the second capacitor structure are sequentially electrically connected.

[0017] In some possible embodiments, the semiconductor device further includes: a carrier substrate, a first contact layer, a first connecting wire, a first conductive structure, a second connecting wire, and a second conductive structure.

[0018] The carrier substrate is arranged on a side of the first capacitor structure away from the second capacitor structure; the first contact layer is arranged on a side of the first electrode and the second electrode away from the substrate; the first connecting wire is arranged on a side of the first contact layer away from the first electrode; the first conductive structure is arranged on a side of the first connecting wire away from the first contact layer; the second connecting wire is arranged on a side of the first contact layer away from the second electrode; and the second conductive structure is arranged on a side of the second connecting wire away from the first contact layer.

[0019] In a second aspect, an embodiment of the present application provides an electronic device, including: any semiconductor device provided in the first aspect.

[0020] In a third aspect, an embodiment of the present application further provides a manufacturing method of a semiconductor device, including: forming a first capacitor structure and a first segment of a conductive column assembly on one side of a substrate. The first capacitor structure is at least partially embedded in the substrate.

[0021] forming a second capacitor structure and a second segment of the conductive column assembly on the other side of the substrate. The second capacitor structure is at least partially embedded in the substrate. The first segment of the conductive column assembly and the second segment of the conductive column assembly are connected one by one to form a conductive column assembly penetrating through the substrate, so that the first capacitor structure and the second capacitor structure are connected in parallel.

[0022] In some possible embodiments, after forming the first capacitor structure and the first segment of the conductive column assembly on one side of the substrate, the method further includes: Bond the side of the substrate provided with the first capacitor structure and the first segment of the electrically conductive pillar assembly to the carrier substrate.

[0023] In some possible embodiments, forming the first capacitor structure and the first segment of the electrically conductive pillar assembly on one side of the substrate comprises: Forming the first capacitor structure and the first hole and the second hole on two sides of the first capacitor structure on one side of the substrate.

[0024] Forming the first segment of the second electrically conductive pillar in the first hole and the first segment of the first electrically conductive pillar in the second hole, the electrically conductive pillar assembly comprising the first electrically conductive pillar and the second electrically conductive pillar.

[0025] Forming the first metal layer and the second metal layer on one side of the substrate, the first metal layer electrically connecting the first segment of the second electrically conductive pillar and the first electrode of the first capacitor structure, and the second metal layer electrically connecting the first segment of the first electrically conductive pillar and the second electrode of the first capacitor structure.

[0026] In some possible embodiments, forming the first capacitor structure and the first hole and the second hole on two sides of the first capacitor structure on one side of the substrate comprises: Forming a trench region with an array of trenches on one side of the substrate.

[0027] Forming the first electrode, the dielectric layer and the second electrode in a stack on the side of the substrate with the trench region, to obtain the first capacitor structure, the first capacitor structure at least partially filling in the trenches.

[0028] Forming the first hole and the second hole on two sides of the trench region on one side of the substrate.

[0029] In some possible embodiments, forming the second capacitor structure and the second segment of the electrically conductive pillar assembly on the other side of the substrate comprises: Forming the second capacitor structure, the fourth hole corresponding to the first hole and the third hole corresponding to the second hole on the other side of the substrate.

[0030] Forming the second segment of the first electrically conductive pillar in the third hole and the second segment of the second electrically conductive pillar in the fourth hole, the first segment of the first electrically conductive pillar corresponding to the second segment of the first electrically conductive pillar one by one, and the first segment of the second electrically conductive pillar corresponding to the second segment of the second electrically conductive pillar one by one.

[0031] Forming the third metal layer and the fourth metal layer on the other side of the substrate, the third metal layer electrically connecting the second segment of the first electrically conductive pillar and the first electrode of the second capacitor structure, and the fourth metal layer electrically connecting the second segment of the second electrically conductive pillar and the second electrode of the second capacitor structure.

[0032] In some possible embodiments, after forming the first electrode, the dielectric layer and the second electrode in a stack on the side of the substrate with the trench region, comprises: A side wall structure is formed on the side surface of the first electrode, the dielectric layer and the second electrode, and the edge of the first electrode is exposed to the dielectric layer and the second electrode.

[0033] A first contact layer is formed to cover the first electrode and the second electrode exposed to the second electrode.

[0034] A first connecting wire and a first conductive structure are sequentially formed on the first contact layer side of the first electrode surface, and a second connecting wire and a second conductive structure are sequentially formed on the first contact layer side of the second electrode surface, so that the first electrode, the first connecting wire and the first conductive structure are electrically connected, and the second electrode, the second connecting wire and the second conductive structure are electrically connected.

[0035] The technical scheme provided by the embodiments of the present application has the beneficial technical effects including: The embodiments of the present application electrically connect the first capacitor structure and the second capacitor structure on both sides of the substrate through the conductive column assembly penetrating the substrate, so that the first capacitor structure and the second capacitor structure are connected in parallel. Compared with the capacitor manufactured on one side of the substrate, the parallel connection of the capacitors on both sides of the substrate can increase the overall capacitance value of the capacitor structure without increasing the substrate area, which is beneficial to improve the integration density of the semiconductor device. Moreover, the conductive column assembly connecting the capacitor structures on both sides of the substrate can be manufactured by the through-silicon via (TSV) technology, and the manufacturing process has strong stability and reliability, and the yield is high.

[0036] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0037] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the accompanying drawings, in which: Figure 1 A top view structural schematic diagram of a semiconductor device provided by the embodiments of the present application is provided; Figure 2 A cross-sectional schematic diagram at AA' in FIG. 1 is provided; Figure 1 Figure 3 A top view structural schematic diagram of a first electrode and a second electrode in a semiconductor device provided by the embodiments of the present application is provided; Figure 4 A structural schematic diagram of another semiconductor device provided by the embodiments of the present application is provided; Figure 5 A flowchart of a manufacturing method of a semiconductor device provided by the embodiments of the present application is provided; Figures 6A-25 ​A cross-sectional structure schematic diagram when different steps are completed in a preparation method of a semiconductor device provided in an embodiment of the present application.

[0038] Reference signs: 100 - substrate; 200 - first capacitor structure; 300 - second capacitor structure; 10 - trench; 101 - first electrode; 1011 - first initial electrode layer; 102 - dielectric layer; 1021 - initial dielectric layer; 103 - second electrode; 1031 - second initial electrode layer; 104 - side wall structure; 105 - first contact layer; 106 - first connection wire; 107 - second connection wire; 108 - first conductive structure; 109 - second conductive structure; 110 - first insulating layer; 111 - second insulating layer; 112 - third insulating layer; 113 - fourth insulating layer; 114 - first protective layer; 115 - first planar layer; 116 - first stop layer; 117 - second planar layer; 118 - first combined layer; 119 - first conductive layer; 120 - second protective layer; 121 - third planar layer; 122 - first hole; 123 - second hole; 124 - pad oxide layer; 125 - second combined layer; 126 - second conductive layer; 127 - fifth insulating layer; 128 - adhesive material layer; 400 - conductive pillar assembly; 410 - first conductive pillar; 411 - first segment of first conductive pillar; 420 - second conductive pillar; 421 - first segment of second conductive pillar; 500 - first metal layer; 600 - second metal layer; 700 - third metal layer; 800 - fourth metal layer; 900 - bearing substrate. Specific embodiments Embodiments of the present application will be described below in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions of the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0040] It should be understood by those skilled in the art that "said" and "the" used herein can also include plural forms unless specifically stated. It should be further understood that the wording "comprising" used in the specification of the present application means that the features, integers, steps, operations, elements and / or components exist, but does not exclude other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technology. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or it can mean that the element and the other element are connected through an intermediate element. In addition, "connected" or "coupled" used herein can include wireless connection or wireless coupling. The term "and / or" used herein means at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0041] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0042] The research and development idea of the present application includes that in a semiconductor device, a capacitor structure is a commonly used device, which is usually used for circuit filtering, coupling or energy storage, etc. In some application scenarios, a capacitor structure with a larger capacitance value is needed. In the related art, the capacitor structure is only manufactured on one side of the substrate. If a capacitor structure with a larger capacitance value is needed, the planar area of the substrate needs to be increased, which is not conducive to the miniaturization development of semiconductor devices.

[0043] The semiconductor device and its manufacturing method, and the electronic equipment provided by the present application aim to solve the above technical problems of the related art.

[0044] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. It should be pointed out that the embodiments described below can be mutually referenced, borrowed or combined. For the same terms, similar features and similar implementation steps in different embodiments, they will not be described repeatedly.

[0045] Please refer to Figures 1-2 The semiconductor device provided by the embodiments of the present application comprises: a substrate 100, a first capacitor structure 200, a second capacitor structure 300 and a conductive column assembly 400.

[0046] The first capacitor structure 200 and the second capacitor structure 300 are respectively arranged on two sides of the substrate 100, and the first capacitor structure 200 and the second capacitor structure 300 are at least partially embedded in the substrate 100.

[0047] The conductive pillar assembly 400 penetrates the substrate 100 and is electrically connected with the first capacitor structure 200 and the second capacitor structure 300 at two ends respectively, so that the first capacitor structure 200 and the second capacitor structure 300 are connected in parallel.

[0048] In the embodiment, the first capacitor structure 200 and the second capacitor structure 300 on two sides of the substrate 100 are electrically connected by the conductive pillar assembly 400 penetrating the substrate 100, so that the first capacitor structure 200 and the second capacitor structure 300 are connected in parallel. Compared with a capacitor manufactured on one side of the substrate 100, the parallel connection of the capacitors on two sides of the substrate 100 can increase the capacitance of the overall capacitor structure without increasing the planar area occupied by the substrate 100, which is conducive to improving the integration density of the semiconductor device. Moreover, the conductive pillar assembly 400 connecting the capacitor structures on two sides in the embodiment can be manufactured by a through-silicon via (TSV) technology, and the manufacturing process has strong stability and reliability, and the yield is high.

[0049] In some possible embodiments, as shown in Figure 2 The first capacitor structure 200 and the second capacitor structure 300 on two sides of the substrate 100 are symmetrical about the geometric center of the substrate 100.

[0050] In the embodiment, the first capacitor structure 200 and the second capacitor structure 300 on two sides of the substrate 100 are symmetrical about the geometric center of the substrate 100, and the basic structures are completely identical. In other words, the second capacitor structure 300 can coincide with the first capacitor structure 200 after being flipped by 180 degrees about the geometric center of the substrate 100. Therefore, the first capacitor structure 200 and the second capacitor structure 300 can be manufactured by the same process, the same set of photolithography processes can be used, and the manufacturing cost of the semiconductor device can be reduced.

[0051] In some possible embodiments, as shown in Figures 2-3 The first capacitor structure 200 and the second capacitor structure 300 each include a first electrode 101, a dielectric layer 102 and a second electrode 103 stacked away from the substrate 100 in sequence.

[0052] The conductive pillar assembly 400 includes a first conductive pillar 410 and a second conductive pillar 420.

[0053] The first conductive pillar 410 is electrically connected with the second electrode 103 of the first capacitor structure 200 and the first electrode 101 of the second capacitor structure 300 at two ends respectively, and the second conductive pillar 420 is electrically connected with the first electrode 101 of the first capacitor structure 200 and the second electrode 103 of the second capacitor structure 300 at two ends respectively.

[0054] In the embodiment, the first conductive pillar 410 penetrates the substrate 100 and electrically connects the second electrode 103 of the first capacitor structure 200 and the first electrode 101 of the second capacitor structure 300, and the second conductive pillar 420 penetrates the substrate 100 and electrically connects the first electrode 101 of the first capacitor structure 200 and the second electrode 103 of the second capacitor structure 300, so that the first capacitor structure 200 and the second capacitor structure 300 are connected in parallel. It can be understood that the combined capacitance of the two capacitors connected in parallel is the sum of the capacitances of the two capacitors. Therefore, the overall capacitance of the first capacitor structure 200 and the second capacitor structure 300 connected in parallel in the embodiment is the sum of the capacitances of the first capacitor structure 200 and the second capacitor structure 300. When the first capacitor structure 200 and the second capacitor structure 300 are centrally symmetrical, assuming that the materials and thicknesses of the first electrode 101, the dielectric layer 102, and the second electrode 103 of the first capacitor structure 200 and the second capacitor structure 300 are the same, the capacitances of the first capacitor structure 200 and the second capacitor structure 300 are also almost the same, and the overall capacitance after being connected in parallel is twice the capacitance of a single first capacitor structure 200 or a single second capacitor structure 300.

[0055] Therefore, the embodiment can multiply the overall capacitance of the capacitor structure on the substrate 100 while ensuring that the planar area of the substrate 100 is not increased, which is beneficial to the miniaturization development of semiconductor devices.

[0056] In some possible embodiments, as shown in FIG. 1, one side of the substrate 100 is provided with an array of trenches 10. The first capacitor structure 200 is at least partially filled in the trench 10 to form a first deep trench capacitor. Figure 3

[0057] In some possible embodiments, the other side of the substrate 100 is provided with an array of trenches 10, and the second capacitor structure 300 is at least partially filled in the trench 10 to form a second deep trench capacitor.

[0058] It can be understood that the capacitance can be increased by increasing the facing area between the first electrode 101 and the second electrode 103. In the embodiments provided in the present application, the trench 10 is formed on the substrate 100, and at least one of the first electrode 101 and the second electrode 103 covers the surface of the trench 10 to form a deep trench capacitor. Compared with a flat plate capacitor, the deep trench capacitor can increase the facing area between the first electrode 101 and the second electrode 103 while ensuring that the planar area of the substrate 100 is unchanged, thereby increasing the capacitance of the first capacitor structure 200 or the second capacitor structure 300, and can be applied to application scenarios that require a larger capacitance.

[0059] In some possible embodiments, as shown in FIG. 1, one side of the substrate 100 is provided with an array of trenches 10. The first capacitor structure 200 is at least partially filled in the trench 10 to form a first deep trench capacitor. Figure 2 ​As shown, the semiconductor device further comprises: a first metal layer 500 and a second metal layer 600 arranged in the same layer, a third metal layer 700 and a fourth metal layer 800 arranged in the same layer. The first metal layer 500 and the fourth metal layer 800 are arranged in a direction away from the substrate 100, and the second metal layer 600 and the third metal layer 700 are arranged in a direction away from the substrate 100.

[0060] The second electrode 103 of the first capacitor structure 200, the second metal layer 600, the first conductive column 410, the third metal layer 700, and the first electrode 101 of the second capacitor structure 300 are sequentially electrically connected.

[0061] The first electrode 101 of the first capacitor structure 200, the first metal layer 500, the second conductive column 420, the fourth metal layer 800, and the second electrode 103 of the second capacitor structure 300 are sequentially electrically connected.

[0062] In the embodiment, the first metal layer 500, the second metal layer 600, the third metal layer 700, and the fourth metal layer 800 are tiled on both sides of the substrate 100 and arranged in parallel with the plane in which the substrate 100 is located. The arrangement direction of the first conductive column 410, the first capacitor structure 200 (or the second capacitor structure 300), and the second conductive column 420 is parallel to the plane in which the substrate 100 is located. The first conductive column 410, the first capacitor structure 200, the second conductive column 420, and the second capacitor structure 300 can be electrically connected through the tiled metal layers, so that the first capacitor structure 200 and the second capacitor structure 300 are connected in parallel.

[0063] In some possible embodiments, as shown in FIG. 1B, Figure 2 As shown, the semiconductor device further comprises: a carrier substrate 900, a first contact layer 105, a first connecting wire 106, a first conductive structure 108, a second connecting wire 107, and a second conductive structure 109.

[0064] The carrier substrate 900 is arranged on the side of the first capacitor structure 200 away from the second capacitor structure 300; the first contact layer 105 is arranged on the side of the first electrode 101 and the second electrode 103 away from the substrate 100; the first connecting wire 106 is arranged on the side of the first contact layer 105 away from the first electrode 101; the first conductive structure 108 is arranged on the side of the first connecting wire 106 away from the first contact layer 105; the second connecting wire 107 is arranged on the side of the first contact layer 105 away from the second electrode 103; and the second conductive structure 109 is arranged on the side of the second connecting wire 107 away from the first contact layer 105.

[0065] In the embodiment, the bearing substrate 900 bears the substrate 100, giving a certain supporting effect. The first conductive structure 108, the first connecting wire 106, the first contact layer 105 and the first electrode 101 are sequentially connected, leading out the first electrode 101, and then electrically connected with the first metal layer 500; the second conductive structure 109, the second connecting wire 107, the first contact layer 105 and the second electrode 103 are sequentially connected, leading out the second electrode 103, and then electrically connected with the second metal layer 600.

[0066] Optionally, the semiconductor device provided in the embodiment of the present application Figure 1 The semiconductor device shown above can be a capacitor unit, and the present application further provides a semiconductor device which can include a plurality of array-arranged capacitor units as described above, which can be referred to Figure 4 The structure diagram shown above. Among them, the second conductive column 420 of the capacitor unit on the left side is shared with the first conductive column 410 of the capacitor unit on the right side, which can reduce the area of the capacitor unit and improve the structural compactness of the semiconductor device.

[0067] Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which includes any semiconductor device provided in the above-mentioned embodiments.

[0068] In the embodiment of the present application, since the electronic device adopts any semiconductor device provided in the above-mentioned embodiments, the principle and technical effects thereof are referred to the above-mentioned embodiments, which will not be described here.

[0069] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.

[0070] It should be noted that the electronic device is not limited to the above-mentioned several kinds, and those skilled in the art can set any semiconductor device provided in the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided in the embodiment of the present application.

[0071] Those skilled in the art can understand that the electronic device provided in the embodiment of the present application can be specially designed and manufactured for the required purpose, or can also include known devices in a general-purpose computer. These devices have any semiconductor device provided in the above-mentioned embodiments.

[0072] Based on the same inventive concept, the embodiment of the present application further provides a manufacturing method of a semiconductor device, and a flowchart of the method is shown in Figure 5 The method includes steps S101-S102: S101: Forming a first capacitor structure 200 and a first segment of a conductive column assembly 400 on one side of a substrate 100. The first capacitor structure 200 is at least partially embedded in the substrate 100. The specific steps correspond to the structure diagram shown in FIG. 6-Figure 24 As shown.

[0073] S102: Forming a second capacitor structure 300 and a second segment of the conductive pillar assembly 400 on the other side of the substrate 100. The second capacitor structure 300 is at least partially embedded in the substrate 100. The first segment of the conductive pillar assembly 400 and the second segment of the conductive pillar assembly 400 are connected one by one to form the conductive pillar assembly 400 penetrating through the substrate 100, so that the first capacitor structure 200 and the second capacitor structure 300 are connected in parallel.

[0074] In the embodiment, the first capacitor structure 200 and the first segment of the conductive pillar assembly 400 are manufactured on one side of the substrate 100, and the first capacitor structure 200 is electrically connected with the first segment of the conductive pillar assembly 400; then the second capacitor structure 300 and the second segment of the conductive pillar assembly 400 are manufactured on the other side of the substrate 100, and the second segment of the conductive pillar assembly 400 is electrically connected with the second capacitor structure 300. The second segment of the conductive pillar assembly 400 and the first segment of the conductive pillar assembly 400 are connected one by one to form the conductive pillar assembly 400 penetrating through the substrate 100, and the first capacitor structure 200 and the second capacitor structure 300 are connected in parallel. Compared with the capacitor manufactured on one side of the substrate 100, the parallel connection of the capacitors on both sides of the substrate 100 can increase the total capacitance of the capacitor structures on the substrate 100 without increasing the planar area of the substrate 100, which is beneficial to the miniaturization of semiconductor devices. Moreover, the conductive pillar assembly 400 connecting the capacitor structures on both sides of the substrate 100 can be manufactured by the through-silicon via (TSV) technology, which has strong feasibility.

[0075] In some possible embodiments, the step S101 of forming the first capacitor structure 200 and the first segment of the conductive pillar assembly 400 on one side of the substrate 100 includes the following steps: As shown. Figures 6A-19 The first capacitor structure 200 and the first hole 122 and the second hole 123 located on both sides of the first capacitor structure 200 are formed on one side of the substrate 100.

[0076] As shown. Figures 20-23 The first segment 421 of the second conductive pillar 420 is formed in the first hole 122, and the first segment 411 of the first conductive pillar 410 is formed in the second hole 123. The conductive pillar assembly 400 includes the first conductive pillar 410 and the second conductive pillar 420.

[0077] As shown. Figure 24As shown, a first metal layer 500 and a second metal layer 600 are formed on one side of the substrate 100. The first metal layer 500 is electrically connected to the first segment 421 of the second conductive pillar 420 and the first electrode 101 of the first capacitor structure 200. The second metal layer 600 is electrically connected to the first segment 411 of the first conductive pillar 410 and the second electrode 103 of the first capacitor structure 200.

[0078] In this embodiment, after the first capacitor structure 200 is manufactured, a first hole 122 and a second hole 123 are manufactured on both sides of the first capacitor structure 200. The first hole 122 and the second hole 123 can be manufactured using TSV technology. Since the substrate 100 has a certain thickness, and the second capacitor structure 300 will be manufactured by inversion later, the first hole 122 and the second hole 123 can be manufactured as blind holes, that is, they do not penetrate the entire substrate 100. This ensures that the first segment 421 of the second conductive pillar 420 formed in the first hole 122 and the first segment 411 of the first conductive pillar 410 formed in the second hole 123 are not exposed on the other side of the substrate 100, which can reduce the risk of contamination.

[0079] In this embodiment, after the first segment 411 of the first conductive pillar 410 and the first segment 421 of the second conductive pillar 420 are manufactured, the first segment 411 of the first conductive pillar 410, the first capacitor structure 200 and the first segment 421 of the second conductive pillar 420 are arranged in a direction parallel to the substrate 100. Therefore, by continuing to manufacture the first metal layer 500 and the second metal layer 600, the first capacitor structure 200 can be electrically connected to the first segment 411 of the first conductive pillar 410 and the first segment 421 of the second conductive pillar 420.

[0080] In some possible embodiments, the steps described above, such as forming a first capacitor structure 200 and a first hole 122 and a second hole 123 on both sides of the first capacitor structure 200, may specifically include the following steps: A trench region with an array of trenches 10 is formed on one side of the substrate 100.

[0081] like Figure 9 As shown, a first electrode 101, a dielectric layer 102, and a second electrode 103 are formed on one side of the substrate 100 having a trench region to obtain a first capacitor structure 200, which at least partially fills the trench.

[0082] like Figure 19 As shown, a first hole 122 and a second hole 123 are formed on one side of the substrate 100, located on both sides of the trench region.

[0083] In the embodiment, the substrate 100 is first patterned to form a trench region with a plurality of trenches 10, and then the first electrode 101, the dielectric layer 102 and the second electrode 103 are sequentially formed on the trench region and the surface of the substrate 100, so that the first electrode 101, the dielectric layer 102 and the second electrode 103 all fall into at least one trench 10 to form a deep trench capacitor. Therefore, the area of the first electrode 101 facing the second electrode 103 corresponds to the sidewall area of the second electrode 103 in the trench 10, and compared with a flat plate capacitor formed by the first electrode 101 and the second electrode 103 both being paved on the substrate 100, the facing area of the two electrodes in the deep trench capacitor is larger, and the capacitance value is also larger.

[0084] Optionally, as shown in Figures 7-9 the above step of forming the stacked first electrode 101, dielectric layer 102 and second electrode 103 on the side of the substrate 100 with the trench region can first sequentially form the stacked first initial electrode layer 1011, initial dielectric layer 1021 and second initial electrode layer 1031, and then sequentially pattern the first initial electrode layer 1011, initial dielectric layer 1021 and second initial electrode layer 1031 to form the first electrode 101, dielectric layer 102 and second electrode 103, so that the edge of the first electrode 101 is exposed from the dielectric layer 102 and the second electrode 103.

[0085] Optionally, as shown in Figures 6A-6H the above step of forming the stacked first initial electrode layer 1011, initial dielectric layer 1021 and second initial electrode layer 1031, actually further includes forming a first insulating layer 110 between the substrate 100 and the first initial electrode layer 1011, forming a second insulating layer 111 between the first initial electrode layer 1011 and the initial dielectric layer 1021, forming a third insulating layer 112 between the initial dielectric layer 1021 and the second initial electrode layer 1031, and covering the fourth insulating layer 113 on the surface of the second initial electrode layer 1031 away from the initial dielectric layer 1021. Based on the technical features disclosed in the present application, those skilled in the art can understand the structure, material or characteristics of the insulating layer, which will not be described here.

[0086] Optionally, the first insulating layer 110, the second insulating layer 111, the third insulating layer 112, the fourth insulating layer 113 and the fifth insulating layer 127 mentioned later can all be made of oxide material, which can be made of the same material or different materials according to actual conditions.

[0087] Optionally, the first initial electrode layer 1011, the initial dielectric layer 1021 and the second initial electrode layer 1031 are partially filled in the trench 10, and the space shape of the trench is cylindrical, thus the first initial electrode layer 1011, the initial dielectric layer 1021 and the second initial electrode layer 1031 are sequentially filled in the trench 10 in a cylindrical shape, the second initial electrode layer 1031 at the innermost side in the trench 10 is away from the surface of the dielectric layer 102 to form a cavity, the cavity is filled with the fourth insulating layer 113, so that the second initial electrode layer 1031 has a larger unfolded area, and the unfolded area of the second electrode 103 formed finally is also larger, the area opposite to the first electrode 101 is larger, and thus the formed capacitor structure has a larger capacitance.

[0088] It can be understood that after the first capacitor structure 200 is manufactured, some film layer structures can be continuously manufactured above the first capacitor structure 200 to play a protection or insulation role. Therefore, some connection lines need to be manufactured to lead out the first electrode 101 or the second electrode 103 of the first capacitor structure 200.

[0089] In some possible embodiments, after the step of forming the laminated first electrode 101, dielectric layer 102 and second electrode 103 on the side of the substrate 100 having the trench area, the following steps are included: As shown in FIG. 1, a side wall structure 104 is formed on the side circumferential surface of the first electrode 101, the dielectric layer 102 and the second electrode 103, and the edge of the first electrode 101 is exposed to the dielectric layer 102 and the second electrode 103. Figure 10

[0090] As shown in FIG. 1, a first contact layer 105 is formed to cover the first electrode 101 and the second electrode 103 exposed to the second electrode 103, respectively. Figure 11

[0091] As shown in FIG. 1, a first connection wire 106 and a first conductive structure 108 are sequentially formed on the side of the first contact layer 105 on the surface of the first electrode 101, and a second connection wire 107 and a second conductive structure 109 are sequentially formed on the side of the first contact layer 105 on the surface of the second electrode 103, so that the first electrode 101, the first connection wire 106 and the first conductive structure 108 are electrically connected, and the second electrode 103, the second connection wire 107 and the second conductive structure 109 are electrically connected. Figures 13-17

[0092] ​​​In the present embodiment, after the first electrode 101, the dielectric layer 102 and the second electrode 103 are formed, the sidewall structure 104 is formed on the side surface of the first electrode 101, and the sidewall structure 104 is also formed on the side surface of the dielectric layer 102 and the second electrode 103. Since the first electrode 101 is exposed from the dielectric layer 102 and the second electrode 103, the sidewall structure 104 on the side surface of the first electrode 101 is disconnected from the sidewall structure 104 on the side surface of the dielectric layer 102 and the second electrode 103. Then, the first contact layer 105 is formed on the surface of the portion of the first electrode 101 exposed from the second electrode 103 and on the surface of the second electrode 103, and the first connecting wire 106 and the first conductive structure 108 are sequentially formed on the first contact layer 105; the second connecting wire 107 and the second conductive structure 109 are sequentially formed on the first contact layer 105.

[0093] Then, the first metal layer 500 is formed on the substrate 100, and the first metal layer 500 is electrically connected to the first segment 421 of the second conductive column 420 and the first conductive structure 108, so that the first metal layer 500 is electrically connected to the first segment 421 of the second conductive column 420 and the first electrode 101 of the first capacitor structure 200; the second metal layer 600 is formed on the substrate 100, and the second metal layer 600 is electrically connected to the first segment 411 of the first conductive column 410 and the second conductive structure 109, so that the second metal layer 600 is electrically connected to the first segment 411 of the first conductive column 410 and the second electrode 103 of the first capacitor structure 200.

[0094] It should be noted that before the first connecting wire 106, the second connecting wire 107, the first conductive structure 108 and the second conductive structure 109 are formed in the above steps, actually, the process of forming some insulating layers or interlayer dielectric layers and other film layers is also included.

[0095] Specifically, after the first contact layer 105 covering the first electrode 101 exposed from the second electrode 103 and the second electrode 103 is formed in the above steps, the following steps are further included: as shown in Figure 13 The first protective layer 114 and the first planar layer 115 are patterned to form a through hole to expose the first contact layer 105. Then, the first connecting wire 106 connected to the first contact layer 105 on the first electrode 101 and the second connecting wire 107 connected to the first contact layer 105 on the second electrode 103 are formed in the through hole.

[0096] In the above steps, the first connecting wire 106 and the first conductive structure 108 are sequentially formed on the first contact layer 105 side of the surface of the first electrode 101, and the second connecting wire 107 and the second conductive structure 109 are sequentially formed on the first contact layer 105 side of the surface of the second electrode 103, which further includes: as shown in Figure 13As shown, the first stop layer 116 and the second planar layer 117 are sequentially formed on the first planar layer 115, the first connecting wire 106 and the second connecting wire 107 away from the substrate 100; as Figure 14 As shown, the first stop layer 116 and the second planar layer 117 are patterned to obtain a through hole exposing the first connecting wire 106 and a through hole exposing the second connecting wire 107; then, as Figures 15-17 As shown, the first anti-reflection layer and the first seed layer are formed in the through hole and on the second planar layer 117, and then the first conductive layer 119 is formed by electrolytic plating. The first conductive layer 119 is polished to leave only the first conductive layer 119 in the through hole, forming the first conductive structure 108 connected to the first connecting wire 106 and the second conductive structure 109 connected to the second connecting wire 107. For the convenience of description, the first anti-reflection layer and the first seed layer are schematically shown as the first combined layer 118 in the schematic diagram.

[0097] After the first conductive structure 108 and the second conductive structure 109 are formed, the method further includes: as Figure 18 As shown, the second protective layer 120 and the third planar layer 121 covering the first conductive structure 108 and the second conductive structure 109 are formed.

[0098] Optionally, the first planar layer 115, the second planar layer 117 and the third planar layer 121 provided by the embodiments of the present application can be made of oxide materials.

[0099] Optionally, the first protective layer 114 and the second protective layer 120 provided by the embodiments of the present application can be made of silicon nitride and the like.

[0100] Optionally, in the above step, the first hole 122 and the second hole 123 are formed on one side of the substrate 100 and located on both sides of the trench area, and then the method further includes: as Figure 20 As shown, the pad oxide layer 124 is formed in the first hole 122 and the second hole 123 to protect the substrate 100 from being eroded in the subsequent process.

[0101] Optionally, after the pad oxide layer 124 is formed, as Figure 21 As shown, the second anti-reflection layer and the second seed layer are continuously formed, as Figure 22 As shown, the second conductive layer 126 is formed by electrolytic plating, and the second conductive layer 126 is polished, as Figure 23 As shown, only the second conductive layer 126 in the first hole 122 and the second hole 123 is left to form the first segment 421 of the second conductive column 420 and the first segment 411 of the first conductive column 410, respectively. For the convenience of description, the second anti-reflection layer and the second seed layer are schematically shown as the second combined layer 125 in the schematic diagram.

[0102] Optionally, in the aforementioned step of forming the first metal layer 500 and the second metal layer 600 on one side of the substrate 100, the following steps are also included: as shown in Figure 24 forming a fifth insulating layer 127 on the side of the first segment 421 of the second conductive pillar 420 and the first segment 411 of the first conductive pillar 410, patterning the fifth insulating layer 127 to form a via exposing the first segment 411 of the first conductive pillar 410 and the second segment of the second conductive pillar 420, and then forming the first metal layer 500 and the second metal layer 600 in the via, with the first metal layer 500 and the second metal layer 600 separated by the remaining fifth insulating layer 127.

[0103] It is considered that the rigidity of the substrate 100 may change after the first capacitor structure 200, the conductive pillar assembly 400 and other structures are manufactured. Therefore, in some possible embodiments, after the first capacitor structure 200 and the first segment of the conductive pillar assembly 400 are formed on one side of the substrate 100 in the aforementioned step S101, the following steps are also included: bonding the side of the substrate 100 provided with the first capacitor structure 200 and the first segment of the conductive pillar assembly 400 to the carrier substrate 900.

[0104] In the present embodiment, as shown in Figure 25 the side of the substrate 100 provided with the first capacitor structure 200 and the first segment of the conductive pillar assembly 400 can be bonded and fixed to the carrier substrate 900 first, and then the substrate 100 and the carrier substrate 900 are inverted as a whole so that the other side of the substrate 100 faces upward, facilitating the manufacture of the second capacitor structure 300 and the second segment of the conductive pillar assembly 400 on the other side of the substrate 100. Moreover, the carrier substrate 900 can provide certain support to the substrate 100, reducing the risk of breakage of the substrate 100 and thus increasing the product yield.

[0105] Optionally, an adhesive material layer 128 can be arranged between the substrate 100 and the carrier substrate 900, so that the substrate 100 and the carrier substrate 900 are bonded and fixed.

[0106] In some possible embodiments, the second capacitor structure 300 and the second segment of the conductive pillar assembly 400 are formed on the other side of the substrate 100, including: forming the second capacitor structure 300, a fourth hole corresponding to the first hole 122 and a third hole corresponding to the second hole 123 on the other side of the substrate 100.

[0107] forming the second segment of the first conductive pillar 410 in the third hole and the second segment of the second conductive pillar 420 in the fourth hole, with the first segment 411 of the first conductive pillar 410 and the second segment of the first conductive pillar 410 corresponding one by one, and the first segment 421 of the second conductive pillar 420 and the second segment of the second conductive pillar 420 corresponding one by one.

[0108] A third metal layer 700 and a fourth metal layer 800 are formed on the other side of the substrate 100, the third metal layer 700 electrically connecting the second segment of the first conductive pillar 410 and the first electrode 101 of the second capacitor structure 300, and the fourth metal layer 800 electrically connecting the second segment of the second conductive pillar 420 and the second electrode 103 of the second capacitor structure 300.

[0109] In the embodiment, the second capacitor structure 300 can be manufactured on the other side of the substrate 100 first, then the fourth hole corresponding to the first hole 122 and the third hole corresponding to the second hole 123 are formed, then the second segment of the first conductive pillar 410 is formed in the third hole and the second segment of the second conductive pillar 420 is formed in the fourth hole, the first segment 411 of the first conductive pillar 410 is connected with the second segment of the first conductive pillar 410 to form the complete first conductive pillar 410, and the first segment 421 of the second conductive pillar 420 is connected with the second segment of the second conductive pillar 420 to form the complete second conductive pillar 420. Then, the third metal layer 700 and the fourth metal layer 800 are formed on the other side of the substrate 100 on the side of the second capacitor structure 300, the first conductive pillar 410 and the second conductive pillar 420, so that the third metal layer 700 electrically connects the second segment of the first conductive pillar 410 and the first electrode 101 of the second capacitor structure 300, and the fourth metal layer 800 electrically connects the second segment of the second conductive pillar 420 and the second electrode 103 of the second capacitor structure 300, that is, the first capacitor structure 200 and the second capacitor structure 300 are connected in parallel.

[0110] Optionally, the first conductive pillar 410, the second conductive pillar 420, the first metal layer 500, the second metal layer 600, the third metal layer 700, the fourth metal layer 800, the first conductive structure 108 and the second conductive structure 109 provided by the embodiment of the application can all include copper material. The first connection wire 106 and the second connection wire 108 can all include tungsten material. The first contact layer includes silicide, which can reduce the contact resistance between the tungsten material and the first electrode 101 or the second electrode 103.

[0111] Optionally, the first capacitor structure 200 and the second capacitor structure 300 provided by the embodiment of the application are central symmetrical, so they can be manufactured by using the same set of manufacturing methods, which can reduce the cost of patterning. Therefore, similar to the manufacturing process of the first capacitor structure 200, the steps of forming the second capacitor structure 300 on the other side of the substrate 100, the fourth hole corresponding to the first hole 122 and the third hole corresponding to the second hole 123 in the above description can specifically include the following steps: A groove region with an array of grooves is formed on the other side of the substrate 100.

[0112] A second capacitor structure 300 is formed on the other side of the substrate 100 by forming the first electrode 101, the dielectric layer 102 and the second electrode 103 in layers, and the second capacitor structure 300 also at least partially fills the trench.

[0113] The third hole and the fourth hole are formed on the other side of the substrate 100 on both sides of the trench region. Since the substrate 100 needs to be inverted before the second capacitor structure 300 is formed on the other side, the arrangement direction of the first hole 122, the first capacitor structure 200 and the second hole 123 when the substrate 100 is upright is opposite to the arrangement direction of the first hole 122, the first capacitor structure 200 and the second hole 123 when the substrate 100 is inverted. Therefore, the third hole formed on the other side of the substrate 100 is in communication with the second hole 123, and the fourth hole is in communication with the first hole 122.

[0114] Optionally, forming the first electrode 101, the dielectric layer 102 and the second electrode 103 in layers on the other side of the substrate 100 can also include: first forming the first initial electrode layer 1011, the initial dielectric layer 1021 and the second initial electrode layer 1031 in layers, and then patterning the first initial electrode layer 1011, the initial dielectric layer 1021 and the second initial electrode layer 1031 in sequence to form the first electrode 101, the dielectric layer 102 and the second electrode 103, so that the edge of the first electrode 101 is exposed to the dielectric layer 102 and the second electrode 103.

[0115] Optionally, after the step of forming the first electrode 101, the dielectric layer 102 and the second electrode 103 in layers on the other side of the substrate 100, the following steps are included: A side wall structure 104 is formed on the side surface of the first electrode 101, the dielectric layer 102 and the second electrode 103, and the edge of the first electrode 101 is exposed to the dielectric layer 102 and the second electrode 103.

[0116] A first contact layer 105 is formed to cover the first electrode 101 and the second electrode 103 exposed to the second electrode 103, respectively.

[0117] A first connecting wire 106 and a first conductive structure 108 are formed in sequence on the side of the first contact layer 105 on the surface of the first electrode 101, and a second connecting wire 107 and a second conductive structure 109 are formed in sequence on the side of the first contact layer 105 on the surface of the second electrode 103, so that the first electrode 101, the first connecting wire 106 and the first conductive structure 108 are electrically connected, and the second electrode 103, the second connecting wire 107 and the second conductive structure 109 are electrically connected.

[0118] It can be understood that, for the convenience of expression and reduction of structure, the first electrode 101, the dielectric layer 102, the second electrode 103, the first contact layer 105, the first connecting wire 106, the second connecting wire 107, the first conductive structure 108 and the second conductive structure 109 on both sides of the substrate 100 are not distinguished in the present application. Based on the present application, it can be understood by those skilled in the art that the first electrode 101, the dielectric layer 102 and the second electrode 103 on one side of the substrate 100 form a first capacitor structure 200, the first conductive structure 108 and the first connecting wire 106 on one side of the substrate 100 are used to lead out the first electrode 101 of the first capacitor structure 200, the second conductive structure 109 and the second connecting wire 107 on one side of the substrate 100 are used to lead out the second electrode 103 of the first capacitor structure 200, the first electrode 101, the dielectric layer 102 and the second electrode 103 on the other side of the substrate 100 form a second capacitor structure 300, the first conductive structure 108 and the first connecting wire 106 on the other side of the substrate 100 are used to lead out the first electrode 101 of the second capacitor structure 300, and the second conductive structure 109 and the second connecting wire 107 on one side of the substrate 100 are used to lead out the second electrode 103 of the second capacitor structure 300.

[0119] It should be noted that in the embodiments of the present application, each film layer structure of the semiconductor structure can be patterned by a patterning process to manufacture each corresponding film layer.

[0120] It should be noted that the "patterning process" mentioned in the embodiments of the present application includes deposition of film layers, coating photoresist, mask exposure, development, patterning, stripping photoresist and the like, which are mature preparation processes in related technologies. The "photolithography process" mentioned in the embodiments of the present application includes coating film layers, mask exposure and development and the like, which are mature preparation processes in related technologies. Among them, deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and patterning can adopt known methods, which are not limited here.

[0121] In the description of the embodiments of the present application, it should be understood that "layer" refers to a thin film of a certain material manufactured on the substrate 100 by deposition or coating process. If the thin film does not need patterning process or photolithography process during the entire manufacturing process, the thin film can also be called layer. If the thin film still needs patterning process or photolithography process during the entire manufacturing process, it can be called a thin film before patterning process and a layer after patterning process. The "layer" after patterning process or photolithography process contains at least one "pattern".

[0122] By applying the embodiments of the present application, at least the following beneficial effects can be achieved: 1. The first capacitor structure 200 and the second capacitor structure 300 on both sides of the substrate 100 are electrically connected by a conductive pillar assembly 400 penetrating the substrate 100, so that the first capacitor structure 200 and the second capacitor structure 300 are connected in parallel. Compared with capacitors manufactured on one side of the substrate 100, the parallel connection of capacitors on both sides of the substrate 100 can increase the overall capacitance of the capacitor structure without increasing the planar area occupied by the substrate 100, which is beneficial to improving the integration density of semiconductor devices. Moreover, in this embodiment, the conductive pillar assembly 400 connecting the double-sided capacitor structures can be manufactured by through-silicon via (TSV) technology, which has strong stability and reliability and a high yield.

[0123] 2. The first capacitor structure 200 and the second capacitor structure 300 on both sides of the substrate 100 are symmetrical about the geometric center of the substrate 100, and their basic structures are completely identical. In other words, the second capacitor structure 300 can coincide with the first capacitor structure 200 after being rotated 180 degrees around the geometric center of the substrate 100. Therefore, the first capacitor structure 200 and the second capacitor structure 300 can be manufactured using the same process, and the same photolithography process can be used, which can reduce the manufacturing cost of semiconductor devices.

[0124] 3. By forming a trench 10 on the substrate 100, at least one of the first electrode 101 and the second electrode 103 is covered on the surface of the trench 10 to form a deep trench capacitor. Compared with a planar capacitor, a deep trench capacitor can increase the facing area between the first electrode 101 and the second electrode 103 while keeping the planar area of ​​the substrate 100 unchanged, thereby increasing the capacitance value of the first capacitor structure 200 or the second capacitor structure 300. It can be applied to application scenarios that require a larger capacitance value capacitor structure.

[0125] 4. The substrate 900 supports the substrate 100, providing a certain degree of support.

[0126] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0127] In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are based on the exemplary directions or positional relationships shown in the drawings, and are for the purpose of facilitating the description or simplifying the description of the embodiments of the present application, and do not indicate or imply that the devices or components indicated thereby must have a particular orientation, or be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0128] The terms "first", "second", "third", etc. are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated thereby. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0129] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integral connection; can be directly connected, or indirectly connected through an intermediate medium; can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0130] In the description of the present application, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0131] The above only describes some embodiments of the present application, and it should be pointed out that, for those skilled in the art, without departing from the technical concept of the present application, other similar implementation means based on the technical idea of the present application also belong to the protection scope of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A first capacitor structure and a second capacitor structure are respectively disposed on both sides of the substrate, and both the first capacitor structure and the second capacitor structure are at least partially embedded in the substrate; A conductive pillar assembly penetrates the substrate, with its two ends electrically connected to the first capacitor structure and the second capacitor structure, respectively, so that the first capacitor structure and the second capacitor structure are connected in parallel.

2. The semiconductor device according to claim 1, characterized in that, The first capacitor structure and the second capacitor structure on both sides of the substrate are symmetrical about the geometric center of the substrate.

3. The semiconductor device according to claim 1, characterized in that, Both the first capacitor structure and the second capacitor structure include: a first electrode, a dielectric layer, and a second electrode stacked sequentially away from the substrate; The conductive pillar assembly includes a first conductive pillar and a second conductive pillar; The two ends of the first conductive post are electrically connected to the second electrode of the first capacitor structure and the first electrode of the second capacitor structure, respectively. The two ends of the second conductive post are electrically connected to the first electrode of the first capacitor structure and the second electrode of the second capacitor structure, respectively.

4. The semiconductor device according to claim 1, characterized in that, The substrate has an array of trenches on one side; the first capacitor structure is at least partially filled in the trenches to form a first deep trench capacitor. And / or, the other side of the substrate has an array of trenches, and the second capacitor structure is at least partially filled in the trenches to form a second deep trench capacitor.

5. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes: a first metal layer and a second metal layer, a third metal layer and a fourth metal layer disposed on the same layer; the first metal layer and the fourth metal layer are disposed in a direction away from the substrate, and the second metal layer and the third metal layer are disposed in a direction away from the substrate; The second electrode, the second metal layer, the first conductive pillar, the third metal layer, and the first electrode of the second capacitor structure are sequentially electrically connected; The first electrode of the first capacitor structure, the first metal layer, the second conductive pillar, the fourth metal layer, and the second electrode of the second capacitor structure are sequentially electrically connected.

6. The semiconductor device according to claim 1, characterized in that, Also includes: A carrier substrate is disposed on the side of the first capacitor structure away from the second capacitor structure; A first contact layer is disposed on the side of the first electrode and the second electrode away from the substrate; A first connecting wire is disposed on the side of the first contact layer away from the first electrode; A first conductive structure is disposed on the side of the first connecting wire away from the first contact layer; The second connecting wire is disposed on the side of the first contact layer away from the second electrode; The second conductive structure is disposed on the side of the second connecting wire away from the first contact layer.

7. An electronic device, characterized in that, include: The semiconductor device as described in any one of claims 1-6 above.

8. A method for manufacturing a semiconductor device, characterized in that, include: The first segment of the first capacitor structure and conductive pillar assembly is formed on one side of the substrate; The first capacitor structure is at least partially embedded in the substrate; A second segment of the second capacitor structure and conductive pillar assembly is formed on the other side of the substrate; The second capacitor structure is at least partially embedded in the substrate; the first segment of the conductive pillar assembly and the second segment of the conductive pillar assembly are connected one-to-one to form a conductive pillar assembly that penetrates the substrate, so that the first capacitor structure and the second capacitor structure are connected in parallel.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, After forming the first segment of the first capacitor structure and the conductive pillar assembly on one side of the substrate, the method further includes: The side of the substrate having the first capacitor structure and the first segment of the conductive pillar assembly is bonded to the carrier substrate.

10. The method for manufacturing a semiconductor device according to claim 8, characterized in that, A first segment of forming a first capacitor structure and a conductive pillar assembly on one side of the substrate includes: A first capacitor structure and a first hole and a second hole located on both sides of the first capacitor structure are formed on one side of the substrate. The conductive post assembly includes the first conductive post and the second conductive post, wherein a first section of the second conductive post is formed in the first hole and a first section of the first conductive post is formed in the second hole; A first metal layer and a second metal layer are formed on one side of the substrate. The first metal layer is electrically connected to a first segment of the second conductive pillar and a first electrode of the first capacitor structure. The second metal layer is electrically connected to a first segment of the first conductive pillar and a second electrode of the first capacitor structure.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, A first capacitor structure and a first hole and a second hole located on both sides of the first capacitor structure are formed on one side of the substrate, including: A trench region having an array of trenches is formed on one side of the substrate; A first electrode, a dielectric layer, and a second electrode are formed on one side of the substrate having the trench region to obtain a first capacitor structure, wherein the first capacitor structure at least partially fills the trench. A first hole and a second hole are formed on one side of the substrate, located on both sides of the trench region.

12. The method for manufacturing a semiconductor device according to claim 10, characterized in that, A second segment forming a second capacitor structure and a conductive pillar assembly on the other side of the substrate includes: A second capacitor structure, a fourth hole corresponding to and communicating with the first hole, and a third hole corresponding to and communicating with the second hole are formed on the other side of the substrate. A second section of the first conductive post is formed in the third hole, and a second section of the second conductive post is formed in the fourth hole. The first section of the first conductive post and the second section of the first conductive post are connected in a one-to-one correspondence, and the first section of the second conductive post and the second section of the second conductive post are connected in a one-to-one correspondence. A third metal layer and a fourth metal layer are formed on the other side of the substrate. The third metal layer is electrically connected to the second segment of the first conductive pillar and the first electrode of the second capacitor structure. The fourth metal layer is electrically connected to the second segment of the second conductive pillar and the second electrode of the second capacitor structure.

13. The method for manufacturing a semiconductor device according to claim 11, characterized in that, After forming a stacked first electrode, dielectric layer, and second electrode on one side of the substrate having the trench region, the process includes: A sidewall structure is formed on the side peripheral surfaces of the first electrode, the dielectric layer, and the second electrode, with the edge of the first electrode exposed in the dielectric layer and the second electrode; Each forms a first contact layer that covers the first electrode and the second electrode exposed to the second electrode; A first connecting wire and a first conductive structure are sequentially formed on one side of the first contact layer on the surface of the first electrode, and a second connecting wire and a second conductive structure are sequentially formed on one side of the first contact layer on the surface of the second electrode, such that the first electrode, the first connecting wire and the first conductive structure are electrically connected, and the second electrode, the second connecting wire and the second conductive structure are electrically connected.

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