Silicon carbide substrate and preparation method thereof, and silicon carbide epitaxial wafer and preparation method thereof

Abstract

The invention provides a silicon carbide substrate for epitaxial growth, a preparation method of the silicon carbide substrate, a silicon carbide epitaxial wafer and a preparation method of the silicon carbide epitaxial wafer. In one aspect, there is provided a method for preparing a silicon carbide substrate for epitaxial growth, the method comprising: performing ion implantation on a surface of the silicon carbide substrate to form a damaged region below the surface; and annealing the silicon carbide substrate subjected to ion implantation so as to recrystallize the damaged region and form a defect gettering layer comprising a dislocation ring. Therefore, the density of defects in the epitaxial layer can be remarkably reduced, and the silicon carbide epitaxial wafer with more excellent crystal quality can be obtained.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a silicon carbide substrate for epitaxial growth, a method for manufacturing the same, and a silicon carbide epitaxial wafer and a method for manufacturing the same. BACKGROUND

[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor material that is widely used in the manufacture of high-power, high-frequency, and high-temperature-resistant electronic devices due to its excellent physical properties such as high breakdown electric field, high thermal conductivity, and high electron saturation velocity. It plays a key role in fields such as electric vehicles, renewable energy conversion, and 5G communications.

[0003] A silicon carbide epitaxial wafer is a basic material for manufacturing the above-mentioned devices. In the related art, a silicon carbide epitaxial wafer is usually prepared by growing a silicon carbide epitaxial layer on a silicon carbide single crystal substrate. However, crystal defects will inevitably be formed in the silicon carbide single crystal substrate during the preparation process. In the subsequent epitaxial growth process, these crystal defects will propagate into the epitaxial layer formed on the silicon carbide single crystal substrate, thereby affecting the performance and yield of the final manufactured devices. SUMMARY

[0004] This section provides a general summary of the present disclosure, and not a comprehensive disclosure of the full scope or all features of the present disclosure.

[0005] Embodiments of the present disclosure provide a method for manufacturing a silicon carbide substrate for epitaxial growth, a silicon carbide substrate for epitaxial growth, a method for manufacturing a silicon carbide epitaxial wafer, and a silicon carbide epitaxial wafer, which can inhibit the propagation of crystal defects in the substrate to the epitaxial layer, thereby improving the crystal quality of the epitaxial layer.

[0006] According to an aspect of the present disclosure, a method for manufacturing a silicon carbide substrate for epitaxial growth is provided. The method includes ion implanting a surface of a silicon carbide substrate to form a damage region below the surface, and annealing the silicon carbide substrate subjected to ion implantation to recrystallize the damage region and form a defect gettering layer including dislocation loops.

[0007] According to another aspect of the present disclosure, a silicon carbide substrate for epitaxial growth is provided. The silicon carbide substrate for epitaxial growth includes a silicon carbide single crystal substrate body and a defect gettering layer. The defect gettering layer is located at a subsurface depth within the silicon carbide single crystal substrate body, and the defect gettering layer includes dislocation loops.

[0008] According to still another aspect of the present disclosure, a silicon carbide substrate for epitaxial growth is provided. The silicon carbide substrate for epitaxial growth includes a silicon carbide single crystal substrate body and a defect gettering layer. The defect gettering layer is located at a subsurface depth within the silicon carbide single crystal substrate body, and the defect gettering layer includes a region enriched with one or more metal impurities.

[0009] According to yet another aspect of the present disclosure, a method for preparing a silicon carbide epitaxial wafer is provided. The method includes: ion implanting a surface of a silicon carbide substrate to form a damage region below the surface; annealing the ion-implanted silicon carbide substrate to recrystallize the damage region and form a defect gettering layer including dislocation loops; and growing a silicon carbide epitaxial layer on the surface of the annealed silicon carbide substrate.

[0010] According to still another aspect of the present disclosure, a silicon carbide epitaxial wafer is provided. The silicon carbide epitaxial wafer includes a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide substrate includes a silicon carbide single crystal substrate body and a defect gettering layer. The defect gettering layer is located at a subsurface depth within the silicon carbide single crystal substrate body, and the defect gettering layer includes dislocation loops. The silicon carbide epitaxial layer is located on a surface of the silicon carbide substrate.

[0011] According to yet another aspect of the present disclosure, a silicon carbide epitaxial wafer is provided. The silicon carbide epitaxial wafer includes a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide substrate includes a silicon carbide single crystal substrate body and a defect gettering layer. The defect gettering layer is located at a subsurface depth within the silicon carbide single crystal substrate body, and the defect gettering layer includes regions enriched with one or more metallic impurities. The silicon carbide epitaxial layer is located on a surface of the silicon carbide substrate.

[0012] In the technical solutions provided by the embodiments of the present disclosure, by pre-constructing a defect gettering layer in a subsurface region (i.e., at a certain depth below the surface) of a silicon carbide substrate, the defect gettering layer can effectively capture and pin crystal defects (such as dislocations) extending upward from the deep substrate body during subsequent epitaxial growth, and adsorb metallic impurities in the substrate, thereby preventing these defects and impurities from entering the newly grown epitaxial layer. Thus, the density of "killer defects" in the epitaxial layer can be significantly reduced, and a silicon carbide epitaxial wafer with more excellent crystal quality can be obtained, thereby improving the performance and yield of semiconductor devices manufactured based on the epitaxial wafer. BRIEF DESCRIPTION OF DRAWINGS

[0013] The features and advantages of the embodiments of the present disclosure will become more apparent from the following description with reference to the accompanying drawings. The drawings are not drawn to scale, and some features can be enlarged or reduced to show details of certain components. In the drawings: Figure 1 A flowchart of a method for preparing a silicon carbide epitaxial wafer according to the related art.

[0014] Figure 2 A flowchart of a method for preparing a silicon carbide substrate for epitaxial growth according to an embodiment of the present disclosure.

[0015] Figure 3 A flowchart of a method for preparing a silicon carbide substrate for epitaxial growth according to an embodiment of the present disclosure. Figure 2A flowchart of the preparation method shown.

[0016] Figure 4 A schematic cross-sectional view of a silicon carbide substrate according to another embodiment of the present disclosure.

[0017] Figure 5 A flowchart of a preparation method of a silicon carbide epitaxial wafer according to an embodiment of the present disclosure.

[0018] Figure 6 A flowchart of the preparation method shown. Figure 5 A flowchart of the preparation method shown.

[0019] Figure 7 A flowchart of the preparation method shown. Figure 5 Another flowchart of the preparation method shown.

[0020] In the drawings, the same or corresponding technical features or components are denoted by the same or corresponding reference numerals. DETAILED DESCRIPTION

[0021] The present disclosure is described in detail below with reference to the accompanying drawings and by way of exemplary embodiments. It is to be noted that the following detailed description of the present disclosure is merely for illustrative purposes and is by no means a limitation on the present disclosure.

[0022] It should be noted that, for the sake of clarity, not all features of a specific embodiment are described and shown in the specification and drawings, and in order to avoid obscuring the technical solutions of the present disclosure that are the focus of the present disclosure, only the device structures closely related to the technical solutions of the present disclosure are described and shown in the specification and drawings, and other details that are not closely related to the technical content of the present disclosure and are known to those skilled in the art are omitted.

[0023] Before the technical solutions of the embodiments of the present disclosure are described, first, refer to Figure 1 The technical problems to be solved by the present disclosure are described in detail.

[0024] In the preparation of a silicon carbide epitaxial wafer in the related art, the substrate 100' is a single-crystal silicon carbide substrate, which can be a commonly used 4H-SiC or 6H-SiC substrate, for example, and can have a size of 6 inches or 8 inches and can be of N-type or P-type. A silicon carbide epitaxial wafer 300' is prepared by growing a silicon carbide epitaxial layer 200' on the substrate 100' using a method such as chemical vapor deposition (CVD). The silicon carbide epitaxial wafer 300' can be prepared by first growing a silicon carbide buffer layer 220' of, for example, 1 μm or 2 μm on the substrate 100', and then growing a silicon carbide main epitaxial layer 240' of, for example, 10 μm on the silicon carbide buffer layer 220'.

[0025] The substrate 100' will inevitably form various crystal defects during the growth process, such as basal plane dislocations (BPDs), threading screw dislocations (TSDs), and the like. When epitaxial growth is performed on the substrate 100', the defects located in the surface or subsurface region of the substrate 100' will extend and propagate into the silicon carbide epitaxial layer 200' with a very high probability (close to 100%).

[0026] These defects propagated into the silicon carbide epitaxial layer 200' will form so-called "killer defects", such as carrot defects, resulting in a serious deterioration of the crystal quality of the silicon carbide epitaxial layer 200', and thus causing problems such as an increase in leakage current, a decrease in breakdown voltage, a decrease in long-term reliability, and the like in devices manufactured using the silicon carbide epitaxial wafer 300', and ultimately significantly reducing the performance and yield of the devices.

[0027] To this end, the present disclosure attempts to perform a pretreatment on the silicon carbide substrate before epitaxial growth, and actively construct a defect gettering layer in the subsurface region of the silicon carbide substrate by a combination of high-energy ion implantation and high-temperature annealing, in order to capture crystal defects and impurities migrating from the bulk of the silicon carbide substrate to the surface on which epitaxial growth is to be performed, thereby protecting the epitaxial layer grown on the surface from the effects of these crystal defects and impurities, and obtaining a high-quality silicon carbide epitaxial wafer.

[0028] Hereinafter, the preparation method of the silicon carbide substrate 100 for epitaxial growth according to the embodiment of the present disclosure will be described in detail with reference to Figure 2 and Figure 3 .

[0029] The preparation method includes a step S210 and a step S220.

[0030] In the step S210, ion implantation is performed on the surface 122 of the silicon carbide substrate 120 to form a damage region 124 below the surface 122.

[0031] The silicon carbide substrate 120 can be a single-crystal silicon carbide substrate, such as a commonly used 4H-SiC or 6H-SiC substrate, which can have a size of 6 inches or 8 inches and can be of N-type or P-type conductivity. The surface 122 of the silicon carbide substrate 120 is a surface for subsequent epitaxial growth thereon. Exemplarily, the surface 122 can be a silicon-dominant face of the silicon carbide substrate 120.

[0032] In ion implantation, high-energy ions penetrate the surface 122, implant into the silicon carbide substrate 120, and stop at the vicinity of their range with energy depletion, thereby forming a buried damage region 124 at a certain depth (subsurface depth) inside the silicon carbide substrate 120 (at this time, the silicon carbide substrate after ion implantation is denoted by 140). The damage region 124 is a region in which the original single-crystal structure is destroyed due to high-energy ion bombardment. The periodic arrangement of atoms in the damage region 124 is broken and can be in a pre-amorphized state or an amorphized state.

[0033] It is conceivable that the implanted ions can be the same element as that constituting the silicon carbide substrate 120, such as silicon (Si) ions. Thus, the introduction of foreign chemical elements into the silicon carbide substrate 120, which can cause unintended electrical effects, can be avoided.

[0034] In order to bury the damage region 124 at a deeper position in the subsurface of the silicon carbide substrate 120, the energy of ion implantation needs to be sufficiently high. It is conceivable that the energy of ion implantation can be greater than 1 MeV. For example, the energy of ion implantation can be 1.5 MeV or higher.

[0035] A higher implantation energy causes the peak concentration position of the damage region 124 to be away from the surface 122, so that the finally formed defect gettering layer 142 (to be described below) is also located in a deeper subsurface region. The isolation of the defect gettering layer 142 from the surface 122 is very important for subsequent device manufacturing, and can make the defect gettering layer 142 itself not adversely affect the active region of the device.

[0036] In addition, the dose of ion implantation also needs to reach a certain level in order to form a high enough density of lattice damage in the damage region 124, so as to form effective gettering sites in the subsequent annealing. It is conceivable that the dose of ion implantation can be greater than 5E14 cm -2 .

[0037] A sufficiently high dose can ensure the formation of a high density of point defects, which is a technical guarantee for the subsequent formation of a high density of dislocation loops through annealing, thereby achieving a high-efficiency gettering function.

[0038] After completing ion implantation, in step S220, the silicon carbide substrate 140 after ion implantation is annealed.

[0039] As Figure 3As shown, by annealing, the damage region 124 can be recrystallized and form a stable defect gettering layer 142 including dislocation loops. At high temperature, point defects (e.g., interstitial atoms and vacancies) in the damage region 124 can migrate and cluster, and eventually form extended defects, i.e., dislocation loops. These high density dislocation loops constitute the main body of the defect gettering layer 142.

[0040] The annealing temperature needs to be high enough to provide the energy required for atomic migration and lattice reconfiguration. It is contemplated that the annealing temperature can be greater than 1600 °C. For example, it can be in the range of 1600-1700 °C. The annealing can be performed in an inert gas (e.g., argon (Ar)) atmosphere, and the annealing time can be greater than 30 minutes to ensure that the recrystallization process is completed.

[0041] By precisely controlling the energy of ion implantation, the depth of the defect gettering layer 142 formed can be controlled. It is contemplated that the defect gettering layer 142 is formed at a depth greater than 1.5 μm from the surface 122.

[0042] For example, when Si ions with an energy of 1.5 MeV are implanted, the projected range Rp is approximately 1.5 μm, and the center of the defect gettering layer 142 formed is also approximately at this depth, with a distribution range approximately in the range of Rp ± 2ΔRp, where ΔRp is the range straggling.

[0043] The silicon carbide substrate 100 for epitaxial growth can be obtained by the above preparation method.

[0044] The silicon carbide substrate 100 for epitaxial growth includes a silicon carbide single crystal substrate body 102 and a defect gettering layer 142.

[0045] The defect gettering layer 142 is located at a subsurface depth d in the silicon carbide single crystal substrate body 102, and the subsurface depth d can be greater than 1.5 μm from the surface 122. The main structural feature of the defect gettering layer 142 is that it includes a high density of dislocation loops therein.

[0046] The working mechanism of the defect gettering layer 142 is described below. During subsequent epitaxial growth, when crystal defects in the deep part of the silicon carbide single crystal substrate body 102, such as basal plane dislocations, begin to slide and propagate upward at high temperature, they will encounter the pre-set defect gettering layer 142. The high density dislocation loop network in the defect gettering layer 142 will generate a strong stress field that can effectively interact with the moving crystal defects, thereby pinning or trapping them inside the defect gettering layer 142, preventing them from continuing to propagate to the surface 122 and the epitaxial layer to be grown. Thus, the defect gettering layer 142 can effectively intercept defects from the silicon carbide single crystal substrate body 102.

[0047] In addition, the defect gettering layer 142 also has a function of chemical gettering. The core region of the dislocation loop is a highly distorted region of the crystal lattice, which is a low-lying point in terms of energy, and has a strong attraction to the mobile metal impurities present in the silicon carbide substrate body 102. During high-temperature annealing or epitaxial growth, these metal impurity atoms will diffuse to the dislocation loop and be captured and enriched.

[0048] Therefore, in some other embodiments of the present disclosure, referring to Figure 4 , a silicon carbide substrate for epitaxial growth 200 is also provided.

[0049] The silicon carbide substrate for epitaxial growth 200 includes a silicon carbide single crystal substrate body 202 and a defect gettering layer 242.

[0050] The defect gettering layer 242 is located at a subsurface depth within the silicon carbide single crystal substrate body 202, and the defect gettering layer 242 can include a region 2422 enriched with one or more metal impurities 20.

[0051] It is envisaged that the defect gettering layer 242 includes a dislocation loop, and the metal impurities 20 are enriched at the dislocation loop. This chemical gettering can further improve the purity of the silicon carbide substrate 200, providing a cleaner growth interface for growing high-quality epitaxial layers.

[0052] Referring to Figure 5 and Figure 6 , according to embodiments of the present disclosure, a method for preparing a silicon carbide epitaxial wafer 300 is also provided.

[0053] The preparation method includes the steps of preparing the above-mentioned silicon carbide substrate for epitaxial growth 100, i.e. ion implantation is performed on the surface 122 of the silicon carbide substrate 120 to form a damage region 124 below the surface 122 (step S210); and then annealing the silicon carbide substrate 140 subjected to ion implantation to recrystallize the damage region 124 and form a defect gettering layer 142 including a dislocation loop (step S220).

[0054] After obtaining the silicon carbide substrate 100 with the defect gettering layer 142, further, the preparation method also includes a step S230 of growing a silicon carbide epitaxial layer 160 on the surface 122 of the silicon carbide substrate 100 subjected to annealing.

[0055] It is envisaged that, as Figure 6 shown, the process of growing the silicon carbide epitaxial layer 160 can include two steps: first, growing a relatively thin silicon carbide buffer layer 162 on the surface 122; and then growing a relatively thick silicon carbide main epitaxial layer 164 on the silicon carbide buffer layer 162.

[0056] The silicon carbide buffer layer 162 functions to provide a high-quality starting surface for the growth of the subsequent silicon carbide main epitaxial layer 164. For example, the silicon carbide buffer layer 162 can have a thickness of 0.5-1.5 μm, while the silicon carbide main epitaxial layer 164 can have a thickness of greater than 7 μm to meet the design requirements of power electronic devices.

[0057] There are various possible implementations regarding the process integration of the annealing step and the epitaxial growth step.

[0058] It is contemplated that the annealing step can be performed independently prior to the growth of the silicon carbide epitaxial layer 160, as shown in FIG. 1A. Figure 6

[0059] That is, the ion implantation and high-temperature annealing can be performed as a separate process to produce a silicon carbide substrate product that has been defect engineered. This substrate product can be directly placed into an epitaxial growth apparatus (e.g., a CVD apparatus) for epitaxial growth without the need for additional annealing.

[0060] It is also contemplated that the annealing step can be combined with the step of growing the silicon carbide buffer layer 162, as shown in FIG. 1B. Figure 7

[0061] Specifically, in an epitaxial growth apparatus, a high-temperature (e.g., greater than 1600°C) in-situ thermal treatment process is performed on the silicon carbide substrate prior to the growth of the silicon carbide buffer layer 162 in an inert gas atmosphere. This thermal treatment process is itself a standard pre-growth step (e.g., for removing surface oxide and etching the surface) that is performed in the epitaxial growth apparatus, and in this case, this thermal treatment process also functions to recrystallize the damage region to form the defect gettering layer. As a result, there is no need for a separate annealing apparatus and process, which simplifies the overall process flow, reduces production costs, and improves production efficiency.

[0062] After the above-described preparation method, a silicon carbide epitaxial wafer 300 can be obtained, as shown in FIG. 1C. Figure 6 Figure 7

[0063] The silicon carbide epitaxial wafer 300 includes a silicon carbide substrate 100 and a silicon carbide epitaxial layer 160 on a surface 122 of the silicon carbide substrate 100.

[0064] The silicon carbide substrate 100 includes a silicon carbide single crystal substrate body 102 and a defect gettering layer 142 at a subsurface depth within the silicon carbide single crystal substrate body 102. The defect gettering layer 142 can include dislocation loops. The silicon carbide epitaxial layer 160 can include a silicon carbide buffer layer 162 and a silicon carbide main epitaxial layer 164.

[0065] ​​​​Alternatively, as discussed previously, it is contemplated that the defect gettering layer can include a region enriched with one or more metallic impurities.

[0066] Due to the presence of the defect gettering layer 142, the crystal defects propagating from the silicon carbide single crystal substrate body 102 are effectively blocked from entering the silicon carbide epitaxial layer 160. As a result, the silicon carbide epitaxial wafer 300 according to the embodiments of the present disclosure has a significantly lower defect density in the epitaxial layer 160 compared to the related art (i.e., growing a buffer layer and an epitaxial layer directly on a regular substrate). Figure 1

[0067] While the present disclosure has been described with reference to exemplary embodiments, it is to be understood that the disclosure is not limited to the specific embodiments disclosed and described herein. Various changes in form and detail can be made to the exemplary embodiments without departing from the scope of the disclosure as defined by the claims.

[0068] Features mentioned and / or shown in the above description of the exemplary embodiments of the present disclosure can be incorporated in one or more other embodiments in the same or analogous manner, combined with features of other embodiments or replace corresponding features of other embodiments. The technical solutions obtained by combining or replacing should also be considered to be included in the protection scope of the present disclosure.​

Claims

1. A method for producing a silicon carbide substrate for epitaxial growth, characterized by, Comprising: ion implanting a surface of a silicon carbide substrate to form a damage region beneath the surface; and annealing the silicon carbide substrate subjected to the ion implantation to recrystallize the damage region and form a defect gettering layer comprising dislocation loops.

2. The method of producing a silicon carbide substrate for epitaxial growth according to claim 1, characterized by, The ions used in the ion implantation are silicon ions.

3. The method of producing a silicon carbide substrate for epitaxial growth according to claim 1, characterized by, The ion implantation has an energy greater than 1 MeV.

4. The production method of a silicon carbide substrate for epitaxial growth according to Claim 1, wherein The ion implantation has a dose greater than 5E14 cm -2 .

5. The method of producing a silicon carbide substrate for epitaxial growth according to Claim 1, wherein The defect gettering layer is formed at a depth greater than 1.5 μm from the surface.

6. The production method of a silicon carbide substrate for epitaxial growth according to Claim 1, wherein The annealing has a temperature in a range of 1600-1700 °C.

7. A silicon carbide substrate for epitaxial growth, characterized by, Comprising: a silicon carbide single crystal substrate body; and a defect gettering layer at a subsurface depth within the silicon carbide single crystal substrate body, the defect gettering layer comprising dislocation loops. The subsurface depth is greater than 1.5 μm from a surface of the silicon carbide single crystal substrate body.

8. The silicon carbide substrate for epitaxial growth of claim 7, wherein Comprising:

9. A silicon carbide substrate for epitaxial growth, characterized by, a silicon carbide single crystal substrate body; and a defect gettering layer at a subsurface depth within the silicon carbide single crystal substrate body, the defect gettering layer comprising regions enriched with one or more metallic impurities. The defect gettering layer comprises dislocation loops, the one or more metallic impurities being enriched at the dislocation loops. Comprising:

10. The silicon carbide substrate for epitaxial growth of claim 9, wherein ion implanting a surface of a silicon carbide substrate to form a damage region beneath the surface; 11. A method of producing a silicon carbide epitaxial wafer, characterized by, annealing the silicon carbide substrate subjected to the ion implantation to recrystallize the damage region and form a defect gettering layer comprising dislocation loops; and growing a silicon carbide epitaxial layer on the surface of the silicon carbide substrate subjected to the annealing. The growing a silicon carbide epitaxial layer on the surface comprises: growing a silicon carbide buffer layer on the surface; and 12. The method of producing a silicon carbide epitaxial wafer according to claim 11, wherein growing a silicon carbide main epitaxial layer on the silicon carbide buffer layer. The silicon carbide buffer layer has a thickness in a range of 0.5-1.5 μm, and the silicon carbide main epitaxial layer has a thickness greater than 7 μm. The annealing is performed independently of growing the silicon carbide epitaxial layer.

13. The method of producing a silicon carbide epitaxial wafer according to claim 12, wherein The annealing is combined with growing the silicon carbide buffer layer.

14. The method for preparing a silicon carbide epitaxial wafer according to claim 12, characterized in that, Comprising:

15. The method of claim 12, wherein the step of growing the silicon carbide epitaxial layer is performed at a temperature of about 1,100°C to about 1,300°C. a silicon carbide substrate, the silicon carbide substrate comprising:

16. A silicon carbide epitaxial wafer, characterized by, a silicon carbide single crystal substrate body; and a defect gettering layer at a subsurface depth within the silicon carbide single crystal substrate body, the defect gettering layer comprising dislocation loops; and a silicon carbide epitaxial layer on the surface of the silicon carbide substrate. Comprising: a silicon carbide substrate, the silicon carbide substrate comprising:

17. A silicon carbide epitaxial wafer, characterized by, a silicon carbide single crystal substrate body; and a defect gettering layer at a subsurface depth within the silicon carbide single crystal substrate body, the defect gettering layer comprising regions enriched with one or more metallic impurities; and a silicon carbide epitaxial layer on the surface of the silicon carbide substrate. ​ ​

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