A method for fabricating a semiconductor structure, a semiconductor structure, and an integrated circuit.

Abstract

This invention discloses a method for fabricating a semiconductor structure, a semiconductor structure, and an integrated circuit, belonging to the field of semiconductor technology. The fabrication method includes at least the following steps: etching multiple interlayer dielectric layers to form vertical contact holes in the device region and irregularly shaped contact holes in the sealing ring region, wherein the radial dimension of the irregularly shaped contact holes decreases with increasing depth; etching a portion of the multilayer dielectric layers surrounding the vertical contact holes to form trenches on the side of the contact holes away from the underlying metal layer and vias on the side of the contact holes closer to the underlying metal layer; simultaneously etching the top of the multilayer dielectric layers to connect adjacent irregularly shaped contact holes; and depositing conductive material layers in the vias, trenches, and irregularly shaped contact holes, wherein the conductive material layers in the vias and trenches form a damascus structure, and the conductive material layers in the irregularly shaped contact holes form a sealing ring. The semiconductor structure fabrication method provided by this invention simplifies the process and reduces defects.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method for fabricating a semiconductor structure, a semiconductor structure, and an integrated circuit. Background Technology

[0002] In integrated circuits, a sealing ring is placed around the chip. The sealing ring is a protective barrier for semiconductor device packaging and wafer dicing, protecting the internal circuitry of the chip from the effects of the wafer dicing process to achieve good chip reliability.

[0003] The sealing ring is disposed in the metal interconnect layer on the semiconductor device, and the damascene structure and the sealing ring can be formed simultaneously in the metal interconnect layer. However, due to the difference in radial dimensions between the damascene structure and the sealing ring, secondary trench defects or fence defects are easily generated when simultaneously etching the interlayer dielectric layer to form the trench of the damascene structure and the contact hole connection of the sealing ring. Furthermore, the step-by-step formation of the damascene structure and the sealing ring requires complex process steps, making the process complicated and costly. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a semiconductor structure, a semiconductor structure, and an integrated circuit, which can solve the problem that secondary trench defects or fence defects are easily generated when the contact holes of the damascus structure and the sealing ring cannot be formed simultaneously.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0006] This invention provides a method for fabricating a semiconductor structure, the semiconductor structure including a device region and a sealing ring region, and the fabrication method includes at least the following steps:

[0007] Multiple interlayer dielectric layers are disposed on the bottom metal layer;

[0008] The multilayer interlayer dielectric layer is etched to form a vertical contact hole in the device region and an irregularly shaped contact hole in the sealing ring region, wherein the radial dimension of the irregularly shaped contact hole decreases with increasing depth;

[0009] Etch a portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole, form a trench on the side of the vertical contact hole away from the bottom metal layer, and form a through hole on the side of the vertical contact hole close to the bottom metal layer;

[0010] Simultaneously etch the top of the multilayer interlayer dielectric layer to connect adjacent irregularly shaped contact holes; and

[0011] Conductive material layers are deposited in the through holes, the trenches, and the irregularly shaped contact holes. The conductive material layers in the through holes and the trenches form a damascus structure, and the conductive material layers in the irregularly shaped contact holes form a sealing ring, with adjacent sealing rings connected.

[0012] In one embodiment of the present invention, the multilayer interlayer dielectric layer includes a nitrogen-doped carbon layer, a first dielectric layer, an etch stop layer, a second dielectric layer, and an anti-reflection layer stacked together. When forming the vertical contact hole and the irregular contact hole, the anti-reflection layer, the second dielectric layer, the etch stop layer, the first dielectric layer, and a portion of the thickness of the nitrogen-doped carbon layer are etched sequentially to form the vertical contact hole in the device region and the irregular contact hole in the sealing ring region.

[0013] In one embodiment of the present invention, the dimensions of the vertical contact hole and the irregular contact hole extending into the nitrogen-doped carbon layer are equal to one-third to two-thirds of the thickness of the nitrogen-doped carbon layer.

[0014] In one embodiment of the present invention, the sidewall of the irregularly shaped contact hole is inclined, or the sidewall of the irregularly shaped contact hole is arc-shaped inward or outward.

[0015] In one embodiment of the present invention, when forming the irregular contact hole, the distance between adjacent irregular contact holes at the top of the irregular contact hole is less than half of the radial dimension of the vertical contact hole.

[0016] In one embodiment of the present invention, forming the trench and the through hole includes the following steps:

[0017] The bottom layer is filled into the vertical contact hole and the irregular contact hole, and the bottom layer is etched back;

[0018] A second patterned photoresist layer is formed, the second patterned photoresist layer exposing the vertical contact hole and a portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole;

[0019] Using the second patterned photoresist layer as a mask, the bottom layer inside the vertical contact hole and part of the multilayer interlayer dielectric layer around the vertical contact hole are simultaneously etched. The trench is formed on the side of the vertical contact hole away from the bottom metal layer, and the via is formed on the side of the vertical contact hole close to the bottom metal layer.

[0020] In one embodiment of the present invention, when the trench is formed by etching a portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole, the etched multilayer interlayer dielectric layer is flush with the bottom layer and remains in the etching stop layer.

[0021] In one embodiment of the present invention, the simultaneous etching of the top of the multilayer interlayer dielectric layer includes the following steps: using a dry etching process to simultaneously etch the surface of the multilayer interlayer dielectric layer, the bottom of the trench, the bottom of the via, and the bottom of the irregular contact hole, so that the nitrogen-doped carbon layer at the bottom of the via and the irregular contact hole is completely etched away.

[0022] The present invention also provides a semiconductor structure, the semiconductor structure including a device region and a sealing ring region, and the semiconductor structure further including at least:

[0023] A multilayer interlayer dielectric layer is disposed on the bottom metal layer;

[0024] A via is formed by etching the multilayer interlayer dielectric layer of the device region to form a vertical contact hole, and the vertical contact hole is located on the side close to the bottom metal layer.

[0025] The trench is formed on the side of the vertical contact hole away from the bottom metal layer by etching a portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole.

[0026] The irregularly shaped contact hole is formed by etching the multilayer interlayer dielectric layer of the sealing ring region. The radial dimension of the irregularly shaped contact hole decreases with increasing depth, and adjacent irregularly shaped contact holes are interconnected.

[0027] A conductive material layer is disposed within the through hole, the trench, and the irregularly shaped contact hole. The conductive material layers in the through hole and the trench form a damascus structure, and the conductive material layer in the irregularly shaped contact hole forms a sealing ring, with adjacent sealing rings connected.

[0028] The present invention also provides an integrated circuit comprising the semiconductor structure described above.

[0029] In summary, the semiconductor structure, semiconductor structure, and integrated circuit provided by this invention have an unexpected effect: by setting the contact holes in the sealing ring region as irregularly shaped contact holes, a multi-layered interconnected sealing ring can be formed during the subsequent removal of the anti-reflective layer and part of the second dielectric layer. Therefore, after forming the vertical contact holes and irregularly shaped contact holes, only the vertical contact holes in the device region need to be etched during the second exposure etching. At this time, only the thickness of the underlying layer formed in the device region needs to be adjusted according to the etching amount of the vertical contact holes in the device region, thereby avoiding the occurrence of secondary trench or fence defects due to the inability to simultaneously adjust the thickness of the underlying layer in the device region and the sealing ring region. Since the irregularly shaped contact holes do not need to be etched during the second exposure etching, only the vertical contact holes need to be etched, which reduces the process difficulty of trench etching. Furthermore, compared to the vertical sealing ring, the metal thickness of the irregularly shaped sealing ring formed in this application is increased, the isolation capability of the sealing ring is enhanced, and the stability and lifespan of the formed chip can be extended.

[0030] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 Electron micrographs of the formed sub-groove defects and fence defects.

[0033] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.

[0034] Figure 3 This is a schematic diagram of the structure forming a multilayer interlayer dielectric layer and a first patterned photoresist layer in one embodiment of this application.

[0035] Figure 4 This is a schematic diagram of the structure forming a vertical contact hole and an irregularly shaped contact hole in one embodiment of this application.

[0036] Figure 5 This is a flowchart illustrating the method for fabricating trenches and through holes in one embodiment of this application.

[0037] Figure 6 This is a schematic diagram of the structure forming the bottom layer in one embodiment of this application.

[0038] Figure 7 This is a schematic diagram of the structure of the etched bottom layer in one embodiment of this application.

[0039] Figure 8 This is a schematic diagram of the structure for forming a second patterned photoresist layer in one embodiment of this application.

[0040] Figure 9 This is a schematic diagram of the structure forming the trench and through hole in one embodiment of this application.

[0041] Figure 10 This is a schematic diagram of the structure with the anti-reflective layer removed in one embodiment of this application.

[0042] Figure 11 This is a schematic diagram of the structure of a conductive material layer deposited in one embodiment of this application.

[0043] Figure 12 This is a schematic diagram of the structure forming the damascus structure and sealing ring in one embodiment of this application.

[0044] Label Explanation:

[0045] 100. Bottom metal layer; 101. Nitrogen-doped carbon layer; 102. First dielectric layer; 103. Etch stop layer; 104. Second dielectric layer; 105. Anti-reflective layer; 106. First patterned photoresist layer; 1061. First opening; 1062. Second opening; 1063. Mask; 1071. Vertical contact hole; 1072. Irregularly shaped contact hole; 1073. Through hole; 1074. Trench; 108. Bottom layer; 109. Second patterned photoresist layer; 110. Conductive material layer; 1101. Damascus structure; 1102. Sealing ring; H. Spacing between adjacent irregularly shaped contact holes. Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0048] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0049] In semiconductor integrated circuits, multiple semiconductor devices are integrated onto a single silicon wafer. After forming multiple semiconductor devices on the silicon wafer, an interlayer dielectric layer is formed on top of these devices, and a metal interconnect layer is formed within the dielectric layer. The metal interconnect layer electrically connects the multiple semiconductor devices according to the circuit design, forming a complete semiconductor integrated circuit. The metal interconnect layer can be implemented using a damascus structure. To form a damascus structure, a first exposure etching process creates vias, followed by a second exposure etching process to create trenches above the vias. Finally, conductive material layers are deposited in the vias and trenches to form the damascus structure.

[0050] A sealing ring is disposed within the interlayer dielectric layer and surrounds the semiconductor device, i.e., surrounds the metal interconnect layer. When multiple semiconductor devices formed on a wafer are diced into multiple chips, the sealing ring protects the semiconductor devices from damage caused by impurities and stress generated during wafer dicing. Forming the sealing ring in the interlayer dielectric layer requires two exposures and etching processes. The first exposure etches to form contact holes, and the second exposure connects the multiple contact holes, depositing a conductive material layer within the contact holes. The conductive material layer deposited within the contact holes forms the sealing ring, and the conductive material layer deposited in the connected portion of the contact holes connects adjacent sealing rings.

[0051] Forming both the damascus structure and the sealing ring requires two exposure and etching processes. If the damascus structure and sealing ring are formed in stages, the wafer needs to be transferred back and forth between the exposure and etching machines, making the process complex and costly. If the damascus structure and sealing ring are formed simultaneously, due to the different radial dimensions of the damascus structure and the sealing ring, an underlayer is filled into the contact holes of the damascus structure and the sealing ring before the second exposure and etching. Then, the underlayer and the interlayer dielectric layer around the contact holes are etched simultaneously to complete the second etching. However, because the contact holes of the damascus structure and the sealing ring have different diameters, there will be a height difference between the underlayer filling the contact holes of the damascus structure and the sealing ring, and the height of the underlayer in the contact holes of the damascus structure is greater than the height of the underlayer in the contact holes of the sealing ring. When re-etching the bottom layer of the contact hole in the damascus steel structure and the bottom layer of the contact hole in the sealing ring, it is impossible to simultaneously control the height of the bottom layer in both the damascus steel structure and the sealing ring to the required height. If the bottom layer height in the sealing ring's contact hole is too low, it will cause issues such as... Figure 1 The sub-groove defect shown in part (a) occurs when the bottom layer height in the contact hole of the damascus structure is too high, as in the case of... Figure 1 The sub-fence defect is shown in section (b).

[0052] Please see Figures 2 to 12 As shown, this invention provides a method for fabricating a semiconductor structure, a semiconductor structure, and an integrated circuit. The semiconductor structure includes a device region and a sealing ring region. The device region is the area on the substrate where a semiconductor device, such as a Static Random-Access Memory (SRAM), is located. The sealing ring region is the area where a sealing ring 1102 is located, and the sealing ring region surrounds the device region. The method for fabricating the semiconductor structure provided by this invention includes steps S110 to S150.

[0053] Step S110: Set multiple interlayer dielectric layers on the bottom metal layer.

[0054] Step S120: Etch multiple interlayer dielectric layers to form vertical contact holes in the device region and irregularly shaped contact holes in the sealing ring region.

[0055] Step S130: Etch a portion of the multilayer interlayer dielectric layer around the vertical contact hole, form a trench on the side of the vertical contact hole away from the bottom metal layer, and form a through hole on the side of the vertical contact hole close to the bottom metal layer.

[0056] Step S140: Simultaneously etch the top of the multilayer interlayer dielectric layer to make adjacent irregular contact holes connected.

[0057] Step S150: Deposit conductive material layers in through holes, trenches and irregularly shaped contact holes. The conductive material layers in through holes and trenches form a damascus structure, and the conductive material layers in irregularly shaped contact holes form a sealing ring.

[0058] Please see Figure 3 As shown, in one embodiment of the present invention, in step S110, the bottom metal layer 100 is a metal layer of the metal interconnect layer near the semiconductor device, and the bottom metal layer 100 includes a plurality of copper contact points. In some embodiments, the bottom metal layer 100 is a metal layer directly connected to the semiconductor device. In other embodiments, the bottom metal layer 100 is a metal layer of adjacent two side metal layers near the semiconductor device.

[0059] Please see Figure 3 As shown, in one embodiment of the present invention, the multilayer interlayer dielectric layer includes a nitrogen-doped carbon (NDC) layer 101, a first dielectric layer 102, an etch stop layer 103, a second dielectric layer 104, and an anti-reflection layer 105 stacked together. The nitrogen-doped carbon layer 101 is disposed on the bottom metal layer 100. The nitrogen-doped carbon layer 101 serves as an etch stop layer, effectively preventing the diffusion of copper atoms and ensuring that copper does not penetrate into the dielectric layer during etching, thereby protecting the dielectric layer from copper corrosion. Furthermore, the nitrogen-doped carbon layer 101 also serves as an etch stop layer 103, preventing over-etching during the etching of contact holes. The first dielectric layer 102 is disposed on the nitrogen-doped carbon layer 101, the etch stop layer 103 is disposed on the first dielectric layer 102, and the second dielectric layer 104 is disposed on the etch stop layer 103. The etch stop layer 103 is a silicon nitride (SiN) layer, which can be used as an etch stop layer 103 when etching the interlayer dielectric layer around the contact hole to form the trench 1074, thus facilitating the definition of the trench 1074 depth. The first dielectric layer 102 and the second dielectric layer 104 are tetraethyl orthosilicate (TEOS) layers, which can be used as interlayer dielectrics for the metal layers, providing isolation for the metal layers. Simultaneously, the first dielectric layer 102 and the second dielectric layer 104 are coated on a low-dielectric-constant silazane polymer or silicon nitride, which enhances adhesion and stability. An anti-reflective layer 105 is disposed on the second dielectric layer 104, and the anti-reflective layer 105, for example, is a silicon oxynitride (SiON) layer, which can improve photolithography accuracy. In this application, nitrogen-doped carbon layer 101, first dielectric layer 102, etch stop layer 103, second dielectric layer 104 and anti-reflection layer 105 can be deposited using any commonly used deposition method in vapor deposition.

[0060] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, when forming the vertical contact hole 1071 and the irregularly shaped contact hole 1072, a first patterned photoresist layer 106 is first formed on the anti-reflection layer 105. In the device region, a first opening 1061 is provided on the first patterned photoresist layer 106, and in the sealing ring region, a second opening 1062 is provided on the first patterned photoresist layer 106. The sidewalls of the first opening 1061 are vertically oriented, and the radial dimension of the second opening 1062 increases with the thickness of the first patterned photoresist layer 106. In this embodiment, the sidewalls of the second opening 1062 are inclined, and the cross-section of the second opening 1062 is, for example, an isosceles trapezoid. In other embodiments, the sidewalls of the second opening 1062 may be arc-shaped, either inward or outward. During the formation of the first patterned photoresist layer 106, photoresist can be spin-coated onto the anti-reflection layer 105, and then the photoresist can be exposed and developed to form the first patterned photoresist layer 106. In order to form a second opening 1062 whose radial dimension increases with the increase of the thickness of the first patterned photoresist layer 106, an irregularly shaped mask 1063 can be used to expose the photoresist layer so that the pattern on the mask 1063 is the same as the pattern of the second opening 1062.

[0061] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, after forming the first patterned photoresist layer 106, using the first patterned photoresist layer 106 as a mask, the multilayer interlayer dielectric layer at the bottom of the first opening 1061 and the interlayer dielectric layer at the bottom of the second opening 1062 are simultaneously etched to form a vertical contact hole 1071 in the device region and an irregularly shaped contact hole 1072 in the sealing ring region. The radial dimension of the irregularly shaped contact hole 1072 decreases with increasing depth. In this embodiment, the sidewalls of the irregularly shaped contact hole 1072 are inclined, and the cross-section of the irregularly shaped contact hole 1072 is, for example, an isosceles trapezoid, and an inverted isosceles trapezoid. In other embodiments, the sidewalls of the irregularly shaped contact hole 1072 may be arc-shaped inwards or outwards.

[0062] Please see Figure 4As shown, in this application, the contact holes in the sealing ring region are configured as irregularly shaped contact holes 1072. During the subsequent removal of the anti-reflective layer 105 and part of the second dielectric layer 104, a multi-layered, interconnected sealing ring 1102 can be formed. Therefore, after forming the vertical contact holes 1071 and the irregularly shaped contact holes 1072, during the second exposure etching, only the vertical contact holes 1071 in the device region need to be etched a second time. At this time, only the thickness of the underlying layer 108 formed in the device region needs to be adjusted according to the etching amount of the vertical contact holes 1071 in the device region, thereby avoiding the occurrence of secondary trenches or fence defects due to the inability to simultaneously adjust the thickness of the underlying layer 108 in both the device region and the sealing ring region. Simultaneously, compared to the vertical sealing ring 1102, the metal thickness of the irregularly shaped sealing ring 1102 formed in this application is increased, enhancing the isolation capability of the sealing ring 1102 and extending the stability and lifespan of the formed chip.

[0063] Please see Figure 4 As shown, in one embodiment of the present invention, the radial dimension of the vertical contact hole 1071 ranges from 250nm to 350nm, specifically, for example, 250nm, 280nm, 300nm, or 320nm. At the top of the irregularly shaped contact hole 1072, the spacing H between adjacent irregularly shaped contact holes 1072 is less than half the radial dimension of the vertical contact hole 1071. At this time, the spacing H between adjacent irregularly shaped contact holes 1072 is small. During the subsequent etching of the anti-reflective layer 105 and a portion of the second dielectric layer 104, a portion of the second dielectric layer 104 between adjacent irregularly shaped contact holes 1072 is etched below the irregularly shaped contact hole 1072, thus connecting the adjacent irregularly shaped contact holes 1072. This application does not limit the radial dimension of the irregularly shaped contact hole 1072; it can be determined based on the size of the sealing ring 1102 and the number of irregularly shaped contact holes 1072.

[0064] Please see Figure 4As shown, in one embodiment of the present invention, the vertical contact hole 1071 and the irregularly shaped contact hole 1072 pass through the anti-reflection layer 105, the second dielectric layer 104, the etch stop layer 103, and the first dielectric layer 102 into the nitrogen-doped carbon layer 101, and the dimensions of the vertical contact hole 1071 and the irregularly shaped contact hole 1072 extending into the nitrogen-doped carbon layer 101 are equal to one-third to two-thirds of the thickness of the nitrogen-doped carbon layer 101. In this embodiment, the dimensions of the vertical contact hole 1071 and the irregularly shaped contact hole 1072 extending into the nitrogen-doped carbon layer 101 are equal to half the thickness of the nitrogen-doped carbon layer 101. At this time, a nitrogen-doped carbon layer 101 of a certain thickness is provided between the vertical contact hole 1071 and the irregularly shaped contact hole 1072 and the bottom metal layer 100, which can prevent copper in the bottom metal layer 100 from contaminating the machine. Furthermore, if the nitrogen-doped carbon layer 101 between the vertical contact hole 1071 and the irregular contact hole 1072 and the bottom metal layer 100 is too thick, the remaining thickness of the nitrogen-doped carbon layer 101 will not be etched away during the subsequent etching process.

[0065] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, dry etching can be used to simultaneously etch the multilayer interlayer dielectric layer at the bottom of the first opening 1061 and the interlayer dielectric layer at the bottom of the second opening 1062, forming a vertical contact hole 1071 in the device region and an irregularly shaped contact hole 1072 in the sealing ring region. The gas used for dry etching is, for example, a mixture of fluorocarbon gases such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), and octafluorocyclobutane (C4F8), oxygen (O2), hydrogen (H2), and inert gases. When etching each interlayer dielectric layer, the specific etching gas can be selected or the proportion of the etching gas can be adjusted according to the material of the interlayer dielectric layer.

[0066] Please see Figures 5 to 9 As shown, in one embodiment of the present invention, step S130, etching a portion of the multilayer interlayer dielectric layer around the vertical contact hole, forming a trench on the side of the vertical contact hole away from the bottom metal layer, and forming a through hole 1073 on the side of the vertical contact hole close to the bottom metal layer, specifically includes steps S131 to S133.

[0067] Step S131: Fill the bottom layer into the vertical contact hole and the irregular contact hole, and then etch the bottom layer back.

[0068] Please see Figure 6 and Figure 7As shown, in one embodiment of the present invention, after forming the vertical contact hole 1071 and the irregularly shaped contact hole 1072, a bottom layer 108 is filled into the vertical contact hole 1071 and the irregularly shaped contact hole 1072 until the bottom layer 108 covers the vertical contact hole 1071 and the irregularly shaped contact hole 1072. The material of the bottom layer 108 is a photoresist material with good flowability, such as liquid photoresist, spin-on glass (SOG), or highly adhesive photoresist. Since the radial dimension of the irregularly shaped contact hole 1072 is larger than the radial dimension of the vertical contact hole 1071, when the bottom layer 108 covers the vertical contact hole 1071 and the irregularly shaped contact hole 1072, the height of the bottom layer 108 on the device region is higher than the height of the bottom layer 108 in the sealing ring region.

[0069] Please see Figure 6 and Figure 7 As shown, in one embodiment of the present invention, a bottom layer 108 is filled into the vertical contact hole 1071 and the irregular contact hole 1072, and the bottom layer 108 is etched back to reduce the thickness of the bottom layer 108 in the vertical contact hole 1071 and the irregular contact hole 1072. This application does not specifically limit the thickness of the bottom layer 108 in the vertical contact hole 1071 and the irregular contact hole 1072, ensuring that when the multilayer interlayer dielectric layer surrounding the vertical contact hole 1071 is subsequently etched to form a trench 1074, the etched multilayer interlayer dielectric layer is flush with the bottom layer 108 and remains at the etch stop layer 103.

[0070] Step S132: Form a second patterned photoresist layer, which exposes the vertical contact hole and a portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole.

[0071] Please see Figure 8 As shown, in one embodiment of the present invention, photoresist can be spin-coated onto the anti-reflective layer 105 and the bottom layer 108 first, and then the photoresist can be exposed and developed to form a second patterned photoresist layer 109. In this application, the second patterned photoresist layer 109 covers the sealing ring region, exposing only the vertical contact hole 1071 and a portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole 1071. The size of the portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole 1071 exposed by the second patterned photoresist layer 109 is set according to the size of the trench 1074 to be formed.

[0072] Step S133: Using the second patterned photoresist layer as a mask, simultaneously etch the bottom layer inside the vertical contact hole and part of the multilayer interlayer dielectric layer around the vertical contact hole, forming a trench on the side of the vertical contact hole away from the bottom metal layer, and forming a through hole on the side of the vertical contact hole close to the bottom metal layer.

[0073] Please see Figure 8 and Figure 9 As shown, in one embodiment of the present invention, after forming the second patterned photoresist layer 109, the bottom layer 108 inside the vertical contact hole 1071 and a portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole 1071 are simultaneously etched, and the etched bottom layer 108 and the portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole 1071 stop within the etching stop layer 103. At this time, the radial dimension of the side of the vertical contact hole 1071 away from the bottom metal layer 100 increases, forming a trench 1074. Meanwhile, the radial dimension of the side of the vertical contact hole 1071 closer to the bottom metal layer 100 remains unchanged, forming a through hole 1073.

[0074] Please see Figure 8 and Figure 9 As shown, in one embodiment of the present invention, a dry etching process is used to simultaneously etch the bottom layer 108 within the vertical contact hole 1071 and a portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole 1071. The gas used for dry etching is, for example, a mixture of fluorocarbon gases such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), and octafluorocyclobutane (C4F8), oxygen (O2), hydrogen (H2), and inert gases. When etching each interlayer dielectric layer, the specific etching gas can be selected or the proportion of the etching gas can be adjusted according to the material of the interlayer dielectric layer.

[0075] Step S134: Remove the bottom layer inside the through holes and irregularly shaped contact holes.

[0076] Please see Figure 8 and Figure 9 As shown, in one embodiment of the present invention, during the etching of trench 1074, the bottom layer 108 in trench 1074 is etched away. After trench 1074 is formed, the bottom layer 108 in through hole 1073 and irregular contact hole 1072 is removed. The method for removing the bottom layer 108 can be determined according to its material; dry stripping methods such as oxygen plasma ashing or reactive gas can be used, or wet stripping methods using organic solvents or alkaline solutions can be used.

[0077] Please see Figure 9 and Figure 10As shown, in one embodiment of the present invention, after etching a portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole 1071 to form a trench 1074, the top of the multilayer interlayer dielectric layer is simultaneously etched, making the adjacent irregularly shaped contact holes 1072 connected. Specifically, a dry etching process is used to simultaneously etch the surface of the multilayer interlayer dielectric layer, the bottom of the trench 1074, the bottom of the via 1073, and the bottom of the irregularly shaped contact hole 1072, so that the nitrogen-doped carbon layer 101 at the bottom of the via 1073 and the irregularly shaped contact hole 1072 is completely etched away, and the via 1073 and the irregularly shaped contact hole 1072 are connected to the underlying metal layer 100. At this time, the anti-reflective layer 105 in the multilayer interlayer dielectric layer is etched away, and a portion of the thickness of the second dielectric layer 104 is also etched away. Because the spacing between the multiple interlayer dielectric layers between the irregularly shaped contact holes 1072 is small, the etching rate of these interlayer dielectric layers is faster. This results in the interlayer dielectric layers between adjacent irregularly shaped contact holes 1072 being lower than the irregularly shaped contact holes 1072, thus enabling communication between adjacent irregularly shaped contact holes 1072. The etching stop layer 103 at the bottom of the through hole 1073 is also etched away, ultimately leaving the bottom of the through hole 1073 as the first dielectric layer 102.

[0078] Please see Figure 9 and Figure 10 As shown, in one embodiment of the present invention, when using a dry etching process to simultaneously etch the surface of multiple interlayer dielectric layers, the bottom of trench 1074, the bottom of via 1073, and the bottom of irregular contact via 1072, the gas used for dry etching is, for example, a mixture of fluorocarbon gases such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), and octafluorocyclobutane (C4F8), oxygen (O2), hydrogen (H2), and inert gases. When etching each interlayer dielectric layer, the specific etching gas can be selected or the proportion of the etching gas can be adjusted according to the material of the interlayer dielectric layer.

[0079] Please see Figure 11 and Figure 12 As shown, in one embodiment of the present invention, after simultaneously etching the top of the multilayer interlayer dielectric layer to connect adjacent irregularly shaped contact holes 1072, a conductive material layer 110 is deposited in the through-hole 1073, the trench 1074, and the irregularly shaped contact holes 1072. The conductive material layer 110 in the through-hole 1073 and the trench 1074 forms a damascus structure 1101, and the conductive material layer 110 in the irregularly shaped contact hole 1072 forms a sealing ring 1102, and adjacent sealing rings 1102 are connected. The conductive material is, for example, copper.

[0080] Please see Figure 12As shown, the semiconductor structure formed in this application includes: a multilayer interlayer dielectric layer disposed on the bottom metal layer 100; a via 1073, formed by etching the multilayer interlayer dielectric layer of the device region to create a vertical contact hole 1071, wherein the vertical contact hole 1071 is located on the side closer to the bottom metal layer 100; a trench 1074, formed by etching a portion of the multilayer interlayer dielectric layer surrounding the vertical contact hole 1071, on the side of the vertical contact hole 1071 away from the bottom metal layer 100; and an irregularly shaped contact hole 1072, which... A multilayer interlayer dielectric layer in the etched sealing ring region forms an irregularly shaped contact hole 1072. The radial dimension of the irregularly shaped contact hole 1072 decreases with increasing depth, and adjacent irregularly shaped contact holes 1072 are interconnected. A conductive material layer 110 is disposed within the through hole 1073, the trench 1074, and the irregularly shaped contact hole 1072. The conductive material layer 110 in the through hole 1073 and the trench 1074 forms a damascus structure 1101, and the conductive material layer 110 within the irregularly shaped contact hole 1072 forms a sealing ring 1102, with adjacent sealing rings 1102 interconnected. For details on the semiconductor structure, please refer to [reference needed]. Figures 2 to 11 The method for forming the semiconductor structure is shown.

[0081] In summary, the present invention provides a method for fabricating a semiconductor structure, a semiconductor structure, and an integrated circuit. The method for fabricating the semiconductor structure includes the following steps: depositing multiple interlayer dielectric layers on a bottom metal layer; etching the multiple interlayer dielectric layers to form vertical contact holes in the device region and irregularly shaped contact holes in the sealing ring region, wherein the radial dimension of the irregularly shaped contact holes decreases with increasing depth; etching a portion of the multiple interlayer dielectric layers surrounding the vertical contact holes to form a trench on the side of the vertical contact holes away from the bottom metal layer and a through hole on the side of the vertical contact holes close to the bottom metal layer; simultaneously etching the top of the multiple interlayer dielectric layers to connect adjacent irregularly shaped contact holes; and depositing conductive material layers in the through holes, the trenches, and the irregularly shaped contact holes, wherein the conductive material layers in the through holes and the trenches form a damascus structure, and the conductive material layers in the irregularly shaped contact holes form sealing rings, wherein adjacent sealing rings are connected. The present invention provides a method for fabricating a semiconductor structure, a semiconductor structure, and an integrated circuit. An unexpected effect is that by setting the contact holes within the sealing ring region as irregularly shaped contact holes, a multi-layered, interconnected sealing ring can be formed during the subsequent removal of the anti-reflective layer and part of the second dielectric layer. Therefore, after forming the vertical contact holes and the irregularly shaped contact holes, only the vertical contact holes in the device region need to be etched during the second exposure etching. At this point, only the thickness of the underlying layer formed in the device region needs to be adjusted according to the etching amount of the vertical contact holes in the device region, thereby avoiding the occurrence of secondary trenches or fence defects due to the inability to simultaneously adjust the thickness of the underlying layers in both the device region and the sealing ring region. Since only the vertical contact holes need to be etched during the second exposure etching, the process difficulty of trench etching can be reduced. Furthermore, compared to a vertical sealing ring, the irregularly shaped sealing ring formed in this application has a higher metal thickness, enhancing the sealing ring's isolation capability and extending the stability and lifespan of the formed chip.

[0082] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The semiconductor structure includes a device region and a seal ring region, and the manufacturing method includes at least the following steps: a plurality of interlayer dielectric layers are disposed on a bottom metal layer; the plurality of interlayer dielectric layers are etched to form a vertical contact hole in the device region and a profiled contact hole in the seal ring region, and a radial dimension of the profiled contact hole decreases with an increase in depth; a portion of the plurality of interlayer dielectric layers around the vertical contact hole is etched to form a trench on a side of the vertical contact hole away from the bottom metal layer and a via on a side of the vertical contact hole close to the bottom metal layer; the top of the plurality of interlayer dielectric layers is etched synchronously to make adjacent profiled contact holes communicate; and a layer of conductive material is deposited in the via, the trench and the profiled contact hole, the layer of conductive material in the via and the trench forms a damascene structure, the layer of conductive material in the profiled contact hole forms a seal ring, and adjacent seal rings communicate.

2. The method of fabricating a semiconductor structure of claim 1, wherein, The plurality of interlayer dielectric layers include a nitrogen-doped carbon layer, a first dielectric layer, an etching stop layer, a second dielectric layer and an anti-reflection layer stacked in sequence, and in forming the vertical contact hole and the profiled contact hole, the anti-reflection layer, the second dielectric layer, the etching stop layer, the first dielectric layer and a portion of the nitrogen-doped carbon layer are etched in sequence to form the vertical contact hole in the device region and the profiled contact hole in the seal ring region.

3. The method of fabricating a semiconductor structure of claim 2, wherein, The vertical contact hole and the profiled contact hole extend into the nitrogen-doped carbon layer to a dimension equal to one third to two thirds of a thickness of the nitrogen-doped carbon layer.

4. The method of fabricating a semiconductor structure of claim 1, wherein, A sidewall of the profiled contact hole is inclined or the sidewall of the profiled contact hole is arc-shaped inwardly or outwardly.

5. The method of fabricating a semiconductor structure of claim 1, wherein, In forming the profiled contact hole, a spacing between adjacent profiled contact holes at a top of the profiled contact hole is less than one half of a radial dimension of the vertical contact hole.

6. The method of fabricating a semiconductor structure of claim 1, wherein, Forming the trench and the via includes the following steps: a bottom layer is filled in the vertical contact hole and the profiled contact hole, and the bottom layer is etched back; a second patterned photoresist layer is formed, the second patterned photoresist layer exposes the vertical contact hole and a portion of the plurality of interlayer dielectric layers around the vertical contact hole; the bottom layer in the vertical contact hole and the portion of the plurality of interlayer dielectric layers around the vertical contact hole are etched synchronously with the second patterned photoresist layer as a mask to form the trench on a side of the vertical contact hole away from the bottom metal layer and the via on a side of the vertical contact hole close to the bottom metal layer.

7. The method of fabricating a semiconductor structure of claim 6, wherein, In etching the portion of the plurality of interlayer dielectric layers around the vertical contact hole to form the trench, the etched plurality of interlayer dielectric layers and the bottom layer are flush and stop at the etching stop layer.

8. The method of fabricating a semiconductor structure of claim 1, wherein, Synchronously etching the top of the plurality of interlayer dielectric layers includes synchronously etching a surface of the plurality of interlayer dielectric layers, a bottom of the trench, a bottom of the via and a bottom of the profiled contact hole using a dry etching process, so that the nitrogen-doped carbon layer at the bottom of the via and the profiled contact hole is etched completely.

9. A semiconductor structure, characterized by The semiconductor structure includes a device region and a seal ring region, and the semiconductor structure further includes at least: a plurality of layers of interlayer dielectric layers disposed on a bottom metal layer; a via formed by etching the plurality of layers of interlayer dielectric layers of the device region to form a vertical contact hole, and the vertical contact hole forms the via on a side proximate to the bottom metal layer; a trench formed by etching a portion of the plurality of layers of interlayer dielectric layers surrounding the vertical contact hole to form the trench on a side of the vertical contact hole distal to the bottom metal layer; a shaped contact hole formed by etching the plurality of layers of interlayer dielectric layers of the seal ring region, the shaped contact hole having a radial dimension that decreases with depth, and adjacent shaped contact holes are in communication; and a layer of conductive material disposed within the via, the trench, and the shaped contact hole, and the layer of conductive material in the via and the trench forms a damascene structure, the layer of conductive material within the shaped contact hole forms a seal ring, and adjacent seal rings are in communication.

10. An integrated circuit, characterized by A semiconductor structure as in claim 9.

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