Multi-type chip stacking packaging structure and manufacturing method

Abstract

The invention discloses a multi-type chip stacking packaging structure and a manufacturing method, and the manufacturing method comprises the steps: carrying out the area sorting of pre-stacked packaging chips, selecting a first packaging chip in a sorting result as a first chip, carrying out the compatible pin layout design of the first chip, and obtaining a substrate chip of a preset pin; taking other packaged chips lower than the first chips in the sorting result as second chips, and laying the plurality of second chips on the surface of the substrate chip to obtain a chip assembly; connecting the pins of the second chips with the micro bumps of the first chip in an aligned manner according to preset pins to obtain a multi-layer stacked structure; and carrying out integral packaging and plastic packaging molding on the multi-layer stacked structure to obtain the multi-type chip stacked packaging structure. By omitting an adapter plate and adopting a staggered stacking mode, the signal transmission path is remarkably shortened, and the technical problems of low signal transmission efficiency and insufficient reliability of a packaging structure caused by the adapter plate in the prior art are effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chip stacking, and in particular to a multi-type chip stacking package structure and a manufacturing method. BACKGROUND

[0002] In modern electronic devices, multi-type chip stacking package structures are widely used in the semiconductor industry. In the prior art, in order to realize the integration of different types of chips, a method of arranging a conversion board on a substrate is usually adopted to connect and stack multiple chips through the conversion board.

[0003] However, the stacking package structure relying on the conversion board in the prior art has a core technical problem, that is, it is difficult to balance the signal transmission efficiency and the reliability of the package structure while achieving high integration. Although the use of the conversion board facilitates the layout and connection of the chips, the additional level and complexity introduced by the conversion board often lead to a longer signal transmission path, thereby reducing the signal transmission efficiency, and the mechanical strength and thermal stability of the conversion board are insufficient, which can easily cause reliability problems in long-term use.

[0004] Specifically, in the prior art, the conversion board serves as an intermediate structure between the chips and the substrate, and its main function is to provide electrical connection and physical support. However, in order to realize the stacking of multiple types of chips, designers need to add complex wiring and connection points on the conversion board, which not only increases the delay of signal transmission, but also can cause signal interference and crosstalk problems due to the high density of wiring. The prior art solves this problem by enhancing the mechanical strength and thermal stability of the conversion board, such as by increasing the material thickness or using high-strength composite materials, but this will lead to an increase in the volume of the conversion board, which is contrary to the goal of high integration and miniaturization. Therefore, when the prior art realizes the stacking of multiple types of chips through the conversion board, it is difficult to balance the signal transmission efficiency and the reliability of the package structure, and solving one problem often leads to the exacerbation of the other problem. SUMMARY

[0005] The purpose of the present application is to provide a multi-type chip stacking package structure and a manufacturing method, which solves the technical problem that the prior art is difficult to balance the signal transmission efficiency and the reliability of the package structure while achieving high integration. To achieve this purpose, the present application adopts the following technical solution: A manufacturing method of a multi-type chip stacking package structure, comprising: sequentially arranging pre-stacked package chips by area, selecting a package chip with the first area in the sorting result as a first chip, and performing compatible pin layout design on the first chip to obtain a base chip with preset pins; arranging multiple second chips, which are other package chips in the sorting result and have an area smaller than the first chip, on the surface of the base chip to obtain a chip combination. According to the preset pin, the pins of each second chip are connected with the micro bumps of the first chip in a one-to-one manner to obtain a multi-layer stacked structure; The multi-layer stacked structure is integrally packaged and molded to obtain a multi-type chip stacked packaging structure.

[0006] Further, the step of sorting the pre-stacked packaging chips by area includes: The size of the plurality of chips to be packaged is measured, and the area is calculated according to the measurement result to obtain a chip area list; The chip area list is sorted in descending order, and the chips are functionally screened according to the sorting result to obtain a candidate base chip set; The compatibility of the candidate base chip set is verified, and the chip area list is updated according to the verification result to obtain a sorting result.

[0007] Further, the step of selecting the first packaging chip in the sorting result as the first chip and performing compatible pin layout design on the first chip to obtain a base chip with preset pins includes: The first packaging chip in the sorting result is selected as the first chip, and the pin requirements of the first chip are functionally classified and analyzed to obtain a pin function allocation table; According to the pin function allocation table, the first chip is regionally divided and modularly laid out and designed to obtain an initial pin layout diagram; According to the initial pin layout diagram, a plurality of layers of high-conductivity copper material are deposited on the silicon wafer of the first chip to form a pin array structure corresponding to the initial pin layout diagram, and a pin array base is generated; Copper or gold micro bumps are electroplated at the preset positions of the pin array base to obtain a base chip with preset pins.

[0008] Further, the step of selecting other packaging chips lower than the first chip in the sorting result as second chips and arranging a plurality of second chips on the surface of the base chip to obtain a chip combination includes: According to the preset functional requirements, the second chips lower than the first chip in the sorting result are functionally classified and screened to obtain a functionally grouped chip set; According to the functionally grouped chip set, the surface of the base chip is partitioned and planned to obtain a partitioned base chip; According to the functional area division of the partitioned base chip, the second chips in the functionally grouped chip set are attached to the first chip in a one-to-one manner to obtain a chip combination.

[0009] Further, the step of connecting the pins of each second chip with the micro bumps of the first chip in a one-to-one manner according to the preset pins to obtain a multi-layer stacked structure includes: Processing a vertical through hole in the pin area of the second chip, and performing preliminary position matching between the vertical through hole and the micro bumps of the first chip to obtain a pre-alignment chip combination; Performing thermal compression bonding treatment on the pre-alignment chip combination, so that the vertical through hole of the second chip and the micro bumps of the first chip form an electrical connection through metal diffusion to obtain a preliminary connection multilayer structure; Performing low-temperature annealing treatment on the preliminary connection multilayer structure to obtain the multilayer stacked structure.

[0010] Further, the step of integrally packaging and plastic encapsulating the multilayer stacked structure to obtain the multi-type chip stacked packaging structure comprises: Injecting low dielectric constant epoxy resin into the gap between the first chip and the second chip under vacuum environment, and performing preliminary curing under low-temperature baking condition to obtain a filled stable structure; Performing surface leveling treatment on the filled stable structure, uniformly coating the packaging layer material on the outside of the chip assembly, forming a packaging layer through molding process to obtain the multi-type chip stacked packaging structure.

[0011] Further, after the step of integrally packaging and plastic encapsulating the multilayer stacked structure, the step further comprises: Scanning the micro bump connection points between the first chip and the second chip, and screening out structures in which all connection points meet the preset geometric and electrical connection standards to obtain a preliminary inspection qualified structure; Applying a multi-frequency pulse signal to the preset pins between the first chip and the second chip to obtain structures in which the signal transmission quality meets the preset threshold to obtain an electrical verification structure; Performing multi-temperature zone thermal cycle stress test on the electrical verification structure to obtain the multi-type chip stacked packaging structure.

[0012] The application also discloses a multi-type chip stacked packaging structure, comprising: a substrate; a chip assembly comprising a plurality of different types of packaging chips, the packaging chips comprising at least a first chip and a second chip, a plurality of the second chips being tiled on the first chip and being connected to each other by a connecting line, wherein the area of the first chip is larger than that of the second chip, and there is a gap between adjacent second chips; a packaging layer wrapped outside the chip assembly. Further, the connecting line is one of a pure gold wire, a copper wire, an aluminum wire or an alloy wire.

[0013] Further, the package chip further comprises a third chip stacked on the second chip and connected with the second chip and / or the first chip through a connecting line.

[0014] Compared with the prior art, the present application has the following beneficial effects: The multi-type chip stacked package structure and the manufacturing method thereof of the present application directly set the chip assembly on the substrate, use the first chip with a larger area as the bearing basis, and stack multiple second chips with smaller areas on the first chip in a staggered manner, realize mutual connection through connecting lines, leave gaps between adjacent second chips, and wrap them with a packaging layer, effectively solving the technical problems of low signal transmission efficiency and insufficient reliability of the packaging structure caused by the dependence on the adapter in the prior art. Compared with the complex structure of chip connection and stacking through the adapter in the prior art, the present application significantly shortens the signal transmission path, reduces the risk of signal delay and crosstalk, and thus greatly improves the signal transmission efficiency. The staggered stacking design reasonably distributes multiple second chips on the first chip, not only optimizes the space utilization, realizes higher integration, but also effectively improves heat dissipation and stress distribution, enhances the thermal stability and mechanical strength of the packaging structure. The staggered stacking method of the present application simplifies the manufacturing process, reduces the steps of complex wiring and adapter processing, reduces the production cost, and at the same time maintains the advantages of miniaturization and high integration. This design not only realizes efficient integration of multiple types of chips, but also takes into account the efficiency of signal transmission and the long-term reliability of the packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0016] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and are not used to limit the conditions that can be implemented by the present application, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0017] Figure 1 The overall steps of the manufacturing method of the multi-type chip stacked package structure are shown in the following figure: Figure 2It is a side view and a sectional view of a multi-type chip stack packaging structure; Figure 3 It is a metal frame structure diagram of a multi-type chip stack packaging structure; Figure 4 It is a packaging chip structure diagram of a multi-type chip stack packaging structure.

[0018] Among them, the reference signs are: 1, first chip; 2, second chip; 3, substrate; 11, wafer; 12, metal frame; 13, silver paste; 14, plastic sealing area; 15, connecting line. DETAILED DESCRIPTION

[0019] In order to make the purposes, features and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described below are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0020] In the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation of the present application. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there can be a component disposed therebetween.

[0021] The technical solutions of the present application will be further described below in conjunction with the drawings and through specific embodiments.

[0022] Reference Figure 1 A manufacturing method of a multi-type chip stack packaging structure, comprising: S1: sorting the pre-stacked packaging chips by area, selecting the first packaging chip in the sorting result as a first chip, and performing compatible pin layout design on the first chip to obtain a base chip with a preset pin; In step S1, the pre-stacked chips include multiple types of chips, such as processors (e.g., CPUs or GPUs), memories (e.g., DRAMs or SRAMs), application-specific integrated circuits (ASICs), etc., which differ in functionality, size, and pin requirements. The purpose of area sorting is to determine which chip has the largest physical size, as the largest-sized chip typically has sufficient surface space to serve as a base chip to carry other smaller-sized chips. The sorting process can be achieved by measuring the physical dimensions (length x width) of the chips, for example, using high-precision optical measurement equipment or design software to extract the size data of the chips. A compatible pin layout design is performed for the first chip, aiming to design a pin layout for the base chip that is compatible with multiple second chips (i.e., other chips with smaller areas) to enable subsequent stacking and connection. The compatible pin layout design is to analyze the pin requirements of all the chips to be packaged, including signal pins (for data transmission), power pins (to provide operating voltage), and ground pins (to ensure circuit stability). Taking chip A (processor) as an example, it is assumed to require 200 signal pins, 50 power pins, and 50 ground pins, while chip B (memory) requires 100 signal pins, 30 power pins, and 20 ground pins, and chip C (ASIC) requires 150 signal pins, 40 power pins, and 30 ground pins. By analyzing these requirements, the maximum number and types of pins that the base chip needs to support can be determined. During design, simulation software (e.g., Cadence or Synopsys) is typically used to classify the pin functions, generating a unified pin assignment diagram that divides the pins into general signal areas, power areas, and ground areas, ensuring that the pin layout of the base chip can match the requirements of all second chips. For example, the general signal area can be designed to support differential signal pairs for high-speed data transmission, the power area needs to provide stable voltage supply, and the ground area is used to reduce electromagnetic interference. The pin layout adopts a modular design, i.e., dividing the pin areas into several functional modules, each module targeting specific signal or power requirements. For example, the general signal area can be designed to support multiple communication protocols (e.g., PCIe or DDR) to accommodate the signal transmission requirements of different chips; the power area needs to consider the operating voltages (e.g., 1.2V or 3.3V) of different chips, providing flexible power distribution through multiple metal interconnection layers. The pins themselves use micro-bump technology, with diameters controlled below 50 microns to achieve high-density connection. The micro-bumps can be made of highly conductive materials (e.g., copper or gold) with an anti-oxidation coating (e.g., nickel-gold composite layer) applied to the surface to improve long-term reliability. The pin pitch is also optimized during design, typically controlled below 100 microns to avoid signal crosstalk and electromagnetic interference. In the actual manufacturing process, multiple metal interconnection layers are deposited on a silicon wafer to form a pin network. These interconnection layers are patterned through photolithography technology to ensure the positions of the micro-bumps match the design Figure 1The micro-bumps are formed by depositing copper or gold material through an electroplating process. The wafer surface is also deposited with a thin insulating layer (such as SiO2) to protect the pins and prevent short circuits. The resulting base chip will have a high-precision pin array.

[0023] S2: The other packaging chips below the first chip in the sorting result are taken as second chips, and the plurality of second chips are arranged on the surface of the base chip to obtain a chip combination; In step S2, the second chips are packaging chips below the first chip in the area sorting result, and the areas of these chips are smaller than that of the base chip, such as processors, memories, sensors, or other application-specific integrated circuits. The diversity of these chips requires that the process of arranging the second chips needs to consider functionality and compatibility in layout design to ensure that the subsequent pin connection can be efficiently and reliably implemented. In actual operation, through a pre-programmed coordinate system, the pins of the second chips are accurately aligned with the micro-bumps on the surface of the base chip according to the pin layout designed in step S1. In the specific implementation of arranging the second chips, the base chip serves as a carrier platform, and the surface of the base chip usually has a pre-designed micro-bump array. After the chip is attached, X-ray detection is performed to check the integrity of the solder joints. In addition, the arrangement of the second chips also needs to consider the spacing between the chips and the heat management problem. Since the second chips may have different functions and power consumption characteristics, the spacing between the chips needs to be accurately calculated to avoid excessive layout that leads to heat accumulation or signal crosstalk. At the same time, the surface of the base chip may be pre-coated with a thin layer of conductive adhesive or flux to enhance the initial adhesion of the second chips to the micro-bumps.

[0024] S3: Aligning and connecting the pins of each second chip with the micro-bumps of the first chip according to the pre-set pins to obtain a multi-layer stacked structure; In step S3, the pins of the second chips are accurately aligned and connected with the micro-bumps of the first chip. In the process of aligning and connecting the pins with the micro-bumps, vertical conductive paths are formed in the chips to realize the transmission of interlayer signals and power. These holes are then filled with high-conductivity materials such as copper to ensure low resistance and high signal transmission efficiency. In actual operation, the pins of the second chips are aligned with the micro-bumps of the first chip, and the micro-bumps are located at the pre-set pin positions of the first chip, serving as the interface for interlayer connection. After alignment, the connection process can be achieved through thermal compression bonding technology, which is a process of pressing the chips under specific temperature and pressure. The specific parameters need to be optimized according to the characteristics of the chip material and the micro-bumps. According to the function and heat management requirements of the chips, high-power chips are preferably placed close to the base chip. The base chip usually has a larger area and better heat dissipation path, such as through the connection to the external heat sink or the heat conduction channel on the substrate, which can effectively manage the heat generated by high-power chips.

[0025] S4: integrally packaging and molding the multi-layer stacked structure to obtain a multi-type chip stacked packaging structure.

[0026] In step S4, the goal of integrally packaging and molding is to comprehensively protect and fix the multi-layer stacked structure formed in step S3 (i.e., the combination of the first chip and the plurality of second chips connected by the pin and micro-bump alignment) to form the final multi-type chip stacked packaging structure. Low dielectric constant epoxy resin is used as the filling material to fill the gaps between the chips, thereby enhancing the electrical stability of the entire stacked structure. The epoxy resin also has good adhesion and mechanical strength, which can effectively fix the chip position during the filling process and prevent displacement due to vibration or thermal expansion in subsequent use. After completing the gap filling, a protective layer is formed on the outside of the multi-layer stacked structure to isolate the external environment and further enhance the structural stability. During the molding process, a molding technique is used to form a protective layer on the top of the stacked structure. The stacked structure is placed in a mold, liquid epoxy resin or other molding material is injected, and then the material is solidified by heating and pressurizing. In order to further optimize the thermal management performance of the stacked structure, a process of adding heat sinks at the bottom of the largest chip substrate (i.e., the first chip) is also included. The selection and design of heat sinks are particularly important for high-performance chips, as the multi-type chip stacked structure generates a large amount of heat during operation, which can lead to performance degradation or even chip damage if not effectively dissipated. The heat sink material is made of high thermal conductivity copper or aluminum to conduct heat from the chip substrate to the external environment. After encapsulation, tests are needed to verify the reliability and durability of the structure. Thermal cycle testing can be used, with test conditions of -40°C to 125°C and 1000 cycles. This test simulates the operating scenario of the chip in an extreme temperature environment to evaluate its thermal stability and mechanical reliability. For example, during the test, the encapsulated chip is placed in a thermal cycle test box, which is rapidly heated from -40°C to 125°C and then cooled down, repeating 1000 times, to observe whether there are cracks, delamination or electrical performance degradation. Through such tests, it can be ensured that the chip can withstand temperature changes and mechanical stress challenges in actual applications (such as smartphones, automotive electronics or servers). If the test results show that the structure is complete and the electrical performance is stable, it indicates that the packaging and molding process in step S4 has achieved the expected results.

[0027] In one embodiment, the step of area sorting the pre-stacked packaging chips includes: measuring the size of the plurality of chips to be packaged, calculating the area according to the measurement results to obtain a chip area list; sorting the chip area list in descending order, and selecting the chips according to the sorting results to obtain a candidate substrate chip set; The candidate base chip set is verified for compatibility, and the chip area list is updated according to a verification result to obtain a ranking result.

[0028] In the above embodiment, the dimensions of multiple chips to be packaged are measured to calculate the chip areas and generate a chip area list. In actual operation, high-resolution optical measurement equipment or laser scanners can be used to accurately measure the length and width of the chips. For example, assuming there are five chips to be packaged, A, B, C, D, and E, the length and width of each chip can be measured one by one. Assuming the measurement results show that the size of chip A is 10 mm x 8 mm, chip B is 12 mm x 10 mm, chip C is 8 mm x 6 mm, chip D is 15 mm x 12 mm, and chip E is 9 mm x 9 mm, the area of chip A is 80 mm², chip B is 120 mm², chip C is 48 mm², chip D is 180 mm², and chip E is 81 mm², calculated by the area formula (area = length x width). These area data are recorded and sorted into a chip area list. The chip area list is sorted in descending order, with the chip with the largest area at the top of the list, because in a multi-layer stacked packaging structure, the chip with the largest area is chosen as the base chip to provide sufficient physical support and pin layout space. Based on the area data in the above example, the chip area list is: D (180 mm²), B (120 mm²), E (81 mm²), A (80 mm²), C (48 mm²). Through a descending order sorting algorithm (such as bubble sort or quick sort), this arrangement order can be quickly obtained. In actual production, the sorting process is usually automatically completed by a computer program, such as writing a sorting script using Python or MATLAB, inputting the area data, and automatically outputting the descending order list. After sorting, the chips are screened according to their functions to determine which chips are suitable as base chips. For example, base chips usually need to have higher electrical performance, more pins, or specific functions (such as master control chips or storage chips). Assuming that chip D is a high-performance processor chip, chip B is a storage chip, chip E is a sensor chip, and chips A and C are auxiliary function chips, through function screening, it may be determined that chips D and B are more suitable as base chips due to their core functions and higher pin requirements, forming a candidate base chip set {D, B}. This screening process needs to be combined with the specific application scenario of the chips, for example, in the packaging of a 5G communication module, the master control chip is usually preferred over other auxiliary chips as the base. Compatibility verification is performed on the candidate base chip set to ensure that the candidate base chips can support the electrical and physical connections of other chips, and to check whether the pin layout, electrical performance, and thermal management capability of the candidate chips meet the requirements of the stacking structure. For example, for the candidate base chip set {D, B}, it needs to be verified whether the number and layout of the pins of chips D and B can effectively connect with the second chips in the subsequent stacking. Assuming that chip D has 200 pins and chip B has 150 pins, while the stacking structure requires at least 180 pins to support the connection requirements of all second chips, chip B may be excluded due to insufficient pins.The compatibility verification also includes checking whether the power consumption and heat output of the chip are within an acceptable range. For example, the electrical performance of chip D when used as a substrate can be simulated by circuit simulation software (such as Cadence or Synopsys) to verify whether it can stably support signal transmission of a multi-layer stacked structure. Thermal simulation analysis (such as using Ansys software) can evaluate the thermal distribution of chip D when running at high load to ensure that it will not affect the performance of other chips due to overheating. If chip D passes the compatibility verification, while chip B fails due to insufficient pins or other reasons, the chip area list is updated, chip D is determined as the first chip, and the remaining chips are rearranged in descending order of area to obtain the final sorting result: D (180 mm2), E (81 mm2), A (80 mm2), C (48 mm2).

[0029] In one embodiment, the step of selecting the package chip ranked first in the sorting result as the first chip and performing compatibility pin layout design on the first chip to obtain a substrate chip with preset pins includes: selecting the package chip ranked first in the sorting result as the first chip, and performing functional classification analysis on the pin requirements of the first chip to obtain a pin function allocation table; performing area division and modular layout design processing on the first chip according to the pin function allocation table to obtain an initial pin layout diagram; depositing a multi-layer high-conductivity copper material on the silicon wafer of the first chip according to the initial pin layout diagram to form a pin array structure corresponding to the initial pin layout diagram, and generating a pin array substrate; electroplating copper or gold micro-bumps at preset positions of the pin array substrate to obtain a substrate chip with preset pins.

[0030] In the above embodiment, the first packaged chip in the sorted result is selected as the first chip, and its pin requirements are functionally classified and analyzed to determine the functional requirements and pin allocation of the first chip in the stacked structure. Assuming that in the previous area sorting process, chip D is selected as the first chip due to its maximum area (e.g., 180 mm²), and it is a high-performance processor chip that needs to support multi-channel signal transmission and power supply. Functional classification analysis requires detailed analysis of the pin requirements of chip D, such as determining which pins are used for power supply (VCC, GND), signal input / output (I / O), clock signal, or high-speed data transmission interface (such as PCIe or DDR). In actual operation, pin function information can be extracted from chip design specifications or circuit schematics, and electronic design automation (EDA) tools (such as Cadence Allegro) can be used to generate a pin function allocation table. Based on the pin function allocation table, the first chip is regionally divided and modularly laid out, the chip surface is divided into different functional areas, and the physical layout of the pins is optimized to improve signal integrity and manufacturing efficiency. Based on the aforementioned pin function allocation table, the silicon wafer surface of chip D is divided into several regions, such as power supply area, signal area, and high-speed interface area. Regional division usually considers the electrical characteristics of the pins and the optimization of signal transmission paths. For example, power supply pins are usually arranged centrally or at the edge to ensure uniform current distribution, while high-speed signal pins need to be as short as possible to reduce signal delay and crosstalk. In actual operation, EDA tools can be used for modular layout design, and pin positions can be optimized by algorithms. For example, assuming that the silicon wafer of chip D is 15 mm x 12 mm, the central area can be divided into power and ground pin areas, the peripheral area can be arranged with I / O pins, and the corner positions can be placed with high-speed interface pins for easy connection with external circuit boards. Based on the initial pin layout, a multi-layer high-conductivity copper material is deposited on the silicon wafer of the first chip. First, a photolithography technique is used to form a photolithography pattern corresponding to the initial pin layout on the silicon wafer, then a copper seed layer is deposited, and then an electroplating process is used to thicken the copper layer to form a high-conductivity pin array structure. Each pin position in this structure corresponds to the layout, for example, power pins can be designed as larger pads to carry higher current, and signal pins can be designed as smaller pads to optimize space utilization. Copper or gold micro-bumps can be electroplated at predetermined positions on the pin array substrate. For example, for the 200 pins of chip D, the micro-bump positions can be defined by photolithography, and then gold micro-bumps can be deposited at each pin position using electroplating equipment. After electroplating, an X-ray detection device is used to check the quality of the micro-bumps to ensure that there are no voids or cracks, and a substrate chip with predetermined pins is obtained.

[0031] In an embodiment, the step of arranging the second chips lower than the first chip in the sorting result on the surface of the base chip to obtain a chip assembly includes: classifying and screening the second chips lower than the first chip in the sorting result according to preset functional requirements to obtain a functional grouping chip set; partitioning the surface of the base chip according to the functional grouping chip set to obtain a partitioned base chip; aligning and mounting the second chips in the functional grouping chip set with the first chip according to the functional area division of the partitioned base chip to obtain a chip assembly.

[0032] In this embodiment, the second chips lower than the first chip in the sorting result are classified and screened, and the preset functional requirements can include computing speed, storage capacity, communication capability, or specific signal processing functions, etc. Based on these requirements, the second chips can be classified, for example, some chips are classified into a functional group responsible for data processing, some other chips are classified into a functional group responsible for signal transmission, and some other chips can be classified into a functional group responsible for power management. After classification, the screening process further excludes chips that cannot meet the requirements in terms of performance or compatibility. For example, if a functional requirement requires the response time of a chip to be lower than a certain threshold, any second chip with a response time higher than the threshold will be excluded. Through such classification and screening, the functional grouping chip set obtained is an optimized chip set, each chip of which corresponds to a specific functional requirement. Based on the characteristics of the functional grouping chip set, the surface of the base chip is reasonably divided. The base chip is usually a larger chip or substrate responsible for carrying multiple second chips and the first chip, and its surface is divided into different functional areas. Based on the characteristics of the second chips, the grid division method can be used to correspond each area of the base chip to a functional grouping chip set. The partition planning also needs to consider the interconnection requirements between chips, such as the path length and delay of signal transmission, and the factors of thermal management. In order to optimize the partition, simulation tools can be introduced to evaluate the performance of different partition schemes, for example, through thermal simulation to ensure that the heat dissipation effect of the chips after partition is good, or through signal integrity analysis to ensure that the communication between the chips will not be disturbed. After multiple iterations and optimization, the partitioned base chip is a base with clear functional area division, and each area reserves appropriate space and electrical connection points for specific second chips or the first chip. According to the coordinate data of the partition planning, the second chips and the first chip are accurately placed in the specified areas of the base chip. In the mounting process, the pins or connection points of the chips need to be aligned with the pads or connection points on the base chip, and after mounting, electrical testing and functional verification are performed to ensure that each chip can work normally and the communication between the chips meets the design requirements, obtaining a chip assembly.

[0033] In an embodiment, the step of connecting the pins of each of the second chips with the micro bumps of the first chip according to the preset pins to obtain the multi-layer stacked structure comprises: processing vertical through holes in the pin area of the second chip, and preliminarily matching the vertical through holes with the micro bumps of the first chip to obtain a preliminarily matched chip combination; performing a thermal compression bonding process on the preliminarily matched chip combination, so that the vertical through holes of the second chip and the micro bumps of the first chip form an electrical connection through metal diffusion to obtain a preliminarily connected multi-layer structure; performing a low-temperature annealing process on the preliminarily connected multi-layer structure to obtain the multi-layer stacked structure.

[0034] In this embodiment, the second chip is processed in the pin area, forming high aspect ratio vertical vias on the silicon substrate, the size and position of these vias correspond to the micro bumps on the first chip. After the via formation, conductive material (such as copper or tungsten) is deposited on the inner wall of the via. After the via processing is completed, the second chip is preliminarily matched with the micro bumps of the first chip. During the alignment process, the chip surface can be coated with auxiliary alignment marks to improve the alignment accuracy. After the preliminary matching is completed, the second chip and the first chip form a pre-alignment chip combination. The pre-alignment chip combination is subjected to thermal compression bonding treatment, and by applying high temperature and pressure, the micro bumps and the conductive material in the via are subjected to metal atom diffusion, thereby forming a stable electrical connection. In specific implementation, the pre-alignment chip combination is placed in a thermal compression bonding device, and the bonding temperature is set between 200°C and 400°C, depending on the material of the micro bumps and the conductive material in the via (such as copper, tin or their alloys). In a high temperature environment, the micro bump material (such as copper or tin) and the conductive material on the inner wall of the via undergo atomic level diffusion to form intermetallic compounds, thereby achieving firm electrical and mechanical connections. After thermal compression bonding is completed, the vertical via of the second chip and the micro bump of the first chip form a preliminary electrical connection, and a preliminary connected multilayer structure is obtained. The preliminary connected multilayer structure is subjected to low temperature annealing treatment to eliminate residual stress introduced during thermal compression bonding, improve the microstructure of intermetallic compounds and enhance the reliability of electrical connection. In specific implementation, the preliminary connected multilayer structure is placed in an annealing furnace, and the annealing temperature is controlled between 100°C and 250°C, which is lower than the thermal compression bonding temperature, to avoid damage to the formed connection. During annealing, metal atoms further diffuse to fill possible small gaps at the bonding interface and release residual stress inside the chip caused by thermal compression. The annealing time is usually several minutes to several hours, depending on the structure size and material properties. To prevent oxidation, annealing is usually carried out in an inert gas (such as nitrogen) or vacuum environment. Low temperature annealing can also improve the crystal structure of intermetallic compounds, making them more uniform and stable, thereby improving the electrical performance and mechanical strength of the multilayer stacked structure. After annealing is completed, a multilayer stacked structure is obtained.

[0035] In an embodiment, the steps of integrally packaging and molding the multilayer stacked structure to obtain a plurality of chip stack packaging structures include: Injecting low dielectric constant epoxy resin into the gap between the first chip and the second chip in a vacuum environment, and preliminarily curing under low temperature baking conditions to obtain a stable filling structure; Performing surface leveling treatment on the stable filling structure to uniformly coat the packaging layer material on the outside of the chip assembly, forming a packaging layer through a molding process to obtain the plurality of chip stack packaging structures.

[0036] In this embodiment, low dielectric constant epoxy resin is injected into the gap between the first chip and the second chip in a vacuum environment to fill the chip gap and enhance the stability and electrical performance of the structure. The low dielectric constant epoxy resin can effectively reduce the signal interference between chips, and injection equipment such as vacuum injection equipment can be used to ensure that the epoxy resin can be uniformly and bubble-free filled into the tiny gap between the chips. The vacuum environment can avoid air being trapped in the gap to form bubbles. In actual operation, a suitable resin formulation is selected according to the size of the chip gap (usually in the micron level), and uniform filling is achieved through precise flow control and injection rate. After the gap is filled, preliminary curing is carried out under low-temperature baking conditions to obtain a filled stable structure. Low-temperature baking is carried out at a temperature range of 80°C to 120°C, and the specific temperature depends on the chemical properties and curing characteristics of the selected epoxy resin. The choice of low-temperature curing is to avoid thermal damage to sensitive elements inside the chip (such as metal interconnection lines or thin film layers) at high temperatures, while ensuring that the resin can gradually crosslink to form a uniform molecular structure. In actual process, this curing process can be carried out in a controllable oven, and the time range is between 30 minutes to 2 hours according to the curing curve of the resin. Surface leveling treatment is performed on the filled stable structure to ensure the flatness of the chip assembly surface. Polishing or plasma etching technology can be used to remove the resin overflow or surface unevenness that may occur during the filling process. In operation, a suitable polishing liquid and polishing pad are selected to avoid damage to the chip surface while maintaining high efficiency of the process. The encapsulation layer material is uniformly coated on the outside of the chip assembly, and a protective encapsulation layer is formed through the molding process to enhance the mechanical strength and environmental adaptability of the chip stacking structure. The encapsulation layer material can be selected as high-performance epoxy molding compound (EMC), which has excellent mechanical strength, heat resistance and moisture resistance, and can effectively protect the chip from the external environment. During the coating process, the encapsulation layer material is uniformly coated on the outside of the chip assembly through dispensing equipment such as dispensing machine or spraying equipment to ensure uniform thickness and no defects. After coating is completed, the molding process can use transfer molding or compression molding technology. Transfer molding injects preheated molding compound into the mold cavity, allowing it to flow and fill the mold under high temperature and pressure, and finally forms a solid encapsulation layer; compression molding places the molding compound directly in the mold and applies pressure to form a uniform encapsulation layer around the chip assembly, resulting in a multi-type chip stacking package structure with high reliability, excellent electrical performance and good mechanical strength.

[0037] In an embodiment, after the step of integrally encapsulating and molding the multi-layer stacking structure, the method further comprises: Scanning the micro-bump connection points between the first chip and the second chip to screen out structures that meet the preset geometric and electrical connection standards, and obtaining a preliminary inspection qualified structure; A multi-frequency pulse signal is applied to a preset pin between the first chip and the second chip, a structure with a signal transmission quality meeting a preset threshold is obtained, and an electrical verification structure is obtained; The electrical verification structure is subjected to a multi-temperature zone thermal cycle stress test, and the multi-type chip stack package structure is obtained.

[0038] In this embodiment, the micro-bump connection points between the first chip and the second chip are scanned. A detection device, such as an X-ray detection system or an optical microscope combined with image processing technology, can be used to non-destructively scan the micro-bump connection points. During the scanning process, the detection device checks the geometric parameters of each micro-bump, such as diameter, height, and spacing from adjacent bumps, to ensure they meet the design specifications. At the same time, an electrical test probe measures the resistance value of the connection points to ensure it is below a pre-set threshold, verifying the integrity of the electrical connection. The scanning data is compared with pre-set standards to screen out structures where all micro-bumps meet the requirements and eliminate stacked structures with defects (such as bump deformation, fracture, or poor contact). The structures that pass the initial inspection are obtained. After obtaining the structures that pass the initial inspection, a multi-frequency pulse signal is applied to the pre-set pins between the first chip and the second chip to verify the reliability and stability of signal transmission between chips, ensuring the performance of the stacked structure in actual working scenarios. In specific implementation, the pre-set pins for testing are determined according to chip design, and a signal generator is used to apply a multi-frequency pulse signal to these pins. The frequency range of the signal needs to cover the low, medium, and high frequency working scenarios that the chip may encounter in actual application, such as from tens of kilohertz to several gigahertz. During the application of the pulse signal, the transmission quality of the signal is monitored, including parameters such as signal integrity, attenuation degree, noise level, and time delay. For example, an oscilloscope or a vector network analyzer can be used to measure the eye diagram quality and bit error rate of the signal to evaluate whether the signal transmission meets the pre-set threshold requirements. Different amplitude and duty cycle pulse signals can be applied during the test process to comprehensively evaluate the dynamic response capability of the interconnection between chips. When the signal transmission quality of all test pins meets the pre-set standard, the electrical verification structure is determined. The electrical verification structure is subjected to multi-temperature zone thermal cycle stress testing. The electrical verification structure is placed in a thermal cycle test device, and multiple temperature zones are controlled, such as a low temperature zone (e.g., -40°C), a normal temperature zone (25°C), and a high temperature zone (125°C or higher). During the test, the structure undergoes multiple rapid cycles from low temperature to high temperature, and the duration and temperature gradient of each cycle are set according to specific application scenarios and industry standards (such as JEDEC standards). During the thermal cycle test, the stacked structure is subjected to mechanical stress caused by thermal expansion and contraction, which may cause fatigue, cracking, or other failure phenomena of the micro-bump connection points. Therefore, the test device checks whether the micro-bump connection points have physical damage or electrical performance degradation through real-time monitoring or post-test analysis. For example, the structure after the test can be evaluated again using X-ray detection or electrical test probes to confirm whether its geometric and electrical properties still meet the initial standards. The structures that pass all thermal cycle stress tests are determined as the final qualified multi-category chip stacked package structure, which is suitable for subsequent mass production or application.

[0039] It is worth noting that all the devices described in the present application can be realized by the prior art, the algorithms described are based on mature algorithms of the prior art, and the chemical substances and conditions used in the preparation process are within the safe range and will not harm the operators or the environment.

[0040] Reference Figures 2 to 4 The present application provides a multi-type chip stack packaging structure, comprising: a substrate; a chip assembly comprising a plurality of different types of packaging chips, the packaging chips at least comprising a first chip and a second chip, a plurality of the second chips being tiled on the first chip and connected to each other by connecting lines, wherein the area of the first chip is greater than that of the second chip, and there is a gap between adjacent second chips; a packaging layer wrapped outside the chip assembly.

[0041] In this embodiment, the substrate is made of insulating material, which can withstand the weight of the chip assembly and the thermal stress generated during operation, while providing the necessary electrical connection channels for signal transmission. The chip assembly contains multiple different types of packaged chips, at least including a first chip and a second chip. The first chip serves as a bearing base and has a larger area, which can provide sufficient physical support space for multiple second chips. The second chip has a smaller area, and multiple second chips are arranged in a tiled manner on the first chip and are electrically interconnected between chips through connecting lines. It should be particularly pointed out that gaps are reserved between adjacent second chips to optimize heat dissipation and stress distribution. The presence of such gaps enables heat to be more effectively dissipated from the chip surface to the outside of the packaging layer during chip operation, thereby reducing the risk of performance degradation or damage of the chip due to overheating. The gap design helps to disperse the mechanical stress generated during chip operation, avoiding the problem of chip cracking or connection failure caused by stress concentration. The packaging layer is the external protective layer of the entire structure, which directly wraps the outside of the chip assembly, providing physical protection and environmental isolation for the chip. The packaging layer uses high-performance epoxy resin or other plastic packaging materials, which have excellent insulation, heat resistance and mechanical impact resistance, and can effectively prevent damage to the chip from external moisture, dust or mechanical impact. In existing chip stack packaging, a transition plate is usually used as a signal relay station and physical support platform between chips, which increases the length of the signal transmission path, leading to an increase in signal delay and crosstalk risk, especially in high-frequency signal transmission scenarios. This problem is particularly prominent. This embodiment directly sets the chip assembly on the substrate and uses the first chip as a bearing base, with multiple second chips stacked in a staggered manner on the first chip, and signal interconnection is achieved through connecting lines, completely eliminating the use of a transition plate. This design significantly shortens the signal transmission path, thereby reducing the risk of signal delay and crosstalk, and greatly improving the efficiency of signal transmission. At the same time, the staggered stacking method makes the distribution of the second chip on the first chip more reasonable, not only fully utilizing the area of the first chip to achieve higher integration, but also optimizing heat dissipation and stress distribution through the gap design, further enhancing the thermal stability and mechanical strength of the packaging structure. The staggered stacking design reduces production costs, improves production efficiency, and also maintains the advantages of miniaturization and high integration of the packaging structure, making it have a wide application prospect in the modern semiconductor industry. It should be noted that the first chip and the second chip described in this embodiment are only used for illustrative description and are not limited to specific types of chips. In actual applications, the first chip and the second chip can be selected according to specific needs, such as processor chips, memory chips, sensor chips, etc., and not only represent two chips. Multiple different types and quantities of chips can be stacked according to actual needs to meet diverse application needs.

[0042] In another embodiment, with reference toFigure 3 and Figure 4 The chip assembly includes multiple different types of packaged chips, each of which is a complete packaging unit itself, containing a metal frame on which a wafer is connected by silver paste, and then wrapped by a plastic sealing area to form a protective layer. The design of this packaged chip ensures that the wafer inside the chip can work stably under the support of the metal frame. Silver paste, as a highly conductive adhesive material, can effectively connect the wafer and the metal frame, ensuring smooth transmission of electrical signals. The presence of the plastic sealing area provides physical protection for the wafer, preventing damage to the chip from external environmental factors such as humidity, dust, or mechanical impact. In addition, the metal frame in this embodiment can be compatible with multiple wafer models to cope with different sizes and PAD pins, using a modular or adjustable structure layout, with multiple adjustable mounting areas reserved on the substrate. These areas can accommodate wafers of different sizes, i.e., different pin interfaces are set on the opposite sides of the metal frame, i.e., contact point arrays are set. Based on the PAD layout of the specific wafer, some contact points are selectively used, so that different wafer models can be adapted without significantly modifying the frame.

[0043] In summary, the present application successfully solves the problems of low signal transmission efficiency and insufficient reliability caused by the dependence on a conversion board in traditional chip packaging by directly setting a chip assembly on a substrate, using a larger first chip as a bearing base, and stacking multiple smaller second chips on the first chip in a staggered manner, connecting each other through connecting lines, and being directly wrapped by a packaging layer. This design not only shortens the signal transmission path and improves the signal transmission efficiency, but also optimizes heat dissipation and stress distribution through gap design, enhancing the thermal stability and mechanical strength of the packaging structure. At the same time, the process of eliminating the conversion board simplifies the manufacturing process, reduces production costs, and maintains the advantages of miniaturization and high integration. This chip stacking packaging structure provides a stable, efficient, and cost-effective solution for high-performance electronic devices, with broad application prospects and important technical value.

[0044] In an embodiment, the connecting line is one of a pure gold wire, a copper wire, an aluminum wire, or an alloy wire. The packaged chip further includes a third chip stacked on the second chip and connected to the second chip and / or the first chip through a connecting line.

[0045] In this embodiment, the third chip increases the level of chip stacking, and also provides more functional options and signal transmission paths. The third chip is stacked on the second chip and is electrically connected with the second chip and / or the first chip through the connecting lines. This multi-level, multi-dimensional chip stacking design enables the entire packaging structure to maintain miniaturization while achieving higher integration and more complex functions. The material selection of the connecting lines is also crucial. Different materials such as pure gold wire, copper wire, aluminum wire, or alloy wire have their own unique electrical conductivity and mechanical strength, and can be selected according to specific application scenarios and requirements. For example, in situations requiring high electrical conductivity and good corrosion resistance, pure gold wire may be the best choice; in scenarios where cost is a concern, copper wire and aluminum wire are more economical and practical. Alloy wire strikes a good balance between electrical conductivity and mechanical strength.

[0046] The above-described embodiments are merely used to illustrate the technical solutions of the present application, but not limit the present application; even though the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent replacements; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of fabricating a multi-die chip stack package structure, comprising: The application relates to a multi-type chip stack packaging structure and a packaging method thereof. The pre-stacked packaging chips are area-sequenced, a first packaging chip in the sequencing result is selected as a first chip, a base chip with preset pins is obtained by performing compatible pin layout design on the first chip; other packaging chips lower than the first chip in the sequencing result are taken as second chips, a plurality of second chips are laid flat on the surface of the base chip to obtain a chip combination; the pins of each second chip are connected to the micro-bumps of the first chip according to the preset pins to obtain a multi-layer stack structure; the multi-layer stack structure is integrally packaged and molded to obtain a multi-type chip stack packaging structure.

2. The method of claim 1, wherein the method further comprises: The step of sequencing the pre-stacked packaging chips includes: the size of a plurality of chips to be packaged is measured, the chip area list is obtained according to the measurement result, the chip area list is sequenced in descending order, the chips are functionally screened according to the sequencing result to obtain a candidate base chip set, and the chip area list is updated according to the verification result to obtain a sequencing result. The step of selecting the first packaging chip in the sequencing result as the first chip and performing compatible pin layout design on the first chip to obtain the base chip with preset pins includes: the first packaging chip in the sequencing result is selected as the first chip, the pin demand of the first chip is functionally classified and analyzed to obtain a pin function allocation table, the first chip is regionally divided and modularly laid out and designed according to the pin function allocation table to obtain an initial pin layout diagram, a plurality of layers of high-conductivity copper materials are deposited on the silicon wafer of the first chip according to the initial pin layout diagram to form a pin array structure corresponding to the initial pin layout diagram, a pin array base is generated, and copper or gold micro-bumps are electroplated at preset positions of the pin array base to obtain the base chip with preset pins.

3. The method of claim 1, wherein the method further comprises: forming a plurality of through-silicon vias (TSVs) in the plurality of chips; and forming a plurality of redistribution layers (RDLs) on the plurality of chips. The step of taking other packaging chips lower than the first chip in the sequencing result as the second chips and laying flat a plurality of second chips on the surface of the base chip to obtain a chip combination includes: the second chips lower than the first chip in the sequencing result are functionally classified and screened according to preset functional requirements to obtain a function-grouped chip set, the surface of the base chip is planned according to the function-grouped chip set to obtain a partitioned base chip, and the second chips in the function-grouped chip set are aligned and attached to the first chip according to the functional area division of the partitioned base chip to obtain the chip combination. The step of connecting the pins of each second chip to the micro-bumps of the first chip according to the preset pins to obtain the multi-layer stack structure includes: vertical through holes are processed in the pin area of the second chip, the vertical through holes are preliminarily positionally matched with the micro-bumps of the first chip to obtain a pre-aligned chip combination, the pre-aligned chip combination is subjected to hot-press bonding treatment, the vertical through holes of the second chip and the micro-bumps of the first chip are electrically connected through metal diffusion to obtain a preliminarily connected multi-layer structure, 4. The method of claim 1, wherein the method further comprises: the preliminarily connected multi-layer structure is subjected to low-temperature annealing treatment to obtain the multi-layer stack structure. ​ ​ ​ 5. The method of claim 1, wherein the method further comprises: forming a plurality of through-silicon-vias (TSVs) in the plurality of chips; and forming a plurality of redistribution layers (RDLs) on the plurality of chips. ​ ​ ​ ​ 6. The method of claim 1, wherein the method further comprises: The step of integrally packaging and plastic encapsulation molding the multi-layer stacked structure to obtain the multi-type chip stacked packaging structure comprises: Injecting low dielectric constant epoxy resin into the gap between the first chip and the second chip under vacuum environment, and performing preliminary curing under low-temperature baking condition to obtain a filled stable structure; Performing surface leveling treatment on the filled stable structure, uniformly coating encapsulation layer material on the outside of the chip assembly, forming an encapsulation layer through molding process to obtain the multi-type chip stacked packaging structure.

7. The method of claim 1, wherein the method further comprises: forming a plurality of through-silicon vias (TSVs) in the plurality of chips; and forming a plurality of redistribution layers (RDLs) on the plurality of chips. After the step of integrally packaging and plastic encapsulation molding the multi-layer stacked structure, the method further comprises: Scanning the micro-bump connection points between the first chip and the second chip, and screening out structures in which all connection points meet the preset geometric and electrical connection standards to obtain a preliminary inspection qualified structure; Applying a multi-frequency pulse signal to the preset pins between the first chip and the second chip, and obtaining structures in which the signal transmission quality meets the preset threshold to obtain an electrical verification structure; Performing multi-temperature zone thermal cycle stress test on the electrical verification structure to obtain the multi-type chip stacked packaging structure.

8. A multi-die chip stack package structure, applied to the manufacturing method of any one of claims 1 to 7, characterized in that, Comprise: a substrate; a chip assembly comprising a plurality of different types of packaging chips, the packaging chips comprising at least a first chip and a second chip, a plurality of the second chips being tiled on the first chip and being connected to each other by a connecting line, wherein the area of the first chip is larger than that of the second chip, and there is a gap between adjacent second chips; an encapsulation layer wrapped outside the chip assembly.

9. The multi-die chip stack package structure of claim 8, wherein, The connecting line is one of a pure gold wire, a copper wire, an aluminum wire, or an alloy wire.

10. The multi-die chip stack package structure of claim 8, wherein, The packaging chip further comprises a third chip, the third chip being stacked on the second chip and being connected to the second chip and / or the first chip by a connecting line.

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